CN117077115A - Cross-language multi-process interaction method, electronic equipment and medium in chip verification stage - Google Patents
Cross-language multi-process interaction method, electronic equipment and medium in chip verification stage Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims 5
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Abstract
The invention relates to the technical field of chips, in particular to a cross-language multi-process interaction method, electronic equipment and a medium in a chip verification stage, wherein the method comprises the following steps of S1, constructing a shared resource pool D n ，D n Comprising interactive identification groups (S m n ,P m n ) The method comprises the steps of carrying out a first treatment on the surface of the Step S2, setting Q processes { P } 1 ,P 2 ,…,P q ,…,P Q According to P 1 ,P 2 ,…,P q ,…,P Q Is performed sequentially; step S3, setting P q And P q+1 Sharing a set of interaction identification sets (S m n ,P m n )，P q+1 Every preset time direction D n Sending and acquiring a first shared identification instruction, and executing P q P when execution is completed q To D n Transmitting the corresponding S m n When P q+1 At D n Obtain a pair ofS of the response m n At the time, to P q+1 Transmitting the corresponding P m n Execute P q+1 Until the Q processes are executed. The invention improves the reliability and efficiency of cross-language multi-process interaction in the chip verification stage.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a cross-language multi-process interaction method, an electronic device, and a medium for a chip verification stage.
Background
In the chip verification stage, a plurality of different processes are involved, communication is required between the different processes, in the prior art, a memory is generally provided, a first identifier is stored in a preset address corresponding to the memory during execution of a first program, the preset address is stored as a second identifier after the execution of the first program is finished, during this period, the second program continuously reads data in the preset address corresponding to the memory, and when the data in the preset address is found to be the second identifier, the second program starts to be executed. However, the data stored in the preset address corresponding to the memory is uncontrollable, the data in the preset address corresponding to the memory may be tampered by hardware, and once tampering occurs, the multiprocess communication cannot be normally interacted, so that the multiprocess interaction reliability is poor. In addition, different processes may correspond to different languages, such as a C++ language and a SystemVerilog language, and the processes in the different languages cannot directly interact, and further need to be converted, so that the efficiency of multi-process interaction is reduced. Therefore, how to improve the reliability and efficiency of cross-language multi-process interaction in the chip verification stage becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a cross-language multi-process interaction method, electronic equipment and medium for a chip verification stage, which improve the reliability and efficiency of the cross-language multi-process interaction for the chip verification stage.
According to a first aspect of the present invention, there is provided a cross-language multi-process interaction method in a chip verification stage, including:
step S1, constructing at least one shared resource pool D in a chip verification stage n The value range of N is 1 to N, N is the total number of the shared resource pools, and the shared resource pool D n Comprising at least one interactive identification group (S m n ,P m n )，S m n For D n Corresponding first shared identifier, P m n For D n The corresponding second sharing identifier has m ranging from 1 to f (n), and f (n) is D n The number of the medium interaction identification groups;
step S2, setting Q processes { P } 1 ,P 2 ,…,P q ,…,P Q }，P q For the Q-th process, the value of Q ranges from 1 to Q, and the Q processes are in accordance with P 1 ,P 2 ,…,P q ,…,P Q Is performed sequentially;
step S3, setting P q And P q+1 Sharing a set of interaction identification sets (S m n ,P m n )，P q+1 Every preset time of each interval corresponds to the shared resource pool D n Sending and acquiring a first shared identification instruction, and executing P q When P q When execution is finished, P q To the corresponding shared resource pool D n Transmitting the corresponding S m n When P q+1 In the corresponding shared resource pool D n Obtain corresponding S m n At the time, to P q+1 Transmitting the corresponding P m n Then execute P q+1 Until the Q processes are executed.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the cross-language multi-process interaction method, the electronic equipment and the medium in the chip verification stage can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
according to the invention, the shared resource pool is set, the shared interaction identification group is set for two processes which are executed successively, and interaction among multiple processes is realized through the corresponding first shared identification and second shared identification, so that the reliability and efficiency of cross-language multi-process interaction in the chip verification stage are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a cross-language multi-process interaction method in a chip verification stage according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a cross-language multi-process interaction method in a chip verification stage, which is shown in fig. 1 and comprises the following steps:
step S1, constructing at least one shared resource pool D in a chip verification stage n The value range of N is 1 to N, N is the total number of the shared resource pools, and the shared resource pool D n Comprising at least one interactive identification group (S m n ,P m n )，S m n For D n Corresponding first shared identifier, P m n For D n The corresponding second sharing identifier has m ranging from 1 to f (n), and f (n) is D n The number of interactive identification groups.
It should be noted that, in the chip verification stage, a plurality of chips, such as graphics processor (Graphics Processing Unit, abbreviated as GPU) chips, may be involved, when a virtual function is started, a plurality of virtual users may be involved, each chip may be involved in a plurality of processes, each virtual user may be involved in a plurality of processes, and as an example, one shared resource pool may be set for each chip, one shared resource pool may be set for each virtual user, one shared resource pool may be set for a plurality of associated chips, or one shared resource pool may be set for a plurality of associated virtual users, where the number of shared resource pools is set according to a specific application scenario, and the number of interactive identifier groups in each shared resource pool is determined according to a specific application scenario.
Step S2, setting Q processes { P } 1 ,P 2 ,…,P q ,…,P Q }，P q For the Q-th process, the value of Q ranges from 1 to Q, and the Q processes are in accordance with P 1 ,P 2 ,…,P q ,…,P Q Is performed sequentially.
Wherein Q processes are according to P 1 ,P 2 ,…,P q ,…,P Q Is executed in sequence, adjacent two processes P q And P q+1 Interaction is required.
Step S3, setting P q And P q+1 Sharing a set of interaction identification sets (S m n ,P m n )，P q+1 Every preset time of each interval corresponds to the shared resource pool D n Sending and acquiring a first shared identification instruction, and executing P q When P q When execution is finished, P q To the corresponding shared resource pool D n Transmitting the corresponding S m n When P q+1 In the corresponding shared resource pool D n Obtain corresponding S m n At the time, to P q+1 Transmitting the corresponding P m n Then execute P q+1 Until the Q processes are executed.
Wherein P is executed q P in the process of (1) q+1 Starting to correspond to the shared resource pool D at preset time intervals n Transmitting and acquiring a first shared identification instruction, and passing through P in real time q And P q+1 Shared S m n Determining P q Whether or not execution is completed, again through P q And P q+1 Shared P m n Start P q+1 Is executed to ensure P 1 ,P 2 ,…,P q ,…,P Q Orderly interaction.
In the chip verification process, a hardware process may be involved, and a software process may be involved, as an example, each process being generated based on a high-level language or on a hardware description language; the shared resource pool is generated based on a hardware description language; the high-level language may be a c++ language or a C language, and the hardware description language may be a SystemVerilog or Verilog language. The chip verification environment is typically a verification platform based on the universal verification methodology (Universal Verification Methodology, UVM) established by SystemVerilog. If the process is generated based on the hardware description language, directly interacting with the shared resource pool; if the process is generated based on a high-level language, the process interacts with the shared resource pool through a preset direct programming interface (Direct Programming Interface, DPI for short), so that multi-process cross-language interaction is realized.
As an example, if the process is generated based on a high-level language, in step S3, the process interacts with the shared resource pool through a preset direct programming interface, including:
and S31, converting the information sent to the shared resource pool by the process generated based on the high-level language into a format corresponding to the hardware description language through the preset direct programming interface, and sending the format to the shared resource pool.
And step S32, converting the information sent by the shared resource pool to the process generated based on the high-level language into a format corresponding to the high-level language through the preset direct programming interface, and sending the information to the process generated based on the high-level language.
The method specifically can call a preset calling function capable of communicating with the shared resource pool through the preset direct programming interface, and convert information sent by a process generated based on a high-level language to the shared resource pool into a format corresponding to a hardware description language, or convert information sent by the shared resource pool to the process generated based on the high-level language into a format corresponding to the high-level language, so that communication between the process generated based on the high-level language and the shared resource pool is realized.
Through the steps S31-S32, the cross-process multi-process shared resource pool can be realized, and the reliability and efficiency of multi-process cross-language communication are improved.
As an example, the step S3 includes:
step S301, for Q processes { P 1 ,P 2 ,…,P q ,…,P Q In every adjacent two P q And P q+1 A set of shared interactive identification groups is set (S m n ,P m n ) Setting q=1, step S302 is performed.
Step S302, setting P q+1 Every preset time of each interval corresponds to the shared resource pool D n Sending and acquiring a first shared identification instruction, and executing P q When P q When execution is finished, P q To the corresponding shared resource pool D n Transmitting S m n When P q+1 In the corresponding shared resource pool D n Obtain corresponding S m n At the time, to P q+1 Transmitting the corresponding P m n Then execute P q+1 When P q+1 After the execution is completed, step S303 is executed.
In step S303, if q+1=q, the flow is ended, and if q+1<Q, q=q+1 is set, and the process returns to step S302.
Q processes { P } can be performed by steps S301-S303 1 ,P 2 ,…,P q ,…,P Q The execution of the process is carried out sequentially, so that the accuracy of the process execution can be ensured, and the execution efficiency can be improved.
Wherein each group (S m n ,P m n ) Is set to a single state mode, and the same interactive identification group (S m n ,P m n ) Can only be made up of one group P at a time q And P q+1 Shared use, and when P q+1 After execution is completed, the corresponding (S m n ,P m n ) Release for other unexecuted P q And P q+1 Sharing use. The singlet mode refers to that the system can send out the data only once in the same time and can send out the data when the data is created againPrompt, and refuse creation. Group (S) m n ,P m n ) Can only be used once after creation, can be released when the use is completed, and can be used again in a singlet mode after the release is completed, and it is noted that the release means deletion, i.e., the release is completed (S m n ,P m n ) And deleting.
Taking q=3 as an example, P 1 P for image data handling process 2 P for image data processing procedure 3 For the image data presentation process, the image data carrying process acquires the image data firstly, then the image data processing process processes the image data after the image data is acquired, and the image data presentation process presents the image data after the data processing process is processed. Image data handling process and image data processing process (S) m n ,P m n ) Is (send) 0 ，poll 0 ) An image data processing process and an image data rendering process (S m n ,P m n ) Is (send) 1 ,poll 1 ). In this embodiment, an image data handling process is first performed to obtain image data to be processed, and in this process, the image data processing process is continuously directed to the shared resource pool D n Transmitting and acquiring a first shared identification instruction, and monitoring a shared resource pool D in real time n Whether or not send is received 0 When sharing resource pool D n Receive send 0 When sending poll to image data processing process 0 The image data processing process starts to be executed, and the image data presenting process continuously transmits the image data to the shared resource pool D n And sending and acquiring a first shared identification instruction. It should be noted that the image data presenting process may start to continuously present to the shared resource pool D at the initial stage n The image data presentation process can also start to continuously send the instruction of acquiring the first shared identification to the shared resource pool D when the image data processing process starts to execute n And sending and acquiring a first shared identification instruction. When the image data processing process is executed, the image data processing process transmits the image data to the shared resource pool D n Send 1 When sharing resourcesSource pool D n Receive send 1 When sending poll to image data rendering process 1 The image data presentation process starts to be executed until the image data presentation process is completed. The orderly and reliable interaction of the image data carrying process, the image data processing process and the image data presenting process is realized. Further, as an example, the image data handling process and the image data rendering process are implemented based on UVM, are implemented in SystemVerilog language, and can be directly associated with the shared resource pool D n Communication, image data processing process is generated based on high-level language, and needs to be connected with shared resource pool D through preset direct programming interface n And (5) communication.
According to the embodiment of the invention, the shared resource pool is arranged, the shared interaction identification group is arranged for two processes which are executed successively, and interaction among multiple processes is realized through the corresponding first shared identification and second shared identification, so that the reliability and efficiency of cross-language multi-process interaction in the chip verification stage are improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. The cross-language multi-process interaction method for the chip verification stage is characterized by comprising the following steps of:
step S1, constructing at least one shared resource pool D in a chip verification stage n The value range of N is 1 to N, N is the total number of the shared resource pools, and the shared resource pool D n Comprising at least one interactive identification group (S m n ,P m n )，S m n For D n Corresponding first shared identifier, P m n For D n The corresponding second sharing identifier has m ranging from 1 to f (n), and f (n) is D n The number of the medium interaction identification groups;
step S2, setting Q processes { P } 1 ,P 2 ,…,P q ,…,P Q }，P q For the Q-th process, the value of Q ranges from 1 to Q, and the Q processes are in accordance with P 1 ,P 2 ,…,P q ,…,P Q Is performed sequentially;
step S3, setting P q And P q+1 Sharing a set of interaction identification sets (S m n ,P m n )，P q+1 Every preset time of each interval corresponds to the shared resource pool D n Sending and acquiring a first shared identification instruction, and executing P q When P q When execution is finished, P q To the corresponding shared resource pool D n Transmitting the corresponding S m n When P q+1 In the corresponding shared resource pool D n Obtain corresponding S m n At the time, to P q+1 Transmitting the corresponding P m n Then execute P q+1 Until the Q processes are executed.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
each process is generated based on a high-level language or on a hardware description language; the shared resource pool is generated based on a hardware description language; if the process is generated based on the hardware description language, directly interacting with the shared resource pool; if the process is generated based on a high-level language, the process interacts with the shared resource pool through a preset direct programming interface.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
if the process is generated based on a high-level language, in the step S3, the process interacts with the shared resource pool through a preset direct programming interface, including:
step S31, converting the information sent to the shared resource pool by the process generated based on the high-level language into a format corresponding to the hardware description language through the preset direct programming interface, and sending the format to the shared resource pool;
and step S32, converting the information sent by the shared resource pool to the process generated based on the high-level language into a format corresponding to the high-level language through the preset direct programming interface, and sending the information to the process generated based on the high-level language.
4. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the high-level language is C++ language or C language.
5. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the hardware description language is SystemVerilog or Verilog.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S3 includes:
step S301, for Q processes { P 1 ,P 2 ,…,P q ,…,P Q In every adjacent two P q And P q+1 A set of shared interactive identification groups is set (S m n ,P m n ) Setting q=1, and executing step S302;
step S302, setting P q+1 Every preset time of each interval corresponds to the shared resource pool D n Sending and acquiring a first shared identification instruction, and executing P q When P q When execution is finished, P q To the corresponding shared resource pool D n Transmitting S m n When P q+1 In the corresponding shared resource pool D n Obtain corresponding S m n At the time, to P q+1 Transmitting the corresponding P m n Then execute P q+1 When P q+1 When the execution is completed, step S303 is executed;
in step S303, if q+1=q, the flow is ended, and if q+1<Q, q=q+1 is set, and the process returns to step S302.
7. The method of claim 6, wherein the step of providing the first layer comprises,
P q+1 starting from the initial moment, every preset time is set to the corresponding shared resource pool D n Sending and acquiring a first shared identification instruction or starting to execute P q At the time P q+1 Starting to correspond to the shared resource pool D at preset time intervals n And sending and acquiring a first shared identification instruction.
8. The method of claim 6, wherein the step of providing the first layer comprises,
each group (S) m n ,P m n ) Is set to a single state mode, and the same interactive identification group (S m n ,P m n ) Can only be made up of one group P at a time q And P q+1 Shared use, and when P q+1 After execution is completed, the corresponding (S m n ,P m n ) Release for other unexecuted P q And P q+1 Sharing use.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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