CN116737473A - Memory reading and writing method for chip verification and related device thereof - Google Patents
Memory reading and writing method for chip verification and related device thereof Download PDFInfo
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Abstract
The embodiment of the application provides a memory reading and writing method for chip verification and a related device thereof, comprising the following steps: acquiring a data reading request, wherein the data reading request comprises a first address of data to be acquired expressed in a first language; converting a first address expressed in a first language into a second address expressed in a second language using an interface function; converting the second address by using a second language, determining a memory and obtaining a granular address; and according to the granulating address, calling a processing command of the memory, and reading the data to be acquired stored in the second address. The embodiment of the application can realize multiple complex operations on the basis of intercommunication among multiple languages in the reading of the back door access, expands the application range of the back door access in the SOC verification process, meets the requirement of memory function verification, and improves the verification efficiency and accuracy.
Description
Technical Field
The present disclosure relates to simulation verification of electronic systems, and more particularly, to a memory read and write method for chip verification and related devices.
Background
When a large amount of data is processed in the SOC, a large amount of simulation time is consumed for data storage and subsequent data comparison, so that the verification speed is reduced. In addition, in the SOC system, the read-write operation is performed by using the same access method, and if a problem occurs in the memory access process, the problem is extremely difficult to be perceived and verification loopholes easily occur. In order to solve the above problems, a mode of accessing the memory by the back door is introduced.
However, the existing mode of accessing the memory by the back door calls the internal function of the memory according to the physical address in the verification environment, and directly writes the internal function into the memory, so that the application range is smaller, and the method is only suitable for simple IP verification, but the actual large-scale SOC verification is more complicated.
Therefore, how to expand the application range of back gate access in SOC verification, meet the requirement of memory function verification, and improve the verification efficiency and accuracy becomes a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
Therefore, the embodiment of the application provides the memory access method to expand the application range of back gate access in SOC verification, meet the requirement of memory function verification, and improve the verification efficiency and accuracy.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
the embodiment of the application provides a memory reading method for chip verification, which comprises the following steps:
acquiring a data reading request, wherein the data reading request comprises a first address of data to be acquired expressed in a first language;
converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
converting the second address by using a second language, determining a memory and obtaining a granular address;
according to the granular address, calling a processing command of the memory, and reading the to-be-stored address stored by the second address
Data is acquired.
Optionally, the first language includes a general purpose programming language, and the second language includes a hardware description language.
Optionally, the general programming language includes a c++ language, and the hardware description language includes a SystemVerilog language. Optionally, the first address includes a first virtual address, the second address includes a second virtual address, the converting the second address using a second language, determining a memory and obtaining a granular address includes:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
Optionally, the memory includes volatile memory or nonvolatile memory.
Optionally, the method further comprises the step of splicing the read data of the granulation address.
The embodiment of the application also provides a memory writing method for chip verification, which comprises the following steps:
acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;
converting a first address of a memory expressed in a first language and the data to be written into a second address expressed in a second language and the data to be written by using an interface function;
converting the second address by using a second language, determining a memory and obtaining a granular address;
and according to the granulating address, calling a processing command of the memory, and writing the data to be written into the memory.
Optionally, the first language includes a general purpose programming language, and the second language includes a hardware description language.
Optionally, the general programming language includes a c++ language, and the hardware description language includes a SystemVerilog language. Optionally, the first address includes a first virtual address, the second address includes a second virtual address, the converting the second address using a second language, determining a memory and obtaining a granular address includes:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
Optionally, the memory includes volatile memory or nonvolatile memory.
Optionally, before the step of writing the data to be written into the memory, the step of splitting the data to be written further includes calling a processing command of the memory according to the granular address.
The embodiment of the application also provides a memory reading device for chip verification, which comprises:
an address acquisition module for acquiring a data reading request including a first address of data to be acquired expressed in a first language;
a language conversion module for converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
an address operation module: for translating the second address using a second language, determining a memory and obtaining a granular address;
and the data reading module is used for calling a processing command of the memory according to the granulating address and reading the data to be acquired stored in the second address.
Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and the address operation module is configured to translate the second address using a second language, determine a memory and obtain a granular address, and includes:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
Optionally, the method further comprises: and the data splicing module is used for splicing the read data of the granulating addresses.
The embodiment of the application also provides a memory writing device for chip verification, which comprises:
the address acquisition module is used for acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;
the language conversion module is used for converting the first address of the memory expressed by using the first language and the data to be written into the second address expressed by using the second language and the data to be written by using the interface function;
the address operation module is used for converting the second address by using a second language, determining a memory and obtaining a granular address;
and the data writing module is used for calling a processing command of the memory according to the granulating address and writing the data to be written into the memory.
Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and the address operation module: for translating the second address using a second language, determining a memory and obtaining a granular address, comprising:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
Optionally, the device further comprises a data splitting module, configured to split the data to be written.
The embodiment of the application also provides a chip which is configured as the chip verified memory reading device or the chip verified memory writing device.
The embodiment of the application also provides electronic equipment comprising the chip.
The embodiment of the application provides a memory reading method for chip verification, which is used for acquiring a data reading request, wherein the data reading request comprises a first address of data to be acquired expressed by a first language; converting a first address expressed in a first language into a second address expressed in a second language using an interface function; converting the second address by using a second language, determining a memory and obtaining a granular address; and according to the granulating address, calling a processing command of the memory, and reading the data to be acquired stored in the second address. In this way, when the back door is used to access the read memory in the SOC verification process, the interface function is utilized to communicate with multiple languages, and meanwhile, in the second language, the address conversion in the data path and the memory selection are executed, so that multiple complex operations can be realized on the basis of the communication of multiple languages in the reading of the back door access, the application range of the back door access in the SOC verification process is enlarged, the requirement of the memory function verification is met, and the verification efficiency and the verification accuracy are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory access device with chip verification;
FIG. 2 is a flow chart of a method for reading a memory with chip verification according to an embodiment of the application;
FIG. 3 is a flowchart showing a method for determining a memory and obtaining a granular address according to a method for reading a memory for chip verification according to an embodiment of the present application;
FIG. 4 is a flowchart of a memory writing method for chip verification according to an embodiment of the present application;
FIG. 5 is another flow chart of a memory writing method for chip verification according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a memory reading device with chip verification according to an embodiment of the present application;
fig. 7 is a schematic diagram of a memory writing device with chip verification according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In SOC (System-on-a-Chip) verification, there are a large number of memory access operations. A storage access method comprises the following steps: firstly, data pre-storing is carried out, and the data obtained after the memory operation of the DUT (Design under Test, tested device) is simulated through simulation; then the DUT performs actual memory operation; and finally, data obtained by performing actual memory operation on the DUT is read and compared with data obtained by simulating the memory operation of the DUT, so that the correctness of the behavior of the DUT is determined.
The method is a front door access method for performing verification operation on the memory, but when a large amount of data is processed, a large amount of simulation time is consumed for pre-storing the data and comparing the data after reading the data, so that the verification speed is reduced. In addition, in the SOC system, the memory is verified by the same access method, and if a problem occurs in the memory access process, the problem is extremely difficult to be perceived and verification loopholes easily occur.
Therefore, the method for accessing the memory by using the back gate can ensure that the back gate access does not occupy simulation time, can rapidly operate the memory, greatly improves simulation efficiency and improves verification speed in the memory access for processing a large amount of data. In addition, by using the comparison mode that the front gate accesses the write data and the rear gate accesses the read data, or the rear gate accesses the write data and the front gate accesses the read data, errors in the front gate operation can be detected, and the verification quality can be improved through various verification means. However, for different types of storage, the back-gate access mode of the simulation model is different, so that no unified method is applicable to most types of storage.
Fig. 1 is a schematic diagram of a memory access device, including a test terminal 1 and a memory 2, where a mode of accessing the memory by a back gate is shown in fig. 1 when performing access verification of the memory, the test terminal 1 calls a read-write function in the memory 2, and directly accesses a physical address in the memory 2.
The above method has limited functions and is only suitable for simple data comparison verification. In the practical large-scale SOC verification, a large number of complex operations need to be sequentially executed, and data needs to be processed for many times in the verification, wherein the problems of virtual-real address conversion and the like are involved; if there are multiple storage devices, the problem of selecting a storage device is involved in accessing the memory. In addition, in SOC verification, the verification language is a hardware description language, such as System Verilog or Verilog, and a general programming language, such as C language or c++ language, is required to be used in the SOC, and a simulation verification driver is required to use a plurality of different languages in SOC verification, and there is data interaction between these languages. Data interaction between these languages is also an important challenge in SOC verification. Therefore, the prior art scheme cannot realize multiple complex data operations in SOC verification and cannot realize intercommunication among multiple languages. Therefore, it is necessary to expand the application range of the back door access.
In order to solve the foregoing problems, an embodiment of the present application provides a method for reading a memory for chip verification, where address conversion in a data path can be implemented on the basis of multi-language interworking when a back door is used to access read data in an SOC verification process, and specific steps of a flow of the method are shown in fig. 2, where the method includes:
step S11: a data read request is obtained, the data read request including a first address of data to be obtained expressed in a first language.
Since simulation and comparison verification of data with actual operation are required in the test environment of SOC verification, in order to verify the memory function, it is necessary to first acquire a data read request.
In SOC verification, a stimulus of the SOC level requires execution of a series of software operations, in which in order to access a memory, an address for accessing the memory needs to be generated, and a first address of data to be acquired is included in a data read request.
Since the verification language is a hardware description language when the memory is verified, and the SOC verification is different from the verification language because the general programming language is required to simulate the verification driver. The first address of the data to be acquired in the data reading request is expressed in a first language under the restriction of the verification language of the back door verification mode.
It will be readily appreciated that the first language is a language for simulating a verification driver, i.e. a generic programming language, which can achieve a simulation verification driver more simply than a hardware description language.
Where test environment refers to hardware, software, devices, data, etc., necessary to complete a test.
Step S12, converting the first address expressed in the first language into the second address expressed in the second language by using the interface function.
As described above, after the first address expressed in the first language is obtained, it is required to be converted into the second language for easy verification in order to implement the subsequent chip verification process.
Based on the foregoing description, the second language is a hardware description language, which can perform the back door access of the memory more simply than a general programming language, and can directly operate the acquired data.
Specifically, the general programming language may include a c++ language, and the hardware description language may be a System Verilog language. The System Verilog language is used as a hardware description language and is also a verification language, so that the System Verilog language can directly use the read data of the memory for verification operation. The System Verilog language combines part of the concept of the C++ language during design and integrates object-oriented programming characteristics, so that the C++ language is the most preferred for being matched with the System Verilog language for use
Language.
Through the interface function, the data conversion between the two languages can be realized more easily. In a specific embodiment, the interface function includes a first language layer and a second language layer, so that the interface function with the corresponding two language layers can be replaced according to the specific languages used to perform data conversion between any two languages. It is easy to understand that when at least one of the first language or the second language is changed, the interface function only needs to be changed according to the kind of the language.
In an alternative implementation, when the first language is a System Verilog language layer, the interface function may be a DPI (Direct Programming Interface ) interface function. DPI consists of two layers: the System Verilog layer and the second language layer are isolated from each other, and the second language layer actually uses which programming language is irrelevant to the System Verilog end of the interface, so that the DPI interface can be connected with the System Verilog language.
In an alternative implementation, the interface function may include a plurality of instructions for invoking a function of a different name, where each instruction is for invoking execution of corresponding function code.
Step S13, converting the second address by using a second language, determining a memory and obtaining a granular address.
In an alternative implementation, the converted second address is a physical address expressed in the second language, and in order to read the data, a specific location of the data is further determined according to the second address.
As mentioned above, since a plurality of memories of the same type or a plurality of different types may be often provided in a computer device, it is necessary to determine a memory to be accessed according to the obtained physical address after obtaining the converted second address, that is, the aforementioned physical address.
It is easy to understand that when the type of memory is a memory, the memory is provided with a plurality of memory particles, which are also called memory chips. These memory particles are composed of a plurality of memory matrices (banks), also known as Logical banks, each of which is structured like a large grid subarray, the number of grids in each Bank being the same. The subarrays have a plurality of columns (columns) and a plurality of rows (rows) so that when data in a certain cell is accessed, the position can be determined by the Column and Row information. Therefore, after the second address is obtained, the address needs to be converted into a granular address composed of the bank, row and column information and capable of accessing the granular memory, so that the data in the storage grain can be operated.
Referring to fig. 3, in a specific embodiment, in order to implement verification of a chip in the case that the acquired first address is a virtual address, that is, when the first address includes the first virtual address and the second address obtained through interface function conversion is also the second virtual address, step S13 of the method for reading a memory for chip verification provided by the embodiment of the present application may include:
step S131: translating the second virtual address using a second language to obtain a physical address, translating the physical address to obtain
Granulating the address.
The second language cannot directly access the memory by using the second virtual address, and the virtual address needs to be converted into the physical address of the memory before the memory can be accessed continuously, and of course, the granular address also needs to be obtained through physical address conversion.
And S132, determining a corresponding memory according to the physical address.
After the physical address is obtained, the granular address and the memory are further determined based on the physical address.
The specific determination method of the granular address is not described in detail.
Since in computer devices, often a plurality of memories of the same type or of different types may be provided, it is also necessary to determine the memory to be accessed from the physical address obtained after obtaining the physical address.
And S14, according to the granulating address, calling a processing command of the memory, and reading the data to be acquired stored in the second address.
After the data is obtained, the data may be validated by a second language or other operations may be performed in conjunction with the SOC.
Because the types of memories are various, in order to adapt to the access needs of various memories, the functions for calling the internal commands of the memories can be changed, so that the internal commands of various memories can be called, and the method is applicable to various memories.
Further, in an alternative implementation, the memory includes volatile memory or nonvolatile memory. The memory access method of the embodiment of the application realizes the access of the back door by calling the own command of the memory, thereby realizing the memory reading of chip verification, and when the memory equipment is replaced, only the calling function is changed for different types of memories, and the reading method of the corresponding memory is called, so that the method can be used for the volatile memories such as the memory and the like, and also can be used for the nonvolatile memories such as the solid state disk and the like.
According to the memory reading method for chip verification, in the SOC verification process, when the memory is read by using the back door access, the interface function is utilized, so that reading of the back door access based on intercommunication of multiple languages is realized, meanwhile, in the second language, address conversion in a data path and memory selection are performed, multiple complex operations are performed based on intercommunication of multiple languages in reading of the back door access, the application range of the back door access is enlarged, the requirement of memory function verification is met, and verification efficiency and correctness are improved.
It should be noted that, inside the SOC, the stimulus at the SOC level is written using a general-purpose programming language, and a special verification language is required to actually perform the SOC verification operation, but the verification language is typically a hardware description language.
Thus, in one alternative implementation, the first language is a general purpose programming language and the second language is a hardware description language.
In an alternative implementation, the general programming language is the C++ language and the hardware description language is the SystemVerilog language.
In particular, in SOC verification, because the stimulus at the SOC level is implemented by a set of analog-driven software stacks based on c++, the first language in initially acquiring and expressing virtual addresses is preferably the c++ language. The second language is mainly used for memory access and virtual address translation, and is preferably SystemVerilog. The SystemVerilog language is a hardware language that combines a Hardware Description Language (HDL) with a modern high level verification language (HVL). The method is mainly used for the chip realization and verification flow. SystemVerilog has all the structure required by the chip design and verification engineer, it integrates object-oriented programming, dynamic threading and inter-thread communication features, so it is easier to interwork with the C++ language, and it integrates the register conversion level circuitry (Register Transfer Level) all around. Therefore, the C++ language and the SystemVerilog language are selected to cooperate with the DPI interface function, so that the intercommunication between the two languages can be more easily realized, and the complex conversion operation of more virtual addresses can be completed.
In an alternative implementation, as shown in fig. 2, the step S14 may further include a step S15: and splicing the read data of the granulating addresses.
When the data to be read is stored in a plurality of banks, the data is stored in a split state, so that after the data in the storage grain is read, the data is spliced into complete data to be transmitted and used for subsequent operations.
The embodiment of the application also provides a memory writing method for chip verification, which can realize address conversion in a data path on the basis of multi-language intercommunication when using a back gate to access writing data in the SOC verification process, thereby realizing the verification of the memory, and the specific steps of the method flow are shown in figure 4, and the method comprises the following steps:
step S21, a data writing request is obtained, wherein the data writing request comprises a first address expressed in a first language and data to be written.
Since simulation and comparison verification of data and actual operation are required in the test environment of SOC verification, in order to verify the memory write function of chip verification, it is necessary to first acquire a data write request.
In SOC verification, the stimulus of the SOC level needs to perform a series of software operations in which, in order to access the memory, an address for accessing the memory needs to be generated, the first address included in the data write request. And in order to write data, the write request also includes the data to be written.
Since the verification language is a hardware description language when the memory is verified, and the SOC verification is different from the verification language because the general programming language is required to simulate the verification driver. The first address in the data write request is expressed in a first language, subject to the verification language limitations of the backdoor verification scheme.
It will be readily appreciated that the first language is a language for simulating a verification driver, i.e. a generic programming language, which can achieve a simulation verification driver more simply than a hardware description language.
Where test environment refers to hardware, software, devices, data, etc., necessary to complete a test.
And S22, converting the first address of the memory expressed in the first language and the data to be written into the second address expressed in the second language and the data to be written by using an interface function.
As described above, after the first address expressed in the first language is obtained, it is required to be converted into the second language for easy verification in order to implement the subsequent chip verification process.
Based on the foregoing description, the second language is a hardware description language that can perform back door access of the memory more simply than a general purpose programming language.
The language selection of the general programming language and the hardware description language is the same as that in the memory reading method for chip verification provided by the embodiment of the present application, and will not be repeated here. Through the interface function, the data conversion between the two languages can be realized more easily. In a specific embodiment, the interface function includes a first language layer and a second language layer, so that the interface function with the corresponding two language layers can be replaced according to the specific languages used to perform data conversion between any two languages. It is easy to understand that when at least one of the first language or the second language is changed, the interface function only needs to be changed according to the kind of the language.
In an alternative implementation, the same as the method for reading the memory for chip verification provided by the embodiment of the present application, when the required first language layer and second language layer are a System Verilog language layer and a c++ language layer, the interface function is DPI.
In an alternative implementation, the interface function may include a plurality of instructions for invoking a function of a different name, where each instruction is for invoking execution of corresponding function code.
Step S23, converting the second address by using a second language, determining a memory and obtaining a granular address.
In an alternative implementation, the converted second address is a physical address expressed in the second language, and in order to write the data, a specific location where the data needs to be written is further determined according to the second address.
As mentioned above, since a plurality of memories of the same type or a plurality of different types may be often provided in a computer device, it is necessary to determine a memory to be accessed according to the obtained physical address after obtaining the converted second address, that is, the aforementioned physical address.
Referring to fig. 5, in a specific embodiment, in order to implement verification of a memory in a case where the acquired first address is a virtual address, that is, the first address includes the first virtual address, and when the second address obtained through interface function conversion is also the second virtual address, step S23 of the method for reading a memory with chip verification provided by the embodiment of the present application may include:
step S231: converting the second virtual address to obtain a physical address by using a second language, and converting the physical address to obtain a granular address;
the second language cannot directly access the memory by using the virtual address, the virtual address needs to be converted into the physical address of the memory before the memory can be accessed continuously, and the granular address also needs to be obtained through physical address conversion.
And step S232, determining a corresponding memory according to the physical address.
After the physical address is obtained, the granular address and the memory are further determined based on the physical address.
The specific determination method of the granular address is not described in detail.
Since in computer devices, often a plurality of memories of the same type or of different types may be provided, it is also necessary to determine the memory to be accessed from the physical address obtained after obtaining the physical address.
And step S24, according to the granulating address, calling a processing command of the memory, and writing the data to be written into the memory.
After writing the data, the second language may be used for verification or other operations in conjunction with the SOC.
Because the types of memories are various, in order to adapt to the access needs of various memories, the functions for calling the internal commands of the memories can be changed, so that the internal commands of various memories can be called, and the method is applicable to various memories.
Further, in an alternative implementation, the memory includes volatile memory or nonvolatile memory. The memory access method of the embodiment of the application realizes the access of the back door by calling the own command of the memory, thereby realizing the memory reading of chip verification, and when the memory equipment is replaced, only the calling function is changed for different types of memories, and the reading method of the corresponding memory is called, so that the method can be used for the volatile memories such as the memory and the like as well as the nonvolatile memories such as the solid state disk and the like.
The memory writing method for chip verification of the embodiment of the application can realize writing of back door access based on intercommunication of multiple languages by using an interface function when the back door access is used for writing into the memory in the SOC verification process, and simultaneously, in the second language, address conversion in a data path is executed, and various complex operations are executed based on the intercommunication of multiple languages in reading of the back door access, thereby enlarging the application range of the back door access, meeting the requirement of memory function verification, and improving the verification efficiency and correctness.
It should be noted that, inside the SOC, the stimulus at the SOC level is written using a general-purpose programming language, and a special verification language is required to actually perform the SOC verification operation, but the verification language is typically a hardware description language. Thus, in one alternative implementation, the first language is a general purpose programming language and the second language is a hardware description language.
In an alternative implementation, the general programming language is the C++ language and the hardware description language is the System Verilog language.
Specifically, in SOC verification, since stimulus at SOC level is implemented based on a software stack of a set of analog drivers (drivers), a general-purpose programming language in initially acquiring and expressing virtual addresses is preferably c++ language. The hardware description language is mainly used for memory access and virtual address conversion, and is preferably the System Verilog language. The System Verilog language is a hardware language that combines Hardware Description Language (HDL) with modern high level verification language (HVL). The method is mainly used for the chip realization and verification flow. System Verilog has all the structure required by chip design and verification engineers, integrates object-oriented programming, dynamic threading, inter-thread communication, and other features, so that it is easier to interwork with the C++ language, and integrates register conversion level circuitry (Register Transfer Level) comprehensively. Therefore, the C++ language and the System Verilog language are selected to more easily realize intercommunication between the two languages and complete complex conversion operation of more virtual addresses.
In an alternative implementation, step S25 is further included before step S24 shown in fig. 4: splitting the data to be written.
In the memory device described in step S23, the data to be written needs to be disassembled and stored in a plurality of banks, so before writing the data into the memory granule, the data to be written needs to be disassembled and corresponding to the banks, and then the data to be written can be written into the memory granule.
In addition, the method for reading and writing the memory for chip verification according to the embodiment of the application can be applied to SOC verification and a monitor by means of language characteristics suitable for various chip verification methodologies because of the application of System Verilog language, and can be directly used as a monitoring means to detect the correctness of memory data.
The embodiment of the application also provides a memory reading device for chip verification, as shown in fig. 6, which comprises:
the read data acquisition module 10: for obtaining a data read request comprising use of a first language
The expressed first address of the data to be acquired;
the language conversion module 11: for converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
data manipulation module 12: for translating the second address using a second language, determining a memory and obtaining a granular address;
the data reading module 13: and the processing command of the memory is called according to the granulation address, and the data to be acquired stored in the second address is read.
In a specific embodiment, in order to implement verification of a memory in a case where the acquired first address is a virtual address, that is, when the first address includes the first virtual address and the second address obtained through interface function conversion is also the second virtual address, the memory reading device for chip verification provided by the embodiment of the present application may include,
data manipulation module 12: for translating the second address using a second language, determining a memory and obtaining a granular address, comprising:
converting the second virtual address to obtain a physical address by using a second language, and converting the physical address to obtain a granular address; and determining a corresponding memory according to the physical address.
After the physical address is obtained, the granular address and the memory are further determined based on the physical address.
In an alternative implementation, in the memory device as described above, the data to be read is disassembled and stored in multiple lattices, so that after the data in the storage grain is read, the data needs to be spliced into complete data before the complete data can be transmitted and used for subsequent operations.
Thus, as shown in fig. 6, the memory reading device for chip verification further includes a data splicing module 14 for splicing the read data of the granulation address.
The embodiment of the application also provides a memory writing device for chip verification, as shown in fig. 7, which comprises:
write data acquisition module 20: the method comprises the steps of obtaining a data writing request, wherein the data writing request comprises a first address expressed in a first language and data to be written;
the language conversion module 21: for converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
data manipulation module 22: for translating the second address using a second language, determining a memory and obtaining a granular address;
the data writing module 23: and according to the granulating address, calling a processing command of the memory, and writing the data to be written into the memory.
In a specific embodiment, in order to implement verification of a memory in a case where the acquired first address is a virtual address, that is, when the first address includes the first virtual address and the second address obtained through interface function conversion is also the second virtual address, the memory writing device for chip verification provided by the embodiment of the present application may include,
the data operation module 22: for translating the second address using a second language, determining a memory and obtaining a granular address, comprising:
converting the second virtual address to obtain a physical address by using a second language, and converting the physical address to obtain a granular address; and determining a corresponding memory according to the physical address.
After the physical address is obtained, the granular address and the memory are further determined based on the physical address.
In an alternative implementation, in the memory device as described above, the data to be written needs to be disassembled and stored in a plurality of lattices, so that, as shown in fig. 7, before the data is written into the storage grain, a data disassembling module 24 is further included for disassembling the data to be written.
In particular, the two memory access devices may be combined into one device, including all the modules.
The embodiment of the application also provides a chip, and in the embodiment of the application, the chip can be configured with any one or more memory access devices.
The embodiment of the application also provides the electronic equipment, and in the embodiment of the application, the electronic equipment can be provided with the chip.
Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.
Claims (20)
1. A memory read method for chip verification, comprising:
acquiring a data reading request, wherein the data reading request comprises a first address of data to be acquired expressed in a first language;
converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
converting the second address by using a second language, determining a memory and obtaining a granular address;
and according to the granulating address, calling a processing command of the memory, and reading the data to be acquired stored in the second address.
2. The chip-authenticated memory reading method according to claim 1, wherein said first language includes a general-purpose programming language and said second language includes a hardware description language.
3. The chip-verified memory reading method of claim 2, wherein the general programming language comprises a c++ language and the hardware description language comprises a System Verilog language.
4. The chip-verified memory reading method of claim 1, wherein the first address comprises a first virtual address, the second address comprises a second virtual address, the converting the second address in the second language, determining the memory and obtaining the granular address, comprising:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
5. The memory reading method of chip authentication of claim 1, wherein the memory comprises a volatile memory or a nonvolatile memory.
6. The method for reading a memory for chip verification according to claim 1, further comprising splicing the read data of the granular address.
7. A memory write method for chip verification, comprising:
acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;
converting a first address of a memory expressed in a first language and the data to be written into a second address expressed in a second language and the data to be written by using an interface function;
converting the second address by using a second language, determining a memory and obtaining a granular address;
and according to the granulating address, calling a processing command of the memory, and writing the data to be written into the memory.
8. The chip-authenticated memory writing method according to claim 7, wherein said first language includes a general-purpose programming language and said second language includes a hardware description language.
9. The memory writing method of chip authentication of claim 8, wherein the general programming language comprises c++ language and the hardware description language comprises System Verilog language.
10. The chip-verified memory writing method of claim 7, wherein the first address comprises a first virtual address and the second address comprises a second virtual address, the translating the second address in the second language, determining memory and obtaining a granular address, comprising:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
11. The memory writing method of chip authentication of claim 7, wherein the memory comprises a volatile memory or a nonvolatile memory.
12. The method for writing a memory for chip verification according to claim 7, wherein said step of calling a process command of said memory according to said granulated address to write data to be written into said memory further comprises splitting said data to be written into.
13. A memory read device for chip verification, comprising:
an address acquisition module for acquiring a data reading request including a first address of data to be acquired expressed in a first language;
a language conversion module for converting a first address expressed in a first language into a second address expressed in a second language using an interface function;
and the data operation module is used for: for translating the second address using a second language, determining a memory and obtaining a granular address;
and the data reading module is used for calling a processing command of the memory according to the granulating address and reading the data to be acquired stored in the second address.
14. The chip-authenticated memory reading device according to claim 13, wherein said first address comprises a first virtual address and said second address comprises a second virtual address, said data manipulation module for translating said second address using a second language, determining memory and obtaining a granular address, comprising:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
15. The chip-authenticated memory reading apparatus according to claim 13, further comprising: and the data splicing module is used for splicing the read data of the granulating addresses.
16. A memory writing device for chip verification, comprising:
the address acquisition module is used for acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;
the language conversion module is used for converting the first address of the memory expressed by using the first language and the data to be written into the second address expressed by using the second language and the data to be written by using the interface function;
the data operation module is used for converting the second address by using a second language, determining a memory and obtaining a granular address;
and the data writing module is used for calling a processing command of the memory according to the granulating address and writing the data to be written into the memory.
17. The chip-verified memory writing device of claim 16, wherein the first address comprises a first virtual address and the second address comprises a second virtual address, the data manipulation module: for translating the second address using a second language, determining a memory and obtaining a granular address, comprising:
translating the second virtual address using a second language to obtain a physical address;
converting the physical address to obtain a granular address;
and determining a corresponding memory according to the physical address.
18. The memory writing device of claim 16, further comprising a data splitting module for splitting the data to be written.
19. A chip, characterized in that the chip is configured as a chip-verified memory reading device according to any of claims 13-15 or as a chip-verified memory writing device according to any of claims 16-18.
20. An electronic device comprising the chip of claim 19.
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| CN117077115A (en) * | 2023-10-13 | 2023-11-17 | 沐曦集成电路(上海)有限公司 | Cross-language multi-process interaction method, electronic equipment and medium in chip verification stage |
| CN117077115B (en) * | 2023-10-13 | 2023-12-15 | 沐曦集成电路(上海)有限公司 | Cross-language multi-process interaction method, electronic equipment and medium in chip verification stage |
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