CN116911393B - Quantum chip design system, quantum chip design method, electronic equipment and storage medium - Google Patents
Quantum chip design system, quantum chip design method, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides a quantum chip design system, a quantum chip design method, electronic equipment and a storage medium, wherein the quantum chip design system comprises the following components: the invention establishes quantum chip tasks through the quantum chip design center and sends different subtasks to the corresponding block chain network to complete the concurrent collaboration of quantum chip sub-center design, and the invention can perform chip layout design, simulation verification and performance analysis on each sub-center block chain network, optimally support the concurrent execution of block chain multi-task block chains, not only establishes a collaborative trust mechanism between each block chain, but also shortens the time of chip design, supports the concurrent collaboration of multi-task, greatly improves the efficiency of chip design and reduces the cost of chip design.
Description
Technical Field
The present invention relates to the field of quantum chip technology, and in particular, to a quantum chip design system, a quantum chip design method, an electronic device, and a storage medium.
Background
Along with development of technology, quantum chips are applied on a large scale, and when complex quantum chips are designed, a plurality of chip design platforms are generally required to be completed together, so that the chip design cost is increased, and the chip design efficiency is reduced.
Disclosure of Invention
In view of the above problems, embodiments of the present invention have been made to provide a quantum chip design system, a quantum chip design method, an electronic device, and a storage medium that overcome or at least partially solve the above problems.
In order to solve the problems, the embodiment of the invention discloses a quantum chip design system, which comprises a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network and a quantum chip design center; the layout design blockchain network, the simulation verification blockchain network and the performance analysis blockchain network are respectively connected with the quantum chip design center;
The quantum chip design center is used for creating quantum chip tasks, and the quantum chip tasks comprise a layout design subtask, a simulation verification subtask and a performance analysis subtask; the layout design subtask is sent to the layout design block chain network; after the layout design block chain network executes the layout design subtask, the simulation verification subtask is sent to the simulation verification block chain network; after the simulation verification blockchain network executes the simulation verification subtask, the performance analysis subtask is sent to the performance analysis blockchain network;
the layout design block chain network is used for executing a layout design intelligent contract according to the layout design subtask, generating a layout design result and sending the layout design result to the quantum chip design center, wherein the layout design result is bound with the simulation verification subtask;
the simulation verification blockchain network is used for executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask, generating a simulation verification result and sending the simulation verification result to the quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
The performance analysis blockchain network is used for performing performance analysis on the simulation verification result according to the performance analysis subtask, generating a performance analysis result and sending the performance analysis result to the quantum chip design center;
the quantum chip design center is used for carrying out combined display on the layout design result, the simulation verification result and the performance analysis result according to a preset combination mode.
Optionally, the system further comprises a layout design blockchain adapter, wherein the layout design blockchain adapter is respectively connected with the layout design blockchain network and the quantum chip design center;
the layout design blockchain adapter is used for receiving the layout design subtasks sent by the quantum chip design center and sending the layout design subtasks to the layout design blockchain network.
Optionally, the layout design blockchain adapter includes first channel protocol metadata, and the layout design blockchain adapter is configured to read a first channel protocol and establish a communication connection with the layout design blockchain network.
Optionally, the system further comprises a simulated verification blockchain adapter connected with the simulated verification blockchain network and the quantum chip design center, respectively;
The simulation verification blockchain adapter is used for receiving the simulation verification subtask sent by the quantum chip design center and sending the simulation verification subtask to the simulation verification blockchain network.
Optionally, the emulation verification blockchain adapter includes second channel protocol metadata, and the emulation verification blockchain adapter is configured to read the second channel protocol and establish a communication connection with the emulation verification blockchain network.
Optionally, the emulation verification blockchain adapter further includes first format conversion metadata, and the emulation verification blockchain adapter is configured to convert a format of the layout design result into a first format supported by the emulation verification blockchain network, and send the layout design result in the first format to the emulation verification blockchain network.
Optionally, the system further comprises a performance analysis blockchain adapter connected with the performance analysis verification blockchain network and the quantum chip design center, respectively;
the performance analysis blockchain adapter is used for receiving the performance analysis subtasks sent by the quantum chip design center and sending the performance analysis subtasks to the performance analysis blockchain network.
Optionally, the performance analysis blockchain adapter includes third channel protocol metadata, and the performance analysis blockchain adapter is configured to read the third channel protocol to establish a communication connection with the performance blockchain network.
Optionally, the performance analysis blockchain adapter further includes second format conversion metadata, and the performance analysis blockchain adapter is configured to convert a format of the simulation verification result into a second format supported by the performance analysis blockchain network, and send the simulation verification result in the second format to the performance analysis blockchain network.
Optionally, the layout design blockchain network is composed of a plurality of layout design nodes, and the layout design blockchain network is used for carrying out node consensus according to the idle state and the storage condition of each layout design node to generate a target layout design node; and executing the intelligent contract of the layout design through the layout design node to generate the layout design result.
Optionally, the layout design blockchain network is used for detecting idle states of all the layout design nodes to generate a plurality of idle layout design nodes; and taking the node with the largest storage space in the plurality of idle layout design nodes as the target layout design node.
Optionally, the simulation verification blockchain network is composed of a plurality of simulation verification nodes, and the simulation verification blockchain network is used for carrying out node consensus according to the idle state and the storage condition of each simulation verification node to generate a target simulation verification node; and executing the simulation verification intelligent contract through the simulation verification node to generate a simulation verification result.
Optionally, the simulation verification blockchain network is used for detecting idle states of all simulation verification nodes to generate a plurality of idle simulation verification nodes; and taking the node with the largest storage space in the plurality of idle simulation verification nodes as the target simulation verification node.
Optionally, the performance analysis blockchain network is composed of a plurality of performance analysis nodes, and the performance analysis blockchain network is used for carrying out node consensus according to the idle state and the storage condition of each performance analysis node to generate a target performance analysis node; and executing a performance analysis intelligent contract through the target performance analysis node to generate the performance analysis result.
Optionally, the performance analysis blockchain network is used for detecting idle states of each performance analysis node to generate a plurality of idle performance analysis nodes; and taking the node with the largest storage space in the plurality of idle performance analysis nodes as the target performance analysis node.
Optionally, the method comprises the step of. The quantum chip design center is used for starting an event arranging engine, and the event arranging engine is used for monitoring whether the layout design subtasks are completed or not; and if the completion of the layout design subtask is monitored, the simulation verification subtask is sent to the simulation verification blockchain network.
Optionally, the orchestration event engine is further configured to monitor whether the simulation verification subtask is completed, and the quantum chip design center is configured to start the orchestration event engine; and if the simulation verification subtask is monitored to be completed, the performance analysis subtask is sent to the performance analysis blockchain network.
The invention also discloses a quantum chip design method which is applied to a quantum chip design system, wherein the system comprises a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network and a quantum chip design center; the layout design blockchain network, the simulation verification blockchain network and the performance analysis blockchain network are respectively connected with the quantum chip design center; the method comprises the following steps:
creating a quantum chip task through the quantum chip design center, wherein the quantum chip task comprises a layout design subtask, a simulation verification subtask and a performance analysis subtask; the layout design subtask is sent to the layout design block chain network; after the layout design block chain network executes the layout design subtask, the simulation verification subtask is sent to the simulation verification block chain network; after the simulation verification blockchain network executes the simulation verification subtask, the performance analysis subtask is sent to the performance analysis blockchain network;
Executing a layout design intelligent contract according to the layout design subtask through the layout design blockchain network, generating a layout design result and sending the layout design result to the quantum chip design center, wherein the layout design result is bound with the simulation verification subtask;
executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask through the simulation verification blockchain network, generating a simulation verification result and sending the simulation verification result to the quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
performing performance analysis on the simulation verification result according to the performance analysis subtask through the performance analysis blockchain network, generating a performance analysis result and sending the performance analysis result to the quantum chip design center;
and combining and displaying the layout design result, the simulation verification result and the performance analysis result in a preset combination mode through the quantum chip design center.
Optionally, the system further comprises a layout design blockchain adapter, wherein the layout design blockchain adapter is respectively connected with the layout design blockchain network and the quantum chip design center;
The layout design blockchain adapter is used for receiving the layout design subtasks sent by the quantum chip design center and sending the layout design subtasks to the layout design blockchain network.
Optionally, the layout design blockchain adapter includes first channel protocol metadata, and the layout design blockchain adapter is configured to read the first channel protocol and establish communication connection with the layout design blockchain network.
Optionally, the system further comprises a simulated verification blockchain adapter connected with the simulated verification blockchain network and the quantum chip design center, respectively;
the simulation verification blockchain adapter is used for receiving the simulation verification subtask sent by the quantum chip design center and sending the simulation verification subtask to the simulation verification blockchain network.
Optionally, the emulation verification blockchain adapter includes second channel protocol metadata, and the emulation verification blockchain adapter is configured to read the second channel protocol and establish a communication connection with the emulation verification blockchain network.
Optionally, the emulation verification blockchain adapter further includes first format conversion metadata, and the emulation verification blockchain adapter is configured to convert a format of the layout design result into a first format supported by the emulation verification blockchain network, and send the layout design result in the first format to the emulation verification blockchain network.
Optionally, the system further comprises a performance analysis blockchain adapter connected with the performance analysis verification blockchain network and the quantum chip design center, respectively;
the performance analysis blockchain adapter is used for receiving the performance analysis subtasks sent by the quantum chip design center and sending the performance analysis subtasks to the performance analysis blockchain network.
Optionally, the performance analysis blockchain adapter includes third channel protocol metadata, and the performance analysis blockchain adapter is configured to read the third channel protocol to establish a communication connection with the performance blockchain network.
Optionally, the performance analysis blockchain adapter further includes second format conversion metadata, and the performance analysis blockchain adapter is configured to convert a format of the simulation verification result into a second format supported by the performance analysis blockchain network, and send the simulation verification result in the second format to the performance analysis blockchain network.
Optionally, the layout design blockchain network is composed of a plurality of layout design nodes, and the executing, by the layout design blockchain network, the layout design intelligent contract according to the layout design subtask, to generate a layout design result includes:
Performing node consensus according to the idle state and the storage condition of each layout design node through the layout design block chain network to generate a target layout design node; and executing the intelligent contract of the layout design through the layout design node to generate the layout design result.
Optionally, the node consensus is performed according to the idle state and the storage condition of each layout design node through the layout design blockchain network, so as to generate a target layout design node, which comprises the following steps:
detecting idle states of all layout design nodes through the layout design block chain network to generate a plurality of idle layout design nodes; and taking the node with the largest storage space in the plurality of idle layout design nodes as the target layout design node.
Optionally, the simulation verification blockchain network is composed of a plurality of simulation verification nodes, and the simulation verification intelligent contract is executed on the layout design result by the simulation verification blockchain network according to the simulation verification subtask to generate a simulation verification result, which includes:
node consensus is carried out through the simulation verification block chain network according to the idle state and the storage condition of each simulation verification node, and a target simulation verification node is generated; and executing the simulation verification intelligent contract through the simulation verification node to generate a simulation verification result.
Optionally, the step of performing node consensus through the simulation verification blockchain network according to the idle state and the storage condition of each simulation verification node to generate a target simulation verification node includes:
detecting idle states of all simulation verification nodes through the simulation verification blockchain network to generate a plurality of idle simulation verification nodes; and taking the node with the largest storage space in the plurality of idle simulation verification nodes as the target simulation verification node.
Optionally, the performance analysis blockchain network is composed of a plurality of performance analysis nodes, and the performance analysis is performed on the simulation verification result according to the performance analysis subtask through the performance analysis blockchain network to generate a performance analysis result, including:
performing node consensus according to the idle state and the storage condition of each performance analysis node through the performance analysis blockchain network to generate a target performance analysis node; and executing a performance analysis intelligent contract through the target performance analysis node to generate the performance analysis result.
Optionally, the performing node consensus through the performance analysis blockchain network according to the idle state and the storage condition of each performance analysis node to generate a target performance analysis node includes:
Detecting idle states of all the performance analysis nodes through the performance analysis blockchain network to generate a plurality of idle performance analysis nodes; and taking the node with the largest storage space in the plurality of idle performance analysis nodes as the target performance analysis node.
Optionally, after the execution of the layout design subtask by the quantum chip design center through the layout design blockchain network, the sending the simulation verification subtask to the simulation verification blockchain network includes:
starting an event arranging engine through the quantum chip design center, wherein the event arranging engine is used for monitoring whether the layout design subtasks are completed or not; and if the completion of the layout design subtask is monitored, the simulation verification subtask is sent to the simulation verification blockchain network.
Optionally, the orchestration event engine is further configured to monitor whether the simulation verification subtask is completed, and after the simulation verification subtask is executed by the simulation verification blockchain network through the quantum chip design center, send the performance analysis subtask to the performance analysis blockchain network, where the steps include:
Starting the event arranging engine through a quantum chip design center; and if the simulation verification subtask is monitored to be completed, the performance analysis subtask is sent to the performance analysis blockchain network.
The invention also discloses an electronic device, comprising: a processor, a memory, and a computer program stored on the memory and capable of running on the processor, which when executed by the processor, performs the steps of the quantum chip design method as described above.
The invention also discloses a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the steps of the quantum chip design method as described above.
The embodiment of the invention has the following advantages:
the invention can carry out chip layout design, simulation verification and performance optimization on each sub-center block chain network to support the concurrent execution of block chain multi-task block chains by sending the subtasks to the corresponding block chain network, thereby not only establishing a cooperative trust mechanism among each block chain, but also shortening the time of chip design, supporting the concurrent cooperation of multiple tasks, greatly improving the efficiency of chip design and reducing the cost of chip design.
Drawings
FIG. 1 is a block diagram of a quantum chip design system provided by an embodiment of the present invention;
FIG. 2 is a flow chart of steps of a quantum chip design method according to an embodiment of the present invention;
FIG. 3 is a block diagram of an electronic device according to an embodiment of the present invention;
fig. 4 is a block diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Along with development of science and technology, the use scale of quantum chips gradually increases, and the demand of complicated chip design can not be satisfied by single chip design platform, and when carrying out complicated chip design, a plurality of chip design platforms are needed to carry out the design jointly, have improved chip design cost, have reduced chip design efficiency.
One of the core concepts of the embodiment of the invention is that the subtasks are sent to the corresponding blockchain networks to complete the concurrent coordination of the quantum chip sub-center design, the invention can carry out chip layout design, simulation verification and performance optimization on each sub-center blockchain network to support the concurrent execution of blockchain multi-task blockchains, thereby not only establishing a cooperative trust mechanism among each blockchain, but also shortening the time of chip design, supporting the concurrent coordination of multiple tasks, greatly improving the efficiency of chip design and reducing the cost of chip design.
Referring to fig. 1, a block diagram of a quantum chip design system provided by an embodiment of the present invention is shown, where the system includes a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network, and a quantum chip design center.
The quantum chip design center is connected with the layout design blockchain network, the simulation verification blockchain network and the performance analysis blockchain network respectively.
The quantum chip design center is used for creating quantum chip tasks, and the quantum chip tasks comprise a layout design subtask, a simulation verification subtask and a performance analysis subtask; transmitting the subtask of the layout design to a block chain network of the layout design; after the layout design block chain network executes the layout design subtask, sending a simulation verification subtask to the simulation verification block chain network; after the simulation verification sub-task is executed by the simulation verification blockchain network, sending a performance analysis sub-task to the performance analysis blockchain network;
in the embodiment of the invention, a quantum chip design center can create a quantum chip task, and the quantum chip task can comprise a layout design subtask, a simulation verification subtask and a performance analysis subtask, wherein the layout design subtask refers to a layout design intelligent contract for completing a chip, the simulation verification subtask refers to a simulation verification intelligent contract for completing the chip, and the performance analysis subtask refers to a performance analysis intelligent contract for completing the chip.
The layout design block chain network is used for executing a layout design intelligent contract according to the layout design subtask, generating a layout design result and sending the layout design result to the quantum chip design center, wherein the layout design result is bound with the simulation verification subtask;
in the embodiment of the invention, after the layout design block chain network receives the layout design subtask, the layout design intelligent contract can be executed, the layout design result is generated and sent to the quantum chip design center, the quantum chip design center can bind and store the layout design result and the simulation verification subtask, and after the layout design subtask is completed, the layout design result and the simulation verification subtask are sent to the simulation verification block chain network together.
The simulation verification blockchain network is used for executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask, generating a simulation verification result and sending the simulation verification result to the quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
in the embodiment of the invention, after receiving the simulation verification subtask, the simulation verification blockchain network can execute a simulation verification intelligent contract, generate a simulation verification result and send the simulation verification result to the quantum chip design center, and the quantum chip design center can bind and store the simulation verification result and the performance analysis subtask and send the simulation verification result and the performance analysis subtask to the performance analysis blockchain network together after the simulation verification subtask is completed.
The performance analysis blockchain network is used for performing performance analysis on the simulation verification result according to the performance analysis subtask, generating a performance analysis result and sending the performance analysis result to the quantum chip design center;
the quantum chip design center is used for carrying out combination display on the layout design result, the simulation verification result and the performance analysis result according to a preset combination mode.
In the embodiment of the invention, the preset combination mode can be set according to the requirement of a user, and in one example, the preset combination mode is a layout design result and a simulation verification result, and then the quantum chip design center displays the layout design result and the simulation verification result; in another example, the preset combination mode is a layout design result, a simulation verification result and a performance analysis result, and then the quantum chip design center displays the layout design result, the simulation verification result and the performance analysis result.
The invention discloses a quantum chip design system, which can complete the concurrent coordination of quantum chip sub-center design by sending subtasks to corresponding block chain networks.
In one embodiment of the present invention, as shown in fig. 1, the system further comprises a layout design blockchain adapter, the layout design blockchain adapter being connected with the layout design blockchain network and the quantum chip design center, respectively; the layout design block chain adapter is used for receiving the layout design subtasks sent by the quantum chip design center and sending the layout design subtasks to the layout design block chain network.
In one embodiment of the present invention, a layout design blockchain adapter includes first channel protocol metadata, the layout design blockchain adapter is configured to read a first channel protocol to establish a communication connection with a layout design blockchain network.
In the embodiment of the invention, the communication protocols between the quantum chip design center and different blockchain networks are different, and in one example, if the communication protocol between the quantum chip and the layout design blockchain network is a first channel protocol, the first channel protocol metadata define the address and the parameter of the first channel protocol, and the layout design blockchain adapter positioned between the quantum chip design center and the layout design blockchain network can read the first channel protocol, so that communication connection is established with the layout design blockchain network.
In one embodiment of the invention, the system further comprises a simulated verification blockchain adapter connected to the simulated verification blockchain network and the quantum chip design center, respectively; the simulation verification block chain adapter is used for receiving a simulation verification subtask sent by the quantum chip design center and sending the simulation verification subtask to the simulation verification block chain network.
In one embodiment of the invention, the emulated verification blockchain adapter includes second channel protocol metadata, and the emulated verification blockchain adapter is configured to read the second channel protocol to establish a communication connection with the emulated verification blockchain network.
In the embodiment of the invention, the communication protocols between the quantum chip design center and different blockchain networks are different, and in one example, if the communication protocol between the quantum chip and the simulated verification blockchain network is a second channel protocol, the address and the parameters of the second channel protocol are defined by the metadata of the second channel protocol, and the simulated verification blockchain adapter positioned between the quantum chip design center and the simulated verification blockchain network can read the second channel protocol, so that communication connection is established with the simulated verification blockchain network.
In one embodiment of the present invention, the emulation verification blockchain adapter further includes first format conversion metadata, and the emulation verification blockchain adapter is configured to convert a format of the layout design result into a first format supported by the emulation verification blockchain network, and send the layout design result in the first format to the emulation verification blockchain network.
In the embodiment of the invention, the simulation verification blockchain adapter can convert the format of the layout design result, so that the simulation verification blockchain network can identify and verify the layout design result, in one example, the format of the layout design result is an a format, the format supported by the simulation verification blockchain network is a b format, the simulation verification blockchain adapter converts the format of the layout design result into the b format, and then the layout design result in the b format is sent to the simulation verification blockchain network.
In one embodiment of the invention, the system further comprises a performance analysis blockchain adapter, the performance analysis blockchain adapter being connected to the performance analysis verification blockchain network and the quantum chip design center, respectively; the performance analysis blockchain adapter is used for receiving the performance analysis subtasks sent by the quantum chip design center and sending the performance analysis subtasks to the performance analysis blockchain network.
In one embodiment of the invention, the performance analysis blockchain adapter includes third channel protocol metadata, and the performance analysis blockchain adapter is configured to read the third channel protocol to establish a communication connection with the performance blockchain network.
In the embodiment of the invention, the communication protocols between the quantum chip design center and different blockchain networks are different, and in one example, if the communication protocol between the quantum chip and the simulation verification blockchain network is a third channel protocol, the address and the parameters of the third channel protocol are defined by the metadata of the third channel protocol, and the blockchain adapter for performance analysis between the quantum chip design center and the blockchain network for performance analysis can read the third channel protocol, so that communication connection is established with the blockchain network for performance analysis.
In one embodiment of the present invention, the performance analysis blockchain adapter further includes second format conversion metadata, and the performance analysis blockchain adapter is configured to convert a format of the simulation verification result into a second format supported by the performance analysis blockchain network, and send the simulation verification result in the second format to the performance analysis blockchain network.
In the embodiment of the invention, the performance analysis blockchain adapter can convert the format of the simulation verification result, so that the simulation verification blockchain network can identify and verify the simulation verification result, in one example, the format of the simulation verification result is an a format, the format supported by the simulation verification blockchain network is a b format, the performance analysis blockchain adapter converts the format of the simulation verification result into the b format, and then the simulation verification result in the b format is sent to the simulation verification blockchain network.
In one embodiment of the invention, the layout design block chain network consists of a plurality of layout design nodes, and the layout design block chain network is used for carrying out node consensus according to the idle state and the storage condition of each layout design node to generate a target layout design node; and executing the intelligent contracts of the layout design through the layout design nodes to generate a layout design result.
In the embodiment of the invention, the layout design blockchain network consists of a plurality of layout design nodes, and after receiving the subtask of the layout design, the layout design blockchain network can select the nodes with processing capacity meeting the preset condition in the plurality of layout design nodes to execute the intelligent contract of the layout design, so that the efficiency of chip design is improved, and the preset condition can be set according to the requirement of a user and is not limited.
In one embodiment of the present invention, a layout design blockchain network is used to detect an idle state of each layout design node to generate a plurality of idle layout design nodes; and taking the node with the largest storage space in the plurality of idle layout design nodes as a target layout design node.
Specifically, 4 layout design nodes exist in the layout design blockchain network, the layout design blockchain network can detect the idle state of the 4 layout design nodes, if a node and b node exist, the storage space of the a node and the b node is continuously detected, if the storage space of the b node is larger than the storage space of the a node, the b node is determined as a target layout design node, and at the moment, the layout design intelligent contract is completed through the b node, so that the efficiency of chip layout design can be improved.
In one embodiment of the invention, the simulation verification block chain network consists of a plurality of simulation verification nodes, and the simulation verification block chain network is used for carrying out node consensus according to the idle state and the storage condition of each simulation verification node to generate a target simulation verification node; and executing the simulation verification intelligent contract through the simulation verification node to generate a simulation verification result.
In the embodiment of the invention, the simulation verification blockchain network is composed of a plurality of simulation verification nodes, after receiving the simulation verification subtask, the simulation verification blockchain network can select the nodes with processing capacity meeting the preset conditions in the plurality of simulation verification nodes to execute the simulation verification intelligent contract, so that the efficiency of chip simulation verification is improved, and the preset conditions can be set according to the user requirements and are not limited.
In one embodiment of the present invention, a simulated verification blockchain network is used to detect an idle state of each simulated verification node, and generate a plurality of idle simulated verification nodes; and taking the node with the largest storage space in the plurality of idle simulation verification nodes as a target simulation verification node.
Specifically, 5 simulation verification nodes exist in the simulation verification blockchain network, the simulation verification blockchain network can detect idle states of the 5 simulation verification nodes, if c nodes and d nodes exist, the storage spaces of the c nodes and the d nodes are continuously detected, if the storage space of the d nodes is larger than the storage space of the c nodes, the d nodes are determined to be target simulation verification nodes, and at the moment, the simulation verification intelligent contract is completed through the d nodes, so that the efficiency of chip simulation verification can be improved.
In one embodiment of the invention, the performance analysis blockchain network consists of a plurality of performance analysis nodes, and the performance analysis blockchain network is used for carrying out node consensus according to the idle state and the storage condition of each performance analysis node to generate a target performance analysis node; and executing the performance analysis intelligent contract through the target performance analysis node to generate a performance analysis result.
In the embodiment of the invention, the performance analysis blockchain network is composed of a plurality of performance analysis nodes, after receiving the performance analysis subtasks, the performance analysis blockchain network can select the nodes with processing capacity meeting preset conditions in the plurality of performance analysis nodes to execute the performance analysis intelligent contract, so that the efficiency of chip performance analysis is improved, and the preset conditions can be set according to the requirements of users and are not limited.
In one embodiment of the present invention, a performance analysis blockchain network is configured to detect an idle state of each performance analysis node, and generate a plurality of idle performance analysis nodes; and taking the node with the largest storage space in the plurality of idle performance analysis nodes as a target performance analysis node.
Specifically, 5 performance analysis nodes exist in the performance analysis blockchain network, the performance analysis blockchain network can detect the idle state of the 5 performance analysis nodes, if c nodes and d nodes exist, the storage spaces of the c nodes and d nodes are continuously detected, if the storage space of the d nodes is larger than the storage space of the c nodes, the d nodes are determined to be target performance analysis nodes, and at the moment, the performance analysis intelligent contract is completed through the d nodes, so that the efficiency of chip performance analysis can be improved.
In one embodiment of the invention, the quantum chip design center is used for starting an event scheduling engine, and the event scheduling engine is used for monitoring whether the subtasks of the layout design are completed; and if the completion of the layout design subtask is monitored, sending the simulation verification subtask to a simulation verification blockchain network.
In the embodiment of the invention, the quantum chip can start the arranging event engine so as to monitor the completion state of the layout design subtask, if the completion state of the layout design subtask is monitored, the simulation verification subtask can be triggered, and the simulation verification subtask can be sent to the simulation verification blockchain network; if the state of the subtask of the layout design is not completed, the simulation verification subtask is not triggered.
In an embodiment of the present invention, the sequence of triggering of different subtasks may also be set in the orchestration event engine.
In one example, the next subtask triggered after the completion of the layout design subtask may be set as a performance analysis subtask, the next subtask triggered after the completion of the performance analysis subtask is a simulation verification subtask, and the sequential triggering sequence of different subtasks in the orchestration event engine may be set according to the requirements of the user, which is not limited herein.
In one embodiment of the invention, the orchestration event engine is further configured to monitor whether the simulation verification subtask is completed, and the quantum chip design center is configured to start the orchestration event engine; and if the completion of the simulation verification subtask is monitored, sending the performance analysis subtask to the performance analysis blockchain network.
In the embodiment of the invention, the event arranging engine can monitor whether the simulation verification subtask is completed or not, if the condition of the simulation verification subtask is monitored to be completed, the performance analysis subtask can be triggered, and the performance analysis subtask can be sent to the performance analysis blockchain network; and if the state of the simulation verification subtask is monitored to be incomplete, not triggering the performance analysis subtask.
The invention discloses a quantum chip design system, which completes quantum chip sub-center design concurrency coordination by sending subtasks to corresponding block chain networks.
Referring to fig. 2, a flowchart of steps of a quantum chip design method provided by an embodiment of the present invention is shown and applied to a quantum chip design system, where the system includes a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network, and a quantum chip design center; the layout design block chain network, the simulation verification block chain network and the performance analysis block chain network are respectively connected with the quantum chip design center; the method may comprise the sub-steps of:
step 101, a quantum chip task is established through a quantum chip design center, wherein the quantum chip task comprises a layout design subtask, a simulation verification subtask and a performance analysis subtask; transmitting the subtask of the layout design to a block chain network of the layout design; after the layout design block chain network executes the layout design subtask, sending a simulation verification subtask to the simulation verification block chain network; after the simulation verification sub-task is executed by the simulation verification blockchain network, sending a performance analysis sub-task to the performance analysis blockchain network;
step 102, executing a layout design intelligent contract according to a layout design subtask through a layout design block chain network, generating a layout design result and sending the layout design result to a quantum chip design center, wherein the layout design result is bound with a simulation verification subtask;
Step 103, executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask through a simulation verification blockchain network, generating a simulation verification result and sending the simulation verification result to a quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
104, performing performance analysis on the simulation verification result according to the performance analysis subtask through the performance analysis blockchain network, generating a performance analysis result and sending the performance analysis result to a quantum chip design center;
and 105, combining and displaying the layout design result, the simulation verification result and the performance analysis result in a preset combination mode through a quantum chip design center.
The invention discloses a quantum chip design method, which completes quantum chip sub-center design concurrency coordination by sending subtasks to corresponding block chain networks.
In one embodiment of the present invention, the system further comprises a layout design blockchain adapter, the layout design blockchain adapter being connected with the layout design blockchain network and the quantum chip design center, respectively;
the layout design blockchain adapter is used for receiving the layout design subtasks sent by the quantum chip design center and sending the layout design subtasks to the layout design blockchain network.
In one embodiment of the present invention, the layout design blockchain adapter includes first channel protocol metadata, and the layout design blockchain adapter is configured to read the first channel protocol and establish a communication connection with the layout design blockchain network.
In one embodiment of the invention, the system further comprises a simulated verification blockchain adapter connected to the simulated verification blockchain network and the quantum chip design center, respectively;
the simulation verification blockchain adapter is used for receiving the simulation verification subtask sent by the quantum chip design center and sending the simulation verification subtask to the simulation verification blockchain network.
In one embodiment of the present invention, the emulated verification blockchain adapter includes second channel protocol metadata, and the emulated verification blockchain adapter is configured to read the second channel protocol to establish a communication connection with the emulated verification blockchain network.
In one embodiment of the present invention, the emulation verification blockchain adapter further includes first format conversion metadata, and the emulation verification blockchain adapter is configured to convert a format of the layout design result into a first format supported by the emulation verification blockchain network, and send the layout design result in the first format to the emulation verification blockchain network.
In one embodiment of the invention, the system further comprises a performance analysis blockchain adapter connected to the performance analysis verification blockchain network and the quantum chip design center, respectively;
the performance analysis blockchain adapter is used for receiving the performance analysis subtasks sent by the quantum chip design center and sending the performance analysis subtasks to the performance analysis blockchain network.
In one embodiment of the present invention, the performance analysis blockchain adapter includes third channel protocol metadata, and the performance analysis blockchain adapter is configured to read a third channel protocol to establish a communication connection with the performance blockchain network.
In one embodiment of the present invention, the performance analysis blockchain adapter further includes second format conversion metadata, and the performance analysis blockchain adapter is configured to convert a format of the simulation verification result into a second format supported by the performance analysis blockchain network, and send the simulation verification result in the second format to the performance analysis blockchain network.
In one embodiment of the present invention, the layout design blockchain network is composed of a plurality of layout design nodes, and the executing the layout design intelligent contract according to the layout design subtask through the layout design blockchain network generates a layout design result, including:
performing node consensus according to the idle state and the storage condition of each layout design node through the layout design block chain network to generate a target layout design node; and executing the intelligent contract of the layout design through the layout design node to generate the layout design result.
In an embodiment of the present invention, the generating, by the layout design blockchain network, a target layout design node according to node consensus according to an idle state and a storage condition of each layout design node includes:
detecting idle states of all layout design nodes through the layout design block chain network to generate a plurality of idle layout design nodes; and taking the node with the largest storage space in the plurality of idle layout design nodes as the target layout design node.
In one embodiment of the present invention, the simulation verification blockchain network is composed of a plurality of simulation verification nodes, and the executing, by the simulation verification blockchain network, a simulation verification smart contract on the layout design result according to the simulation verification subtask, generates a simulation verification result, including:
Node consensus is carried out through the simulation verification block chain network according to the idle state and the storage condition of each simulation verification node, and a target simulation verification node is generated; and executing the simulation verification intelligent contract through the simulation verification node to generate a simulation verification result.
In an embodiment of the present invention, the generating, by the simulation verification blockchain network, a target simulation verification node according to node consensus according to an idle state and a storage condition of each simulation verification node includes:
detecting idle states of all simulation verification nodes through the simulation verification blockchain network to generate a plurality of idle simulation verification nodes; and taking the node with the largest storage space in the plurality of idle simulation verification nodes as the target simulation verification node.
In one embodiment of the present invention, the performance analysis blockchain network is composed of a plurality of performance analysis nodes, and the performance analysis is performed on the simulation verification result according to the performance analysis subtask by the performance analysis blockchain network to generate a performance analysis result, including:
performing node consensus according to the idle state and the storage condition of each performance analysis node through the performance analysis blockchain network to generate a target performance analysis node; and executing a performance analysis intelligent contract through the target performance analysis node to generate the performance analysis result.
In an embodiment of the present invention, the generating, by the performance analysis blockchain network, a target performance analysis node according to node consensus according to idle states and storage conditions of each performance analysis node includes:
detecting idle states of all the performance analysis nodes through the performance analysis blockchain network to generate a plurality of idle performance analysis nodes; and taking the node with the largest storage space in the plurality of idle performance analysis nodes as the target performance analysis node.
In one embodiment of the present invention, after the execution of the layout design subtask by the quantum chip design center through the layout design blockchain network, the sending the simulation verification subtask to the simulation verification blockchain network includes:
starting an event arranging engine through the quantum chip design center, wherein the event arranging engine is used for monitoring whether the layout design subtasks are completed or not; and if the completion of the layout design subtask is monitored, the simulation verification subtask is sent to the simulation verification blockchain network.
In an embodiment of the present invention, the orchestration event engine is further configured to monitor whether the simulation verification subtask is completed, and send, by the quantum chip design center, the performance analysis subtask to the performance analysis blockchain network after the simulation verification subtask is completed by the execution of the simulation verification blockchain network, where the orchestration event engine includes:
Starting the event arranging engine through a quantum chip design center; and if the simulation verification subtask is monitored to be completed, the performance analysis subtask is sent to the performance analysis blockchain network.
The invention discloses a quantum chip design method, which can arrange quantum chip design cooperative subtasks through a quantum chip design center, bind corresponding quantum chip design blockchain adapters, send the subtasks to corresponding blockchain networks through the corresponding blockchain adapters, and finish quantum chip sub-center design concurrency coordination.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Referring to fig. 3, a block diagram of an electronic device 20 according to an embodiment of the present invention is shown, including:
the processor 201, the memory 202, and the computer program 2021 stored in the memory 202 and capable of running on the processor 201, where the computer program 2021 when executed by the processor 201 implements the respective processes of the above-mentioned GPU monitoring method embodiment of the image processor, and the same technical effects are achieved, so that repetition is avoided and detailed description is omitted herein.
Referring to fig. 4, a block diagram of a computer readable storage medium 30 according to an embodiment of the present invention is shown, where a computer program 301 is stored on the computer readable storage medium 30, and when the computer program 301 is executed by a processor, the processes of the above-mentioned GPU monitoring method embodiment of an image processor are implemented, and the same technical effects can be achieved, so that repetition is avoided and redundant description is omitted.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The system, the method, the electronic device and the storage medium for designing the quantum chip provided by the invention are described in detail, and specific examples are applied to illustrate the principle and the implementation of the invention, and the description of the examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (20)
1. The quantum chip design system is characterized by comprising a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network and a quantum chip design center; the layout design blockchain network, the simulation verification blockchain network and the performance analysis blockchain network are respectively connected with the quantum chip design center;
the quantum chip design center is used for creating quantum chip tasks, and the quantum chip tasks comprise a layout design subtask, a simulation verification subtask and a performance analysis subtask; the layout design subtask is sent to the layout design block chain network; after the layout design block chain network executes the layout design subtask, the simulation verification subtask is sent to the simulation verification block chain network; after the simulation verification blockchain network executes the simulation verification subtask, the performance analysis subtask is sent to the performance analysis blockchain network;
The layout design block chain network is used for executing a layout design intelligent contract according to the layout design subtask, generating a layout design result and sending the layout design result to the quantum chip design center, wherein the layout design result is bound with the simulation verification subtask;
the simulation verification blockchain network is used for executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask, generating a simulation verification result and sending the simulation verification result to the quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
the performance analysis blockchain network is used for performing performance analysis on the simulation verification result according to the performance analysis subtask, generating a performance analysis result and sending the performance analysis result to the quantum chip design center;
the quantum chip design center is used for carrying out combined display on the layout design result, the simulation verification result and the performance analysis result according to a preset combination mode.
2. The system of claim 1, further comprising a layout design blockchain adapter connected to the layout design blockchain network and the quantum chip design center, respectively;
The layout design blockchain adapter is used for receiving the layout design subtasks sent by the quantum chip design center and sending the layout design subtasks to the layout design blockchain network.
3. The system of claim 2, wherein the layout design blockchain adapter includes first channel protocol metadata, the layout design blockchain adapter to read the first channel protocol to establish a communication connection with the layout design blockchain network.
4. The system of claim 1, further comprising a simulated verification blockchain adapter connected to the simulated verification blockchain network and the quantum chip design center, respectively;
the simulation verification blockchain adapter is used for receiving the simulation verification subtask sent by the quantum chip design center and sending the simulation verification subtask to the simulation verification blockchain network.
5. The system of claim 4, wherein the emulated validation blockchain adapter includes second channel protocol metadata, the emulated validation blockchain adapter to read the second channel protocol to establish a communication connection with the emulated validation blockchain network.
6. The system of claim 4, wherein the simulated verification blockchain adapter further comprises first format conversion metadata, the simulated verification blockchain adapter to convert a format of the layout design result to a first format supported by the simulated verification blockchain network and to send the layout design result in the first format to the simulated verification blockchain network.
7. The system of claim 1, further comprising a performance analysis blockchain adapter connected to the performance analysis verification blockchain network and the quantum chip design center, respectively;
the performance analysis blockchain adapter is used for receiving the performance analysis subtasks sent by the quantum chip design center and sending the performance analysis subtasks to the performance analysis blockchain network.
8. The system of claim 7, wherein the performance analysis blockchain adapter includes third channel protocol metadata, the performance analysis blockchain adapter to read the third channel protocol to establish a communication connection with the performance analysis blockchain network.
9. The system of claim 7, wherein the performance analysis blockchain adapter further comprises second format conversion metadata, the performance analysis blockchain adapter to convert the format of the simulated verification result to a second format supported by the performance analysis blockchain network and to send the simulated verification result in the second format to the performance analysis blockchain network.
10. The system according to claim 1, wherein the layout design blockchain network is composed of a plurality of layout design nodes, and the layout design blockchain network is used for performing node consensus according to idle states and storage conditions of each layout design node to generate a target layout design node; and executing the intelligent contract of the layout design through the layout design node to generate the layout design result.
11. The system of claim 10, wherein the layout design blockchain network is configured to detect an idle state of each layout design node to generate a plurality of idle layout design nodes; and taking the node with the largest storage space in the plurality of idle layout design nodes as the target layout design node.
12. The system of claim 1, wherein the simulated verification blockchain network is composed of a plurality of simulated verification nodes, and the simulated verification blockchain network is used for performing node consensus according to the idle state and the storage condition of each simulated verification node to generate a target simulated verification node; and executing the simulation verification intelligent contract through the simulation verification node to generate a simulation verification result.
13. The system of claim 12, wherein the simulated verification blockchain network is configured to detect an idle state of each simulated verification node, generating a plurality of idle simulated verification nodes; and taking the node with the largest storage space in the plurality of idle simulation verification nodes as the target simulation verification node.
14. The system of claim 1, wherein the performance analysis blockchain network is composed of a plurality of performance analysis nodes, and the performance analysis blockchain network is used for performing node consensus according to idle states and storage conditions of each performance analysis node to generate a target performance analysis node; and executing a performance analysis intelligent contract through the target performance analysis node to generate the performance analysis result.
15. The system of claim 14, wherein the performance analysis blockchain network is configured to detect an idle state of each performance analysis node to generate a plurality of idle performance analysis nodes; and taking the node with the largest storage space in the plurality of idle performance analysis nodes as the target performance analysis node.
16. The system of claim 1, wherein the quantum chip design center is configured to start an orchestration event engine configured to monitor whether the layout design subtask is complete; and if the completion of the layout design subtask is monitored, the simulation verification subtask is sent to the simulation verification blockchain network.
17. The system of claim 16, wherein the orchestration event engine is further configured to monitor whether the simulation verification subtask is complete, the quantum chip design center being configured to start the orchestration event engine; and if the simulation verification subtask is monitored to be completed, the performance analysis subtask is sent to the performance analysis blockchain network.
18. The quantum chip design method is characterized by being applied to a quantum chip design system, wherein the system comprises a layout design blockchain network, a simulation verification blockchain network, a performance analysis blockchain network and a quantum chip design center; the layout design blockchain network, the simulation verification blockchain network and the performance analysis blockchain network are respectively connected with the quantum chip design center; the method comprises the following steps:
Creating a quantum chip task through the quantum chip design center, wherein the quantum chip task comprises a layout design subtask, a simulation verification subtask and a performance analysis subtask; the layout design subtask is sent to the layout design block chain network; after the layout design block chain network executes the layout design subtask, the simulation verification subtask is sent to the simulation verification block chain network; after the simulation verification blockchain network executes the simulation verification subtask, the performance analysis subtask is sent to the performance analysis blockchain network;
executing a layout design intelligent contract according to the layout design subtask through the layout design blockchain network, generating a layout design result and sending the layout design result to the quantum chip design center, wherein the layout design result is bound with the simulation verification subtask;
executing a simulation verification intelligent contract on the layout design result according to the simulation verification subtask through the simulation verification blockchain network, generating a simulation verification result and sending the simulation verification result to the quantum chip design center, wherein the simulation verification result is bound with the performance analysis subtask;
Performing performance analysis on the simulation verification result according to the performance analysis subtask through the performance analysis blockchain network, generating a performance analysis result and sending the performance analysis result to the quantum chip design center;
and combining and displaying the layout design result, the simulation verification result and the performance analysis result in a preset combination mode through the quantum chip design center.
19. An electronic device, comprising: a processor, a memory and a computer program stored on the memory and capable of running on the processor, which when executed by the processor performs the steps of the quantum chip design method of claim 18.
20. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the quantum chip design method of claim 18.
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