CN117046735B - Method and system for merging and distributing patterns of multiple chips in wafer - Google Patents
Method and system for merging and distributing patterns of multiple chips in wafer Download PDFInfo
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- CN117046735B CN117046735B CN202311316332.6A CN202311316332A CN117046735B CN 117046735 B CN117046735 B CN 117046735B CN 202311316332 A CN202311316332 A CN 202311316332A CN 117046735 B CN117046735 B CN 117046735B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 51
- 238000001228 spectrum Methods 0.000 claims abstract description 44
- 238000001514 detection method Methods 0.000 claims abstract description 27
- 230000003287 optical effect Effects 0.000 claims abstract description 18
- 238000009954 braiding Methods 0.000 claims abstract description 5
- 238000012216 screening Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 16
- 238000004806 packaging method and process Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000007689 inspection Methods 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Abstract
The invention discloses a method and a system for merging and distributing patterns of various chips in a wafer, which comprises the following steps: s1, performing automatic optical detection scanning and wafer testing on chips in a wafer to obtain a first scanning pattern and a second testing pattern; s2, combining the first scanning spectrum and the second testing spectrum to obtain a first combined spectrum; s3, distributing the first combined map to a printer station, and executing marking operation on chips of all chip categories by the printer station; performing automatic optical detection scanning on the marked chip to obtain a third scanning map; s4, combining the third scanning spectrum and the first combined spectrum to obtain a second combined spectrum; and S5, distributing the second combined spectrum to a sorting machine, and executing sorting operation by the braiding machine according to the second combined spectrum. The method and the system disclosed by the invention save the design cost of the wafer, and realize the requirements of designing or testing various chip types on one wafer, and simultaneously, independently printing and independently sorting and packaging different chip types.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a method and a system for combining and distributing patterns of multiple chips in a wafer.
Background
Wafer level packaging (Wafer Level Packaging, abbreviated as WLP) is an advanced packaging technology, and WLP is a technology that most or all of packaging and testing are directly performed on a whole wafer, and then dicing is performed to produce a single chip. The packaging structure has the advantages of small packaging size, excellent electrical performance, good heat dissipation, high transmission speed, short production period and the like, and is rapidly developed in recent years.
WLP is mostly a Single Die (Single Die) design in mass production mode, and the design diagram is shown in fig. 1, and only one Die class, namely BIN 1, is used. However, in the new product design development stage, to maximize the design space of a wafer, more than 2 circuit designs, such as BIN 1 and BIN 9 shown in fig. 2, are designed in one Reticle (Reticle). Chips designed by bottom (Fab Metal) circuits of different wafer factories are packaged in the same wafer, diced, and printed (Marking) and sorted according to chip types of different circuit designs, so that the purpose of verifying chip types of various designs in one wafer is achieved. Or in the wafer-level test, other test chip types are required to be printed (Marking) and sorted separately besides the main chip types, so that the purpose of maximum utilization of chips is achieved.
These special chiplet-like operating requirements present a significant challenge to current wafer-level packaging mapping systems.
The existing WLP atlas merging is based on Wafer names (Wafer IDs), atlas of different atlas sites are merged and distributed according to the chip coordinates and the unique qualified chips of a defined single chip class, and the atlas of qualified chips of multiple chip classes cannot be automatically merged and distributed at the same time. At present, qualified chip merging for various chip types can only be manually merged for a plurality of times according to a single chip type in sequence. The first scanning pattern refers to a test result pattern after automatic optical inspection scanning (AOI) test, the second testing pattern refers to a test result pattern after wafer test (CP), when the first scanning pattern and the second testing pattern are combined into a first combined pattern, only single chip type can be designated for manual multiple times of combination each time, a plurality of single qualified patterns are produced, and the loading of a plurality of patterns in the same production batch cannot be supported during mass production.
The method has the advantages that labor cost is wasted, the risk of map merging errors is high, mass production of qualified chips in various chip types cannot be realized, and the working efficiency is low.
Disclosure of Invention
The invention aims to overcome the defects, and based on the complex design of multiple chip types of the current client and the sorting requirement of multiple testing BINs, an independent design develops a map system which can simultaneously define the testing qualification requirement of multiple chip types on a wafer and is used for carrying out map merging, distributing printing and distributing sorting automatic processing based on the requirements. The merging system greatly saves the design cost of the wafer, and rapidly and efficiently meets the requirements of designing or testing various BINs on a wafer and simultaneously printing and independently sorting and packaging different chip types.
On one hand, the invention discloses a method for merging and distributing patterns of various chips in a wafer, which comprises the following steps:
s1, performing automatic optical detection scanning on chips in a wafer to obtain a first scanning map containing all chip categories, wherein the number of the chip categories is more than one;
carrying out wafer test on chips in the wafer to obtain a second test pattern containing all chip types;
the first scanning patterns mark all qualified chips in the chip categories as first qualified chips, and unqualified chips are first unqualified chips; the second test patterns mark all qualified chips as second qualified chips, and unqualified chips are second unqualified chips; performing functional classification on the second qualified chips and forming different chip categories;
s2, combining the first scanning spectrum and the second testing spectrum to realize one-time combination of all chip types, and obtaining a first combined spectrum, wherein the first combined spectrum marks qualified chips of all chip types as third qualified chips and unqualified chips as third unqualified chips;
s3, distributing the first combined map to a printer station, and executing marking operation on chips of all chip categories by the printer station; performing automatic optical detection scanning on the marked chip to obtain a third scanning map; the third scanning pattern marks all qualified chips in the chip category as fourth qualified chips, and unqualified chips are fourth unqualified chips;
s4, combining the third scanning spectrum and the first combined spectrum to obtain a second combined spectrum; the second combined map marks all qualified chips in the chip categories as fifth qualified chips, and unqualified chips are fifth unqualified chips;
and S5, distributing the second combined spectrum to a sorting machine, and executing sorting operation by the braiding machine according to the second combined spectrum.
On the other hand, the invention also discloses a system for merging and distributing patterns of various chips in the wafer, which comprises:
the pattern acquisition module is used for acquiring a first scanning pattern after automatic optical detection scanning of chips in the wafer and a second testing pattern after wafer testing;
the chip screening marking module is used for carrying out BIN separation operation on different types of chips in the wafer in the map, screening out qualified chips and unqualified chips in the map and carrying out function classification marking on the qualified chips;
the map processing module is used for combining maps;
and the distribution module is used for distributing the combined atlas to the sorting machine table.
Compared with the prior art, the invention has the beneficial effects that:
the invention can combine and distribute logic through multiple BIN patterns in the single wafer level packaging process, and simultaneously process the combining and distributing operation of qualified chips of various chip types.
Drawings
FIG. 1 is a design drawing of a chip of one type only in a Shan Zhangjing circle described in the background art;
FIG. 2 is a design drawing of a Shan Zhangjing circle with various chips as described in the background art;
FIG. 3 is a first scan pattern of example 1 of the present invention;
FIG. 4 is a second test pattern of example 1 of the present invention;
fig. 5 is a first combined map in example 1 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
In the existing Printed Circuit Board (PCB) manufacturing process, an automatic optical inspection scanning device is responsible for inspecting the quality of the PCB. Wafer testing (CP) is an apparatus for testing electrical properties of a Wafer, which is an essential link in the semiconductor field, between Wafer fabrication and packaging throughout the Chip fabrication process, and is aimed at each Die (Die) in a Wafer (Wafer) in order to ensure that each Die in the Wafer substantially meets the characteristics or design specifications of the device, typically including verification of voltage, current, timing and function. The specific operation of wafer test is to connect the Die pins exposed outside with a test machine through probes after wafer fabrication is completed.
Example 1
The embodiment discloses a pattern merging and distributing method for multiple chips in a wafer, which comprises the following steps:
s1, performing automatic optical detection scanning on chips in a wafer to obtain a first scanning map containing all chip types, wherein the chip types are more than one;
carrying out wafer test on chips in the wafer to obtain a second test pattern containing all chip types;
the first scanning pattern marks all the qualified chips in the chip category as first qualified chips, and the unqualified chips are first unqualified chips; the second test patterns mark all qualified chips as second qualified chips, and unqualified chips are second unqualified chips; performing functional classification on the second qualified chips and forming different chip categories;
the first qualified chip is qualified in defect detection of the chip surface and dirt detection of the wafer surface in automatic optical detection scanning; the first unqualified chip refers to the defect detection of the chip surface or the unqualified dirt detection of the wafer surface in the automatic optical detection scanning; the second qualified chip refers to a chip with qualified electrical performance detection in the wafer test, and the second unqualified chip refers to a chip with unqualified electrical performance detection in the wafer test.
S2, combining the first scanning spectrum and the second testing spectrum, and realizing one-time combination of all chip types to obtain a first combined spectrum, wherein the first combined spectrum marks qualified chips of all chip types as third qualified chips, and unqualified chips are third unqualified chips.
The merging rule of the first scanning spectrum and the second testing spectrum is as follows: the same chip category positions in the two patterns are a first qualified chip and a second qualified chip, and the combined chips are a third qualified chip in the first combined pattern; the same chip type position is the first unqualified chip or the second unqualified chip, and the combined chip is the third unqualified chip in the first combined map.
The first scanning spectrum and the second testing spectrum also respectively comprise an alignment chip and a blank chip, when the first scanning spectrum and the second testing spectrum are combined, the same chip type position is the alignment chip, and after the combination, the alignment chip is also arranged in the first combined spectrum; the same chip category position is a blank chip, and the blank chips are in the first combined map after combination.
S3, distributing the first combined map to a printer station, and executing marking operation on chips of all chip categories by the printer station; performing automatic optical detection scanning on the marked chip to obtain a third scanning map; the third scanning pattern marks all qualified chips in the chip category as fourth qualified chips, and unqualified chips are fourth unqualified chips; the printer station supports each chip type to print different marks;
after the marking operation, the chip needs to be automatically optically detected and scanned so as to prevent the chip from being damaged or damaged in the marking operation process.
S4, combining the third scanning spectrum and the first combined spectrum to obtain a second combined spectrum; the second combined map marks all qualified chips in the chip categories as fifth qualified chips, and unqualified chips are fifth unqualified chips;
the merging rule of the third scanning spectrum and the first merging spectrum is as follows: the same chip category positions are a third qualified chip and a fourth qualified chip, and the third qualified chip and the fourth qualified chip are combined and then are a fifth qualified chip in a second combined map; the same chip category position is a third unqualified chip or a fourth unqualified chip, and the combined chips are fifth unqualified chips in the second combined map.
The third scanning pattern also comprises an alignment chip and a blank chip, when the third scanning pattern is combined with the first combined pattern, the same chip category position is the alignment chip, and after the combination, the alignment chip is also in the second combined pattern; the same chip category position is a blank chip, and the blank chips are in the second combined map after combination.
And S5, distributing the second combined spectrum to a sorting machine, and executing sorting operation by the braiding machine according to the second combined spectrum.
The printer station, the sorting station and the braiding station can select a whole set of equipment in the existing market, such as EO laser marking system-LCSM 3302FC sold by Iou laser technology (Suzhou) limited company, according to the characteristics of the machine station, the printer station is in a map of all chip categories, and the printer station recognizes the map and prints different imprinting contents of a multi-chip category (BIN); the sorting machine is characterized in that different BINs are divided into different patterns, and folder names are used as the distinction.
In this embodiment, fig. 3 is a first scan map of a wafer after automatic optical inspection scanning, and is labeled with a chip category BIN 1 (a portion labeled with numeral 1 in the figure) and a chip category BIN 0 (a portion labeled with numeral 0 in the figure), where BIN 0 is an aligned chip or a blank chip; FIG. 4 is a second test pattern of a wafer after testing, labeled BIN 1 (the portion labeled with numeral 1 in the figure) and BIN 9 (the portion labeled with numeral 0 in the figure); fig. 5 is a first combined pattern formed by combining the patterns of fig. 3 and 4. The merging rule is as follows:
BIN 1+BIN 1=BIN 1；
BIN 1+BIN 9=BIN 9；
BIN 0+BIN 1=BIN 0；
BIN 0+BIN 9=BIN 0。
the rules of the subsequent second combined atlas are similar to those of the first combined atlas, and will not be described herein.
Example 2
The embodiment provides a system for merging and distributing patterns of multiple chips in a wafer, which comprises:
the pattern acquisition module is used for acquiring a first scanning pattern after automatic optical detection scanning of chips in the wafer and a second testing pattern after wafer testing;
the chip screening marking module is used for carrying out BIN separation operation on different types of chips in the wafer in the map, screening out qualified chips and unqualified chips in the map and carrying out function classification marking on the qualified chips;
the map processing module is used for combining maps;
and the distribution module is used for distributing the combined atlas to the sorting machine table.
Those of skill in the art may implement the various illustrative logical blocks, steps, or combinations of both in the present embodiments. To clearly illustrate this interchangeability of hardware and software, various illustrative components (illustrative components), elements, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design requirements of the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation is not to be understood as beyond the scope of the embodiments of the present invention.
The method and the system disclosed by the invention can be used for simultaneously processing the merging and distributing operations of qualified chips required by various clients through the multi-chip class atlas merging and distributing method in the single-chip wafer level packaging process. The merging system greatly saves the design cost of the wafer, and rapidly and efficiently meets the requirements of designing or testing various B chip types on a wafer, and simultaneously, printing and sorting and packaging the different chip types independently.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that other modifications and improvements can be made without departing from the inventive concept of the present invention.
Claims (8)
1. The pattern merging and distributing method for the multiple chips in the wafer is characterized by comprising the following steps of:
s1, performing automatic optical detection scanning on chips in a wafer to obtain a first scanning map containing all chip categories, wherein the number of the chip categories is more than one;
carrying out wafer test on chips in the wafer to obtain a second test pattern containing all chip types;
the first scanning patterns mark all qualified chips in the chip categories as first qualified chips, and unqualified chips are first unqualified chips; the second test patterns mark all qualified chips as second qualified chips, and unqualified chips are second unqualified chips; performing functional classification on the second qualified chips and forming different chip categories;
s2, combining the first scanning spectrum and the second testing spectrum to realize one-time combination of all chip types, and obtaining a first combined spectrum, wherein the first combined spectrum marks qualified chips of all chip types as third qualified chips and unqualified chips as third unqualified chips;
s3, distributing the first combined map to a printer station, and executing marking operation on chips of all chip categories by the printer station; performing automatic optical detection scanning on the marked chip to obtain a third scanning map; the third scanning pattern marks all qualified chips in the chip category as fourth qualified chips, and unqualified chips are fourth unqualified chips;
s4, combining the third scanning spectrum and the first combined spectrum to obtain a second combined spectrum; the second combined map marks all qualified chips in the chip categories as fifth qualified chips, and unqualified chips are fifth unqualified chips;
and S5, distributing the second combined spectrum to a sorting machine, and executing sorting operation by the braiding machine according to the second combined spectrum.
2. The method for merging and distributing patterns of multiple chips in a wafer according to claim 1, wherein the first qualified chip is qualified for both defect detection of the chip surface and dirt detection of the wafer surface in automatic optical detection scanning; the first unqualified chip refers to unqualified defect detection of the chip surface or dirt detection of the wafer surface in automatic optical detection scanning; the second qualified chips refer to chips with qualified electrical performance detection in the wafer test, and the second unqualified chips refer to chips with unqualified electrical performance detection in the wafer test.
3. The method for merging and distributing patterns of multiple chips in a wafer according to claim 2, wherein in step S2, the merging rule of the first scan pattern and the second test pattern is: the same chip category position is a first qualified chip and a second qualified chip, and the combined chips are third qualified chips in a first combined map; the same chip type position is the first unqualified chip or the second unqualified chip, and the combined chips are the third unqualified chip in the first combined map.
4. The method for merging and distributing patterns of multiple chips in a wafer according to claim 3, wherein the first scan pattern and the second test pattern further comprise an alignment chip and a blank chip, respectively, when merging, the same chip type position is the alignment chip, and after merging, the chips are still in the first merged pattern; the same chip category position is a blank chip, and the blank chips are in the first combined map after combination.
5. The method for merging and distributing patterns of multiple chips in a wafer according to claim 4, wherein the merging rule of the third scan pattern and the first merging pattern is as follows: the same chip category positions are a third qualified chip and a fourth qualified chip, and the third qualified chip and the fourth qualified chip are combined and then are a fifth qualified chip in a second combined map; the same chip category position is a third unqualified chip or a fourth unqualified chip, and the combined chips are fifth unqualified chips in the second combined map.
6. The method for merging and distributing patterns of multiple chips in a wafer according to claim 5, wherein the third scan pattern also includes an alignment chip and a blank chip, and when merging with the first merged pattern, the same chip type position is the alignment chip, and after merging, the second merged pattern is also the alignment chip; the same chip category position is a blank chip, and the blank chips are in the second combined map after combination.
7. The method according to claim 6, wherein in step S3, the printer stage supports printing different imprints for each chip type.
8. A pattern merging and distributing system for a plurality of chips in a wafer, applying the method as set forth in any one of claims 1 to 7, comprising:
the pattern acquisition module is used for acquiring a first scanning pattern after automatic optical detection scanning of chips in the wafer and a second testing pattern after wafer testing;
the chip screening marking module is used for carrying out BIN separation operation on different types of chips in the wafer in the map, screening out qualified chips and unqualified chips in the map and carrying out function classification marking on the qualified chips;
the map processing module is used for combining maps;
and the distribution module is used for distributing the combined atlas to the sorting machine table.
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| CN112838017A (en) * | 2019-11-22 | 2021-05-25 | 长鑫存储技术有限公司 | Photoetching pattern detection method and system |
| CN116362166A (en) * | 2023-05-29 | 2023-06-30 | 青岛泰睿思微电子有限公司 | Pattern merging system and method for chip packaging |
-
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- 2023-10-12 CN CN202311316332.6A patent/CN117046735B/en active Active
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| CN102623368A (en) * | 2012-03-31 | 2012-08-01 | 上海集成电路研发中心有限公司 | Wafer defect detection method |
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