CN117042468A - Resistive random access memory and preparation method thereof - Google Patents
Resistive random access memory and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
Abstract
The application provides a resistive random access memory and a preparation method thereof. After the main structure of the resistive random access memory is etched, a gas passivation step is added, so that the side wall of the etched resistive random access part is fully passivated, the defects after etching are reduced, a conductive channel area is limited, the barrier for oxygen vacancy/oxygen ion migration outwards is increased, a uniform and reliable high-low resistance state is provided, and the resistive random access memory device has good uniformity and reliability.
Description
Technical Field
The application relates to the technical field of semiconductor memories, in particular to a resistive random access memory and a preparation method thereof.
Background
The moore's law becomes progressively ineffective and the drawbacks of the traditional computational separation von neumann structure become more and more apparent, and the defects in data handling and computational efficiency become progressively exposed. Recently, with the vigorous development of artificial intelligence and other technologies and the increasing data volume, the market gradually increases the attention of research and development of novel nonvolatile devices. The resistive random access memory (Resistive Random Access Memory, RRAM) is a nonvolatile memory based on the reversible conversion of the resistance of a non-conductive material between a high-resistance state and a low-resistance state under the action of an external electric field. The resistive random access memory has been receiving attention due to its simple structure, fast read/write speed, low cost and CMOS (Complementary Metal Oxide Semiconductor ) process compatibility. Among them, the most commonly used is RRAM based on oxygen vacancy type, at which oxygen vacancy directional migration eventually forms conductive filaments, the device changes from original high resistance to low resistance, this step is called SET (SET), and the setting of the first step often requires a larger operating voltage, called Forming (electrical initialization) step; while the step of reversing from low resistance back to high resistance is called RESET (RESET), often a negative voltage is applied to the same electrode or a forward voltage is applied to the low electrode. Current interest in RRAM remains in reliability, especially whether the oxygen vacancies of the resistive layer are susceptible to outward migration resulting in a change in the retention time.
In order to solve the reliability problem faced by the resistive memory array, the current research is mainly to keep on changing materials or adjusting the thickness of the resistive layer. For example, the mixing ratio of the material of the resistive layer to oxygen is changed (the value of x in AOx is changed) in the process, and various different materials such as (SiOx, hfOx, taOx, VOx, etc.) or thickening the resistive layer are tried, or a coating layer (such as SiNx, etc.) is added around the device, so as to achieve the purpose of improving the holding time. However, the selection of multiple materials causes respective drawbacks, such as a decrease in the state number (most materials can only reach less than 2bit state number), and no significant improvement in the recovery. In addition, such methods tend to introduce additional materials and increase process complexity, involving synergistic optimization of the design between the different materials and intangibly increasing process costs.
Disclosure of Invention
In view of the above problems, an object of the present application is to provide a resistive random access memory and a method for manufacturing the same, in which passivation gas is added to perform passivation confinement after the main structure of the resistive random access memory is etched, so that the sidewall of the etched resistive random access portion is fully oxidized, the sidewall defect after etching is reduced, a conductive channel area is defined, the barrier for oxygen vacancy/oxygen ion migration is increased, and a uniform and reliable high-low resistance state is provided, so that the resistive random access memory device has good uniformity and reliability.
The application provides a resistive random access memory, which comprises a bottom electrode, a resistive random access portion and a top electrode which are arranged in a stacked manner, wherein after the bottom electrode, the resistive random access portion and the top electrode are etched, the etched side wall of the resistive random access portion is processed through passivation gas to form a passivation layer.
The resistance change part comprises a single-layer metal oxide layer or more than two metal oxide layers which are attached together, wherein the single-layer metal oxide layer comprises one metal oxide, and the more than two metal oxide layers comprise the same metal oxide or more than two metal oxides; alternatively, the resistive portion includes an organic material.
The metal oxide includes a fully stoichiometric oxide or a non-stoichiometric oxide.
The application also provides a preparation method of the resistive random access memory, which is used for preparing the resistive random access memory and comprises the following steps:
s1: depositing a first insulating medium layer after the front-end process is finished based on a CMOS (complementary metal oxide semiconductor) process, arranging first interconnection metal in the first insulating medium layer, and depositing a first barrier layer on the first interconnection metal and the upper part of the first insulating medium layer;
s2: forming a first hole in the first barrier layer, and depositing a connecting end of first interconnection metal in the first hole;
s3: sequentially stacking and depositing a bottom electrode layer, a resistance change part layer, a top electrode layer and a protection part layer above the first barrier layer and the connecting end to form a stacked structure, and etching the stacked structure to form the bottom electrode, the resistance change part, the top electrode and the protection part which are stacked;
s4: introducing passivation gas, wherein the passivation gas reacts with the side wall of the resistance change part, and forming the passivation layer on the side wall of the resistance change part;
s5: depositing a second barrier layer on the bottom electrode, the resistive part, the top electrode, the periphery of the protective part and the upper part of the first barrier layer, and depositing a second insulating dielectric layer on the upper part of the second barrier layer;
s6: and forming a second hole in the second insulating dielectric layer and the second barrier layer, and depositing second interconnection metal in the second hole.
The passivation gas includes an oxidizing gas, a reducing gas, and an inert gas.
And etching the laminated structure into the bottom electrode, the resistive part, the top electrode and the protection part which are laminated by a photoetching technology.
And the way of introducing the passivation gas to perform passivation reaction with the side wall of the resistance change part comprises an annealing process or a plasma enhancement process.
The resistance change part comprises a single layer of material or more than two layers of materials, wherein,
the single layer of material comprises AlOx, hfOx, taOx, zrOx, siOx, VO x A material selected from the group consisting of MnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx, and organic materials, the material comprising a stoichiometric and non-stoichiometric composition of the material;
each of the two or more layers of material includes AlOx, hfOx, taOx, zrOx, siOx, VO x The same material in the organic materials, namely, mnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx and the like, wherein each layer is ordered according to chemical proportion to form the resistance change part;
each of the two or more layers of material comprises a different material.
The first interconnection metal and the second interconnection metal each comprise copper, the first barrier layer and the second barrier layer each comprise a silicon carbide film, the protection part layer comprises metal, metal nitride or conductive metal oxide, and the bottom electrode and the top electrode each comprise metal, metal nitride or conductive metal oxide.
The first holes are formed by adopting a photoetching technology, and the second holes are formed by adopting a dual damascene process.
According to the resistive random access memory and the preparation method thereof, after the bottom electrode, the resistive random access part and the top electrode are etched, passivation gas is introduced to fully passivate the side wall of the etched resistive random access part again, a passivation layer with higher passivation degree is formed on the side wall, the side wall etching defect is optimized, and ion movement is limited. The application adopts the gas material compatible with the back-end process under the condition of extremely low additional process cost, increases the energy barrier of ion migration at the side wall, reduces the oxygen vacancy/oxygen ion migration probability, optimizes the reliability of the resistive random access memory, provides uniform and reliable high-low resistance states, ensures that the resistive random access memory has good uniformity and reliability, and has important significance for improving the integration density of the array of the cross structure of the resistive random access memory and producing the array on a large scale.
To the accomplishment of the foregoing and related ends, one or more aspects of the application comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the application. These aspects are indicative, however, of but a few of the various ways in which the principles of the application may be employed. Furthermore, the application is intended to include all such aspects and their equivalents.
Drawings
Other objects and results of the present application will become more apparent and readily appreciated by reference to the following description and claims in conjunction with the accompanying drawings and a more complete understanding of the application. In the drawings:
fig. 1 is a schematic diagram of a resistive random access memory according to embodiment 1 of the present application;
FIG. 2 is a flowchart of a method for manufacturing a resistive random access memory according to embodiment 2 of the present application;
fig. 3 is a schematic structural diagram of the embodiment 2 according to the present application after step S1;
fig. 4 is a schematic structural diagram of the embodiment 2 according to the present application after step S2;
FIG. 5 is a schematic diagram showing the structure of the device after step S3-1 according to embodiment 2 of the present application;
FIG. 6 is a schematic diagram of the structure after step S3-2 according to embodiment 2 of the present application;
fig. 7 is a schematic structural diagram of the embodiment 2 according to the present application after step S4;
fig. 8 is a schematic structural diagram of the embodiment 2 according to the present application after step S5;
fig. 9 is a schematic structural diagram after step S6 according to embodiment 2 of the present application;
the semiconductor device comprises a 1-bottom electrode, a 2-resistive part, a 3-top electrode, 4-passivation gas, a 5-passivation layer, a 6-first insulating dielectric layer, 7-first interconnection metal, an 8-first barrier layer, a 9-connection end, a 10-bottom electrode layer, a 11-resistive part layer, a 12-top electrode layer, a 13-protection part layer, a 14-protection part, a 15-second barrier layer, a 16-second insulating dielectric layer and a 17-second interconnection metal.
The same reference numerals will be used throughout the drawings to refer to similar or corresponding features or functions.
Detailed Description
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that such embodiment(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments
The application is capable of various modifications and embodiments, and particular embodiments are illustrated in the drawings and described herein. However, the present application is not limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present application.
Ordinal terms such as first, second, etc., are used to describe various elements and are not limited to the terms. The terms are used only to distinguish one component from another. For example, a second component may be named a first component, and similarly, a first component may be named a second component without departing from the scope of the claims of the present application. The term and/or includes a combination of a plurality of associated recorded items or any one of a plurality of associated recorded items.
It should be understood that when reference is made to a component being "connected" or "in contact with" another component, this includes not only the case where it is directly connected or in contact with the other component, but also the case where the other component is present in the middle. Conversely, when it is referred to that a certain component is "directly connected" or "directly contacted" with another component, it is understood that the other component is not present in the middle thereof.
In the description of the embodiment, when it is described that a certain component is formed "on (above) or under (below) (on or under)" another component, the arrangement of the other component including two components in direct contact with each other or at least one of the components is included between the two components. When the expression "upper" or "lower" is used, it may include not only the upper direction but also the lower direction with reference to a certain component.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The expression in the singular includes the expression in the plural unless the context clearly indicates otherwise. In the present application, it should be understood that the terms "comprises" or "comprising," etc. are used to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art, including technical or scientific terms. The terms defined in the dictionary generally used should be interpreted in accordance with the meanings possessed by the text of the related art, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application.
In order to more clearly explain the technical scheme of the application, the following is a simple explanation of some technical terms related to the application.
Specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Example 1
Fig. 1 is a schematic diagram of a resistive random access memory according to embodiment 1 of the present application;
as shown in fig. 1, the resistive random access memory provided in this embodiment is an oxygen vacancy type resistive random access memory, and can make oxygen vacancies stably and reliably generated in an insulating resistive random access layer, form a conductive channel to connect two electrodes, and make the resistive state turn over stably and reliably, so as to improve the storage property of the device.
The resistive random access memory comprises a bottom electrode 1, a resistive random access part 2 and a top electrode 3 which are arranged in a stacked mode, wherein after the bottom electrode 1, the resistive random access part 2 and the top electrode 3 are etched, the etched side wall of the resistive random access part 2 is processed through passivation gas, and a passivation layer 5 is formed.
In the manufacturing process of the resistive random access memory, the bottom electrode layer, the resistive random access part layer and the top electrode layer are deposited layer by layer, after a protective layer is deposited on the upper part of the top electrode layer, the shapes of the bottom electrode 1, the resistive random access part 2 and the top electrode 3 are manufactured through an etching process, after etching, the outer layers of the side walls of the bottom electrode 1, the resistive random access part 2 and the top electrode 3 are damaged, the oxidation interface of the side wall of the resistive random access part 2 generates defects, and oxygen vacancies/oxygen ions can migrate outwards. At this time, passivating gas is introduced to enable a new thin oxide interface to be formed on one circle of the side wall of the etched resistance change part 2, the passivation layer 5 with higher oxidation degree is high in barrier height, the outward movement of ions is limited, the generation of oxygen vacancies is facilitated, and the conductive channel is formed more stably and reliably.
The passivation gas includes oxidizing gas, reducing gas, inert gas, etc., specifically including but not limited to N 2 O、O 2 、N 2 Or NH 3 Etc. Process for oxidation treatment of side wall by passivation gasIncluding but not limited to plasma treating the gas-entraining atmosphere, annealing the gas-entraining atmosphere.
The resistive random access memory structure is a metal layer-insulator layer-metal layer structure or a metal layer-semiconductor layer-metal layer structure, the bottom electrode 1 and the top electrode 3 are metal layers, and the resistive random access portion 2 is an insulator layer or a semiconductor layer. Wherein, any metal layer, insulating layer or semiconductor layer can be formed into a single-layer or multi-layer heterojunction structure by single material components of the same material, can be formed into a multi-layer structure by different material components of the same material, can be formed into a single-layer or multi-layer structure by single material components of different materials, and can be formed into a multi-layer structure by different material components of different materials.
The bottom electrode 1 and the top electrode 3 may be made of an active material or an inert material, and may include a metal (Ti, al, au, W, cu, ta, hf, pt, ir, ru, pd, co, ni, etc.), or a metal nitride (TiN, taN, alN), or a conductive metal oxide (IrO) x 、RuO x 、SrO x ) And the like, wherein one or any two or more than two of the materials form a level.
In this embodiment, the material of the resistive portion 2 may be a metal oxide or an organic material.
If the material of the resistive portion 2 is metal oxide, the thickness may be 1nm to 100nm, and the resistive portion may include a single metal oxide layer or two or more metal oxide layers bonded together. The single metal oxide layer may comprise a metal oxide. The two or more metal oxide layers include the same metal oxide or include two or more metal oxides. The two metal oxide layers may each comprise one metal oxide, and the two or more metal oxide layers may comprise any two or more materials.
The metal oxide is a fully stoichiometric oxide or a non-stoichiometric oxide.
The metal oxide may be TaO x 、HfO x 、SiO x 、AlO x 、VO x 、NbO x 、MgO、TiO x 、CuO x 、ZrO x 、ZnO x Or SrTiO x And the like.
As the resistive portion 2, a metal oxide is prepared by PVD (Physical Vapor Deposition ) or ALD (Atomic layer deposition, atomic layer deposition).
If the material of the resistance change part 2 is organic material, the thickness is 10nm-500nm; parylene may be used. The organic material is prepared as a resistance change layer by adopting a CVD (ChemicalVapor Deposition ) method. And adding corresponding thin film post-treatment procedures such as an annealing process and the like according to the material properties.
The resistive random access memory in the embodiment can be used for introducing passivation gas at proper time in the CMOS production process, the side walls of the bottom electrode 1, the resistive random access part 2, the top electrode 3 and the like are further optimized in a full contact mode, the high-concentration passivation gas is used for promoting full passivation of the side walls, the reliability of the device is further improved, and the resistive random access memory with high reliability is realized.
Example 2
FIG. 2 is a flowchart of a method for manufacturing a resistive random access memory according to embodiment 2 of the present application;
as shown in fig. 2, the method for manufacturing the resistive random access memory according to the embodiment is used for manufacturing the resistive random access memory according to the embodiment 1, and includes the following steps:
s1: based on the CMOS process, after the front-end process is finished, a first insulating dielectric layer 6 is deposited, a first interconnection metal 7 is arranged in the first insulating dielectric layer 6, and a first barrier layer 8 is deposited on the first interconnection metal 7 and the upper part of the first insulating dielectric layer 6. The structure after step S1 is shown in fig. 3.
The substrate may be a silicon substrate or a glass substrate. After the front-end process is finished, a flat first insulating dielectric layer 6 is deposited above the transistor, a first interconnection metal 7 pattern is defined on the first insulating dielectric layer 6, and deposition holes of the first interconnection metal 7 are engraved at corresponding positions in the first insulating dielectric layer 6 according to the pattern. A first interconnect metal 7 is deposited in the deposition hole, and then a first barrier layer 8 is deposited over the first insulating dielectric layer 6 and the first interconnect metal 7, the thickness of the first barrier layer 8 may be 5nm to 500nm, and the first barrier layer 8 may be a silicon carbide film. The first interconnect metal 7 may be copper.
S2: a first hole is provided in the first barrier layer 8, and a connection terminal 9 of the first interconnect metal 7 is deposited in the first hole. The structure after step S2 is shown in fig. 4.
The first hole is opened in the upper part of the first barrier layer 8 using photolithographic techniques. The same material as the first interconnect metal 7 is deposited in the first hole as a connection terminal 9 of the first interconnect metal 7 for connection to the bottom electrode 1. The connection terminals 9 are deposited by PVD process.
S3: a bottom electrode layer 10, a resistive part layer 11, a top electrode layer 12 and a protective part layer 13 are sequentially laminated and deposited over the first barrier layer 8 and the connection terminal 9 to form a laminated structure, and the laminated structure is etched to form a bottom electrode 1, a resistive part 2, a top electrode 3 and a protective part 14 which are laminated and arranged.
Step S3 may be divided into two steps S3-1 and S3-2.
S3-1, sequentially stacking and depositing a bottom electrode layer 10, a resistance change part layer 11, a top electrode layer 12 and a protection part layer 13 above the first barrier layer 8 and the connection end 9 to form a stacked structure. The structure after step S3-1 is shown in FIG. 5.
A planar bottom electrode layer 10 is deposited over the first barrier layer 8 and the connection terminals 9, a planar resistive switching layer 11 is deposited over the bottom electrode layer 10, a top electrode layer 12 is deposited planar over the resistive switching layer 11, and a planar protective layer 13 is deposited over the top electrode layer 12. In this embodiment, the thicknesses of the bottom electrode layer 10 and the top electrode layer 12 may be 5nm-400nm, and the material may be TiN; the protective layer 13 is made of TaN; the resistive switching layer 11 comprises Ta bonded together 2 O 5 Layers, taOx layer and TaOy layer, or TaOy layer, taOx layer and Ta laminated together 2 O 5 The thickness of the resistive part layer 11 can be 1nm to 300nm; the layers were deposited by PVD.
S3-2, etching the heterogeneous laminated structure to form a laminated bottom electrode 1, a resistive part 2, a top electrode 3 and a protection part 14.
Patterning the laminated structure by using a photolithography technique, and etching the laminated structure into the bottom electrode 1, the resistive part 2, the top electrode 3 and the protection part 14 which are arranged above the connection end 9 by using the photolithography technique to form a main structure of the resistive random access memory. The structure after step S3-2 is shown in FIG. 6.
The resistive portion 2 may also be a single layer material or more than two layers of material, wherein the single layer material comprises AlOx, hfOx, taOx, zrOx, siOx, VO x One of the materials, mnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx or organic materials, the material comprising the stoichiometric and non-stoichiometric components of the material; each of the two or more layers of material includes AlOx, hfOx, taOx, zrOx, siOx, VO x The same materials in the organic materials, such as MnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx and the like, each layer is ordered according to chemical proportion to form a resistance change part; each of the two or more layers of material comprises a different material.
The guard layer may also include a metal (W, cu, al, ta, hf, ti, pt, ir, ru, pd, etc.) or a metal nitride (TiN, taN, alN) or a conductive metal oxide (IrO, ruO, srTiO).
S4: and introducing passivation gas 4 to perform passivation limiting, wherein the passivation gas 4 reacts with the side wall of the resistance change part 2, and a new thin passivation layer 5 is formed on the side wall of the resistance change part 2. The structure after step S4 is shown in fig. 7.
The oxidation interface of the side wall of the resistance change part 2 is damaged after etching, and passivation gas 4 is introduced into the side wall of the resistance change part 2 by adopting an annealing process or a plasma enhancement mode to react with the side wall of the resistance change part 2. In this embodiment, the passivation gas 4 may be N 2 O，N 2 O is fully contacted with the side wall of the etched resistance change part 2, the barrier height of the side wall of the resistance change layer is improved, and a new thin passivation layer Ta is obviously formed around the side wall 2 O x (x is more than or equal to 4-5, and the oxidation degree is higher).
S5: a second barrier layer 15 is deposited over the bottom electrode 1, the resistive portion 2, the top electrode 3, the periphery of the guard portion 14 and the first barrier layer 8, and a second insulating dielectric layer 16 is deposited over the second barrier layer 15. The structure after step S5 is shown in fig. 8.
The second barrier layer 15 may comprise a silicon carbide film with a thickness of 1nm-100nm, and the second barrier layer 15 covers the first barrier layer 8 and the periphery of the bottom electrode 1, the resistive switching element 2, the top electrode 3, and the protective element 14 to protect the main structure of the resistive switching memory. A second insulating dielectric layer 16 is deposited flat to completely cover the second barrier layer 15.
S6: a second hole is opened in the second insulating dielectric layer 16, the second barrier layer 15, and a second interconnect metal 17 is deposited in the second hole. The structure after step S6 is shown in fig. 9.
A second hole is formed in the lamination of the second insulating dielectric layer 16 and the second barrier layer 15 by adopting a dual damascene process, and Cu is filled in the second hole to serve as a second interconnection metal 17.
In this embodiment, after each layer is deposited, a CMP (Chemical Mechanical Polishing ) process is used to planarize the layer.
The resistive random access memory and the method of manufacturing the same according to the present application are described above by way of example with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that various modifications may be made to the resistive random access memory and the method of manufacturing the same as set forth in the present application above without departing from the spirit of the present application. Accordingly, the scope of the application should be determined from the following claims.
Claims (10)
1. A resistive random access memory is characterized by comprising a bottom electrode, a resistive random access part and a top electrode, wherein,
and after the bottom electrode, the resistance changing part and the top electrode are etched, the etched side wall of the resistance changing part is subjected to passivation limiting through passivation gas to form a passivation layer.
2. The resistive random access memory of claim 1, wherein the resistive portion comprises a single metal oxide layer or two or more metal oxide layers bonded together, the single metal oxide layer comprising one metal oxide, the two or more metal oxide layers comprising the same metal oxide, or comprising two or more metal oxide heterojunctions;
alternatively, the resistive portion includes an organic material.
3. The resistive-switching memory of claim 2, wherein the metal oxide comprises a fully stoichiometric oxide or a non-stoichiometric oxide.
4. A method for manufacturing a resistive random access memory according to any one of claims 1-3, comprising the steps of:
s1: depositing a first insulating medium layer after the front-end process is finished based on a CMOS (complementary metal oxide semiconductor) process, arranging first interconnection metal in the first insulating medium layer, and depositing a first barrier layer on the first interconnection metal and the upper part of the first insulating medium layer;
s2: forming a first hole in the first barrier layer, and depositing a connecting end of first interconnection metal in the first hole;
s3: sequentially stacking and depositing a bottom electrode layer, a resistance change part layer, a top electrode layer and a protection part layer above the first barrier layer and the connecting end to form a stacked structure heterojunction, and etching the stacked structure to form a bottom electrode, a resistance change part, a top electrode and a protection part which are stacked;
s4: introducing passivation gas, wherein the passivation gas enables the side wall of the resistance change part to generate passivation limit reaction, and the passivation layer is formed on the side wall of the resistance change part;
s5: depositing a second barrier layer on the bottom electrode, the resistive part, the top electrode, the periphery of the protective part and the upper part of the first barrier layer, and depositing a second insulating dielectric layer on the upper part of the second barrier layer;
s6: and forming a second hole in the second insulating dielectric layer and the second barrier layer, and depositing second interconnection metal in the second hole.
5. The method of manufacturing a resistive random access memory according to claim 4, wherein the passivation gas comprises an oxidizing gas, a reducing gas, and an inert gas.
6. The method of manufacturing a resistive random access memory according to claim 4, wherein the stacked structure of the hetero integration is etched into the bottom electrode, the resistive portion, the top electrode, and the protective portion which are stacked by a photolithography technique.
7. The method of claim 4, wherein the passivating gas is introduced to passivate the sidewall of the resistive portion to remove sidewall defects and define conductive channel regions, including an annealing process or a plasma enhanced process.
8. The method of manufacturing a resistive random access memory according to claim 4, wherein the resistive portion comprises a single layer of material or more than two layers of material, wherein,
the single layer of material comprises AlOx, hfOx, taOx, zrOx, siOx, VO x A material selected from the group consisting of MnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx, and organic materials, the material comprising a stoichiometric and non-stoichiometric composition of the material;
each of the two or more layers of material includes AlOx, hfOx, taOx, zrOx, siOx, VO x The same materials in the organic materials, such as MnOx, tiOx, cuOx, znOx, WOx, agOx, srTiOx, caTiOx, and the like, each layer is ordered according to chemical proportion to form the resistance change part,
or each of the two or more layers of material may comprise a different material to form a heterojunction.
9. The method of manufacturing a resistive random access memory according to claim 4, wherein the first interconnect metal and the second interconnect metal each comprise copper, the first barrier layer and the second barrier layer each comprise a silicon carbide film, the guard portion layer comprises a metal or a metal nitride or a conductive metal oxide, and the bottom electrode and the top electrode each comprise a metal or a metal nitride or a conductive metal oxide.
10. The method of manufacturing a resistive random access memory according to claim 4, wherein the first hole is formed by a photolithography technique and the second hole is formed by a dual damascene process.
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