CN117038648B - Semiconductor chip set structure and manufacturing method - Google Patents
Semiconductor chip set structure and manufacturing method Download PDFInfo
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- CN117038648B CN117038648B CN202311291675.1A CN202311291675A CN117038648B CN 117038648 B CN117038648 B CN 117038648B CN 202311291675 A CN202311291675 A CN 202311291675A CN 117038648 B CN117038648 B CN 117038648B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 227
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000001681 protective effect Effects 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 61
- 230000002209 hydrophobic effect Effects 0.000 claims description 33
- 238000005452 bending Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 13
- 238000009434 installation Methods 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 13
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 13
- 230000017525 heat dissipation Effects 0.000 description 9
- 238000012545 processing Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000005871 repellent Substances 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 230000013011 mating Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000002940 repellent Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The utility model provides a semiconductor chip group structure and a manufacturing method, which relate to the technical field of semiconductors and have the technical scheme that: the semiconductor device comprises a semiconductor chip and a protective structure arranged outside the semiconductor chip; the signal input and output ends of the semiconductor chip are arranged on the side face; the protective structure at least comprises an electrostatic shielding layer, wherein the electrostatic shielding layer surrounds the semiconductor chip, is in direct contact with the semiconductor chip, and is provided with at least an opening corresponding to the signal input and output end; further comprises: the semiconductor chip is placed in the mounting groove together with the protection structure, and the signal input and output ends correspond to the wiring channels. The semiconductor chip set structure and the manufacturing method provided by the utility model have the advantage of high stability.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a semiconductor chip set structure and a manufacturing method thereof.
Background
In recent years, the development of chips and the preparation technology of circuits have been greatly advanced, and the chips in the semiconductor field have the characteristics of small surface area, small thickness, high pin count density, low thermal impedance, excellent electrical performance and the like, and can better meet the requirements of customers on signal transmission and signal processing in the use process.
However, in designing a semiconductor chip integrated package, it is necessary to consider that in actual use, different environments may have different effects on the semiconductor chips during the process of collecting and processing related signals, especially the humidity change in the environment and the related effects of static electricity generated by friction on the semiconductor chips.
For the above problems, a solution is needed.
Disclosure of Invention
The utility model aims to provide a semiconductor chip set structure and a manufacturing method thereof, which have the advantage of high stability.
In a first aspect, the present utility model provides a semiconductor chipset structure, which has the following technical scheme:
the semiconductor device comprises a semiconductor chip and a protective structure arranged outside the semiconductor chip;
the signal input and output ends of the semiconductor chip are arranged on the side face;
the protective structure at least comprises an electrostatic shielding layer, wherein the electrostatic shielding layer surrounds the semiconductor chip, is in direct contact with the semiconductor chip, and is provided with at least an opening corresponding to the signal input and output end;
further comprises:
the semiconductor chip is placed in the mounting groove together with the protection structure, and the signal input and output ends correspond to the wiring channels.
The semiconductor chip is provided with a plurality of mounting grooves, the semiconductor chip and a protective structure are arranged on the semiconductor chip, the semiconductor chip is connected with the electrostatic shielding layer, and the semiconductor chip is connected with the external wiring.
Further, in the utility model, the electrostatic shielding layer comprises a metal strip which is in annular sealing, the metal strip is in bending arrangement, the metal strip in bending arrangement comprises a first turning area positioned at the inner side and a second turning area positioned at the outer side, the first turning area is used for being in direct contact with the semiconductor chip, and the second turning area is provided with a first mounting structure.
The electrostatic shielding layer is formed by adopting the annular closed metal strip, the metal strip is bent, the contact area between the bent metal strip and air can be increased, a small cavity can be formed between the metal strip and the semiconductor chip, the contact area between the metal strip and air can be increased, the heat dissipation effect can be improved, the mobility of air can be improved, and the heat dissipation effect can be improved.
Further, in the present utility model, the protective structure further includes a hydrophobic layer disposed on an outer layer of the electrostatic shielding layer and correspondingly covering the upper layer and the lower layer of the semiconductor chip, the hydrophobic layer includes a structural support portion, a hydrophobic film disposed on an outer side of the structural support portion, and a second mounting structure disposed on an inner side of the structural support portion, and the second mounting structure is correspondingly connected to the first mounting structure.
Through the arrangement, the waterproof effect can be achieved.
Further, in the utility model, the metal strip comprises an upper branch strip, a lower branch strip, a left branch strip and a right branch strip, wherein the upper branch strip, the right branch strip, the lower branch strip and the left branch strip are all bent and connected end to end in sequence.
Further, in the present utility model, the upper branch, the right branch, the lower branch, and the left branch are each formed by connecting a plurality of first bending portions and second bending portions alternately in order in a posture inclined by 45 °.
Further, in the utility model, the middle area of the outer side surface of the first bending part is provided with a first groove which is concave inwards, the middle area of the outer side surface of the second bending part is provided with a second groove which is concave inwards, and the first groove and the second groove are communicated with each other.
Further, in the present utility model, the first mounting structure is a circular mounting bar extending from one side of the metal bar to the other side, the mounting bar spans the first groove and the second groove, and the second mounting structure is a clamping groove matched with the mounting bar.
In a second aspect, the present utility model further provides a method for manufacturing a semiconductor chipset structure, which is used for manufacturing the semiconductor chipset structure, including:
acquiring a functional requirement;
selecting the types and the number of the semiconductor chips according to the functional requirements, and determining the installation position of each semiconductor chip on the interconnection main body and the corresponding connection relation;
selecting a corresponding electrostatic shielding layer according to the size of each semiconductor chip, and surrounding the electrostatic shielding layer on the semiconductor chip to be in direct contact with the semiconductor chip;
setting wires in the wiring channels of the interconnection body according to the mounting positions and the connection relation;
and placing each semiconductor chip together with the electrostatic shielding layer in the corresponding mounting groove of the interconnection main body according to the mounting position, and connecting the semiconductor chip with the lead.
Further, in the present utility model, the electrostatic shielding layer is a metal strip with a ring shape and closed, the metal strip includes an upper branch strip, a lower branch strip, a left branch strip, and a right branch strip, and the step of surrounding the electrostatic shielding layer on the semiconductor chip includes:
selecting the upper branch, the lower branch, the left branch and the right branch with corresponding sizes and the number of the upper branch, the lower branch, the left branch and the right branch according to the sizes of the semiconductor chips;
the upper branch strip is arranged on the upper surface of the semiconductor chip, the lower branch strip is arranged on the lower surface of the semiconductor chip, the upper branch strip and the lower branch strip are respectively contacted with the outer surface of the semiconductor chip, and the left branch strip and the right branch strip are arranged on the side surface of the semiconductor chip and correspondingly connected with the upper branch strip and the lower branch strip so as to complete the surrounding of the semiconductor chip.
Further, in the present utility model, the upper branch and the lower branch are provided with first mounting structures, and the method further includes:
after the upper branch strip and the lower branch strip are arranged, a hydrophobic layer is arranged on the first mounting structure according to the distribution of the upper branch strip and the lower branch strip.
As can be seen from the above, the semiconductor chip set structure and the manufacturing method thereof provided by the utility model have the advantages that the signal input/output ends of the semiconductor chips are arranged on the side surfaces, the electrostatic shielding layer is surrounded on the semiconductor chips, the electrostatic shielding layer is in direct contact with the semiconductor chips, the corresponding openings are arranged on the side surfaces of the semiconductor chips, the semiconductor chips and the external wiring can be realized, the electrostatic shielding layer is surrounded on the semiconductor chips, the influences of static electricity generated in the air on the semiconductor chips in the data acquisition and processing process can be isolated, in addition, the interconnection main body is arranged on the basis, the interconnection main body is provided with the plurality of mounting grooves which can accommodate the semiconductor chips and the protection structure, and the wiring channels are arranged in the interconnection main body, so that the semiconductor chips arranged in the mounting grooves are mutually communicated, and the plurality of semiconductor chips can cooperatively work, thereby improving the working efficiency.
Drawings
Fig. 1 is a schematic diagram of a semiconductor chipset structure according to the present utility model.
Fig. 2 is a schematic structural diagram of an interconnect body provided by the present utility model.
Fig. 3 is a schematic diagram of a semiconductor chipset structure according to the present utility model.
Fig. 4 is a schematic diagram illustrating a portion of a semiconductor chipset structure according to the present utility model.
Fig. 5 is a schematic structural view of a metal strip according to the present utility model.
Fig. 6 is a schematic diagram of a semiconductor chipset structure according to the present utility model.
Fig. 7 is a schematic diagram of a semiconductor chipset structure according to the present utility model.
Fig. 8 is a flowchart of a method for manufacturing a semiconductor chipset according to the present utility model.
In the figure: 100. a semiconductor chip; 200. a protective structure; 300. an interconnect body; 210. an electrostatic shielding layer; 220. a hydrophobic layer; 211. a supporting strip is arranged; 212. a lower branch; 213. a left branch; 214. a right branch; 215. a first turning region; 216. a second turning region; 217. a first mounting structure; 218. a first bending part; 219. a second bending part; 2110. a first groove; 2111. a second groove; 2112. a limit part; 2113. a mating region; 2114. a clamping part; 221. a structural support; 222. a hydrophobic film; 223. a second mounting structure; 310. and a mounting groove.
Detailed Description
The following description of the embodiments of the present utility model will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the utility model are shown. The components of the present utility model, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present utility model.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present utility model, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In the design and production process of semiconductors, the performance of the semiconductor chips is usually required to be tested, the semiconductor chips are generally exposed in the external environment for the convenience of disassembly and assembly in the test process, and the cooperative performance among a plurality of semiconductor chips can be tested according to requirements.
Therefore, it is necessary to take corresponding antistatic measures for the semiconductor chip, and in general, in the prior art, the whole circuit board is placed in a closed protective box, however, the above manner needs to place the whole circuit board in a closed structure, and although the antistatic effect can be achieved, heat generated by the whole integrated circuit cannot be dispersed, heat collection is easily caused, and thus the overall performance and stability are affected.
In addition, when the plurality of semiconductor chips cooperate, signal interference may occur between the plurality of semiconductor chips, thereby affecting performance and stability.
In this way, the utility model provides protection for the semiconductor chip, so that the problem that the whole circuit board is covered to cause heat collection and further influence the performance and stability can be avoided, and meanwhile, the protection for the semiconductor chip can also avoid signal interference possibly generated among a plurality of semiconductor chips.
Specifically, referring to fig. 1 to 7, the present utility model provides a semiconductor chipset structure, which has the following technical scheme:
comprises a semiconductor chip 100 and a protective structure 200 arranged outside the semiconductor chip 100;
the signal input/output terminals of the semiconductor chip 100 are provided on the side;
the protective structure 200 at least comprises an electrostatic shielding layer 210, wherein the electrostatic shielding layer 210 surrounds the semiconductor chip 100, is in direct contact with the semiconductor chip 100, and is provided with at least an opening corresponding to the signal input/output end;
further comprises:
the semiconductor chip 100 is placed in the mounting groove 310 together with the protective structure 200, and the signal input and output ends correspond to the wiring channels.
The semiconductor chip 100 is generally flat, and the upper surface and the lower surface thereof are the largest two planes, and the conventional semiconductor chip 100 generally has leads disposed on the lower surface, whereas in the scheme of the present utility model, the signal input/output terminals of the semiconductor chip 100 are disposed on the side surfaces, so that the electrostatic shielding layer 210 can cover at least the upper surface and the lower surface of the semiconductor chip 100, thereby maximally realizing the electrostatic shielding effect.
The electrostatic shielding layer 210 surrounds the semiconductor chip 100 and is in direct contact with the semiconductor chip 100, so that the semiconductor chip 100 can be directly protected without covering the whole circuit board, the problem of excessive heat concentration is avoided, and meanwhile, the problem of interference possibly occurring between different chips can be avoided. Since the electrostatic shielding layer 210 directly surrounds the semiconductor chip 100 and is in direct contact with the semiconductor chip 100, an opening corresponding to the signal input/output terminal is provided in the electrostatic shielding layer 210, and connection of the semiconductor chip 100 to other elements is ensured.
The interconnect body 300 is a structure for placing the semiconductor chips 100, so that the semiconductor chips 100 can be mutually connected to achieve cooperative work, in the conventional prior art, the semiconductor chips 100 are generally directly disposed on a circuit board, however, the scheme of the present utility model is not so, in order to avoid the excessive temperature of the whole circuit board, the electrostatic shielding layer 210 is directly enclosed on the semiconductor chips 100, and at the same time, the present utility model can play a role in preventing signal interference possibly generated between different semiconductor chips 100, and in order to further improve the protection effect, the present utility model sets the signal input/output ends of the semiconductor chips 100 on the side surfaces, so that the electrostatic shielding layer 210 can enclose the top surface and the bottom surface with the largest area in the semiconductor chips 100, and since the semiconductor chips 100 of the present utility model set the signal input/output ends on the side surfaces, and the top surface and the bottom surface are enclosed by the electrostatic shielding layer 210, it is difficult to directly connect with the conventional circuit board, so the present utility model proposes to provide an interconnect body 300, and in which the interconnect wires 300 are disposed on the interconnect body, so that the different semiconductor chips 100 can be mutually connected.
The wiring channel is disposed on the side of the mounting groove 310 of the interconnection body 300, so that on one hand, the wires can be protected, and on the other hand, the wires can be prevented from being exposed to cause interference, and the assembly and the disassembly are convenient.
In summary, in the present utility model, the signal input/output terminal of the semiconductor chip 100 is disposed on the side, the electrostatic shielding layer 210 is then enclosed on the semiconductor chip 100, and the electrostatic shielding layer 210 is directly contacted with the semiconductor chip 100, and the electrostatic shielding layer 210 is disposed on the side of the semiconductor chip 100, so that the semiconductor chip 100 and the external wiring can be made by the corresponding opening, and the electrostatic shielding layer 210 is enclosed on the semiconductor chip 100, so that the influence of static electricity generated in the air on the semiconductor chip 100 during the data acquisition and processing process can be isolated, and in addition, the interconnect main body 300 is disposed, the interconnect main body 300 is provided with the plurality of mounting slots 310 for accommodating the semiconductor chip 100 and the protection structure 200, and the wiring channels are disposed in the interconnect main body 300, so that the semiconductor chips 100 disposed in the mounting slots 310 can be mutually communicated, and the plurality of semiconductor chips 100 can work cooperatively, thereby improving the working efficiency.
In order to achieve the purpose of electrostatic shielding, a layer of antistatic coating can be generally coated on the corresponding component, but this method is not suitable for antistatic of the semiconductor chip 100, and in addition, a metal net can be used for antistatic, however, the conventional metal net is usually covered in a cage in one direction, so that the fixation of the metal net can be achieved usually by matching with other fixing structures, for example, the chinese patent with the publication number CN215187552U specifically discloses an antistatic circuit board, which specifically discloses that a metal shielding cover is used for antistatic, however, the metal shielding cover needs to be arranged at an opening of a box cover to cage the whole circuit board body, and the problem of difficult disassembly exists.
In this regard, further referring to fig. 3 to 5, in some embodiments of the present utility model, the electrostatic shielding layer 210 includes a metal strip that is annularly enclosed, the metal strip is provided with a bending arrangement, the metal strip provided with the bending arrangement includes a first turning region 215 located on the inner side and a second turning region 216 located on the outer side, the first turning region 215 is used for directly contacting the semiconductor chip 100, and the second turning region 216 is provided with a first mounting structure 217.
The electrostatic shielding layer 210 is formed by adopting the annular closed metal strip, the metal strip is bent, the contact area between the metal strip and the semiconductor chip 100 can be increased by the bent metal strip, a small cavity can be formed between the metal strip and the semiconductor chip 100, the heat dissipation effect can be improved by increasing the contact area between the metal strip and the air, the fluidity of the air can be improved by the small cavity formed between the metal strip and the semiconductor chip 100, and the heat dissipation effect can be further improved. The metal strip that buckles the setting has included the first turn district 215 that is located the inboard and is located the second turn district 216 of outside, and first turn district 215 is used for with semiconductor chip 100 direct contact, can need not to set up additional fixed knot like this and constructs to fix the metal strip, has simple structure, easy dismounting's effect.
In addition, in the design and production process of the semiconductor chip 100, it is necessary to test the performance of the semiconductor chip 100, and in order to facilitate the disassembly and assembly, the semiconductor chip 100 is usually exposed to the external environment, which results in the semiconductor chip 100 being susceptible to the external environment, and in the external environment, there is a possibility that water droplets splash to affect the semiconductor chip 100, so that it is also necessary to improve the waterproof performance of the semiconductor chip 100.
In this regard, in some embodiments of the present utility model, the protection structure 200 further includes a hydrophobic layer 220, the hydrophobic layer 220 is disposed on an outer layer of the electrostatic shielding layer 210 to cover the upper and lower layers of the semiconductor chip 100, the hydrophobic layer 220 includes a structure supporting part 221, a hydrophobic film 222 disposed outside the structure supporting part 221, and a second mounting structure 223 disposed inside the structure supporting part 221, and the second mounting structure 223 is correspondingly connected to the first mounting structure 217.
The hydrophobic layer 220 is disposed outside the electrostatic shielding layer 210, so that the influence of water droplets on the semiconductor chip 100 can be avoided, wherein the hydrophobic layer 220 covers the upper and lower layers of the semiconductor chip 100, i.e., covers the upper and lower surfaces of the semiconductor chip 100, and since the semiconductor chip 100 needs to be disposed in the mounting groove 310 of the interconnect body 300, it is only necessary to prevent the water droplets from invading from above the semiconductor chip 100 or the influence of water accumulation on the semiconductor chip 100 is formed in the mounting groove 310, and therefore, the hydrophobic layer 220 can be disposed only at the upper and lower positions of the semiconductor chip 100.
The hydrophobic layer 220 includes a structural supporting portion 221, a hydrophobic film 222, and a second mounting structure 223, the hydrophobic film 222 is mainly used for isolating water molecules, the structural supporting portion 221 is used for providing support, the second mounting structure 223 is used for being matched with the first mounting structure 217, and further the hydrophobic layer 220 is fixedly disposed on the electrostatic shielding layer 210, wherein the first mounting structure 217 is disposed in the second turning region 216 of the metal strip.
By the above arrangement, a multi-layered wrap structure of the water-repellent layer 220-electrostatic shielding layer 210-semiconductor chip 100-electrostatic shielding layer 210-water-repellent layer 220 is formed.
The hydrophobic layer 220 is mainly used for preventing intrusion of water molecules, so that the hydrophobic layer 220 is a sealed structure, and generally, covering the hydrophobic layer 220 on the upper and lower positions of the semiconductor chip 100 greatly affects heat dissipation of the semiconductor chip 100, and easily causes overheating of the semiconductor chip 100, thereby affecting performance and stability.
However, in the solution of the present utility model, the metal strip adopts a bent structure, which includes the first bending region 215 located at the inner side and the second bending region 216 located at the outer side, and a plurality of small cavities are formed between the metal strip and the semiconductor chip 100, and a plurality of small cavities are also formed between the metal strip and the hydrophobic layer 220, and the small cavities ensure the fluidity of air, and meanwhile, the first bending region 215 of the metal strip disposed in a bent manner directly contacts with the semiconductor chip 100, and meanwhile, has a larger contact area with air, so that even if the hydrophobic layer 220 is disposed to cover the semiconductor chip 100 itself, good heat dissipation performance can be ensured.
Further, in some embodiments, the metal strip includes an upper branch 211, a lower branch 212, a left branch 213 and a right branch 214, and the upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 are all bent and connected end to end in sequence.
The metal strip is a ring-shaped closed structure, and is aimed at achieving electrostatic shielding and preventing possible signal interference between different semiconductor chips 100, and when testing the performance of the semiconductor chips 100 in cooperation, different kinds of semiconductor chips 100 with different functions may be used, and the sizes of the different semiconductor chips 100 may be different, so in order to adapt to the semiconductor chips 100 with different sizes, it is generally necessary to prepare ring-shaped closed metal strips with different sizes, which may cause problems of high cost and non-versatility of the metal strip.
In this regard, the present utility model proposes that the upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 are sequentially connected end to form a closed annular structure, that is, the upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 may be assembled and disassembled respectively, in some specific embodiments, the front end and the rear end of the upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 may be provided with fastening structures, and the connection is realized through the fastening structures, so as to facilitate the assembly, disassembly and replacement.
Specifically, in some embodiments, the fastening structures of the upper branch 211, the right branch 214, the lower branch 212, and the left branch 213 may be specifically barb structures, and the barbs at one end are bent upward, the barbs at the other end are bent downward, and the upper branch 211, the right branch 214, the lower branch 212, and the left branch 213 are connected to each other by barb structures.
The metal strips mainly depend on the upper branch strip 211 and the lower branch strip 212 to contact the semiconductor chip 100, and the left branch strip 213 and the right branch strip 214 may or may not contact the semiconductor chip 100, and the left branch strip 213 and the right branch strip 214 are still bent, which is still aimed at improving heat dissipation performance.
Further, in some embodiments, the upper branch 211, the right branch 214, the lower branch 212, and the left branch 213 are formed by sequentially connecting a plurality of first bending portions 218 and second bending portions 219 alternately in a posture inclined by 45 °.
The upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 extend along a straight line integrally so as to realize the matching with the semiconductor chip 100, wherein the upper branch 211, the right branch 214, the lower branch 212 and the left branch 213 are formed by a plurality of first bending parts 218 and second bending parts 219, the first bending parts 218 and the second bending parts 219 are sequentially connected in an alternating manner by an inclined 45 DEG posture, a first turning area 215 and a second turning area 216 are formed at the connecting parts, and through the arrangement, the first bending parts 218 and the second bending parts 219 are inclined at an inclined angle of 45 DEG, so that good stress performance can be ensured to support the hydrophobic layer 220, and meanwhile, the connection stability with the semiconductor chip 100 is ensured, and due to the inclined arrangement at the inclined angle of 45 DEG, the cavity formed between the metal strip and the semiconductor chip 100 is equal to the size of the cavity formed between the metal strip and the hydrophobic layer 220, so that the heat dissipation effect is more uniform.
Further, in some of these embodiments, a middle region of the outer side surface of the first bending portion 218 is provided with a first groove 2110 recessed inward, and a middle region of the outer side surface of the second bending portion 219 is provided with a second groove 2111 recessed inward, and the first groove 2110 and the second groove 2111 communicate with each other.
Wherein the first and second grooves 2110 and 2111 are used to further improve the water-proof performance, and if the hydrophobic layer 220 leaks due to quality problems, water flows generally along the second mounting structure 223 into the first mounting structure 217, and in this regard, the present utility model can prevent the water flow from falling on the semiconductor chip 100 directly along the second mounting structure 223 and the first mounting structure 217 after penetrating from the hydrophobic layer 220, but load the water flow through the first and second grooves 2110 and 2111, thereby improving the water-proof performance.
In addition, since the first groove 2110 and the second groove 2111 are formed, the contact area of the metal strip with air is increased, and the heat radiation performance is further improved.
Further, in some of these embodiments, first mounting structure 217 is a circular mounting bar extending from one side of the metal bar to the other, the mounting bar spans first recess 2110 and second recess 2111, and second mounting structure 223 is a card slot that mates with the mounting bar.
Specifically, in some preferred embodiments, the limiting portions 2112 having a diameter larger than the diameter of the mounting bar are respectively extended inward from both sides of the metal bar, and the limiting portions 2112 are extended from the sides of the metal bar to the sides of the first groove 2110 or the second groove 2111, i.e., the region of the mounting bar between the limiting portions 2112 at both sides is the fitting region 2113 to be fitted with the second mounting structure 223, if water flows from the water repellent layer 220, the water flows along the second mounting structure 223 to the fitting region 2113, and then flows from the fitting region 2113 to the first groove 2110 and the second groove 2111, thereby maximally avoiding the influence of the water flow on the semiconductor chip 100, and effectively improving the water-repellent performance.
In addition, the mating region 2113 has a gap between the first groove 2110 and the second groove 2111, which allows air to flow, thereby improving heat dissipation.
Wherein in some embodiments the width of the metal strip may span across the semiconductor chip 100.
In other embodiments, as shown in fig. 3, the width of the metal strips is smaller than the width of the semiconductor chip 100, and a plurality of metal strips may be arranged on the semiconductor chip 100, and the metal strips may be separated from each other and separately provided, or may be provided with a connection structure to connect the plurality of metal strips to each other, where the plurality of metal strips may be arranged in parallel.
In addition, in the scheme of the present utility model, since various semiconductor chips 100 may be placed in the mounting groove 310 of the interconnect body 300, and various semiconductor chips 100 may have different sizes, the size of the mounting groove 310 is generally fixed in order to be able to be easily manufactured and used, and in order to be able to stably cooperate with the semiconductor chips 100, the clamping portion 2114 may be provided in the electrostatic shielding layer 210, and in order to be able to cooperate with semiconductor chips 100 of different sizes, the position of the clamping portion 2114 provided on the electrostatic shielding layer 210 is different for clamping and positioning the semiconductor chips 100, and the peripheral size of the electrostatic shielding layer 210 is kept fixed, matched with the size of the mounting groove 310, so that different semiconductor chips 100 may be stably arranged in the mounting groove 310.
In a second aspect, referring to fig. 1 to 8, the present utility model further provides a method for manufacturing a semiconductor chipset structure, for manufacturing the semiconductor chipset structure, including:
s110, acquiring a function requirement;
s120, selecting the types and the numbers of the semiconductor chips 100 according to the functional requirements, and determining the installation position of each semiconductor chip 100 on the interconnection main body 300 and the corresponding connection relation;
s130, selecting a corresponding electrostatic shielding layer 210 according to the size of each semiconductor chip 100, and surrounding the electrostatic shielding layer 210 on the semiconductor chip 100 to be in direct contact with the semiconductor chip 100;
s140, setting wires in the wiring channels of the interconnection body 300 according to the installation positions and the connection relation;
s150, each semiconductor chip 100 is placed in the corresponding mounting groove 310 of the interconnect body 300 together with the electrostatic shielding layer 210 according to the mounting position, and is connected to the wire.
According to different functional requirements, different types of semiconductor chips 100 may be selected, or different processing tasks may be arranged for the semiconductor chips 100 of the same type to achieve cooperative work, in this process, each semiconductor chip 100 may have a connection relationship corresponding to each other, for example, three semiconductor chips 100 are selected in total, which are A, B, C respectively, wherein the chip a is responsible for collecting and processing initial data and obtaining a data, the chip B is responsible for processing a data into B data, and the chip C is responsible for processing B data into C data and outputting the B data, at this time, the connection relationship between the three semiconductor chips 100 is a and B connection, and the connection between B and C is assumed, and at this time, A, B, C is correspondingly placed on the three mounting slots 310 in sequence according to the connection sequence on the interconnect body 300.
Wherein the plurality of mounting grooves 310 on the interconnect body 300 are provided to satisfy the mounting requirements of a plurality of semiconductor chips 100.
Referring specifically to fig. 2, wherein the dashed arrows in fig. 2 indicate the signal connection relationship between the respective semiconductor chips 100, the plurality of semiconductor chips 100 are connected to each other, thereby achieving the purpose of cooperative work.
After the semiconductor chip 100 is found according to the functional requirement, the dimensions of the semiconductor chips 100 of different types may be different, so that the electrostatic shielding layer 210 may be stably connected to the semiconductor chip 100, and therefore, the electrostatic shielding layer 210 needs to be selected according to the dimensions of the semiconductor chip 100, and the electrostatic shielding layer 210 is wrapped around the semiconductor chip 100 and is directly contacted with the semiconductor chip 100.
As described above, when the semiconductor chips 100 need to cooperate, there is a corresponding connection relationship between the semiconductor chips 100 according to the respective responsible functions, and at this time, wires need to be laid in the connection channels on the side surfaces of the mounting slots 310 of the interconnect main body 300 according to the connection relationship and the corresponding mounting positions, and finally, the semiconductor chips 100 together with the electrostatic shielding layer 210 are placed in the mounting slots 310.
Further, in some embodiments, the electrostatic shielding layer 210 is a metal strip with a ring shape, the metal strip includes an upper branch 211, a lower branch 212, a left branch 213, and a right branch 214, and the step of surrounding the electrostatic shielding layer 210 on the semiconductor chip 100 includes:
the upper branch 211, the lower branch 212, the left branch 213, and the right branch 214, and the number of the upper branch 211, the lower branch 212, the left branch 213, and the right branch 214, which are correspondingly sized, are selected according to the size of the semiconductor chip 100;
the upper and lower branches 211 and 212 are disposed on the upper and lower surfaces of the semiconductor chip 100 and the upper and lower branches 211 and 212 are respectively contacted with the outer surfaces of the semiconductor chip 100, and the left and right branches 213 and 214 are disposed on the sides of the semiconductor chip 100 to be correspondingly connected with the upper and lower branches 211 and 212 to complete the surrounding of the semiconductor chip 100.
Specifically, the upper branch 211 and the lower branch 212 are provided with a first mounting structure 217, and the method further comprises:
after the upper and lower branches 211 and 212 are disposed, the water-repellent layer 220 is disposed on the first mounting structure 217 according to the distribution of the upper and lower branches 211 and 212.
Through the above scheme, the electrostatic shielding layer 210 and the hydrophobic layer 220 can be reasonably arranged on the semiconductor chip 100, and the electrostatic shielding and waterproof effects are effectively realized because the electrostatic shielding layer 210 is arranged around the semiconductor chip 100 and the hydrophobic layer 220 is arranged on the basis of the electrostatic shielding layer 210, so that the problem of heat collection of the whole circuit board can be avoided, and signal interference possibly generated between the semiconductor chips 100 is prevented.
The above description is only an example of the present utility model and is not intended to limit the scope of the present utility model, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.
Claims (8)
1. A semiconductor chipset structure comprising a semiconductor chip (100) and a guard structure (200) arranged outside the semiconductor chip (100), characterized in that:
the signal input and output ends of the semiconductor chip (100) are arranged on the side face;
the protective structure (200) at least comprises an electrostatic shielding layer (210), wherein the electrostatic shielding layer (210) surrounds the semiconductor chip (100), is in direct contact with the semiconductor chip (100), and is provided with at least an opening corresponding to the signal input and output end;
further comprises:
the semiconductor chip comprises an interconnection main body (300), wherein a plurality of mounting grooves (310) are formed in the interconnection main body (300), wiring channels communicated with other mounting grooves (310) are formed in the side surfaces of the mounting grooves (310), the semiconductor chip (100) and the protective structure (200) are placed in the mounting grooves (310), and the signal input and output ends correspond to the wiring channels;
the electrostatic shielding layer (210) comprises a metal strip which is in annular sealing, the metal strip is in bending arrangement, the metal strip in bending arrangement comprises a first turning region (215) positioned at the inner side and a second turning region (216) positioned at the outer side, the first turning region (215) is used for being in direct contact with the semiconductor chip (100), and the second turning region (216) is provided with a first mounting structure (217);
the protection structure (200) further comprises a hydrophobic layer (220), the hydrophobic layer (220) is arranged on the outer layer of the electrostatic shielding layer (210) and correspondingly covers the upper layer and the lower layer of the semiconductor chip (100), the hydrophobic layer (220) comprises a structural supporting portion (221), a hydrophobic film (222) arranged on the outer side of the structural supporting portion (221) and a second mounting structure (223) arranged on the inner side of the structural supporting portion (221), and the second mounting structure (223) is correspondingly connected with the first mounting structure (217).
2. The semiconductor chipset structure according to claim 1, wherein the metal strip comprises an upper branch (211), a lower branch (212), a left branch (213) and a right branch (214), and the upper branch (211), the right branch (214), the lower branch (212) and the left branch (213) are all bent and connected end to end in sequence.
3. A semiconductor chipset structure according to claim 2, characterized in that the upper branch (211), the right branch (214), the lower branch (212) and the left branch (213) are each formed by connecting a plurality of first bending portions (218) and second bending portions (219) alternately in order in a posture inclined by 45 °.
4. A semiconductor chipset structure according to claim 3, characterized in that the middle area of the outer side surface of the first bending part (218) is provided with a first concave groove (2110) which is concave inwards, the middle area of the outer side surface of the second bending part (219) is provided with a second concave groove (2111) which is concave inwards, and the first concave groove (2110) and the second concave groove (2111) are communicated with each other.
5. A semiconductor chipset structure according to claim 4, characterized in that the first mounting structure (217) is a circular mounting bar extending from one side of the metal bar to the other, the mounting bar straddling the first recess (2110) and the second recess (2111), the second mounting structure (223) being a card slot cooperating with the mounting bar.
6. A method of manufacturing a semiconductor chipset structure of any of claims 1 to 5, comprising:
acquiring a functional requirement;
selecting the types and the numbers of the semiconductor chips (100) according to the functional requirements, and determining the installation position of each semiconductor chip (100) on the interconnection main body (300) and the corresponding connection relation;
selecting a corresponding electrostatic shielding layer (210) according to the size of each semiconductor chip (100), and surrounding the electrostatic shielding layer (210) on the semiconductor chip (100) to be in direct contact with the semiconductor chip (100);
providing wires in the wiring channels of the interconnect body (300) according to the mounting locations and connection relationships;
each of the semiconductor chips (100) together with the electrostatic shielding layer (210) is placed in the corresponding mounting groove (310) of the interconnect body (300) according to the mounting position, and is connected with the wire.
7. The method of manufacturing a semiconductor chipset structure of claim 6, wherein the electrostatic shielding layer (210) is a ring-shaped closed metal strip, the metal strip including an upper branch (211), a lower branch (212), a left branch (213), and a right branch (214), the step of surrounding the electrostatic shielding layer (210) on the semiconductor chip (100) comprising:
selecting the upper branch (211), the lower branch (212), the left branch (213) and the right branch (214) of corresponding sizes, and the number of the upper branch (211), the lower branch (212), the left branch (213) and the right branch (214) according to the size of the semiconductor chip (100);
the upper branch strips (211) are arranged on the upper surface of the semiconductor chip (100), the lower branch strips (212) are arranged on the lower surface of the semiconductor chip (100), the upper branch strips (211) and the lower branch strips (212) are respectively contacted with the outer surface of the semiconductor chip (100), and the left branch strips (213) and the right branch strips (214) are arranged on the side surface of the semiconductor chip (100) and correspondingly connected with the upper branch strips (211) and the lower branch strips (212) so as to complete the surrounding of the semiconductor chip (100).
8. A method of manufacturing a semiconductor chipset structure according to claim 7, characterized in that the upper branch (211) and the lower branch (212) are provided with a first mounting structure (217), the method further comprising:
after the upper branch bar (211) and the lower branch bar (212) are arranged, a hydrophobic layer (220) is arranged on the first mounting structure (217) according to the distribution of the upper branch bar (211) and the lower branch bar (212).
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