CN117038617A - Power semiconductor packaging structure and manufacturing method thereof - Google Patents

Power semiconductor packaging structure and manufacturing method thereof Download PDF

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Publication number
CN117038617A
CN117038617A CN202311287711.7A CN202311287711A CN117038617A CN 117038617 A CN117038617 A CN 117038617A CN 202311287711 A CN202311287711 A CN 202311287711A CN 117038617 A CN117038617 A CN 117038617A
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CN
China
Prior art keywords
conductive
chip
conductive layer
protection plate
power semiconductor
Prior art date
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Pending
Application number
CN202311287711.7A
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Chinese (zh)
Inventor
周晓阳
陈泳槟
刘军
陈大雄
李博强
朱贤龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Core Juneng Semiconductor Co ltd
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Guangdong Core Juneng Semiconductor Co ltd
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Application filed by Guangdong Core Juneng Semiconductor Co ltd filed Critical Guangdong Core Juneng Semiconductor Co ltd
Priority to CN202311287711.7A priority Critical patent/CN117038617A/en
Publication of CN117038617A publication Critical patent/CN117038617A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/20—Bonding
    • B23K26/21—Bonding by welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60292—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the use of an electron or laser beam

Abstract

The application relates to a power semiconductor packaging structure and a manufacturing method thereof, wherein the power semiconductor packaging structure comprises: the device comprises a substrate, a chip, a conductive protection plate and a conductive connecting piece. The source electrode of the chip is connected with the conductive protection plate in a welding way, the conductive protection plate is connected with the first connecting part of the conductive connecting piece in a melting way by adopting a laser welding process, and the quick and efficient connection can be realized without adopting solder, so that the connection reliability of the source electrode of the chip and the first connecting part of the conductive connecting piece is improved, and the failure rate is greatly reduced; in addition, in the laser welding process, as the conductive protection plate is arranged above the source electrode of the chip, the conductive protection plate has a good protection effect on the fragile and vulnerable source electrode, and the normal and smooth implementation of the laser welding process is ensured; in addition, the needed avoiding space is smaller, the size of a high-temperature melting and spreading molten pool is relatively smaller, the difference of thermal expansion coefficients of all layers after molding is greatly reduced, and the thermal cycle reliability is greatly improved.

Description

Power semiconductor packaging structure and manufacturing method thereof
Technical Field
The present application relates to the field of semiconductor packaging technology, and in particular, to a power semiconductor packaging structure and a method for manufacturing the same.
Background
The power semiconductor module packaging structure in the related art comprises, but is not limited to, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor Insulated gate field effect transistor), an IGBT (Insulated-gate Bipolar Transistor Insulated gate bipolar transistor) and the like, wherein the electrical connection mode of the source electrode/emitter electrode of the chip and the lower bridge chip/DC-main flow is mainly a wire bonding process, namely, the wire bonding process is carried out by using an ultrasonic welding process, a welding head comprises a welding chopper, a cutter and a wire clamp, the transducer above the welding head converts electric energy into high-frequency ultrasonic vibration energy in the horizontal direction, the ultrasonic vibration energy is transmitted to the chopper, the chopper is pressed down to weld a lead, the welding is completed, the cutter is cut, and finally the wire clamp is utilized to break.
However, the packaging reliability of the plurality of bonding pads scattered on the power semiconductor packaging structure in the working condition is lower, the failure rate is higher, larger parasitic parameters are brought, and the electrical performance of the device is reduced. In addition, the wire bonding is limited by the process, and a certain arc height is often needed to prevent collapse short circuit and tangent buffer space to prevent a cutter from damaging a chip or other mounting devices, namely, the corresponding requirement of large packaging space is large, so that the waste of the packaging space is caused, and meanwhile, the miniaturization process of the device size is hindered.
Disclosure of Invention
Based on this, it is necessary to overcome the defects of the prior art, and to provide a power semiconductor package structure and a method for manufacturing the same, which can improve product reliability, reduce failure rate, and reduce the volume of package space.
A power semiconductor package structure, the power semiconductor package structure comprising:
the substrate is provided with a first surface, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are arranged on the first surface, and an insulation interval is formed between the first conductive layer and the second conductive layer;
the chip is welded and connected to the first conductive layer;
the conductive protection plate is welded and connected to the source electrode of the chip;
the conductive connecting piece is provided with a first connecting part and a second connecting part which are opposite to each other, the first connecting part is connected to the conductive protection plate by adopting a laser welding process, and the second connecting part is connected to the second conductive layer by adopting a laser welding process.
In one embodiment, the conductive connection comprises a conductive tab and/or at least one conductive lead.
In one embodiment, the conductive connection is provided as an integrally stamped conductive frame.
In one embodiment, the substrate is provided as a first split plate and a second split plate; the first conductive layer is arranged on the first split plate, and the second conductive layer is arranged on the second split plate.
In one embodiment, the die is bonded to the first conductive layer using a sintering process; the conductive protection plate is welded and connected to the source electrode of the chip by adopting a sintering process.
A manufacturing method of a power semiconductor packaging structure comprises the following steps:
providing a substrate, a chip, a conductive protection plate and a conductive connecting piece, wherein a first surface of the substrate is provided with a first conductive layer and a second conductive layer which are mutually arranged at intervals;
welding the chip on the first conductive layer, and welding the conductive protection plate on the source electrode of the chip;
and welding the first connecting part of the conductive connecting piece on the conductive protection plate by adopting a laser welding process, and welding the second connecting part of the conductive connecting piece on the second conductive layer by adopting a laser welding process.
In one embodiment, in the laser welding process, the depth of a laser molten pool formed at the welding part of the first connecting part and the conductive protection plate is controlled to be 0.2mm-0.4mm, and the width of the laser molten pool is controlled to be 0.8mm-1.6mm; and/or controlling the depth of a laser molten pool formed at the welding part of the second connecting part and the second conductive layer to be 0.2mm-0.4mm, and controlling the width of the laser molten pool to be 0.8mm-1.6mm.
In one embodiment, the laser welding process uses a laser power of 5000W-8000W, a pulse width of 10ms-20ms, and a welding time of 3S-15S.
In one embodiment, the step of solder-connecting the die to the first conductive layer and solder-connecting the conductive protection plate to the source of the die includes:
bonding the chip on the first conductive layer by adopting soldering paste;
attaching the conductive protection plate to a source electrode of the chip by adopting soldering paste;
and then adopting a sintering process to enable the chip to be welded and fixed on the first conductive layer, and synchronously enabling the conductive protection plate to be welded and fixed on the source electrode of the chip.
In one embodiment, the step of attaching the chip to the first conductive layer using solder paste includes: solder paste is arranged on the drain electrode of the chip or the first conductive layer, and the drain electrode of the chip and the first conductive layer are aligned and attached together; the step of attaching the conductive protection plate to the source electrode of the chip by using solder paste comprises the following steps: solder paste is arranged on the conductive protection plate or the source electrode of the chip, and the conductive protection plate and the source electrode of the chip are aligned and attached together; the soldering paste adopts silver paste or tin paste.
According to the power semiconductor packaging structure and the manufacturing method thereof, the conductive protection plate is added, the source electrode of the chip is connected with the conductive protection plate in a welding way, the conductive protection plate is connected with the first connecting part of the conductive connecting piece in a melting way by adopting a laser welding process, and the rapid and efficient connection can be realized without adopting solder, so that the connection reliability of the source electrode of the chip and the first connecting part of the conductive connecting piece is improved, and the failure rate is greatly reduced; likewise, the second connecting part of the conductive connecting piece is in fusion connection with the second conductive layer by adopting a laser welding process, no welding flux is needed, quick and efficient connection can be realized, the connection reliability is improved, and the failure rate is reduced; in addition, in the laser welding process, as the conductive protection plate is arranged above the source electrode of the chip, the conductive protection plate has a good protection effect on the fragile and vulnerable source electrode, and the normal and smooth implementation of the laser welding process is ensured; in addition, compared with the wire bonding mode or reflow soldering process in the related art, the laser soldering process in the embodiment performs local high-temperature energy soldering through focusing, heating and soldering are not needed, the cooling of local heat after soldering is faster, the needed avoiding space is smaller, the size of a molten pool for high-temperature melting and spreading is relatively smaller, the difference of thermal expansion coefficients of all layers after molding is greatly reduced, and the thermal cycle reliability is greatly improved.
Drawings
Fig. 1 is a diagram illustrating a power semiconductor package structure according to an embodiment of the present application.
10. A substrate; 11. a first conductive layer; 12. a second conductive layer; 13. an insulation interval; 14. a third conductive layer; 20. a chip; 30. an electrically conductive protective plate; 40. a conductive connection; 41. a first connection portion; 42. a second connecting portion; 50. a first weld layer; 60. and a second solder layer.
Detailed Description
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. The present application may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the application, whereby the application is not limited to the specific embodiments disclosed below.
As described in the background art, the power semiconductor packaging structure product in the related art has the problems of low reliability, easy failure and larger requirement on the packaging space volume, and the inventor finds that the reason for the problem is that a plurality of scattered bonding welding spots can be acted by the coupling field of the current, heat and stress of the whole chip in working conditions, so that the service life test is more severe, the corresponding packaging reliability is lower, the failure rate is higher, larger parasitic parameters are brought, and the electrical performance of the device is reduced. In addition, the formed bonding welding spots with deformed wire diameters become fragile nodes in the whole packaging structure, the reliability of the whole packaging structure is lowered, and the failure rate is increased. In addition, the wire bonding is limited by the process, and a certain arc height is often needed to prevent collapse short circuit and tangent buffer space to prevent a cutter from damaging a chip or other mounting devices, namely, the corresponding requirement of large packaging space is large, so that the waste of the packaging space is caused, and meanwhile, the miniaturization process of the device size is hindered.
Based on the above reasons, the present application provides a power semiconductor package structure and a method for manufacturing the same, which can improve product reliability, reduce failure rate, and reduce package space volume.
Referring to fig. 1, fig. 1 shows a power semiconductor package structure according to an embodiment of the present application. An embodiment of the present application provides a power semiconductor package structure, including: a substrate 10, a chip 20, a conductive protection plate 30 and a conductive connection 40. The substrate 10 is provided with a first surface, and a first conductive layer 11 and a second conductive layer 12 provided on the first surface. The first conductive layer 11 and the second conductive layer 12 are formed with an insulating space 13. The chip 20 is soldered to the first conductive layer 11. The conductive protection plate 30 is solder-connected to the source of the chip 20. The conductive connecting member 40 is provided with a first connecting portion 41 and a second connecting portion 42 opposite to each other. The first connection portion 41 is connected to the conductive protection plate 30 using a laser welding process, and the second connection portion 42 is connected to the second conductive layer 12 using a laser welding process.
In the power semiconductor packaging structure, the source electrode of the chip 20 is welded with the conductive protection plate 30 due to the addition of the conductive protection plate 30, the conductive protection plate 30 is in fusion connection with the first connection part 41 of the conductive connecting piece 40 by adopting a laser welding process, and no welding flux is needed, so that quick and efficient connection can be realized, the connection reliability of the source electrode of the chip 20 and the first connection part 41 of the conductive connecting piece 40 is improved, and the failure rate is greatly reduced; likewise, the second connection portion 42 of the conductive connecting member 40 is in fusion connection with the second conductive layer 12 by using a laser welding process, and no solder is needed, so that quick and efficient connection can be realized, the connection reliability is improved, and the failure rate is reduced; in addition, in the laser welding process, as the conductive protection plate 30 is arranged above the source electrode of the chip 20, the conductive protection plate 30 plays a good role in protecting the fragile and vulnerable source electrode, and ensures the normal and smooth implementation of the laser welding process; in addition, compared with the wire bonding mode or reflow soldering process in the related art, the laser soldering process in the embodiment performs local high-temperature energy soldering through focusing, heating and soldering are not needed, the cooling of local heat after soldering is faster, the needed avoiding space is smaller, the size of a molten pool for high-temperature melting and spreading is relatively smaller, the difference of thermal expansion coefficients of all layers after molding is greatly reduced, and the thermal cycle reliability is greatly improved.
The first surface of the substrate 10, i.e., the front surface of the substrate 10, and the second surface of the substrate 10 are disposed opposite to the first surface, i.e., the back surface of the substrate 10.
It should be noted that, the drain electrode of the chip 20 is located at a side of the chip 20 facing the first conductive layer 11, and is specifically welded to the first conductive layer 11; the source of the chip 20 is located on the side of the chip 20 facing away from the first conductive layer 11, and is in particular soldered to the conductive protection plate 30.
The current direction of the power semiconductor packaging structure is as follows: the first conductive layer 11- & gt the first welding layer 50 between the chip 20 and the first conductive layer 11- & gt the back drain electrode of the chip 20- & gt the front source electrode of the chip 20- & gt the second welding layer 60 between the chip 20 and the conductive protection plate 30- & gt the conductive connecting piece 40- & gt the second conductive layer 12 are integrally formed, so that large-area planar electrical connection is formed, the reliability is high, and the failure probability can be reduced.
In the related art, in order to meet the high power requirement (high voltage 800V-1000V/high current 90A-500A) of the power device itself, 4-8 wires are often required to be bonded to a single chip 20, and the more the number of wires, the more the production steps, the slower the speed and the lower the production efficiency. Based on this, in one embodiment, the conductive connection 40 comprises a conductive tab. The function of one conductive connecting piece is equivalent to that of a plurality of conductive leads, and the connection operation with the conductive protection plate 30 and the second conductive layer 12 can be more convenient in the production process of the power semiconductor packaging structure, so that the production efficiency is improved. In addition, the current is increased, the parasitic inductance is reduced, and the heat dissipation capacity is enhanced.
Of course, as some alternatives, the conductive connection member 40 may be provided as at least one conductive lead, or as a combination of a conductive connection sheet and a conductive lead.
In some embodiments, the thickness of the conductive tabs is 0.3mm-0.6mm, specifically, for example, 0.3mm, 0.4mm, 0.5mm, 0.6mm, etc., so that, on the one hand, the conductive tabs have a thickness large enough to make themselves strong enough; on the other hand, the thickness is not too large, so that the material waste is avoided, and the cost can be saved. Of course, the thickness of the conductive connecting sheet can be any value except 0.3mm-0.6mm, and particularly can be flexibly adjusted and set according to actual requirements.
In some embodiments, the thickness of the conductive protection plate 30 is set to be 0.03mm-0.3mm, specifically, for example, values of 0.03mm, 0.08mm, 0.1mm, 0.15mm, 0.2mm, 0.3mm, and the like, and may be any value other than 0.03mm-0.3mm, which can be specifically and flexibly adjusted and set according to practical requirements.
In some embodiments, the thickness of the first solder layer 50 between the chip 20 and the first conductive layer 11 is set to 0.03mm-0.09mm, specifically, for example, 0.03mm, 0.05mm, 0.06mm, 0.07mm, 0.09mm. In this way, the thickness of the first solder layer 50 is sufficiently large, so that the reliability of the electrical connection between the chip 20 and the first conductive layer 11 can be improved and the failure rate can be reduced when the chip 20 and the first conductive layer 11 are sintered and connected together by using solder paste.
In some embodiments, the conductive connecting member 40, the conductive protective plate 30, the first conductive layer 11, and the second conductive layer 12 are each independently selected from suitable metal materials, and the metal materials include, but are not limited to, copper, aluminum, platinum, iron, silver, gold stainless steel, and alloy materials thereof, which can be flexibly adjusted and set according to practical requirements, and are not limited herein.
The conductive connecting piece may be shaped like a regular shape, for example, a straight line, a U-shape, an L-shape, a U-shape, or the like, or may be shaped like an irregular shape. The two surfaces can be straight surfaces and are arranged on the same plane; the conductive frame may be formed in a curved shape by, for example, integrally pressing with a die.
In one embodiment, the conductive connector 40 includes, but is not limited to, a stamped, swaged conductive frame formed as a single piece.
In one embodiment, the substrate 10 is provided as a first split plate and a second split plate. The first conductive layer 11 is provided on the first split plate, and the second conductive layer 12 is provided on the second split plate. The first split plate and the second split plate can be connected into a whole or divided into two independent plates.
Referring to fig. 1, in some embodiments, die 20 includes, but is not limited to, being soldered to first conductive layer 11 using a sintering process, ultrasonic soldering, or reflow soldering. The conductive protective plate 30 includes, but is not limited to, a source electrode soldered to the die 20 using a sintering process, ultrasonic soldering, or reflow soldering. In this embodiment, specifically, the chip 20 is welded to the first conductive layer 11 by using a sintering process, and the chip 20 is welded to the conductive protection plate 30 by using a sintering process, at this time, the first welding layer 50 between the chip 20 and the first conductive layer 11 is a sintered layer, the second welding layer 60 between the chip 20 and the conductive protection plate 30 is a sintered layer, specifically, for example, all the second welding layers are silver sintered layers, and the mismatch degree of the thermal expansion coefficients of the connection structure of the sintered layer and the laser welding pool is smaller, so that the thermal conductivity is higher, the thermal cycle firmness of the interface is better, the stability of the packaging structure under the working condition of 20175 ℃ of the silicon carbide chip is improved, the fatigue failure probability caused by the temperature cycle in the service life period is reduced, the reliability of the power module product is further improved, and the safety risk is reduced.
In addition, the whole area sintering process and the laser welding process are combined with each other, compared with wire bonding, the process time is reduced, the process steps such as wire bonding, solder paste/soldering lug reflow and the like are reduced, and the whole production efficiency is greatly improved.
In some embodiments, the substrate 10 includes, but is not limited to, a ceramic substrate 10.
Referring to fig. 1, in some embodiments, a third conductive layer 14 is disposed on the back surface of the substrate 10. The third conductive layer 14 includes, but is not limited to, various metallic materials such as copper, aluminum, gold, silver, and the like. The first conductive layer 11 and the second conductive layer 12 are formed by, for example, soldering an active metal material to the front surface of the substrate 10, and the third conductive layer 14 is formed by, for example, soldering an active metal material to the back surface of the substrate 10. Alternatively, the respective thicknesses of the first conductive layer 11 and the second conductive layer 12 are set to, for example, 0.3mm, the thickness of the substrate 10 is set to, for example, 0.32mm, and the thickness of the third conductive layer 14 is set to, for example, 0.3mm.
Referring to fig. 1, in some embodiments, a method for manufacturing a power semiconductor package structure includes the following steps:
step S100, providing a substrate 10, a chip 20, a conductive protection plate 30 and a conductive connecting piece 40, wherein a first surface of the substrate 10 is provided with a first conductive layer 11 and a second conductive layer 12 which are arranged at intervals;
step 200, the chip 20 is welded on the first conductive layer 11, and the conductive protection plate 30 is welded on the source of the chip 20;
in step S300, the first connection portion 41 of the conductive connecting member 40 is welded to the conductive protection plate 30 by using a laser welding process, and the second connection portion 42 of the conductive connecting member 40 is welded to the second conductive layer 12 by using a laser welding process.
Wherein, after the first connection part 41 is welded and connected with the conductive protection plate 30 by adopting a laser welding process, the first connection part 41 and the conductive protection plate 30 are mutually fused into a whole; similarly, after the second connection portion 42 is welded to the second conductive layer 12 by a laser welding process, the second connection portion 42 and the second conductive layer 12 are fused together.
According to the manufacturing method of the power semiconductor packaging structure, the conductive protection plate 30 is added, the source electrode of the chip 20 is connected with the conductive protection plate 30 in a welding way, the conductive protection plate 30 is connected with the first connecting part 41 of the conductive connecting piece 40 in a melting way by adopting a laser welding process, and the quick and efficient connection can be realized without adopting welding flux, so that the connection reliability of the source electrode of the chip 20 and the first connecting part 41 of the conductive connecting piece 40 is improved, and the failure rate is greatly reduced; likewise, the second connection portion 42 of the conductive connecting member 40 is in fusion connection with the second conductive layer 12 by using a laser welding process, and no solder is needed, so that quick and efficient connection can be realized, the connection reliability is improved, and the failure rate is reduced; in addition, in the laser welding process, as the conductive protection plate 30 is arranged above the source electrode of the chip 20, the conductive protection plate 30 plays a good role in protecting the fragile and vulnerable source electrode, and ensures the normal and smooth implementation of the laser welding process; in addition, compared with the wire bonding mode or reflow soldering process in the related art, the laser soldering process in the embodiment performs local high-temperature energy soldering through focusing, heating and soldering are not needed, the cooling of local heat after soldering is faster, the needed avoiding space is smaller, the size of a molten pool for high-temperature melting and spreading is relatively smaller, the difference of thermal expansion coefficients of all layers after molding is greatly reduced, and the thermal cycle reliability is greatly improved.
In some embodiments, in the laser welding process, the depth of the laser melting pool formed at the welding portion of the first connection portion 41 and the conductive protection plate 30 is controlled to be 0.2mm-0.4mm, and the width of the laser melting pool is controlled to be 0.8mm-1.6mm; and/or the depth of the laser melt pool formed at the welding portion of the second connection portion 42 and the second conductive layer 12 is controlled to be 0.2mm to 0.4mm, and the width of the laser melt pool is controlled to be 0.8mm to 1.6mm.
In one embodiment, in the laser welding process, the depth of the formed laser melt pool is controlled to be, for example, 0.2mm to 0.4mm, specifically, for example, 0.2mm, 0.3mm, 0.4mm, etc., and the width of the laser melt pool is controlled to be, for example, 0.8mm to 1.6mm, specifically, for example, 0.8mm, 1mm, 1.2mm, 1.4mm, 1.6mm, etc., regardless of the welding position of the first connecting portion 41 and the conductive protection plate 30 or the welding position of the second connecting portion 42 and the second conductive layer 12, so that it has been found that the tensile force of the interface layer is 500N to 1000N after the welding is completed, which can meet the product requirements.
Of course, as some alternatives, the depth of the formed laser melting pool can be controlled and flexibly adjusted to any value except 0.2mm-0.4mm according to actual requirements, and the width of the laser melting pool can be controlled and flexibly adjusted to any value except 0.8mm-1.6mm, and the specific arrangement is not limited herein.
In some embodiments, the laser power employed in the laser welding process includes, but is not limited to, 5000W-8000W, such as 5000W, 6000W, 6500W, 6600W, 6800W, 7000W, 8000W. Of course, the power may be set to any power other than 5000W to 8000W according to actual requirements. The pulse width of the laser light may be, but not limited to, 10ms to 20ms, for example, 10ms, 13ms, 15ms, 16ms, 20ms, or any value other than 10ms to 20 ms. The primary welding time includes, but is not limited to, 3S to 15S, specifically, for example, 3S, 8S, 9S, 10S, 15S, etc., and may be any value set to 15S or more.
In some embodiments, step S200 specifically includes:
step S210, bonding the chip 20 on the first conductive layer 11 by adopting soldering paste;
step S220, adhering the conductive protection plate 30 to the source electrode of the chip 20 by using solder paste;
step S230, a sintering process is then used to solder-fix the die 20 to the first conductive layer 11, and simultaneously solder-fix the conductive protection plate 30 to the source of the die 20.
In this way, the first welding layer 50 of the chip 20 and the first conductive layer 11 is a sintering layer, the second welding layer 60 between the chip 20 and the conductive protection plate 30 is a sintering layer, the mismatch degree of the thermal expansion coefficient of the connection structure of the sintering layer and the laser welding pool is smaller, the thermal conductivity is higher, the interface thermal cycle firmness is better, the stability of the packaging structure under the working condition of the silicon carbide chip 175 ℃ is improved, the fatigue failure probability caused by the temperature cycle in the service life period is reduced, the reliability of the power module product is further improved, and the safety risk is reduced. In addition, the whole area sintering process and the laser welding process are combined with each other, compared with wire bonding, the process time is reduced, the process steps such as wire bonding, solder paste/soldering lug reflow and the like are reduced, and the whole production efficiency is greatly improved.
In some embodiments, the step of attaching the chip 20 to the first conductive layer 11 using solder paste includes: solder paste is provided on the drain electrode of the chip 20 or the first conductive layer 11, and the drain electrode of the chip 20 and the first conductive layer 11 are aligned and bonded together.
In some embodiments, the step of attaching the conductive protective plate 30 to the source of the chip 20 using solder paste includes: solder paste is provided on the conductive protection plate 30 or the source electrode of the chip 20, and the conductive protection plate 30 and the source electrode of the chip 20 are aligned and bonded together.
Solder paste includes, but is not limited to, silver paste and tin paste. The silver paste is specifically adopted in the embodiment, so that welding can be completed at a relatively low temperature, the welding strength is high, a large amount of waste gas and waste residues can be avoided, and the method is environment-friendly and energy-saving.
In the description of the present application, it should be understood that, if any, these terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., are used herein with respect to the orientation or positional relationship shown in the drawings, these terms refer to the orientation or positional relationship for convenience of description and simplicity of description only, and do not indicate or imply that the apparatus or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, if any, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the terms "plurality" and "a plurality" if any, mean at least two, such as two, three, etc., unless specifically defined otherwise.
In the present application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly. For example, the two parts can be fixedly connected, detachably connected or integrated; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, the meaning of a first feature being "on" or "off" a second feature, and the like, is that the first and second features are either in direct contact or in indirect contact through an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that if an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. If an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein, if any, are for descriptive purposes only and do not represent a unique embodiment.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (10)

1. A power semiconductor package structure, characterized in that the power semiconductor package structure comprises:
the substrate is provided with a first surface, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are arranged on the first surface, and an insulation interval is formed between the first conductive layer and the second conductive layer;
the chip is welded and connected to the first conductive layer;
the conductive protection plate is welded and connected to the source electrode of the chip;
the conductive connecting piece is provided with a first connecting part and a second connecting part which are opposite to each other, the first connecting part is connected to the conductive protection plate by adopting a laser welding process, and the second connecting part is connected to the second conductive layer by adopting a laser welding process.
2. The power semiconductor package according to claim 1, wherein the conductive connection comprises a conductive tab and/or at least one conductive lead.
3. The power semiconductor package according to claim 1, wherein the conductive connection member is provided as an integrally stamped conductive frame.
4. The power semiconductor package according to claim 1, wherein the substrate is provided as a first split plate and a second split plate; the first conductive layer is arranged on the first split plate, and the second conductive layer is arranged on the second split plate.
5. The power semiconductor package according to any one of claims 1 to 4, wherein the chip is soldered to the first conductive layer using a sintering process; the conductive protection plate is welded and connected to the source electrode of the chip by adopting a sintering process.
6. The manufacturing method of the power semiconductor packaging structure is characterized by comprising the following steps:
providing a substrate, a chip, a conductive protection plate and a conductive connecting piece, wherein a first surface of the substrate is provided with a first conductive layer and a second conductive layer which are mutually arranged at intervals;
welding the chip on the first conductive layer, and welding the conductive protection plate on the source electrode of the chip;
and welding the first connecting part of the conductive connecting piece on the conductive protection plate by adopting a laser welding process, and welding the second connecting part of the conductive connecting piece on the second conductive layer by adopting a laser welding process.
7. The method of manufacturing a power semiconductor package according to claim 6, wherein in the laser welding process, a depth of a laser melt pool formed at a welding portion of the first connection portion and the conductive protection plate is controlled to be 0.2mm to 0.4mm, and a width of the laser melt pool is controlled to be 0.8mm to 1.6mm; and/or controlling the depth of a laser molten pool formed at the welding part of the second connecting part and the second conductive layer to be 0.2mm-0.4mm, and controlling the width of the laser molten pool to be 0.8mm-1.6mm.
8. The method of manufacturing a power semiconductor package according to claim 6, wherein the laser power is 5000W to 8000W, the pulse width is 10ms to 20ms, and the welding time is 3S to 15S.
9. The method of manufacturing a power semiconductor package according to claim 6, wherein the step of solder-connecting the die to the first conductive layer and solder-connecting the conductive protection plate to the source of the die comprises:
bonding the chip on the first conductive layer by adopting soldering paste;
attaching the conductive protection plate to a source electrode of the chip by adopting soldering paste;
and then adopting a sintering process to enable the chip to be welded and fixed on the first conductive layer, and synchronously enabling the conductive protection plate to be welded and fixed on the source electrode of the chip.
10. The method of manufacturing a power semiconductor package according to claim 9, wherein the attaching the chip to the first conductive layer using solder paste comprises: solder paste is arranged on the drain electrode of the chip or the first conductive layer, and the drain electrode of the chip and the first conductive layer are aligned and attached together; the step of attaching the conductive protection plate to the source electrode of the chip by using solder paste comprises the following steps: solder paste is arranged on the conductive protection plate or the source electrode of the chip, and the conductive protection plate and the source electrode of the chip are aligned and attached together; the soldering paste adopts silver paste or tin paste.
CN202311287711.7A 2023-10-08 2023-10-08 Power semiconductor packaging structure and manufacturing method thereof Pending CN117038617A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305620A (en) * 2006-05-08 2007-11-22 Fuji Electric Holdings Co Ltd Manufacturing method of semiconductor device
CN113491010A (en) * 2019-03-05 2021-10-08 罗姆股份有限公司 Semiconductor device and bonding method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305620A (en) * 2006-05-08 2007-11-22 Fuji Electric Holdings Co Ltd Manufacturing method of semiconductor device
CN113491010A (en) * 2019-03-05 2021-10-08 罗姆股份有限公司 Semiconductor device and bonding method

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