CN117012625A - Silicon carbide thick epitaxial wafer with low surface resistance and preparation method thereof - Google Patents
Silicon carbide thick epitaxial wafer with low surface resistance and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002245 particle Substances 0.000 claims abstract description 22
- 150000003376 silicon Chemical class 0.000 claims abstract description 22
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 18
- 238000004943 liquid phase epitaxy Methods 0.000 claims abstract description 12
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000002135 nanosheet Substances 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims description 25
- 239000011259 mixed solution Substances 0.000 claims description 20
- 239000001257 hydrogen Substances 0.000 claims description 15
- 229910052739 hydrogen Inorganic materials 0.000 claims description 15
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000003756 stirring Methods 0.000 claims description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 238000001816 cooling Methods 0.000 claims description 11
- 229910002804 graphite Inorganic materials 0.000 claims description 10
- 239000010439 graphite Substances 0.000 claims description 10
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 9
- 229910052726 zirconium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000007731 hot pressing Methods 0.000 claims description 7
- 238000005245 sintering Methods 0.000 claims description 7
- 238000000498 ball milling Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000002156 mixing Methods 0.000 claims description 5
- 239000000843 powder Substances 0.000 claims description 5
- 238000001132 ultrasonic dispersion Methods 0.000 claims description 5
- 238000001291 vacuum drying Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims 1
- 238000002679 ablation Methods 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 9
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 abstract description 7
- 239000005052 trichlorosilane Substances 0.000 abstract description 7
- 238000000407 epitaxy Methods 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 5
- 125000004432 carbon atom Chemical group C* 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 239000013589 supplement Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 41
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 4
- 239000005977 Ethylene Substances 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 239000012300 argon atmosphere Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002064 nanoplatelet Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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Abstract
The invention discloses a silicon carbide thick epitaxial wafer with low surface resistance, which comprises a silicon carbide substrate, a first epitaxial layer and a second epitaxial layer. The novel point is that the traditional silicon source (such as silane, dichlorosilane and trichlorosilane) is replaced by new modified silicon melt, so that the silicon source is provided for epitaxy, and more importantly, the problems of poor crystal defect and poor ablation resistance of the silicon carbide thick epitaxial wafer are solved. The carbon atoms of the graphene nano-sheets in the modified silicon melt migrate in the liquid phase epitaxy process to supplement the carbon vacancies of the epitaxial layer, so that the purpose of repairing the carbon vacancies is achieved, the purpose of prolonging the carrier life of the silicon carbide epitaxial wafer is improved, and the prefabricated particles added in the modified silicon melt can enable the silicon carbide thick epitaxial wafer to have good ablation resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductor materials, and relates to a silicon carbide thick epitaxial wafer with low surface resistance and a preparation method thereof.
Background
In recent years, with the continuous development of the photovoltaic and new energy automobile industries, the industry demand for power semiconductor devices is also growing. Silicon carbide (SiC) is highly colored on device semiconductors with its excellent physical properties. The power device manufactured by the silicon carbide material can remarkably improve the module efficiency and reduce the volume.
Since all devices are now realized on epitaxy, the quality of epitaxy has a very large impact on the performance of the device, but the quality of epitaxy is affected by the crystal and the substrate. For silicon carbide epitaxy, basically many defects are directly copied from the substrate, so the quality of the substrate, the level of processing, and especially the control of defects are important for epitaxial growth. With the improvement of silicon carbide crystal growth technology, defects from the aspect of crystals, such as micropipes, BPDs, TSDs and the like, are well controlled, and defects introduced by technological means such as cutting, grinding, polishing and the like are not easy to eliminate in the processing process of a substrate. These all affect the subsequent epitaxial growth and create different defects that affect device performance. In addition, the high-temperature annealing can cause damage to the surface of the epitaxial wafer, and how to improve the ablation resistance of the silicon carbide thick epitaxial wafer is also a difficult problem to be solved in the industry.
Disclosure of Invention
The invention aims to provide a silicon carbide thick epitaxial wafer with low surface resistance and a preparation method thereof, and solves the problems of short service life of carriers and poor ablation resistance of the silicon carbide epitaxial wafer in the background art.
The aim of the invention can be achieved by the following technical scheme:
a silicon carbide thick epitaxial wafer with low surface resistance comprises a silicon carbide substrate, a first epitaxial layer and a second epitaxial layer.
Further, the thickness of the first epitaxial layer is 0.4-1.6 mu m, and the thickness of the second epitaxial layer is 5-18 mu m.
The silicon carbide thick epitaxial wafer with low surface resistance is prepared by the following steps:
step A1, placing a silicon carbide substrate into a high-temperature annealing furnace, and introducing hydrogen for high-temperature annealing;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer;
and A3, growing a second epitaxial layer on the silicon carbide wafer with the first epitaxial layer prepared in the step A2 by adopting a CVD method, annealing at 1500-1700 ℃ for 20-30min, and cooling to room temperature to obtain the silicon carbide thick epitaxial wafer with low surface resistance.
Further, the hydrogen flow in the step A1 is 50-100slm, the temperature is kept at 1500-1600 ℃, and the annealing time is 5-30min.
Further, in the liquid phase epitaxy in the step A2, the modified silicon melt is used as a silicon source, carbon powder is used as a carbon source, and the growth temperature is 2100-2300 ℃.
Further, the growth condition of the CAD method in the step A3 is that the growth pressure is 60-220mbar, the temperature is 1560-1650 ℃, the hydrogen flow is 40-190slm, and the molar ratio of carbon to silicon is 0.6-1.1:1, the growth rate is 15-26 mu m/h, wherein ethylene is used as a carbon source, trichlorosilane is used as a silicon source, and nitrogen is used as a doping agent.
Wherein the modified silicon melt is prepared by the following steps:
step S1, placing graphene nano sheets into a beaker containing absolute ethyl alcohol, and performing ultrasonic dispersion with power of 430-450W for 1-1.5h to obtain a mixed solution a;
s2, pouring aluminum powder and zirconium boride into a beaker containing absolute ethyl alcohol, and stirring for 50-70min at a rotating speed of 150-200rpm to obtain a mixed solution b;
step S3, mixing the mixed solution a and the mixed solution b, stirring for 40-50min at 53-55 ℃ and 1300-1400rpm, vacuum drying for 24h, putting the dried powder into a ball mill in argon atmosphere, ball milling for 3-3.5h at 400-500rpm, and finally vacuum hot-pressing and sintering to obtain prefabricated particles;
s4, respectively placing the prefabricated particles and the instant silicon in a resistance furnace, and preserving heat for 1-1.5 hours at 160-180 ℃ for later use;
and S5, placing the prefabricated particles treated in the step S4 into a graphite crucible, heating to melt, adding the instant silicon treated in the step S4 into the graphite crucible, stirring for 6-8min, cooling to 755-760 ℃ and preserving heat to obtain the modified silicon melt.
Further, the dosage ratio of the graphene nanoplatelets to the absolute ethyl alcohol in the step S1 is 3.2-3.8mg:300-400mL.
Further, the dosage ratio of the aluminum powder, the zirconium boride and the absolute ethyl alcohol in the step S2 is 0.15-0.16g:25.6-28.9mg:200-250mL.
Further, the condition of the vacuum hot-pressing sintering in the step S3 is that the temperature is 430-460 ℃ and the pressure is 65-70MPa.
Further, in step S5, the mass ratio of the preformed particles to the instant silicon is 1:5-7.
A silicon carbide thick epitaxial wafer with low surface resistance comprises the following preparation method:
a1, placing a silicon carbide substrate into a high-temperature annealing furnace, and introducing hydrogen for high-temperature annealing;
a2, carrying out liquid phase epitaxy on the silicon carbide substrate prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer;
a3, growing a second epitaxial layer on the silicon carbide wafer with the first epitaxial layer obtained in the step A2 by adopting a CVD method to obtain the silicon carbide thick epitaxial wafer with low surface resistance.
The invention has the beneficial effects that: the invention provides a silicon carbide thick epitaxial wafer and a preparation method thereof, and the novel point is that a traditional silicon source (such as silane, dichlorosilane and trichlorosilane) is replaced by a new modified silicon melt, so that the silicon source is provided for epitaxy, and more importantly, the problems of poor crystal defect and ablation resistance of the silicon carbide thick epitaxial wafer are solved. In the liquid phase epitaxy process, carbon atoms of the graphene nano-sheets in the modified silicon melt migrate to supplement carbon vacancies of an epitaxial layer, so that the purpose of repairing the carbon vacancies is achieved, and the purpose of prolonging the carrier life of the silicon carbide epitaxial wafer is achieved. And the carbon atoms of the graphene nanoplatelets are sp 2 The hybridization mode is used for covalent bond connection, so that the internal stress is lower, the bonding strength is better, and the hybrid material has excellent characteristics in the aspects of electricity, mechanics and optics.
Secondly, the prefabricated particles added in the modified silicon melt can lead the silicon carbide thick epitaxial wafer to have good anti-ablation performance, firstly, al has higher melting point and larger latent heat of phase change, and has high heat conductivity coefficient and high-temperature oxygen resistanceGood chemical property, is a better high-temperature phase change material, and oxidizes Al formed 2 O 3 Has the advantages of high melting point, low thermal expansion coefficient, good mechanical property, thermal shock stability, corrosion resistance and the like. In addition, the zirconia layer generated by zirconium boride oxidation serves as a heat insulating layer and prevents oxygen from diffusing into the internal SiC layer, and the zirconia can promote the viscous flow of a base layer, so that cracks can realize self-healing, and the requirements of good oxidation resistance and ablation resistance of the silicon carbide thick epitaxial wafer are met.
Drawings
The present invention is further described below with reference to the accompanying drawings for the convenience of understanding by those skilled in the art.
Fig. 1 is a schematic structural diagram of a low-area-resistance silicon carbide thick epitaxial wafer of the present invention.
In the figure, 1, a silicon carbide substrate; 2. a first epitaxial layer; 3. and a second epitaxial layer.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The modified silicon melt is prepared by the following steps:
step S1, placing 3.2mg graphene nano-sheets into a beaker containing 300mL of absolute ethyl alcohol, and performing ultrasonic dispersion with 430W power for 1h to obtain a mixed solution a;
s2, pouring 0.15g of aluminum powder and 25.6mg of zirconium boride into a beaker containing 200mL of absolute ethyl alcohol, and stirring for 50min at a rotating speed of 150rpm to obtain a mixed solution b;
step S3, mixing the mixed solution a and the mixed solution b, stirring at 53 ℃ and 1300rpm for 40min, vacuum drying for 24h, putting the dried powder into a ball mill in an argon atmosphere, ball milling at 400rpm for 3h, and finally vacuum hot-pressing sintering at 430 ℃ and 65MPa to obtain prefabricated particles;
step S4, respectively placing the prefabricated particles and the instant silicon in a resistance furnace, and preserving heat for 1h at 160 ℃ for later use;
step S5, placing the prefabricated particles treated in the step S4 into a graphite crucible, heating to melt, adding the instant silicon treated in the step S4 into the graphite crucible, stirring for 6min, cooling to 755 ℃ and preserving heat to obtain a modified silicon melt, wherein the mass ratio of the prefabricated particles to the instant silicon is 1:5.
example 2
The modified silicon melt is prepared by the following steps:
step S1, putting 3.5mg graphene nano sheets into a beaker containing 350mL of absolute ethyl alcohol, and performing 40-power ultrasonic dispersion for 1h to obtain a mixed solution a;
s2, pouring 0.15g of aluminum powder and 26.7mg of zirconium boride into a beaker containing 230mL of absolute ethyl alcohol, and stirring at 170rpm for 60min to obtain a mixed solution b;
step S3, mixing the mixed solution a and the mixed solution b, stirring for 45min at 54 ℃ and 1350rpm, vacuum drying for 24h, putting the dried powder into a ball mill in an argon atmosphere, ball milling for 3h at 450rpm, and finally vacuum hot-pressing sintering at 440 ℃ and 68MPa to obtain prefabricated particles;
step S4, respectively placing the prefabricated particles and the instant silicon in a resistance furnace, and preserving heat at 170 ℃ for 1 hour for later use;
step S5, placing the prefabricated particles treated in the step S4 into a graphite crucible, heating to melt, adding the instant silicon treated in the step S4 into the graphite crucible, stirring for 7min, cooling to 757 ℃ and preserving heat to obtain a modified silicon melt, wherein the mass ratio of the prefabricated particles to the instant silicon is 1:6.
example 3
The modified silicon melt is prepared by the following steps:
step S1, placing 3.8mg graphene nano-sheets into a beaker containing 400mL of absolute ethyl alcohol, and performing ultrasonic dispersion with 450W power for 1.5 hours to obtain a mixed solution a;
s2, pouring 0.16g of aluminum powder and 28.9mg of zirconium boride into a beaker containing 250mL of absolute ethyl alcohol, and stirring at 200rpm for 70min to obtain a mixed solution b;
step S3, mixing the mixed solution a and the mixed solution b, stirring for 50min at 55 ℃ and 1400rpm, vacuum drying for 24h, putting the dried powder into a ball mill in an argon atmosphere, ball milling for 3.5h at 500rpm, and finally vacuum hot-pressing sintering at the temperature of 460 ℃ and the pressure of 70MPa to obtain prefabricated particles;
step S4, respectively placing the prefabricated particles and the instant silicon in a resistance furnace, and preserving heat for 1.5 hours at 180 ℃ for later use;
step S5, placing the prefabricated particles treated in the step S4 into a graphite crucible, heating to melt, adding the instant silicon treated in the step S4 into the graphite crucible, stirring for 8min, cooling to 760 ℃ and preserving heat to obtain a modified silicon melt, wherein the mass ratio of the prefabricated particles to the instant silicon is 1:7.
example 4
Referring to fig. 1, a silicon carbide thick epitaxial wafer with low surface resistance comprises a silicon carbide substrate 1, a first epitaxial layer 2 with a thickness of 0.4 μm, and a second epitaxial layer 3 with a thickness of 5 μm.
The silicon carbide thick epitaxial wafer with low surface resistance is prepared by the following steps:
step A1, placing a silicon carbide substrate 1 into a high-temperature annealing furnace, introducing hydrogen, and performing high-temperature annealing, wherein the flow rate of the hydrogen is 50slm, the temperature is kept at 1500 ℃, and the annealing time is 5min;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate 1 prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer 2, wherein the modified silicon melt prepared in the embodiment 1 is used as a silicon source, carbon powder is used as a carbon source, and the growth temperature is 2100 ℃;
and A3, growing a second epitaxial layer 3 on the silicon carbide wafer with the first epitaxial layer 2 prepared in the step A2 by adopting a CVD method, annealing at 1500 ℃, preserving heat for 20min, and cooling to room temperature to obtain a silicon carbide thick epitaxial wafer with low surface resistance, wherein the growth condition of the CAD method is that the growth pressure is 60mbar, the temperature is 1560 ℃, the hydrogen flow is 40slm, and the molar ratio of carbon to silicon is 0.6:1, the growth rate was 15 μm/h, wherein ethylene was used as a carbon source, trichlorosilane as a silicon source, and nitrogen as a dopant.
Example 5
Referring to fig. 1, a silicon carbide thick epitaxial wafer with low surface resistance comprises a silicon carbide substrate 1, a first epitaxial layer 2 with a thickness of 0.9 μm, and a second epitaxial layer 3 with a thickness of 10 μm.
The silicon carbide thick epitaxial wafer with low surface resistance is prepared by the following steps:
step A1, placing a silicon carbide substrate 1 into a high-temperature annealing furnace, introducing hydrogen, and performing high-temperature annealing, wherein the hydrogen flow is 80slm, the temperature is kept at 1550 ℃, and the annealing time is 21min;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate 1 prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer 2, wherein the modified silicon melt prepared in the embodiment 2 is used as a silicon source, carbon powder is used as a carbon source, and the growth temperature is 2200 ℃;
and A3, growing a second epitaxial layer 3 on the silicon carbide wafer with the first epitaxial layer 2 prepared in the step A2 by adopting a CVD method, annealing at 1600 ℃, preserving heat for 25min, and cooling to room temperature to obtain a silicon carbide thick epitaxial wafer with low surface resistance, wherein the growth condition of the CAD method is 130mbar, the temperature is 1600 ℃, the hydrogen flow is 100slm, the molar ratio of carbon to silicon is 0.8:1, the growth rate is 21 mu m/h, wherein ethylene is used as a carbon source, trichlorosilane is used as a silicon source, and nitrogen is used as a doping agent.
Example 6
Referring to fig. 1, a silicon carbide thick epitaxial wafer with low surface resistance comprises a silicon carbide substrate 1, a first epitaxial layer 2 with a thickness of 1.6 μm, and a second epitaxial layer 3 with a thickness of 18 μm.
The silicon carbide thick epitaxial wafer with low surface resistance is prepared by the following steps:
step A1, placing a silicon carbide substrate 1 into a high-temperature annealing furnace, introducing hydrogen, and performing high-temperature annealing, wherein the flow of the hydrogen is 100slm, the temperature is kept at 1600 ℃, and the annealing time is 30min;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate 1 prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer 2, wherein the modified silicon melt prepared in the embodiment 3 is used as a silicon source, carbon powder is used as a carbon source, and the growth temperature is 2300 ℃;
and A3, growing a second epitaxial layer 3 on the silicon carbide wafer with the first epitaxial layer 2 prepared in the step A2 by adopting a CVD method, annealing at 1700 ℃, preserving heat for 30min, and cooling to room temperature to obtain a silicon carbide thick epitaxial wafer with low surface resistance, wherein the growth condition of the CAD method is 220mbar, the temperature is 1650 ℃, the hydrogen flow is 190slm, the molar ratio of carbon to silicon is 1.1:1, the growth rate is 26 mu m/h, wherein ethylene is used as a carbon source, trichlorosilane is used as a silicon source, and nitrogen is used as a doping agent.
Comparative example 1
Silicon carbide epitaxial wafer with low surface resistance produced by Qingdao super carbon new material technology Co.
Comparative example 2
The method for producing a silicon carbide thick epitaxial wafer of comparative example 2 was different from example 4 in that trichlorosilane was used as a silicon source for liquid phase epitaxy in step A2.
Comparative example 3
Comparative example 3 was a method for producing a thick silicon carbide epitaxial wafer having low sheet resistance, referring to example 4, except that aluminum powder and zirconium boride were not added to the modified silicon melt.
The silicon carbide thick epitaxial wafers obtained in examples 4 to 6 and comparative examples 1 to 3 were subjected to the following performance test (1) using a Candela8520 defect tester; (2) Ablation resistance was tested with reference to the national army standard GJB323A-96 ablation test method for ablation Material, and the test results are shown in Table 1:
TABLE 1
As can be seen from Table 1, the silicon carbide thick epitaxial wafers prepared in examples 4 to 6 have less total defects, lower average mass ablation rate, and better carrier lifetime and ablation resistance than those prepared in comparative examples 1 to 3.
The preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (9)
1. The silicon carbide thick epitaxial wafer with low surface resistance is characterized by comprising a silicon carbide substrate (1), a first epitaxial layer (2) and a second epitaxial layer (3);
the silicon carbide thick epitaxial wafer with low surface resistance is prepared by the following steps:
step A1, placing a silicon carbide substrate (1) into a high-temperature annealing furnace, and introducing hydrogen for high-temperature annealing;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate (1) prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer (2);
and A3, growing a second epitaxial layer (3) on the silicon carbide wafer with the first epitaxial layer (2) prepared in the step A2 by adopting a CVD method, annealing, and cooling to room temperature to obtain the silicon carbide thick epitaxial wafer with low surface resistance.
2. The low surface resistance thick epitaxial wafer of silicon carbide of claim 1, wherein: the thickness of the first epitaxial layer (2) is 0.4-1.6 mu m, and the thickness of the second epitaxial layer (3) is 5-18 mu m.
3. The low surface resistance thick epitaxial wafer of silicon carbide of claim 1, wherein: and A2, performing liquid phase epitaxy by using a modified silicon melt as a silicon source and carbon powder as a carbon source, wherein the growth temperature is 2100-2300 ℃.
4. A low surface resistance thick epitaxial wafer of silicon carbide according to claim 3 wherein: the modified silicon melt is prepared by the following steps:
step S1, adding graphene nano sheets into absolute ethyl alcohol, and performing ultrasonic dispersion to obtain a mixed solution a;
s2, adding aluminum powder and zirconium boride into absolute ethyl alcohol, and uniformly stirring to obtain a mixed solution b;
step S3, mixing the mixed solution a and the mixed solution b, uniformly stirring, vacuum drying, ball milling the dried powder, and vacuum hot-pressing sintering to obtain prefabricated particles;
s4, respectively placing the prefabricated particles and the instant silicon into a resistance furnace for drying for later use;
and S5, placing the prefabricated particles treated in the step S4 into a graphite crucible, heating to melt, adding the instant silicon treated in the step S4 into the graphite crucible, cooling to 755-760 ℃ after the instant silicon is completely melted, and preserving heat to obtain the modified silicon melt.
5. The low surface resistance thick epitaxial wafer of claim 4, wherein: the dosage ratio of the graphene nano-sheets to the absolute ethyl alcohol in the step S1 is 3.2-3.8mg:300-400mL.
6. The low surface resistance thick epitaxial wafer of claim 4, wherein: the dosage ratio of the aluminum powder to the zirconium boride to the absolute ethyl alcohol in the step S2 is 0.15-0.16g:25.6-28.9mg:200-250mL.
7. The low surface resistance thick epitaxial wafer of claim 4, wherein: and the condition of vacuum hot-pressing sintering in the step S3 is that the temperature is 430-460 ℃ and the pressure is 65-70MPa.
8. The low surface resistance thick epitaxial wafer of claim 4, wherein: and step S5, the mass ratio of the prefabricated particles to the instant silicon is 1:5-7.
9. The method for preparing the silicon carbide thick epitaxial wafer with low surface resistance according to claim 1, which is characterized in that: the preparation method comprises the following preparation steps:
step A1, placing a silicon carbide substrate (1) into a high-temperature annealing furnace, and introducing hydrogen for high-temperature annealing;
step A2, carrying out liquid phase epitaxy on the silicon carbide substrate (1) prepared in the step A1 to obtain a silicon carbide wafer with a first epitaxial layer (2);
and A3, growing a second epitaxial layer (3) on the silicon carbide wafer with the first epitaxial layer (2) prepared in the step A2 by adopting a CVD method, annealing, and cooling to room temperature to obtain the silicon carbide thick epitaxial wafer with low surface resistance.
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| CN116230543A (en) * | 2022-12-13 | 2023-06-06 | 北京中科纳通电子技术有限公司 | Full-printing method of transistor |
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