CN117010305A - Semiconductor device and data transmission method - Google Patents
Semiconductor device and data transmission method Download PDFInfo
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- CN117010305A CN117010305A CN202210465354.8A CN202210465354A CN117010305A CN 117010305 A CN117010305 A CN 117010305A CN 202210465354 A CN202210465354 A CN 202210465354A CN 117010305 A CN117010305 A CN 117010305A
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000008054 signal transmission Effects 0.000 claims abstract description 139
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000872 buffer Substances 0.000 claims description 7
- 238000012937 correction Methods 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 description 28
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000013307 optical fiber Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000009365 direct transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12004—Combinations of two or more optical elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The invention relates to the technical field of semiconductors, and provides a semiconductor device and a data transmission method. Wherein the semiconductor device comprises: a first chip; a second chip; a photonic integrated circuit chip; a first plurality of electrical signal transmission lines configured to transmit electrical signals of the first chip to the second chip; and a second electric signal transmission line configured to transmit an electric signal of the second chip to the photonic integrated circuit chip, wherein the second chip is configured to convert the plurality of electric signals respectively transmitted by the first plurality of electric signal transmission lines into electric signals transmitted to the second electric signal transmission line, wherein each of the first plurality of electric signal transmission lines has a lower data transmission rate than the second electric signal transmission line.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a data transmission method.
Background
In recent years, photonic integrated circuits are increasingly used for optical communications, photonic computing, and optical interconnects. In general, in a semiconductor device integrated with a photonic integrated circuit, the photonic integrated circuit performs electrical signal data communication with other electronic chips, and it is important to ensure a high communication rate and reduce power consumption.
Disclosure of Invention
In one exemplary embodiment, a semiconductor device is provided, including: a first chip; a second chip; a photonic integrated circuit chip; a first plurality of electrical signal transmission lines configured to transmit electrical signals of the first chip to the second chip; and a second electric signal transmission line configured to transmit an electric signal of the second chip to the photonic integrated circuit chip, wherein the second chip is configured to convert the plurality of electric signals respectively transmitted by the first plurality of electric signal transmission lines into electric signals transmitted to the second electric signal transmission line, wherein each of the first plurality of electric signal transmission lines has a lower data transmission rate than the second electric signal transmission line.
In some embodiments, the second chip core is configured to serialize parallel data in a first plurality of electrical signal transmission lines and then transmit to one of the second electrical signal transmission lines.
In some embodiments, the photonic integrated circuit chip includes a modulator, the photonic integrated circuit chip driving the modulator with the electrical signal of the second electrical signal transmission line.
In some embodiments, the data transmission rate of each of the first plurality of electrical signal transmission lines is 8GBbps or less and the data transmission rate of the second electrical signal transmission line is 16Gbps or more.
In some embodiments, the data transmission rate of each of the first plurality of electrical signal transmission lines is less than or equal to 50% of the data transmission rate of the second electrical signal transmission line.
In some embodiments, the semiconductor device includes a substrate through which a first plurality of electrical signal transmission lines pass.
In some embodiments, the first chip includes at least one of a sender buffer, a forward error correction encoder, and a scrambler.
In one exemplary embodiment, a data transmission method of a semiconductor device is provided, including: the first chip sends parallel data to the second chip through a first plurality of electric signal transmission lines; the second chip converts the parallel data from the first plurality of electrical signal transmission lines into serial data; a second electrical signal transmission line transmits the serial data to a photonic integrated circuit chip; wherein each of the first plurality of electrical signal transmission lines has a lower data transmission rate than the second electrical signal transmission line.
In some embodiments, the data transmission rate of each of the first plurality of electrical signal transmission lines is 8GBbps or less and the data transmission rate of the second electrical signal transmission line is 16Gbps or more.
In some embodiments, the data transmission rate of each of the first plurality of electrical signal transmission lines is less than or equal to 50% of the data transmission rate of the second electrical signal transmission line.
In some embodiments, the semiconductor device includes a substrate through which a first plurality of electrical signal transmission lines pass.
In one exemplary embodiment, a semiconductor device is provided, including: a first chip; a second chip; a photonic integrated circuit chip; a third electrical signal transmission line configured to transmit an electrical signal of the photonic integrated circuit to the second chip; a fourth plurality of electrical signal transmission lines configured to transmit electrical signals of the second chip to the first chip; wherein the second chip is configured to convert the plurality of electrical signals respectively transmitted by the third electrical signal transmission lines into electrical signals transmitted to a fourth plurality of electrical signal transmission lines, wherein each of the fourth plurality of electrical signal transmission lines has a lower data transmission rate than the third electrical signal transmission lines.
In some embodiments, the second chip core is configured to deserialize serial data in the third electrical signal transmission line and then transmit to a fourth plurality of electrical signal transmission lines.
In some embodiments, the data transmission rate of each of the first plurality of electrical signal transmission lines is 8GBbps or less and the data transmission rate of the second electrical signal transmission line is 16Gbps or more.
In one exemplary embodiment, a data transmission method of a semiconductor device is provided, including: the photon integrated circuit chip sends serial data to the second chip through a third electric signal transmission line; the second chip converts the serial data from the third electric signal transmission line into parallel data; a fourth plurality of electrical signal transmission lines transmitting the parallel data to the first chip; wherein each of the fourth plurality of electrical signal transmission lines has a lower data transmission rate than the third electrical signal transmission line.
In some embodiments, a data transmission rate of each of the fourth plurality of electrical signal transmission lines is 8GBbps or less, and a data transmission rate of the third electrical signal transmission line is 16Gbps or more.
In some embodiments, the data transmission rate of each of the fourth plurality of electrical signal transmission lines is less than or equal to 50% of the data transmission rate of the third electrical signal transmission line.
In some embodiments, the semiconductor device includes a substrate through which a first plurality of electrical signal transmission lines pass.
In some embodiments, the semiconductor device includes an Interposer (Interposer) through which the first plurality of electrical signal transmission lines pass.
The data transmission method may be implemented by a semiconductor device.
In the invention, the relatively lower electric signal data transmission rate is arranged between the first chip and the second chip, the higher electric signal data transmission rate is arranged between the second chip and the photon integrated circuit chip, and the high power consumption required by the higher electric signal transmission rate is reduced, thereby saving the power consumption, simplifying the design of the circuit unit required by the transmission between the first chip and the second chip, and simultaneously ensuring the data input and output rate of the photon integrated circuit chip.
Various aspects, features, advantages, etc. of embodiments of the invention will be described in detail below with reference to the accompanying drawings. The above aspects, features, advantages and the like of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Drawings
FIG. 1 shows a schematic diagram of a semiconductor device of one embodiment;
fig. 2 shows a schematic diagram of a semiconductor device of an embodiment.
Detailed Description
In order to facilitate understanding of the various aspects, features and advantages of the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the various embodiments described below are for illustration only and are not intended to limit the scope of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B. Herein, the chip may include a bare chip (die).
As shown in fig. 1, there is provided a semiconductor device including: a first chip, a second chip, and a photonic integrated circuit chip; a first plurality of electrical signal transmission lines configured to transmit electrical signals of the first chip to the second chip; and a second electric signal transmission line configured to transmit an electric signal of the second chip to the photonic integrated circuit chip, wherein the second chip is configured to convert the plurality of electric signals respectively transmitted by the first plurality of electric signal transmission lines into electric signals transmitted to the second electric signal transmission line, wherein each of the first plurality of electric signal transmission lines has a lower data transmission rate than the second electric signal transmission line.
In an exemplary embodiment, each of the first plurality of electrical signal transmission lines transmits data, for example, 2Gbps,8Gbps, and for example, 512Mbps to 8Gbps, to the second chip at a transmission rate of 1 to 8Gbps; the second chip serially processes the plurality of signals of the first plurality of electrical signal transmission lines to form a serial signal, e.g., a 56Gbps serial signal, that is input to the second electrical signal transmission line, which is transmitted to the photonic integrated circuit that may be used to drive a modulator in the photonic integrated circuit so that data originally represented by the electrical signal from the first chip may be converted to an optical signal representation. The transmission rate of the serial signal may be, for example, 16Gbps or more, for example, 16 to 56Gbps, and may be, for example, 16 to 100Gbps, but is not limited thereto. By way of example, the first set of electrical signal transmission lines may include 8 electrical signal transmission lines, the data transmitted by which are serially converted into 1-way serial data by parallel-to-serial conversion in the second chip, and transmitted to the photonic integrated circuit chip in 1 second electrical signal transmission line.
Therefore, the data transmission speed between the first chip and the second chip is relatively low, the transmission speed between the second chip and the photonic integrated circuit chip is relatively high, the electric signal transmission between the first chip and the second chip is not required to be designed with excessive circuit units, the power consumption is reduced, the photonic integrated circuit chip is ensured to receive the electric signal with relatively high transmission speed, the electric signal can be converted into an optical signal which propagates at a high speed in the photonic integrated circuit chip, the direct transmission of the low-speed electric signal of the first chip to the photonic integrated circuit chip can be avoided, and excessive connection ports are required. In addition, the first chip and the second chip can be manufactured independently by adopting proper manufacturing processes. The photonic integrated circuit chip can transmit an electrical signal to the second chip at a higher rate, and the second chip transmits a plurality of parallel signals at a lower rate to the first chip through a deserialization process, and the photonic integrated circuit chip outputs high-speed transmission of signals and the whole semiconductor device has lower power consumption. Further, power consumption may also be saved by smaller, lower power transmit output buffers, simpler CDR (clock and data recovery) units, simpler CTLEs.
Illustratively, as shown in fig. 1, the second chip includes a CRC encoder and a scrambler, and after receiving the electrical signals from the first plurality of electrical signal transmission lines, the second chip processes the electrical signals through the CRC encoder, the scrambler and the serializer, and the multiple parallel electrical signals are serialized into one (one) electrical signal and transmitted to the photonic integrated circuit through the second electrical signal transmission line.
In some embodiments, a common reference clock may be used in the first chip, the second chip, thereby simplifying the clock recovery circuit and reducing the complexity of the circuit design.
For example, the second chip and the photonic integrated circuit chip may have a plurality of second electric signal transmission lines, for example, 6 (6) second electric signal transmission lines, and the first chip and the second chip may have 48 (48) first electric signal transmission lines, and after serializing processing of the second chip, 1 (1) of the second electric signal transmission lines transmit data from 8 first electric signal transmission lines. Wherein 1 second electric signal transmission line corresponds to the data of a group of 8 first electric signal transmission lines.
The semiconductor device may further include a third electric signal transmission line and a fourth group of electric signal transmission lines, for example. The photonic integrated circuit chip may output an electrical signal to the second chip via a third electrical signal transmission line. For example, an optical signal propagated by an optical waveguide in the photonic integrated circuit is photoelectrically converted into an electrical signal, which is transmitted in a third electrical signal transmission line, and output to the second chip. The second chip deserializes the higher transmission rate electrical signal from the photonic integrated circuit chip to form a plurality of electrical signals (multiplexed electrical signals) that are transmitted to the first chip in a fourth plurality of electrical signal transmission lines. Illustratively, the photonic integrated circuit chip transmits electrical signals of 16 to 56Gbps to the second chip via a third electrical signal transmission line. Illustratively, the second chip transmits a plurality of (multiplexed) parallel electrical signals to the first chip via a fourth plurality of electrical signal transmission lines, each of which has a relatively low electrical signal transmission rate, e.g., 1Gbps to 8Gbps.
Illustratively, the data transmission rate of each of the first plurality of electrical signal transmission lines is 50% or less of the data transmission rate of the second electrical signal transmission line, and illustratively, the former is 10% to 50%, such as 20% to 30% of the latter.
The second chip includes a Deserializer (descrambler), a descrambler, and a CRC decoding module, and after receiving the electrical signals transmitted from the photonic integrated circuit, the second chip processes the electrical signals through the Deserializer, the descrambler, and the CRC decoding module, and deserializes the serial electrical signals into a plurality of parallel signals, and transmits the parallel signals to the first chip through a fourth plurality of electrical signal transmission lines, so that data from the photonic integrated circuit can be transmitted to the first chip.
By way of example, the data layer in the first chip may include modules, units, lines, etc. that receive or transmit data.
In some embodiments, the semiconductor device includes an Interposer (Interposer) that may serve as a carrier substrate, and the first chip and the second chip may be packaged by the Interposer (Interposer), such as a silicon Interposer, through which the first plurality of electrical signal transmission lines may pass, for example, and the first chip and the second chip may be disposed on the same side of the silicon Interposer or on both sides of the silicon Interposer. In some embodiments, each of the first plurality of electrical signal transmission lines includes a TSV structure to provide more conductive paths to accommodate I/O port requirements of the first chip, the second chip. The second electrical signal transmission line, the third electrical signal transmission line, and the fourth plurality of electrical signal transmission lines may also pass through the interposer. For example, the semiconductor device may include a substrate, and the first chip and the second chip may be disposed on the substrate.
Illustratively, various electrical signal transmission lines herein may include electrically conductive wires, electrical connection contacts, soldered structures, or the like.
The photonic integrated circuit chip can also comprise optical coupling interfaces, waveguides, photoelectric conversion units, electro-optical conversion units, photoelectric conversion units and other photonic devices, and the number of the various photonic devices can be configured as required, and can be one or more. The electro-optical conversion unit may include a modulator to convert an electrical signal into an optical signal, for example. Illustratively, the optical coupling interface may be used to optically couple with a laser or an optical fiber to input or output an optical signal, e.g., using the optical fiber for input or output of an optical signal; the optical coupling interface may include a grating coupler, an end-face coupler, or the like. Illustratively, a waveguide may be used to propagate an optical signal, serving as a channel for information propagation. By way of example, the photoelectric conversion unit may comprise a photo detector for converting an optical signal into an electrical signal, which photo detector may comprise, for example, a photodiode.
For example, the waveguide in the photonic integrated circuit may input an initial optical signal that does not carry information through the first optical coupling interface, and after being modulated by an electrical signal, an optical signal carrying information is generated, and the optical signal carrying information may be output through the second optical coupling structure, for example, to an optical fiber.
For example, one optical coupling interface of the photonic integrated circuit may be used to receive an information-bearing optical signal from an optical fiber, which is converted to an electrical signal in the photonic integrated circuit and then transmitted to a second chip.
In some embodiments, high-speed transmitted electrical signals input to the photonic integrated circuit chip are converted to optical signals. For example, modulation of light by an electrical signal may be implemented by a modulator, whereby an electrical signal carrying data is converted into an optical signal, whereby data or information output by the first chip is transmitted via the second chip to the photonic integrated circuit chip, where the electrical signal is converted into an optical signal for transmitting the data or information, which may also be used for photonic calculations. Illustratively, the modulator may employ, for example, a micro-ring modulator that may support high modulation rates based on carrier depletion effects.
In some embodiments, an optical signal carrying data or information is transmitted in a waveguide and then output through an optical coupling interface, such as to an optical fiber.
In the embodiment of fig. 2, which illustrates one example of the semiconductor device, in the first chip, an electric signal of initial data passes through a transmitting side Buffer (Tx Buffer), a forward error correction Encoder (FEC Encoder), a Scrambler (Scrambler) to process the signal, for example, to form an electric signal of 8Gbps. Wherein a forward error correction Encoder (FEC Encoder) may perform error correction encoding and a scrambler performs scrambling. The first plurality of electrical signal lines may comprise a plurality of electrical signal lines at a transmission rate of 8Gbps, and further, the second chip may comprise a serializer, an amplifying circuit, or other necessary circuitry for serializing, the plurality of (multiple) 8Gbps transmission rate electrical signals being serialized into one (multiple) serial signal, the serial signal being transmitted at a transmission rate of 40Gbps,56Gbps, to the photonic integrated circuit in the second electrical signal line, which may be used for modulating light, for example.
As shown in fig. 2, the electrical signal from the photonic integrated circuit may be transmitted to the second chip through a third electrical signal transmission line. The second chip of the optical integrated circuit comprises a Deserializer (Deserizer), after receiving the electric signal transmitted by the optical integrated circuit, the second chip deserializes the serial data into a plurality of parallel data, and the parallel data is transmitted to the first chip through a fourth plurality of electric signal transmission lines. Thus, data from the photonic integrated circuit may be transferred to the first chip.
The first chip may include a Descrambler (Descrambler), a forward error correction Decoder (FEC Decoder), a receiver Buffer (Rx Buffer), and process data represented by the electrical signal from the second chip. Illustratively, the data is processed sequentially through a descrambler, a forward error correction decoder, and a receiver buffer.
It will be appreciated by those skilled in the art that the foregoing disclosure is merely illustrative of the present invention and that no limitation on the scope of the claimed invention is intended, as defined by the appended claims and equivalents thereof.
Claims (19)
1. A semiconductor device, comprising:
a first chip;
a second chip;
a photonic integrated circuit chip;
a first plurality of electrical signal transmission lines configured to transmit electrical signals of the first chip to the second chip;
a second electrical signal transmission line configured to transmit an electrical signal of the second chip to the photonic integrated circuit chip, wherein,
the second chip is configured to convert a plurality of electric signals respectively transmitted by the first plurality of electric signal transmission lines into electric signals transmitted to a second electric signal transmission line, wherein each of the first plurality of electric signal transmission lines has a lower data transmission rate than the second electric signal transmission line.
2. The semiconductor device according to claim 1, wherein the second chip core is configured to serialize parallel data in a first plurality of electric signal transmission lines and then transmit to one of the second electric signal transmission lines.
3. The semiconductor device according to claim 1, wherein the photonic integrated circuit chip includes a modulator, the photonic integrated circuit chip driving the modulator with an electrical signal of the second electrical signal transmission line.
4. The semiconductor device according to claim 1, wherein a data transmission rate of each of the first plurality of electric signal transmission lines is 8GBbps or less, and a data transmission rate of the second electric signal transmission line is 16Gbps or more.
5. The semiconductor device according to claim 1, wherein a data transmission rate of each of the first plurality of electric signal transmission lines is 50% or less of a data transmission rate of the second electric signal transmission line.
6. The semiconductor device according to any one of claims 1 to 4, comprising a substrate through which the first plurality of electric signal transmission lines pass.
7. The semiconductor apparatus of any one of claims 1-4, wherein the first chip comprises at least one of a transmit side buffer, a forward error correction encoder, and a scrambler.
8. A data transmission method of a semiconductor device, comprising:
the first chip sends parallel data to the second chip through a first plurality of electric signal transmission lines;
the second chip converts the parallel data from the first plurality of electrical signal transmission lines into serial data;
a second electrical signal transmission line transmits the serial data to a photonic integrated circuit chip;
wherein each of the first plurality of electrical signal transmission lines has a lower data transmission rate than the second electrical signal transmission line.
9. The data transmission method according to claim 8, wherein a data transmission rate of each of the first plurality of electric signal transmission lines is 8GBbps or less, and a data transmission rate of the second electric signal transmission line is 16Gbps or more.
10. The data transmission method according to claim 8, wherein a data transmission rate of each of the first plurality of electric signal transmission lines is 50% or less of a data transmission rate of the second electric signal transmission line.
11. A data transmission method as claimed in any one of claims 8 to 10, said semiconductor device comprising a substrate through which a first plurality of electrical signal transmission lines pass.
12. The data transmission method of any one of claims 8-10, wherein the semiconductor device includes an Interposer (Interposer) through which the first plurality of electrical signal transmission lines pass.
13. A semiconductor device, comprising:
a first chip;
a second chip;
a photonic integrated circuit chip;
a third electrical signal transmission line configured to transmit an electrical signal of the photonic integrated circuit to the second chip;
a fourth plurality of electrical signal transmission lines configured to transmit electrical signals of the second chip to the first chip;
wherein,
the second chip is configured to convert the plurality of electric signals respectively transmitted by the third electric signal transmission lines into electric signals transmitted to a fourth plurality of electric signal transmission lines, wherein each of the fourth plurality of electric signal transmission lines has a lower data transmission rate than the third electric signal transmission lines.
14. The semiconductor device according to claim 13, wherein the second chip core is configured to deserialize serial data in the third electric signal transmission line and then transmit to a fourth plurality of electric signal transmission lines.
15. The semiconductor device according to claim 13, wherein a data transmission rate of each of the first plurality of electric signal transmission lines is 8GBbps or less, and a data transmission rate of the second electric signal transmission line is 16Gbps or more.
16. A data transmission method of a semiconductor device, comprising:
the photon integrated circuit chip sends serial data to the second chip through a third electric signal transmission line;
the second chip converts the serial data from the third electric signal transmission line into parallel data;
a fourth plurality of electrical signal transmission lines transmitting the parallel data to the first chip;
wherein each of the fourth plurality of electrical signal transmission lines has a lower data transmission rate than the third electrical signal transmission line.
17. The data transmission method according to claim 16, wherein a data transmission rate of each of the fourth plurality of electric signal transmission lines is 8GBbps or less, and a data transmission rate of the third electric signal transmission line is 16Gbps or more.
18. The data transmission method according to claim 16, wherein a data transmission rate of each of the fourth plurality of electric signal transmission lines is 50% or less of a data transmission rate of the third electric signal transmission line.
19. The data transmission method of any one of claims 16-18, wherein the semiconductor device includes an Interposer (Interposer) through which the first plurality of electrical signal transmission lines pass.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210465354.8A CN117010305A (en) | 2022-04-29 | 2022-04-29 | Semiconductor device and data transmission method |
| PCT/CN2023/091054 WO2023208089A1 (en) | 2022-04-29 | 2023-04-27 | Semiconductor device and data transmission method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210465354.8A CN117010305A (en) | 2022-04-29 | 2022-04-29 | Semiconductor device and data transmission method |
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| Publication Number | Publication Date |
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| CN117010305A true CN117010305A (en) | 2023-11-07 |
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| CN202210465354.8A Pending CN117010305A (en) | 2022-04-29 | 2022-04-29 | Semiconductor device and data transmission method |
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| CN (1) | CN117010305A (en) |
| WO (1) | WO2023208089A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101857677B1 (en) * | 2011-07-21 | 2018-05-14 | 에스케이하이닉스 주식회사 | Semiconductor integrated circuit and method of transmitting signal thereof |
| KR20140082338A (en) * | 2012-12-24 | 2014-07-02 | 에스케이하이닉스 주식회사 | Semiconductor integrated circuit |
| CN203301663U (en) * | 2013-05-31 | 2013-11-20 | 深圳市载德光电技术开发有限公司 | DVI signal multimode single-optical-fiber transmitter |
| TW202209323A (en) * | 2020-02-14 | 2022-03-01 | 美商爾雅實驗室公司 | Remote memory architectures enabled by monolithic in-package optical i/o |
| CN213547715U (en) * | 2020-12-09 | 2021-06-25 | 深圳市朗强科技有限公司 | High-definition video data sending device, receiving device and transmission system |
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2022
- 2022-04-29 CN CN202210465354.8A patent/CN117010305A/en active Pending
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| WO2023208089A1 (en) | 2023-11-02 |
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