CN213547715U

CN213547715U - High-definition video data sending device, receiving device and transmission system

Info

Publication number: CN213547715U
Application number: CN202022932195.7U
Authority: CN
Inventors: 高炳海
Original assignee: Shenzhen Lenkeng Technology Co Ltd
Current assignee: Shenzhen Lenkeng Technology Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-06-25
Anticipated expiration: 2030-12-09

Abstract

The utility model discloses a high definition video data's transmitting device, receiving arrangement and transmission system, transmission system includes: the device comprises an input interface, a conversion chip, a first integrated circuit and a first communication module; the input interface is used for receiving high-definition video data in different color space formats; the conversion chip is used for outputting the high-definition video data to the first integrated circuit through a first communication time sequence interface of the conversion chip; the first integrated circuit is used for processing the high-definition video data to obtain a data packet; the first communication module is used for sending the data packet; the transmission rate of the first communication module is not lower than a first threshold; the input interface, the conversion chip, the first integrated circuit and the first communication module are connected in sequence. Adopt the utility model discloses, the first communication module of sending equipment accessible reaches and transmits high definition video data for receiving arrangement based on net twine or optic fibre, can realize the super low time delay transmission of high definition video that the quality is harmless.

Description

High-definition video data sending device, receiving device and transmission system

Technical Field

The utility model relates to the field of communication technology, especially, relate to high definition video data's transmitting device, receiving equipment and transmission system.

Background

With the rapid development of science and technology, people have increasingly high requirements on aspects such as definition, image quality or fluency during video playing, and have increasingly long requirements on video transmission distance, but the data volume of high-definition video is large, so that higher transmission bandwidth is required.

Disclosure of Invention

Based on the defect of problem and prior art that exist above, the utility model provides a high definition video data's transmitting device, receiving equipment and transmission system, the first communication module of transmitting device accessible and based on net twine or optic fibre will not have compressed high definition video data to transmit for receiving equipment, can realize the super low time delay transmission of high definition video that the quality is harmless.

In a first aspect, the utility model provides a high definition video data's transmitting device, this transmitting device includes:

the device comprises an input interface, a conversion chip, a first integrated circuit and a first communication module; the input interface is used for receiving high-definition video data in different color space formats; the conversion chip is used for outputting the high-definition video data to the first integrated circuit through a first communication time sequence interface of the conversion chip; the first integrated circuit is used for processing the high-definition video data to obtain a data packet; the first communication module is used for sending the data packet; the transmission rate of the first communication module is not lower than a first threshold; the input interface, the conversion chip, the first integrated circuit and the first communication module are connected in sequence.

In a second aspect, the utility model provides a high definition video data's transmitting device, this transmitting device includes:

the device comprises an input interface, a first integrated circuit and a first communication module; the input interface is used for receiving high-definition video data in different color space formats; the first integrated circuit is used for processing the high-definition video data to obtain a data packet; the first communication module is used for sending the data packet; the transmission rate of the first communication module is not lower than a first threshold.

The third aspect, the utility model provides a high definition video data's receiving equipment, this receiving equipment includes:

the second communication module, the second integrated circuit, the conversion chip and the output interface; the second communication module is used for acquiring a data packet; the second integrated circuit is used for processing the data packet to obtain high-definition video data; the conversion chip is used for outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip; the transmission rate of the second communication module is not lower than a second threshold; an output interface for: and outputting the high-definition video data to an output device connected with the receiving device.

In a fourth aspect, the utility model provides a receiving equipment of high definition video data, this receiving equipment includes:

a second communication module, a second integrated circuit and an output interface; the second communication module is used for acquiring a data packet; the second integrated circuit is used for processing the data packet to obtain high-definition video data; the transmission rate of the second communication module is not lower than a second threshold; an output interface for: and outputting the high-definition video data to an output device connected with the receiving device.

In a fifth aspect, the utility model provides a high definition video data's transmission system, this transmission system includes:

a transmitting device and a receiving device; the sending equipment and the receiving equipment are connected based on network cables or optical fibers; wherein the content of the first and second substances,

the transmission apparatus includes: the device comprises an input interface, a conversion chip, a first integrated circuit and a first communication module; the input interface, the conversion chip, the first integrated circuit and the first communication module are connected with each other;

the sending device is configured to:

receiving high-definition video data through the input interface, and converting the high-definition video data into high-definition video data through the conversion chip; processing the high-definition video data into a data packet through the first integrated circuit, and transmitting the data packet through the first communication module;

the receiving apparatus includes: the device comprises a second communication module, a second integrated circuit and a conversion chip;

the receiving device is configured to:

the second communication module is used for acquiring a data packet, the second integrated circuit is used for processing the data packet to acquire high-definition video data, and a conversion chip is used for converting the high-definition video data into the high-definition video data.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

Fig. 1 to 20 are schematic structural diagrams of a transmitting apparatus for high definition video data according to the present invention;

fig. 21 to 40 are schematic structural diagrams of a receiving device for high definition video data provided by the present invention;

fig. 41 is a schematic diagram of a transmission system for high definition video data provided by the present invention.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention.

Referring to fig. 1, it is a schematic structural diagram of a sending device for high definition video data with different color space formats according to the present invention. As shown in fig. 1, the transmitting device 10, may include, but is not limited to: the input interface 101, the first integrated circuit 102, and the first communication module 103 may further include a conversion chip, and it should be noted that the conversion chip and the first integrated circuit 102 are respectively and independently integrated in the transmitting device 10; wherein the content of the first and second substances,

an input interface 101, configured to receive high definition video data in different color space formats;

the conversion chip is used for outputting the high-definition video data to the first integrated circuit through a first communication time sequence interface of the conversion chip after receiving the high-definition video data through an interface coupled with the input interface 101;

wherein, first communication chronogenesis interface includes: LVDS (Low-Voltage Differential Signaling) interface, ttl (Transistor logic) interface, MIPI interface, or custom interface. It should be noted that the LVDS interface or the TTL interface is an interface for separately transmitting audio and video in the high-definition video data; the custom interface is an interface for mixed transmission of audio and video in high-definition video data.

A first integrated circuit 102 operable to process high definition video data into data packets based on a communication protocol;

the first communication module 103 is configured to transmit a data packet.

It should be noted that the high definition video data in different color space formats in the embodiment of the present application is source data or raw data.

It should be noted that the high definition video data in different color space formats described above may include, but is not limited to: such as text, data, sound, graphics, image, or video (e.g., high definition video with 1080P, 4K, or 8K resolution, frame rate of 30FPS, 60FPS, 100FPS, or 120 FPS), and the like. High definition video data may also include, but is not limited to, the following features: high Dynamic Range hdr (high Dynamic Range imaging), the different color space format may be 4: 2: YUV method of 2, 4: 2: YUV method of 0, 4: 4: 4 YUV mode or 8bit depth RGB mode.

It should be noted that the input interface 101 may include, but is not limited to:

an HDMI (High Definition Multimedia Interface) Interface, a Type-C Interface, a dp (displayport) Interface, a usb (universal serial bus) Interface, a VGA Interface, an LVDS Interface, a TTL Interface, a dvi (digital visual Interface) Interface, or an mipi (mobile Industry Processor Interface) Interface.

The communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the first integrated circuit 102 may include, but is not limited to: an FPGA chip or an ASIC chip.

The first integrated circuit 102 may be specifically configured to:

packaging high-definition video data into a UDP data packet based on a UDP communication protocol; or

Packaging high-definition video data into a TCP data packet based on a TCP communication protocol; or

And packaging the high-definition video data into a custom data packet based on a custom communication protocol.

It should be noted that the first integrated circuit 102 may be further configured to:

the method comprises the steps of compressing high-definition video data based on a distortion-free coding algorithm to obtain first data, and packaging the first data through a communication protocol to obtain a data packet.

A distortion-free encoding algorithm comprising:

run length coding algorithm, Huffman coding algorithm, constant block coding algorithm of binary image, quad-tree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm.

Taking the customized arithmetic coding algorithm as an example, the first integrated circuit 102 may compress redundant data in the high definition video data based on the customized arithmetic coding algorithm to obtain first data, and encapsulate the first data through a communication protocol to obtain a data packet.

For example, when the high definition video data is 0 occupying 6 bytes, that is, 000000000000, the first integrated circuit compresses the redundant data in the high definition video data based on the custom arithmetic coding algorithm, and then obtains the first data (0600) only occupying 2 bytes, thereby realizing compression of the redundant data in the high definition video data.

It should be noted that the transmission rate of the first communication module 103 is not lower than the first threshold;

the first communication module 103 may include, but is not limited to: an electrical or optical module, wherein the electrical module comprises: the system comprises a PHY chip and an RJ-45 interface, wherein the transmission rate of an optical module is not lower than a first threshold; the transmission rate of the electrical module is not less than a first threshold; the first threshold may include, but is not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps, or 25 Gbps.

The transmitting device 10 may be further configured to:

outputting the data packet to the receiving device through the first communication module after the transmitting device 10 transmits the data packet to the first communication module 103; alternatively, the first and second electrodes may be,

after the sending device 10 sends the data packet to the first communication module 103, the data packet is output to the switch through the first communication module, and the switch is operable to forward the data packet to the receiving device.

It should be understood that the transmitting device 10 of fig. 1 is only one example provided by the embodiments of the present application, and that the transmitting device 10 may have more or less components than those shown, may combine two or more components, or may have a different configuration implementation of the components.

Referring to fig. 1, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 2, the transmitting device 10 includes: the device comprises an input interface 101, a conversion chip, an FPGA chip and an electric module.

The FPGA chip can be used for:

after the high definition video data output through the first communication timing interface of the conversion chip is output to the FPGA chip, the high definition video data is encapsulated into UDP packets based on the UDP communication protocol, or,

after the high definition video data output through the first communication timing interface of the conversion chip is output to the FPGA chip, it is packaged as a TCP packet based on the TCP communication protocol, or,

and after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the FPGA chip, the high-definition video data are packaged into a custom data packet based on a custom communication protocol.

An electrical module comprising: a PHY chip (ethernet physical layer data transceiver) and an RJ-45 interface; an electrical module operable to:

after the FPGA chip outputs the data packet to the MAC unit integrated in the FPGA chip and outputs the data packet to the PHY chip through the second communication timing interface of the MAC unit,

the UDP data packet is output to the RJ-45 interface after being modulated by the PHY chip, and is sent to the receiving equipment by the RJ-45 interface, or,

the TCP data packet is output to the RJ-45 interface after being modulated by the PHY chip, and is sent to the receiving device by the RJ-45 interface, or,

the user-defined data packet is output to the RJ-45 interface after being modulated by the PHY chip and is sent to the receiving equipment by the RJ-45 interface,

alternatively, the first and second electrodes may be,

after the FPGA chip outputs the data packet to an MAC unit integrated in the FPGA chip and outputs the data packet to a PHY chip through a second communication time sequence interface of the MAC unit, the PHY chip outputs the UDP data packet to an RJ-45 interface after coding and modulating, and the UDP data packet is sent to a switch through the RJ-45 interface, the switch is used for forwarding the UDP data packet to receiving equipment, or,

the TCP data packet is output to the RJ-45 interface after being coded and modulated by the PHY chip, and is sent to the switch by the RJ-45 interface, and the switch is used for forwarding the TCP data packet to the receiving equipment, or,

the PHY chip is used for outputting the custom data packet to the RJ-45 interface after coding and modulating, and sending the custom data packet to the switch through the RJ-45 interface, and the switch is used for forwarding the custom data packet to the receiving equipment.

It should be noted that, when the receiving apparatus includes: the first receiving device and the second receiving device,

the electrical module is for:

after the FPGA chip outputs the data packet to an MAC unit integrated in the FPGA chip and outputs the data packet to a PHY chip through a second communication time sequence interface of the MAC unit, the data packet is output to an RJ-45 interface after being coded and modulated through the PHY chip and is sent to a first receiving device and a second receiving device through the RJ-45 interface, or,

and the data packet is output to the RJ-45 interface after being coded and modulated through the PHY chip and is sent to the switch through the RJ-45 interface, and the switch is used for forwarding the data packet to the first receiving equipment and the second receiving equipment. The second communication timing interface may include, but is not limited to: an XFI interface, an MII (Media Independent interface) interface, a GMII (Gigabit Media Independent interface) interface, an SGMII (serial Media Independent interface) interface, an RGMII (reduced Media Independent interface) interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAAUI interface.

It should be noted that the functions or definitions of the interfaces or modules not specifically set forth in fig. 2 refer to the embodiment of fig. 1.

Referring to fig. 1, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an electrical module, as shown in fig. 3, the transmitting device 10 includes: an input interface 101, a conversion chip, an ASIC chip, and an electrical module.

An ASIC chip operable to:

after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the ASIC chip, the high-definition video data are packaged into UDP data packets based on a UDP communication protocol; alternatively, the first and second electrodes may be,

after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the ASIC chip, the high-definition video data are packaged into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the ASIC chip, the high-definition video data are packaged into a custom data packet based on a custom communication protocol;

when the reception apparatus includes: the first receiving device and the second receiving device,

the electrical module is for:

after the ASIC chip outputs the packet to the MAC unit integrated in the ASIC chip, the packet is output to the PHY chip through the second communication timing interface of the MAC unit,

the data packet is encoded and modulated by the PHY chip and then output to the RJ-45 interface, and then sent to the first receiving device and the second receiving device through the RJ-45 interface, or,

and the data packet is output to the RJ-45 interface after being coded and modulated through the PHY chip and is sent to the switch through the RJ-45 interface, and the switch is used for forwarding the data packet to the first receiving equipment and the second receiving equipment.

It should be noted that the functions or definitions of the interfaces or modules not specifically set forth in fig. 3 refer to the embodiments of fig. 1 or 2.

Referring to fig. 1, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an optical module, as shown in fig. 4, the transmitting device 10 includes: input interface 101, conversion chip, FPGA chip and optical module.

The FPGA chip can be used for:

after the high definition video data output through the first communication timing interface of the conversion chip is output to the FPGA chip, the high definition video data is packaged into UDP packets based on the UDP communication protocol, or,

after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the FPGA chip, the high-definition video data are packaged into a custom data packet based on a custom communication protocol;

an optical module operable to:

after the FPGA chip outputs the data packet to the MAC unit integrated in the FPGA chip and outputs the data packet to the optical module through the second communication time sequence interface of the MAC unit,

converts the UDP packet into an optical signal and transmits the optical signal to a receiving device, or,

converts the TCP packets to optical signals and transmits the optical signals to the receiving device, or,

the custom packet is converted to an optical signal and the optical signal is sent to a receiving device, or,

converts the UDP packet into an optical signal and sends the optical signal to a switch, which forwards the optical signal to a receiving device, or,

converts the TCP packets to optical signals and sends the optical signals to the switch, which forwards the optical signals to the receiving device, or,

and converting the custom data packet into an optical signal, and sending the optical signal to an exchanger, wherein the exchanger is used for forwarding the optical signal to the receiving equipment.

the optical module is used for:

converting the data packet into an optical signal and transmitting the optical signal to the first receiving device and the second receiving device, or,

the optical module is used for converting the data packet into an optical signal and sending the optical signal to the switch, and the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.

It should be noted that the function or definition of the interface or module not detailed in fig. 4 refers to the embodiment of fig. 1.

Referring to fig. 1, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an optical module, as shown in fig. 5, the transmitting device 10 includes: input interface 101, conversion chip, ASIC chip and optical module.

An ASIC chip operable to:

and after the high-definition video data output by the first communication time sequence interface of the conversion chip is output to the ASIC chip, the high-definition video data are packaged into a custom data packet based on the custom communication protocol.

the optical module is used for:

after the ASIC chip outputs the data packet to the MAC unit integrated in the ASIC chip, the data packet is output to the optical module through the second communication timing interface of the MAC unit,

converts the data packet into an optical signal and transmits the optical signal to the first receiving device and the second receiving device, or,

the optical module is used for:

and converting the data packet into an optical signal and sending the optical signal to the switch, wherein the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.

It should be noted that, please refer to the embodiments of fig. 1 and 4 for the functions or definitions of the interfaces or modules not detailed in fig. 5.

Referring to fig. 6, it is a schematic structural diagram of another high definition video data sending device provided in the present invention. As shown in fig. 6, the transmitting device 10, may include but is not limited to: the input interface 101, the first integrated circuit 102, and the first communication module 103 may further include: a conversion chip, wherein the conversion chip is integrated inside the first integrated circuit 102;

an input interface 101 for receiving high definition video data;

a first integrated circuit 102 operable to process high definition video data into data packets;

the first integrated circuit 102 may be specifically configured to:

after outputting the high-definition video data to the first integrated circuit through the first communication time sequence interface of the conversion chip, packaging the high-definition video data into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

after the high-definition video data are output to the first integrated circuit through the first communication time sequence interface of the conversion chip, the high-definition video data are packaged into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

after the high-definition video data are output to the first integrated circuit through the first communication time sequence interface of the conversion chip, the high-definition video data are packaged into a custom data packet based on a custom communication protocol.

after the high-definition video data are output to the first integrated circuit through the first communication time sequence interface of the conversion chip, the high-definition video data are compressed based on a distortion-free coding algorithm to obtain first data, and the first data are packaged through the communication protocol (such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol) to obtain a data packet.

A distortion-free encoding algorithm comprising:

run length coding algorithm, Huffman coding algorithm, constant block coding algorithm of binary image, quad-tree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm. The first communication module 103 is configured to transmit a data packet.

It should be noted that the function or definition of the interface or module not detailed in fig. 6 refers to the embodiment of fig. 1.

Referring to fig. 6, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 7, the transmitting device 10 may include, but is not limited to: the input interface 101, the FPGA chip and the electric module, wherein, the FPGA chip is integrated with a conversion chip.

The FPGA chip can be used for:

the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip is packaged into a UDP data packet based on a UDP communication protocol, or,

the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip is packaged into a TCP data packet based on a TCP communication protocol, or,

and packaging the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip into a custom data packet based on a custom communication protocol.

after the FPGA chip outputs the data packet to an MAC unit integrated in the FPGA chip and outputs the data packet to a PHY chip through a second communication time sequence interface of the MAC unit, the PHY chip outputs the UDP data packet to the RJ-45 interface and sends the UDP data packet to receiving equipment through the RJ-45 interface, or,

the TCP packets are output to the RJ-45 interface through the PHY chip, sent to the receiving device through the RJ-45 interface, or,

outputting the custom data packet to the RJ-45 interface through the PHY chip, and sending the custom data packet to receiving equipment through the RJ-45 interface;

alternatively, the first and second electrodes may be,

the UDP data packet is output to the RJ-45 interface through the PHY chip, and is sent to the switch through the RJ-45 interface, where the switch is configured to forward the UDP data packet to the receiving device, or,

the TCP packets are output to the RJ-45 interface through the PHY chip, sent to the switch through the RJ-45 interface, the switch is used to forward the TCP packets to the receiving device, or,

the PHY chip outputs the custom data packet to the RJ-45 interface, and the custom data packet is sent to the switch through the RJ-45 interface, and the switch is used for forwarding the custom data packet to the receiving equipment.

the electrical module is configured to:

outputting the data packet to the RJ-45 interface through the PHY chip, sending the data packet to the first receiving device and the second receiving device through the RJ-45 interface, or,

the data packet is output to the RJ-45 interface through the PHY chip, and is sent to a switch through the RJ-45 interface, and the switch is used for forwarding the data packet to the first receiving device and the second receiving device.

It should be noted that, please refer to the embodiments of fig. 1 and fig. 6 for the functions or definitions of the interfaces or modules not detailed in fig. 7.

Referring to fig. 6, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an electrical module, as shown in fig. 8, the transmitting device 10 may include, but is not limited to: an input interface 101, an ASIC chip, and an electrical module, wherein the ASIC chip has a conversion chip integrated therein.

An ASIC chip operable to:

packaging high-definition video data output by a first communication time sequence interface of a conversion chip in an ASIC chip into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

packaging high-definition video data output by a first communication time sequence interface of a conversion chip in an ASIC chip into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

and packaging the high-definition video data output by a first communication time sequence interface of a conversion chip in the ASIC chip into a custom data packet based on a custom communication protocol through the ASIC chip.

the electrical module is for:

the data packet is encoded and modulated by the PHY chip and then output to the RJ-45 interface, and then sent to the first receiving device and the second receiving device by the RJ-45 interface, or,

It should be noted that, please refer to the embodiments of fig. 1 and fig. 7 for the functions or definitions of the interfaces or modules not detailed in fig. 8.

Referring to fig. 6, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an optical module, as shown in fig. 9, the transmitting device 10 may include, but is not limited to: the optical module comprises an input interface 101, an FPGA chip and an optical module, wherein a conversion chip is integrated in the FPGA chip.

The FPGA chip can be used for:

the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip is packaged into UDP data packets based on a UDP communication protocol through the FPGA chip, or,

the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip is packaged into a TCP data packet based on a TCP communication protocol through the FPGA chip, or,

and packaging the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip into a custom data packet based on a custom communication protocol through the FPGA chip.

An optical module operable to:

converts the UDP packets to optical signals and sends the optical signals to a switch, which forwards the optical signals to a receiving device, or,

converts the TCP packets to optical signals and sends the optical signals to a switch, which forwards the optical signals to a receiving device, or,

the optical module is used for converting the data packet into an optical signal and sending the optical signal to the first receiving device and the second receiving device; alternatively, the first and second electrodes may be,

the optical module is used for converting the data packet into an optical signal through the optical module and sending the optical signal to the switch, and the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.

It should be noted that the function or definition of the interface or module not elaborated in fig. 9 refers to the embodiment of fig. 1.

Referring to fig. 6, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an optical module, as shown in fig. 10, the transmitting device 10 may include, but is not limited to: the input interface 101, the ASIC chip and the optical module, wherein the ASIC chip has a conversion chip integrated therein.

An ASIC chip operable to:

after the high definition video data output through the first communication timing interface of the conversion chip is output to the ASIC chip, the high definition video data is encapsulated into UDP packets based on the UDP communication protocol by the ASIC chip, or,

after the high definition video data output through the first communication timing interface of the conversion chip is output to the ASIC chip, the high definition video data is packaged into TCP packets based on the TCP communication protocol by the ASIC chip, or,

after the high-definition video data output through the first communication time sequence interface of the conversion chip are output to the ASIC chip, the high-definition video data are packaged into a custom data packet through the ASIC chip based on a custom communication protocol.

the optical module is used for:

the optical module converts the data packet into an optical signal and sends the optical signal to the switch, and the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.

It should be noted that, please refer to the embodiments of fig. 1 and 9 for the functions or definitions of the interfaces or modules not detailed in fig. 10.

Fig. 11 is a schematic structural diagram of another high-definition video data transmitting device according to the present invention. As shown in fig. 11, the transmitting device 10, may include but is not limited to: the input interface 101, the first integrated circuit 102, the first communication module 103, and the conversion chip, wherein the conversion chip and the first communication module 103 are integrated inside the first integrated circuit 102.

An input interface 101 for receiving high definition video data;

the conversion chip is used for outputting the high-definition video data to the first integrated circuit 102 through a first communication time sequence interface of the conversion chip;

the first integrated circuit 102 is configured to process high-definition video data output by a first communication timing interface of a conversion chip in the first integrated circuit 102 to obtain a data packet;

the first integrated circuit 102 is specifically configured to encapsulate, based on a communication protocol (e.g., a UDP communication protocol, a TCP communication protocol, or a custom communication protocol), high-definition video data output by the first communication timing interface of the conversion chip in the first integrated circuit 102 into a data packet (e.g., a UDP data packet, a TCP data packet, or a custom data packet);

the first integrated circuit 102 may be further specifically configured to compress high-definition video data output by a first communication timing interface of a conversion chip in the first integrated circuit 102 based on a distortion-free coding algorithm to obtain first data, and encapsulate the first data through a communication protocol to obtain a data packet.

The first communication module 103 is configured to transmit a data packet.

It should be noted that the functions or definitions of the interfaces or modules not detailed in fig. 11 refer to the embodiment of fig. 1.

Referring to fig. 11, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 12, the transmitting device 10 may include, but is not limited to: the input interface 101, the FPGA chip, the electric module, and the conversion chip, wherein, conversion chip and electric module are integrated in the interior of FPGA chip.

The FPGA chip is used for:

packaging high-definition video data output by a first communication time sequence interface of a conversion chip in an FPGA chip into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

packaging high-definition video data output by a first communication time sequence interface of a conversion chip in an FPGA chip into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

the high-definition video data output by a first communication time sequence interface of a conversion chip in the FPGA chip are packaged into a custom data packet based on a custom communication protocol; alternatively, the first and second electrodes may be,

the method comprises the steps of compressing high-definition video data output by a first communication time sequence interface of a conversion chip in an FPGA chip based on a distortion-free coding algorithm to obtain first data, and packaging the first data through a communication protocol (such as a UDP communication protocol, a TCP communication protocol or a self-defined communication protocol) to obtain a data packet (such as a UDP data packet, a TCP data packet or a self-defined data packet).

Wherein, first communication chronogenesis interface includes: LVDS interface, TTL interface, MIPI interface or custom interface.

The transmission rate of the electrical module is not lower than the first threshold, the electrical module comprising: a PHY chip and an RJ-45 interface;

the electrical module is for:

after the FPGA chip outputs the data packet to the MAC unit integrated in the FPGA chip and outputs the data packet to the PHY chip through the second communication time sequence interface of the MAC unit, the data packet is output to the RJ-45 interface through the PHY chip and is sent to the receiving equipment through the RJ-45 interface, or,

the data packet is encoded and modulated by the PHY chip and then output to the RJ-45 interface, and is sent to the switch by the RJ-45 interface, and the switch is used for forwarding the data packet to the receiving equipment;

the data packet includes: UDP packets, TCP packets, or custom packets.

It should be noted that the function or definition of the interface or module not elaborated in fig. 12 refers to the embodiment of fig. 1.

Referring to fig. 11, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 13, the transmitting device 10 may include, but is not limited to: the system comprises an input interface 101, an FPGA chip, an optical module and a conversion chip, wherein the conversion chip and the optical module are integrated in the FPGA chip.

The transmission rate of the optical module is not lower than a first threshold;

the optical module is used for:

converts the data packets into optical signals and transmits the optical signals to a receiving device, or,

and converting the data packet into an optical signal and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to the receiving equipment.

It should be noted that the function or definition of the interface or module not described in detail in fig. 13 refers to the embodiment of fig. 12.

Referring to fig. 11, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 14, the transmitting device 10 may include, but is not limited to: the input interface 101, the ASIC chip, the electrical module, and the conversion chip, wherein the conversion chip and the electrical module are integrated inside the ASIC chip.

An ASIC chip to:

the high-definition video data output by a first communication time sequence interface of a conversion chip in an ASIC chip are packaged into a custom data packet based on a custom communication protocol; alternatively, the first and second electrodes may be,

the method comprises the steps of compressing high-definition video data output by a first communication time sequence interface of a conversion chip in an ASIC chip based on a distortion-free coding algorithm to obtain first data, and packaging the first data through a communication protocol (such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol) to obtain a data packet (such as a UDP data packet, a TCP data packet or a custom data packet).

The electrical module is for:

after the ASIC chip outputs the data packet to the MAC unit integrated in the ASIC chip and outputs the data packet to the PHY chip through the second communication time sequence interface of the MAC unit, the PHY chip outputs the data packet to the RJ-45 interface after coding and modulating, and sends the data packet to the receiving equipment through the RJ-45 interface, or,

it should be noted that the function or definition of the interface or module not elaborated in fig. 14 refers to the embodiment of fig. 11.

Referring to fig. 11, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, as shown in fig. 15, the transmitting device 10 may include, but is not limited to: the input interface 101, the ASIC chip, the optical module, and the conversion chip, wherein the conversion chip and the optical module are integrated inside the ASIC chip.

The optical module is used for:

converting the data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to receiving equipment;

the data packet includes: UDP packets, TCP packets, or custom packets.

Referring to fig. 16, it is a schematic structural diagram of a high definition video data transmitting device provided in the present invention. As shown in fig. 16, the transmitting device 10, may include but is not limited to: an input interface 101, a first integrated circuit 102 and a first communication module 103, wherein the input interface 101, the first integrated circuit 102 and the first communication module 103 are connected to each other.

a first integrated circuit 102 for processing high definition video data into data packets based on a communication protocol;

the first communication module 103 is configured to transmit a data packet.

The communication protocol comprises: a UDP (User Datagram Protocol) communication Protocol, a TCP (Transmission Control Protocol) communication Protocol, or a custom communication Protocol;

it should be noted that the first integrated circuit 102 may include, but is not limited to: an FPGA chip or an ASIC chip.

The first integrated circuit 102 may be specifically configured to:

encapsulating the high definition video data into UDP packets based on the UDP communication protocol, or,

the high definition video data is encapsulated into TCP packets based on the TCP communication protocol, or,

and encapsulating the high-definition video data into a custom data packet based on a custom communication protocol.

the method comprises the steps of compressing high-definition video data based on a distortion-free coding algorithm to obtain first data, and encapsulating the first data through the communication protocol (such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol) to obtain a data packet.

It should be noted that the transmission rate of the first communication module is not lower than the first threshold; the first communication module 103 may include, but is not limited to: an electrical or optical module, wherein the electrical module comprises: a PHY chip (Ethernet physical layer data transceiver) and an RJ-45 interface, wherein the transmission rate of the electric module is not lower than a first threshold value; the transmission rate of the optical module is not lower than a first threshold; the first threshold may include, but is not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps, or 25 Gbps.

It should be noted that the functions or definitions of the interfaces or modules not detailed in fig. 16 refer to the embodiment of fig. 1.

Referring to fig. 16, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an electrical module, referring to fig. 17, it is a schematic structural diagram of another high definition video data transmitting device provided by the present invention. As shown in fig. 17, the transmitting device 10, may include but is not limited to: input interface 101, an FPGA chip, and an electrical module.

An input interface 101 for receiving high definition video data;

the FPGA chip is used for:

An electrical module comprising: a PHY chip and an RJ-45 interface; an electrical module operable to:

the UDP packet is output to the RJ-45 interface through the PHY chip, sent to the receiving device through the RJ-45 interface, or,

outputting the custom data packet to an RJ-45 interface through a PHY chip, and sending the custom data packet to receiving equipment through the RJ-45 interface;

alternatively, the first and second electrodes may be,

after the FPGA chip outputs the data packet to the MAC unit integrated in the FPGA chip and outputs the data packet to the PHY chip through the second communication time sequence interface of the MAC unit, the electric module is used for:

the data packet is output to the RJ-45 interface through the PHY chip, and is sent to the first receiving device and the second receiving device through the RJ-45 interface, or,

and the PHY chip outputs the data packet to the RJ-45 interface after coding and modulating, and the data packet is sent to the switch through the RJ-45 interface, and the switch is used for forwarding the data packet to the first receiving equipment and the second receiving equipment.

It should be noted that, please refer to the embodiment of fig. 1 and 16 for the functions or definitions of the interfaces or modules not detailed in fig. 17.

Referring to fig. 16, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an electrical module, referring to fig. 18, as shown in fig. 8, the transmitting device 10 may include, but is not limited to: an input interface 101, an ASIC chip, and an electrical module.

An ASIC chip operable to:

the high definition video data received by the input interface 101 is encapsulated into UDP packets based on the UDP communication protocol, or alternatively,

the high definition video data received by the input interface 101 is encapsulated into TCP packets based on the TCP communication protocol, or,

the high definition video data received by the input interface 101 is encapsulated into a custom data packet based on a custom communication protocol.

It should be noted that, please refer to the embodiment of fig. 1 and 17 for the functions or definitions of the interfaces or modules not detailed in fig. 18.

Referring to fig. 16, when the first integrated circuit 102 is an FPGA chip and the first communication module 103 is an optical module, referring to fig. 19, as shown in fig. 19, the transmitting device 10 may include, but is not limited to: input interface 101, FPGA chip and optical module.

The FPGA chip is used for:

An optical module operable to:

converting the UDP data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to receiving equipment;

converts the TCP data packets into optical signals and sends the optical signals to a switch, which forwards the optical signals to a receiving device,

converting the user-defined data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to receiving equipment;

it should be noted that the function or definition of the interface or module not detailed in fig. 19 refers to the embodiment of fig. 1.

Referring to fig. 16, when the first integrated circuit 102 is an ASIC chip and the first communication module 103 is an optical module, referring to fig. 20, as shown in fig. 20, the transmitting device 10 may include, but is not limited to: input interface 101, ASIC chip and optical module.

An ASIC chip to:

It should be noted that, please refer to the embodiment of fig. 1 and fig. 19 for the functions or definitions of the interfaces or modules not detailed in fig. 20.

Fig. 21 is a schematic structural diagram of another receiving device for high-definition video data according to the present invention. As shown in fig. 21, the receiving device 20 may include, but is not limited to: the second communication module 201, the second integrated circuit 202, and the output interface 203 may further include: a conversion chip, it should be noted that the conversion chip and the second integrated circuit 202 are separately integrated in the transceiver 20; wherein the content of the first and second substances,

a second communication module 201 operable to: acquiring a data packet from a sending device, or acquiring the data packet from a switch;

a second integrated circuit 202 operable to: processing the data packet into high-definition video data based on a communication protocol;

and the conversion chip is used for outputting the high-definition video data to the output interface 203 through the third communication time sequence interface of the conversion chip. Wherein, the third communication timing interface may include but is not limited to: HDMI interface, Type-C interface, DP interface, USB interface, VGA interface, DVI interface or MIPI interface.

An output interface 203 operable to: the high definition video data is output to an output device (e.g., a display device) connected to the receiving device 20.

The second integrated circuit 202 may be specifically configured to:

when the data packet is a UDP data packet, decapsulating the UDP data packet into high definition video data based on a UDP communication protocol, or,

when the data packet is a TCP data packet, the TCP data packet is decapsulated into high definition video data based on a TCP communication protocol, or,

and when the data packet is the custom data packet, decapsulating the custom data packet into high-definition video data based on a custom communication protocol.

The second integrated circuit 202, further operable to:

decapsulating the data packet based on a communication protocol (such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol) to obtain first data, decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data;

more specifically, when the data packet is a UDP data packet, decapsulating the UDP data packet based on a UDP communication protocol to obtain first data, and decompressing the first data based on a lossless decoding algorithm to obtain high-definition video data; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, decapsulating the TCP data packet based on a TCP communication protocol to obtain first data, and decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data; alternatively, the first and second electrodes may be,

and when the data packet is the user-defined data packet, decapsulating the user-defined data packet based on a user-defined communication protocol to obtain first data, and decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data.

A distortion-free decoding algorithm comprising:

run decoding algorithm, Huffman decoding algorithm, constant block decoding algorithm of binary image, quadtree decoding algorithm, wavelet transform decoding algorithm or custom arithmetic decoding algorithm.

The second integrated circuit 202 may be specifically configured to: and after the data packet is unpacked to obtain first data, interpolating the first data based on a user-defined arithmetic decoding algorithm to recover high-definition video data.

It should be noted that the second integrated circuit 202 may include, but is not limited to: an FPGA chip or an ASIC chip.

It should be noted that the second communication module 201 may include, but is not limited to: an electrical or optical module; the transmission rate of the optical module is not lower than a second threshold; the transmission rate of the electrical module is not lower than a second threshold; the second threshold may include, but is not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps, or 25 Gbps.

It should be understood that the receiving apparatus 20 of fig. 21 is only one example provided by the embodiments of the present application, and the receiving apparatus 20 may have more or less components than those shown, may combine two or more components, or may have a different configuration implementation of the components.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, referring to fig. 22, as shown in fig. 22, the receiving device 20 may include but is not limited to: an electrical module, an FPGA chip, a conversion chip, and an output interface 203. Wherein, the electric module includes: a PHY chip (ethernet physical layer data transceiver) and an RJ-45 interface; the conversion chip and the FPGA chip are respectively and independently integrated in the receiving device 20;

an electrical module operable to:

receiving the UDP data packet sent by the sending device through the RJ-45 interface, and outputting the UDP data packet to the FPGA chip through the PHY chip and a fourth communication timing interface of the MAC unit in the FPGA chip, where the fourth communication timing interface may include but is not limited to: an XFI interface, an MII interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAUI interface, or,

the TCP data packets transmitted by the transmitting device are received through the RJ-45 interface, and the TCP data packets are output to the FPGA chip through the PHY chip and the fourth communication timing interface of the MAC unit in the FPGA chip, or,

the custom data packet sent by the sending equipment is received through the RJ-45 interface, and the custom data packet is output to the FPGA chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the FPGA chip, or,

the UDP data packet forwarded by the switch through the RJ-45 interface is output to the FPGA chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the FPGA chip, or,

the TCP packets forwarded by the switch through the RJ-45 interface are output to the FPGA chip through the PHY chip and the fourth communication timing interface of the MAC unit in the FPGA chip, or,

and outputting the custom data packet to the FPGA chip through the PHY chip and a fourth communication time sequence interface of the MAC unit in the FPGA chip by the custom data packet forwarded by the switch through the RJ-45 interface.

The FPGA chip is specifically used for:

decapsulating the UDP data packet into high definition video data based on the UDP communication protocol, or,

decapsulating the TCP data packets into high definition video data based on the TCP communication protocol, or,

decapsulating the custom data packet into high definition video data based on a custom communication protocol, or,

and after the data packet is unpacked to obtain first data, interpolating the first data based on a distortion-free decoding algorithm to recover high-definition video data.

It should be noted that the function or definition of the interface or module not elaborated in fig. 22 refers to the embodiment of fig. 21.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, referring to fig. 23, as shown in fig. 23, the receiving device 20 may include, but is not limited to: electrical module, ASIC chip, conversion chip, and output interface 203. Wherein, the electric module includes: a PHY chip and an RJ-45 interface; the conversion chip and the ASIC chip are respectively and independently integrated in the receiving equipment;

an electrical module operable to:

receiving the UDP packet transmitted by the transmitting device through the RJ-45 interface, outputting the UDP packet to the ASIC chip through the PHY chip and a fourth communication timing interface of the MAC unit in the ASIC chip, or,

the TCP packets transmitted by the transmitting device are received through the RJ-45 interface, output to the ASIC chip through the PHY chip and the fourth communication timing interface of the MAC unit in the ASIC chip, or,

the custom data packet sent by the sending device is received through the RJ-45 interface, and the custom data packet is output to the ASIC chip through the PHY chip and the fourth communication timing interface of the MAC unit in the ASIC chip, or,

the UDP packet forwarded by the switch through the RJ-45 interface is output to the ASIC chip through the PHY chip and the fourth communication timing interface of the MAC unit in the ASIC chip, or,

the TCP packets forwarded by the switch through the RJ-45 interface are output to the ASIC chip through the PHY chip and the fourth communication timing interface of the MAC unit in the ASIC chip, or,

and outputting the custom data packet to the ASIC chip through the fourth communication time sequence interface of the MAC unit in the PHY chip and the ASIC chip by the custom data packet forwarded by the switch through the RJ-45 interface.

An ASIC chip, particularly useful for:

and decapsulating the UDP data packet output by the electrical module into high-definition video data based on a UDP communication protocol, or,

and decapsulating the TCP data packet output by the electrical module into high-definition video data based on a TCP communication protocol, or,

decapsulating the custom data packet output by the electrical module into high-definition video data based on a custom communication protocol; either, or alternatively,

It should be noted that, please refer to the embodiment of fig. 21 and 22 for the functions or definitions of the interfaces or modules not detailed in fig. 23.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, referring to fig. 24, as shown in fig. 24, the receiving device 20 may include but is not limited to: optical module, FPGA chip, conversion chip and output interface 203.

An optical module operable to:

receiving the optical signal transmitted by the transmitting device, converting the optical signal into a UDP data packet, and outputting the UDP data packet to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip, or,

receiving the optical signal transmitted by the transmitting device, converting the optical signal into a TCP packet, and outputting the TCP packet to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip, or,

receiving the optical signal sent by the sending device, converting the optical signal into a custom data packet, and outputting the custom data packet to the FPGA chip through a fourth communication time sequence interface of the MAC unit in the FPGA chip, or,

receiving the optical signal forwarded by the switch, converting the optical signal into a UDP data packet, and outputting the UDP data packet to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip, or,

receiving the optical signal forwarded by the switch, converting the optical signal into a TCP packet, and outputting the TCP packet to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip, or,

and receiving the optical signal forwarded by the switch, converting the optical signal into a user-defined data packet, and outputting the UDP data packet to the FPGA chip through a fourth communication time sequence interface of the MAC unit in the FPGA chip.

The FPGA chip can be used for:

and de-encapsulating the custom data packet into high-definition video data based on the custom communication protocol.

A conversion chip operable to: converting high-definition video data obtained after the FPGA chip is processed into high-definition video data;

an output interface 203 operable to: and outputting the high-definition video data to an output device (such as a display device).

It should be noted that the function or definition of the interface or module not elaborated in fig. 24 refers to the embodiment of fig. 21.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, referring to fig. 25, as shown in fig. 25, the receiving device 21 may include, but is not limited to: optical module, ASIC chip, conversion chip and output interface 203.

An ASIC chip operable to:

and decapsulating the UDP data packet output by the optical module into high-definition video data based on a UDP communication protocol, or,

and decapsulating the TCP data packet output by the optical module into high-definition video data based on the TCP communication protocol, or,

and decapsulating the custom data packet output by the optical module into high-definition video data based on a custom communication protocol.

It should be noted that, please refer to the embodiment of fig. 21 and 24 for the functions or definitions of the interfaces or modules not detailed in fig. 25.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 26, the receiving device 20 may include, but is not limited to: the second communication module 201, the second integrated circuit 202 and the output interface 203 further include: a conversion chip integrated inside the second integrated circuit 202;

the second integrated circuit 202 may be specifically configured to:

when the data packet is a UDP data packet, decapsulating the UDP data packet into high-definition video data based on a UDP communication protocol, and outputting the high-definition video data to the output interface 203 through the third communication timing interface of the conversion chip; the third communication timing interface includes: an HDMI interface, a Type-C interface, a DP interface, a USB interface, a VGA interface or an MIPI interface; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, the TCP data packet is decapsulated into high definition video data based on the TCP communication protocol, the high definition video data is output to the output interface 203 through the third communication timing interface of the conversion chip, or,

when the data packet is the custom data packet, the custom data packet is decapsulated into high-definition video data based on the custom communication protocol, and the high-definition video data is output to the output interface 203 through the third communication timing interface of the conversion chip.

An output interface 203 operable to: the high definition video data is output to a display device (e.g., a display).

It should be noted that the function or definition of the interface or module not described in detail in fig. 26 refers to the embodiment of fig. 21.

Referring to fig. 26, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, as shown in fig. 27, the receiving device 23 may include, but is not limited to: an electrical module, an FPGA chip, and an output interface 203. The FPGA chip is integrated with a conversion chip.

An electrical module operable to:

receiving a UDP data packet sent by sending equipment through an RJ-45 interface, and outputting the UDP data packet to an FPGA chip through a PHY chip and a fourth communication time sequence interface of an MAC unit in the FPGA chip, wherein the fourth communication time sequence interface comprises: an XFI interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface or an RXAAUI interface; alternatively, the first and second electrodes may be,

The FPGA chip can be used for:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the FPGA chip through a fourth communication time sequence interface of an MAC unit in the FPGA chip to obtain high-definition video data, and outputting the high-definition video data to an output interface through a third communication time sequence interface of a conversion chip; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, the TCP data packet input into the FPGA chip is unpacked through a fourth communication time sequence interface of an MAC unit in the FPGA chip to obtain high-definition video data, and the high-definition video data is output to an output interface through a third communication time sequence interface of a conversion chip; alternatively, the first and second electrodes may be,

when the data packet is a custom data packet, the custom data packet input into the FPGA chip is unpacked through a fourth communication time sequence interface of an MAC unit in the FPGA chip to obtain high-definition video data, and the high-definition video data is output to an output interface through a third communication time sequence interface of a conversion chip.

An output interface 203 operable to:

the high definition video data is output to a display device (e.g., a display).

It should be noted that, please refer to the embodiments in fig. 21 and fig. 26 for the functions or definitions of the interfaces or modules not described in detail in fig. 27.

Referring to fig. 26, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 28, the receiving device 23 may include, but is not limited to: an electrical module, an ASIC chip, and an output interface 203. Wherein, the ASIC chip is integrated with a conversion chip.

An electrical module operable to:

An ASIC chip operable to:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the ASIC chip through a fourth communication time sequence interface of an MAC unit in the ASIC chip to obtain high-definition video data, and outputting the high-definition video data to an output interface through a third communication time sequence interface of a conversion chip; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip to obtain high-definition video data, outputting the high-definition video data to an output interface through a third communication timing interface of the conversion chip, or,

when the data packet is a custom data packet, the custom data packet input to the ASIC chip is unpacked through a fourth communication time sequence interface of an MAC unit in the ASIC chip to obtain high-definition video data, and the high-definition video data is output to an output interface through a third communication time sequence interface of a conversion chip.

It should be noted that, please refer to the embodiments in fig. 21 and 27 for the functions or definitions of the interfaces or modules not described in detail in fig. 28.

Referring to fig. 26, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, as shown in fig. 29, the receiving device 23 may include, but is not limited to: optical module, FPGA chip and output interface 203. The FPGA chip is integrated with a conversion chip.

An optical module operable to:

and receiving the optical signal forwarded by the switch, converting the optical signal into a custom data packet, and outputting the custom data packet to the FPGA chip through a fourth communication time sequence interface of the MAC unit in the FPGA chip.

The FPGA chip can be used for:

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the FPGA chip through a fourth communication timing interface of an MAC unit in the FPGA chip to obtain high-definition video data, and outputting the high-definition video data to an output interface through a third communication timing interface of a conversion chip; alternatively, the first and second electrodes may be,

It should be noted that the function or definition of the interface or module not elaborated in fig. 29 refers to the embodiment of fig. 21.

Referring to fig. 26, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 30, the receiving device 23 may include, but is not limited to: optical module, ASIC chip and output interface 203. Wherein, the ASIC chip is integrated with the conversion chip.

An electrical module operable to:

receiving a TCP data packet sent by sending equipment through the RJ-45 interface, and outputting the TCP data packet to the ASIC chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the ASIC chip; alternatively, the first and second electrodes may be,

receiving a custom data packet sent by sending equipment through the RJ-45 interface, and outputting the custom data packet to the ASIC chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the ASIC chip; alternatively, the first and second electrodes may be,

An ASIC chip operable to:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the ASIC chip by the fourth communication timing interface of the MAC unit in the ASIC chip to obtain high-definition video data, outputting the high-definition video data to the output interface by the third communication timing interface of the conversion chip, or,

It should be noted that, please refer to the embodiment of fig. 21 and 29 for the functions or definitions of the interfaces or modules not detailed in fig. 30.

Referring to fig. 21, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 31, the receiving device 20 may include, but is not limited to: the second communication module 201, the second integrated circuit 202 and the output interface 203 further include: the conversion chip, the second communication module 201 and the conversion chip are integrated inside the second integrated circuit 202;

a second integrated circuit 202 operable to: processing the data packet input to the second integrated circuit 202 through the fourth communication timing interface of the MAC unit in the second integrated circuit 202 to obtain high-definition video data, and outputting the high-definition video data to the output interface 203 through the third communication timing interface of the conversion chip;

Fig. 31 is a schematic structural diagram of a receiving device for high definition video data according to the present invention. As shown in fig. 32, the receiving device 20, may include but is not limited to: besides the electric module, the FPGA chip and the output interface 203, the method further includes: the conversion chip, the electric module and the conversion chip are integrated in the FPGA chip;

an electrical module comprising: a PHY chip and an RJ-45 interface;

the electrical module is for:

the UDP data packet sent by the sending equipment is received through the RJ-45 interface, and the UDP data packet is output to the FPGA chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the FPGA chip, or,

the UDP data packet forwarded by the switch is received through the RJ-45 interface, and the UDP data packet is output to the FPGA chip through the PHY chip and a fourth communication time sequence interface of an MAC unit in the FPGA chip, or,

the TCP packets forwarded by the switch are received through the RJ-45 interface and output to the FPGA chip through the PHY chip and the fourth communication timing interface of the MAC unit in the FPGA chip, or,

and receiving the custom data packet forwarded by the switch through the RJ-45 interface, and outputting the custom data packet to the FPGA chip through the PHY chip and a fourth communication time sequence interface of the MAC unit in the FPGA chip.

The FPGA chip is used for decapsulating the UDP data packet input to the FPGA chip at a fourth communication time sequence interface of the MAC unit in the FPGA chip to obtain high-definition video data, and then outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip; alternatively, the first and second electrodes may be,

the FPGA chip is used for decapsulating the TCP data packet input to the FPGA chip at a fourth communication time sequence interface of the MAC unit in the FPGA chip to obtain high-definition video data, and then outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip; alternatively, the first and second electrodes may be,

and the FPGA chip is used for decapsulating the custom data packet input to the FPGA chip at a fourth communication time sequence interface of the MAC unit in the FPGA chip to obtain high-definition video data, and outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip.

It should be noted that the FPGA chip may also be configured to decapsulate a data packet (e.g., a UDP data packet, a TCP data packet, or a custom data packet) to obtain first data, decompress the first data based on a distortion-free decoding algorithm to obtain high-definition video data, and output the high-definition video data to the output interface through a third communication timing interface of the conversion chip; a distortion-free decoding algorithm comprising: run decoding algorithm, Huffman decoding algorithm, constant block decoding algorithm of binary image, quadtree decoding algorithm, wavelet transform decoding algorithm or custom arithmetic decoding algorithm;

it should be noted that the function or definition of the interface or module not described in detail in fig. 32 refers to the embodiment of fig. 31.

Fig. 31 is a schematic structural diagram of a receiving device for high definition video data according to the present invention. As shown in fig. 33, the receiving device 20 may include, but is not limited to: besides the optical module, the FPGA chip and the output interface 203, the optical module further includes: the conversion chip, the optical module and the conversion chip are integrated in the FPGA chip;

an optical module for:

It should be noted that, please refer to the embodiments in fig. 31 and fig. 32 for the functions or definitions of the interfaces or modules not described in detail in fig. 33.

Fig. 31 is a schematic structural diagram of a receiving device for high definition video data according to the present invention. As shown in fig. 34, the receiving device 20, may include but is not limited to: the electrical module, the ASIC chip, and the output interface 203 further include: the conversion chip, the electric module and the conversion chip are integrated in the ASIC chip;

an electrical module comprising: a PHY chip and an RJ-45 interface;

the electrical module is for:

the UDP packet forwarded by the switch is received through the RJ-45 interface, output to the ASIC chip through the PHY chip and a fourth communication timing interface of the MAC unit in the ASIC chip, or,

the TCP packets forwarded by the switch are received through the RJ-45 interface, output to the ASIC chip through the PHY chip and the fourth communication timing interface of the MAC unit in the ASIC chip, or,

and receiving the custom data packet forwarded by the switch through the RJ-45 interface, and outputting the custom data packet to the ASIC chip through the PHY chip and a fourth communication time sequence interface of the MAC unit in the ASIC chip.

An ASIC chip, which is used for decapsulating the UDP data packet input to the ASIC chip by the fourth communication time sequence interface of the MAC unit in the ASIC chip to obtain high-definition video data, and then outputting the high-definition video data to the output interface by the third communication time sequence interface of the conversion chip, or,

an ASIC chip, for decapsulating the TCP data packet input to the ASIC chip at the fourth communication timing interface of the MAC unit in the ASIC chip to obtain high definition video data, and then outputting the high definition video data to the output interface through the third communication timing interface of the conversion chip, or,

and the ASIC chip is used for decapsulating the custom data packet input to the ASIC chip at a fourth communication time sequence interface of the MAC unit in the ASIC chip to obtain high-definition video data, and then outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip.

It should be noted that the ASIC chip may further be configured to decapsulate a data packet (e.g., a UDP data packet, a TCP data packet, or a custom data packet) to obtain first data, decompress the first data based on a distortion-free decoding algorithm to obtain high-definition video data, and output the high-definition video data to the output interface through a third communication timing interface of the conversion chip; a distortion-free decoding algorithm comprising: run decoding algorithm, Huffman decoding algorithm, constant block decoding algorithm of binary image, quadtree decoding algorithm, wavelet transform decoding algorithm or custom arithmetic decoding algorithm;

it should be noted that the function or definition of the interface or module not elaborated in fig. 34 refers to the embodiment of fig. 31.

Fig. 31 is a schematic structural diagram of a receiving device for high definition video data according to the present invention. As shown in fig. 35, the receiving device 20 may include, but is not limited to: besides the optical module, the ASIC chip, and the output interface 203, the optical module further includes: the optical module and the conversion chip are integrated inside the ASIC chip;

an optical module for:

receiving the optical signal transmitted by the transmitting device, and converting the optical signal into a UDP packet, outputting the UDP packet to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip, or,

receiving an optical signal transmitted by the transmitting device, and converting the optical signal into a TCP packet, outputting the TCP packet to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip, or,

receiving the optical signal transmitted by the transmitting device, converting the optical signal into a custom data packet, and outputting the custom data packet to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip, or,

receiving the optical signal forwarded by the switch, converting the optical signal into a UDP packet, and outputting the UDP packet to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip, or,

receiving the optical signal forwarded by the switch, converting the optical signal into a TCP packet, and outputting the TCP packet to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip, or,

and receiving the optical signal forwarded by the switch, converting the optical signal into a custom data packet, and outputting the custom data packet to the ASIC chip through a fourth communication time sequence interface of the MAC unit in the ASIC chip.

It should be noted that, please refer to the embodiments in fig. 31 and 34 for the functions or definitions of the interfaces or modules not described in detail in fig. 35.

Referring to fig. 36, it is a schematic structural diagram of a receiving device for high definition video data according to the present invention. As shown in fig. 36, the receiving device 20, may include but is not limited to: a second communication module 201, a second integrated circuit 202 and an output interface 203, wherein the second communication module 201, the second integrated circuit 202 and the output interface 203 are connected to each other.

a second integrated circuit 202 operable to: and processing the data packet based on a communication protocol to obtain high-definition video data.

An output interface 203 operable to: the high definition video data is output to an output device (e.g., a display device).

The second integrated circuit 202 may be specifically configured to:

when the data packet is a UDP data packet, decapsulating the UDP data packet based on a UDP communication protocol to obtain high definition video data, or,

when the data packet is a TCP data packet, decapsulating the UDP data packet based on a TCP communication protocol to obtain high-definition video data, or,

when the data packet is a user-defined data packet, decapsulating the user-defined data packet based on a user-defined communication protocol to obtain high-definition video data;

the second integrated circuit 202 may be further configured to:

when the data packet is a UDP data packet, decapsulating the UDP data packet based on a UDP communication protocol to obtain first data, decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data; alternatively, the first and second electrodes may be,

A distortion-free decoding algorithm comprising:

It should be noted that the output interface 203 may include, but is not limited to:

HDMI interface, Type-C interface, DP interface, USB interface, VGA interface, DVI interface or MIPI interface.

It should be noted that the transmission rate of the second communication module 201 is not lower than the second threshold;

the second communication module 201 may include, but is not limited to: an electrical or optical module; the transmission rate of the optical module is not lower than a second threshold; the transmission rate of the electrical module is not lower than a second threshold; wherein the second threshold may include, but is not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps or 25 Gbps; wherein, the electric module includes: a PHY chip and an RJ-45 interface.

Referring to fig. 36, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, as shown in fig. 37, the present invention is a schematic structural diagram of another high definition video data transmitting device. As shown in fig. 37, the receiving device 20, may include but is not limited to: an electrical module, an FPGA chip, and an output interface 203.

An electrical module operable to:

the RJ-45 interface receives the TCP data packet sent by the sending equipment, and the PHY chip and the fourth communication time sequence interface of the MAC unit in the FPGA chip output the TCP data packet to the FPGA chip, or,

the RJ-45 interface receives the user-defined data packet sent by the sending equipment, the PHY chip and the fourth communication time sequence interface of the MAC unit in the FPGA chip output the user-defined data packet to the FPGA chip, or,

The FPGA chip can be used for:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the FPGA chip by the fourth communication timing interface of the MAC unit in the FPGA chip to obtain high definition video data, and outputting the high definition video data to the output interface 203 by the third communication timing interface of the conversion chip, or,

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the FPGA chip through the fourth communication timing interface of the MAC unit in the FPGA chip to obtain high definition video data, outputting the high definition video data to the output interface 203 through the third communication timing interface of the conversion chip, or,

when the data packet is a custom data packet, decapsulating the custom data packet input to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip to obtain high-definition video data, and outputting the high-definition video data to the output interface 203 through a third communication timing interface of the conversion chip;

it should be noted that the FPGA chip may also be used to:

the data packet (such as a UDP data packet, a TCP data packet or a custom data packet) is unpackaged based on a communication protocol (such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol) to obtain first data, and the first data is decompressed based on a distortion-free decoding algorithm to obtain high-definition video data.

An output interface 203 for:

outputting the high-definition video data to output equipment connected with the receiving equipment;

it should be noted that the function or definition of the interface or module not elaborated in fig. 37 refers to the embodiment of fig. 36.

Referring to fig. 36, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 38, the receiving device 20 may include, but is not limited to: an electrical module, an ASIC chip, and an output interface 203.

An ASIC chip to:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the ASIC chip through the fourth communication timing interface of the MAC unit in the ASIC chip to obtain high definition video data, and outputting the high definition video data to the output interface 203 through the third communication timing interface of the conversion chip, or,

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the ASIC chip through the fourth communication timing interface of the MAC unit in the ASIC chip to obtain high definition video data, outputting the high definition video data to the output interface 203 through the third communication timing interface of the conversion chip, or,

when the data packet is a custom data packet, decapsulating the custom data packet input to the ASIC chip through a fourth communication timing interface of the MAC unit in the ASIC chip to obtain high-definition video data, and outputting the high-definition video data to the output interface 203 through a third communication timing interface of the conversion chip;

the FPGA chip can also be used for:

It should be noted that, for the functions or definitions of the interfaces or modules not described in detail in fig. 38, please refer to the embodiments in fig. 36 and fig. 37.

Referring to fig. 36, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an FPGA chip, as shown in fig. 39, the receiving device 20 may include, but is not limited to: optical module, FPGA chip and output interface 203.

An optical module operable to:

receiving the optical signal forwarded by the switch, converting the optical signal into the UDP packet, and outputting the UDP packet to the FPGA chip through a fourth communication time sequence interface of the MAC unit in the FPGA chip, or,

receiving the optical signal forwarded by the switch, converting the optical signal into the TCP packet, and outputting the TCP packet to the FPGA chip through a fourth communication timing interface of the MAC unit in the FPGA chip, or,

The FPGA chip can be used for:

when the data packet is a UDP data packet, after the MAC unit in the FPGA chip receives the UDP data packet output by the optical module, the UDP data packet input to the FPGA chip is decapsulated through the fourth communication timing interface of the MAC unit in the FPGA chip to obtain high definition video data, and the high definition video data is output to the output interface 203 through the third communication timing interface of the conversion chip, or,

when the data packet is a custom data packet, the custom data packet input into the FPGA chip is unpackaged through a fourth communication time sequence interface of an MAC unit in the FPGA chip to obtain high-definition video data, the high-definition video data is output to an output interface 203 or the output interface through a third communication time sequence interface of a conversion chip,

an output interface 203 for:

it should be noted that the function or definition of the interface or module not detailed in fig. 39 refers to the embodiment in fig. 36.

Referring to fig. 36, when the second communication module 201 is an electrical module and the second integrated circuit 202 is an ASIC chip, as shown in fig. 40, the receiving device 20 may include, but is not limited to: optical module, ASIC chip and output interface 203.

An ASIC chip operable to:

when the data packet is a custom data packet, the custom data packet input to the ASIC chip is decapsulated through the fourth communication timing interface of the MAC unit in the ASIC chip to obtain high definition video data, and the high definition video data is output to the output interface 203 through the third communication timing interface of the conversion chip, which should be described, for the function or definition of an interface or a module not described in detail in fig. 40, please refer to fig. 36 and fig. 39.

Referring to fig. 41, the present invention provides a schematic diagram of a transmission system for high definition video data. As shown in fig. 31, the transmitting device 10, may include but is not limited to: the communication device comprises an input interface 101, a first conversion chip, a first integrated circuit 102 and a first communication module 103, wherein the input interface 101, the first conversion chip, the first integrated circuit 102 and the first communication module 103 are connected in sequence. The receiving device 20, may include but is not limited to: the communication device comprises a second communication module 201, a second integrated circuit 202, a second conversion chip and an output interface 203, wherein the second communication module 201, the second integrated circuit 202, the second conversion chip and the output interface 203 are connected in sequence. In particular, the method comprises the following steps of,

the first conversion chip is used for outputting the high-definition video data to the first integrated circuit 102 through a first communication time sequence interface of the first conversion chip;

the first communication module 103 is configured to send the data packet to the receiving device, or send the data packet to a switch, where the switch is configured to forward the data packet to the receiving device.

The second conversion chip is used for outputting the high-definition video data to the output interface 203 through a third communication time sequence interface of the second conversion chip;

It should be noted that the functions or definitions of the interfaces or modules not described in detail in fig. 41 refer to the embodiments in fig. 1 and 21.

Claims

1. A transmitting device of high definition video data, comprising:

2. The transmitting device of claim 1,

the input interface includes: an HDMI interface, a Type-C interface, a DP interface, a USB interface, a VGA interface, a DVI interface or an MIPI interface; alternatively, the first and second electrodes may be,

the first communication timing interface comprising:

LVDS interface, TTL interface, the MIPI interface or self-defined interface.

3. The transmitting device of claim 1,

when the first integrated circuit is an FPGA chip, the FPGA chip is configured to:

and encapsulating the high-definition video data into a UDP data packet based on a UDP communication protocol, or,

encapsulating the high definition video data into TCP data packets based on a TCP communication protocol, or,

packaging the high-definition video data into a custom data packet based on a custom communication protocol; alternatively, the first and second electrodes may be,

when the first integrated circuit is an ASIC chip, the ASIC chip is configured to:

4. The transmitting device of claim 1,

the first integrated circuit may be specifically configured to:

compressing high-definition video data based on a distortion-free coding algorithm to obtain first data, and encapsulating the first data through a communication protocol to obtain a data packet;

wherein the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the first integrated circuit includes: an FPGA chip or an ASIC chip; the distortion-free coding algorithm comprises the following steps: run length coding algorithm, Huffman coding algorithm, constant block coding algorithm of binary image, quad-tree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm.

5. The transmitting device of claim 3 or 4,

when the first communication module is an electrical module, the transmission rate of the electrical module is not lower than the first threshold; the electrical module includes: a PHY chip and an RJ-45 interface;

the electrical module is configured to:

after the first integrated circuit outputs the packet to a MAC unit integrated in the first integrated circuit and outputs the packet to the PHY chip through a second communication timing interface of the MAC unit, the packet is output to the RJ-45 interface through the PHY chip, transmitted to a receiving device through the RJ-45 interface, or,

outputting the data packet to the RJ-45 interface through the PHY chip, and sending the data packet to a switch through the RJ-45 interface, wherein the switch is used for forwarding the data packet to the receiving equipment; alternatively, the first and second electrodes may be,

when the first communication module is an optical module, the transmission rate of the optical module is not lower than the first threshold;

the optical module is used for:

after the first integrated circuit outputs the data packet to a MAC unit integrated in the first integrated circuit, the data packet is output to the optical module through a second communication timing interface of the MAC unit,

convert the data packets into optical signals and transmit the optical signals to a receiving device, or,

converting the data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to the receiving equipment;

wherein the second communication timing interface comprises: an XFI interface, an MII interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface or an RXAAUI interface; the data packet includes: UDP packets, TCP packets, or custom packets.

6. The transmitting device of claim 5,

the electrical module is configured to:

after the first integrated circuit outputs the packet to a MAC unit integrated in the first integrated circuit, the packet is output to the PHY chip through a second communication timing interface of the MAC unit,

outputting the data packet to the RJ-45 interface through the PHY chip, and sending the data packet to a switch through the RJ-45 interface, wherein the switch is used for forwarding the data packet to the first receiving device and the second receiving device; alternatively, the first and second electrodes may be,

the optical module is used for:

and converting the data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.

7. A transmission apparatus for high definition video data,

8. The transmitting device of claim 7, wherein the input interface comprises:

9. The transmitting device of claim 7, further comprising:

a conversion chip integrated inside the first integrated circuit;

packaging the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data output by the first communication time sequence interface of the conversion chip in the FPGA chip into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data output by a first communication time sequence interface of the conversion chip in the FPGA chip into a custom data packet based on a custom communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data output by a first communication time sequence interface of the conversion chip in the ASIC chip into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data output by a first communication time sequence interface of the conversion chip in the ASIC chip into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data output by a first communication time sequence interface of the conversion chip in the ASIC chip into a custom data packet based on a custom communication protocol; wherein the first communication timing interface comprises: LVDS interface, TTL interface, MIPI interface or custom interface.

10. The transmitting device of claim 7, further comprising:

a conversion chip integrated inside the first integrated circuit;

the first integrated circuit to:

compressing the high-definition video data output by a first communication time sequence interface of the conversion chip in the first integrated circuit based on a distortion-free coding algorithm to obtain first data, and packaging the first data through a communication protocol to obtain a data packet;

11. The transmitting device of claim 7,

packaging the high-definition video data into a UDP data packet based on a UDP communication protocol; alternatively, the first and second electrodes may be,

packaging the high-definition video data into a TCP data packet based on a TCP communication protocol; alternatively, the first and second electrodes may be,

when the first integrated circuit is an ASIC chip; the ASIC chip is configured to:

encapsulating the high-definition video data into the UDP data packet based on the UDP communication protocol; alternatively, the first and second electrodes may be,

encapsulating the high-definition video data into the TCP data packet based on the TCP communication protocol; alternatively, the first and second electrodes may be,

and packaging the high-definition video data into the custom data packet based on the custom communication protocol.

12. The transmitting device of claim 7,

the first integrated circuit is specifically configured to:

13. The transmitting device of claim 9, 10, 11 or 12,

the first communication module is integrated inside the first integrated circuit;

when the first communication module includes: when the electric module is to be electrically operated,

a transmission rate of the electrical module is not below the first threshold, the electrical module comprising: a PHY chip and an RJ-45 interface;

the electrical module is configured to:

the optical module is used for:

wherein the data packet includes: UDP packets, TCP packets, or custom packets; the second communication timing interface, comprising: an XFI interface, an MII interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAUI interface.

14. The transmitting device of claim 9, 10, 11 or 12,

the electrical module is configured to:

after the first integrated circuit outputs the packet to a MAC unit integrated in the first integrated circuit and outputs the packet to the PHY chip through a second communication timing interface of the MAC unit, the packet is output to the RJ-45 interface through the PHY chip, transmitted to the first receiving device and the second receiving device through the RJ-45 interface, or,

the optical module is used for:

converting the data packet into an optical signal, and sending the optical signal to a switch, where the switch is configured to forward the optical signal to the first receiving device and the second receiving device;

15. A receiving device for high definition video data, comprising:

the second communication module, the second integrated circuit, the conversion chip and the output interface; the second communication module is used for acquiring a data packet; the second integrated circuit is used for processing the data packet to obtain high-definition video data; the conversion chip is used for outputting the high-definition video data to the output interface through a third communication time sequence interface of the conversion chip; the transmission rate of the second communication module is not lower than a second threshold; an output interface for: outputting the high-definition video data to an output device connected with the receiving device; the third communication timing interface includes: HDMI interface, Type-C interface, DP interface, USB interface, VGA interface or MIPI interface.

16. The receiving device of claim 15,

when the second communication module is an electrical module, the transmission rate of the electrical module is not lower than the second threshold; the electrical module includes: a PHY chip and an RJ-45 interface;

the electrical module is configured to:

receiving, by the RJ-45 interface, a UDP packet sent by a sending device, and outputting, by the PHY chip and a fourth communication timing interface of an MAC unit in the second integrated circuit, the UDP packet to the second integrated circuit, where the fourth communication timing interface includes: an XFI interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface or an RXAAUI interface; alternatively, the first and second electrodes may be,

receiving a TCP packet transmitted by a transmitting device through the RJ-45 interface, outputting the TCP packet to the second integrated circuit through the PHY chip and a fourth communication timing interface of a MAC unit in the second integrated circuit, or,

receiving a custom data packet sent by a sending device through the RJ-45 interface, outputting the custom data packet to the second integrated circuit through the PHY chip and a fourth communication timing interface of an MAC unit in the second integrated circuit, or,

receiving, by the RJ-45 interface, a UDP packet forwarded by a switch, outputting, by the PHY chip and a fourth communication timing interface of a MAC unit in the second integrated circuit, the UDP packet to the second integrated circuit, or,

receiving a TCP packet forwarded by a switch through the RJ-45 interface, outputting the TCP packet to the second integrated circuit through the PHY chip and a fourth communication timing interface of a MAC unit in the second integrated circuit, or,

receiving a custom packet forwarded by a switch through the RJ-45 interface, outputting the custom packet to the second integrated circuit through the PHY chip and a fourth communication timing interface of an MAC unit in the second integrated circuit, or,

the second communication module is an optical module; the transmission rate of the optical module is not lower than the second threshold;

the optical module is used for:

receiving an optical signal transmitted by a transmitting device, converting the optical signal into a UDP packet, and outputting the UDP packet to the second integrated circuit through a fourth communication timing interface of the MAC unit in the second integrated circuit, or,

receiving an optical signal transmitted by the transmitting device, converting the optical signal into a TCP packet, and outputting the TCP packet to the second integrated circuit through a fourth communication timing interface of the MAC unit in the second integrated circuit, or,

receiving an optical signal transmitted by the transmitting device, converting the optical signal into a custom data packet, and outputting the custom data packet to the second integrated circuit through a fourth communication timing interface of an MAC unit in the second integrated circuit, or,

receiving an optical signal forwarded by a switch, converting the optical signal into the UDP packet, and outputting the UDP packet to the second integrated circuit through a fourth communication timing interface of the MAC unit in the second integrated circuit, or,

receiving the optical signal forwarded by the switch, converting the optical signal into the TCP packet, and outputting the TCP packet to the second integrated circuit through a fourth communication timing interface of the MAC unit in the second integrated circuit, or,

and receiving the optical signal forwarded by the switch, converting the optical signal into the custom data packet, and outputting the custom data packet to the second integrated circuit through a fourth communication time sequence interface of the MAC unit in the second integrated circuit.

17. The receiving device of claim 15, wherein when the second integrated circuit is an FPGA chip, the FPGA chip is to:

when the data packet is a UDP data packet, decapsulating the UDP data packet into high-definition video data based on a UDP communication protocol, or,

when the data packet is a TCP data packet, the TCP data packet is de-encapsulated into high definition video data based on a TCP communication protocol, or,

when the data packet is a user-defined data packet, decapsulating the user-defined data packet into high-definition video data based on a user-defined communication protocol; alternatively, the first and second electrodes may be,

when the second integrated circuit is an ASIC chip, the ASIC chip is configured to:

and when the data packet is a custom data packet, decapsulating the custom data packet into high-definition video data based on a custom communication protocol.

18. The receiving device of claim 15,

the second integrated circuit is specifically configured to:

decapsulating the data packet based on a communication protocol to obtain first data, and decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data;

the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol;

the distortion-free decoding algorithm comprises the following steps:

19. The receiving device of claim 15, wherein the output interface comprises: HDMI interface, Type-C interface, DP interface, USB interface, VGA interface, DVI interface or MIPI interface.

20. A receiving device for high definition video data, comprising:

21. The receiving device of claim 20,

the electrical module is configured to:

receiving a UDP data packet sent by a sending device through the RJ-45 interface, and outputting the UDP data packet to the second integrated circuit through the PHY chip and a fourth communication time sequence interface of an MAC unit in the second integrated circuit; the fourth communication timing interface includes: an XFI interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAUI interface, or,

the optical module is used for:

22. The receiving device of claim 20,

the second communication module is integrated in the second integrated circuit; the second communication module is to output the data packet to the second integrated circuit; the data packet includes: UDP packets, TCP packets, or custom packets.

23. The receiving device of claim 21 or 22, further comprising:

a conversion chip integrated inside the second integrated circuit;

when the second integrated circuit is an FPGA chip, the FPGA chip is configured to:

when the data packet is a UDP data packet, decapsulating the UDP data packet input to the FPGA chip by using a fourth communication timing interface of an MAC unit in the FPGA chip to obtain high definition video data, where a third communication timing interface of the conversion chip is configured to output the high definition video data to the output interface, and the third communication timing interface includes: the third communication timing interface includes: an HDMI interface, a Type-C interface, a DP interface, a USB interface, a VGA interface or an MIPI interface; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the FPGA chip through a fourth communication timing interface of an MAC unit in the FPGA chip to obtain high-definition video data, wherein the third communication timing interface of the conversion chip is used for outputting the high-definition video data to the output interface, or,

when the data packet is a custom data packet, decapsulating the custom data packet input to the FPGA chip through a fourth communication timing interface of an MAC unit in the FPGA chip to obtain high definition video data, where the third communication timing interface of the conversion chip is used to output the high definition video data to the output interface, or,

when the data packet is a UDP data packet, the UDP data packet of the chip is unpacked and high-definition video data is obtained, wherein the UDP data packet is input into the ASIC chip through a fourth communication time sequence interface of an MAC unit in the ASIC chip, and the third communication time sequence interface of the conversion chip is used for outputting the high-definition video data to the output interface; alternatively, the first and second electrodes may be,

when the data packet is a TCP data packet, decapsulating the TCP data packet input to the ASIC chip through a fourth communication timing interface of an MAC unit in the ASIC chip to obtain high-definition video data, wherein the third communication timing interface of the conversion chip is used for outputting the high-definition video data to the output interface; alternatively, the first and second electrodes may be,

when the data packet is a custom data packet, the custom data packet input to the ASIC chip is unpacked through a fourth communication time sequence interface of an MAC unit in the ASIC chip to obtain high-definition video data, and the third communication time sequence interface of the conversion chip is used for outputting the high-definition video data to the output interface.

24. The receiving device of claim 21 or 22, further comprising:

a conversion chip integrated inside the second integrated circuit;

the second integrated circuit to:

decapsulate the data packet based on a communication protocol to obtain first data, decompress the first data based on a distortion-free decoding algorithm to obtain high-definition video data, where a third communication timing interface of the conversion chip is configured to output the high-definition video data to the output interface; wherein the content of the first and second substances,

the communication protocol comprises: UDP communication protocol, TCP communication protocol, or custom communication protocol; the second integrated circuit comprising: an FPGA chip or an ASIC chip;

the distortion-free decoding algorithm comprises the following steps:

run decoding algorithm, Huffman decoding algorithm, constant block decoding algorithm of binary image, quadtree decoding algorithm, wavelet transform decoding algorithm or custom arithmetic decoding algorithm; the third communication timing interface, comprising: the third communication timing interface includes: HDMI interface, Type-C interface, DP interface, USB interface, VGA interface or MIPI interface.

25. The receiving device of claim 21 or 22,

when the data packet is a UDP data packet, decapsulating the UDP data packet based on a UDP communication protocol to obtain high-definition video data, or,

when the data packet is a TCP data packet, decapsulating the TCP data packet based on a TCP communication protocol to obtain the high-definition video data, or,

when the data packet is a custom data packet, decapsulating the custom data packet based on a custom communication protocol to obtain the high-definition video data; alternatively, the first and second electrodes may be,

when the data packet is a UDP data packet, decapsulating the UDP data packet based on a UDP communication protocol to obtain the high-definition video data, or,

and when the data packet is a custom data packet, decapsulating the custom data packet based on a custom communication protocol to obtain the high-definition video data.

26. The receiving device of claim 21 or 22,

the second integrated circuit is specifically configured to:

decapsulating the data packet based on a communication protocol to obtain first data, and decompressing the first data based on a distortion-free decoding algorithm to obtain high-definition video data; wherein the content of the first and second substances,

the distortion-free decoding algorithm comprises the following steps:

27. The receiving device of claim 20, further comprising:

the output interface includes: HDMI interface, Type-C interface, DP interface, USB interface, VGA interface, DVI interface or MIPI interface.

28. A transmission system for high definition video data, comprising:

the sending device is configured to:

receiving high-definition video data in different color space formats through the input interface, and outputting the high-definition video data to the first integrated circuit through a first communication time sequence interface of the conversion chip; processing the high-definition video data into a data packet through the first integrated circuit, and transmitting the data packet through the first communication module;

the receiving apparatus includes: the second communication module, the second integrated circuit, the conversion chip and the output interface;

the receiving device is configured to:

the second communication module is used for acquiring a data packet, the second integrated circuit is used for processing the data packet to acquire high-definition video data, and the third communication time sequence interface of the conversion chip is used for outputting the high-definition video data to the output interface; an output interface for: and outputting the high-definition video data to an output device connected with the receiving device.