CN117009267A

CN117009267A - Method for inserting time information in source synchronous data stream

Info

Publication number: CN117009267A
Application number: CN202311277094.2A
Authority: CN
Inventors: 杨庸; 孙吉利; 万传彬; 赵行伦
Original assignee: Chengdu Boyu Lihua Technology Co ltd
Current assignee: Chengdu Boyu Lihua Technology Co ltd
Priority date: 2023-10-07
Filing date: 2023-10-07
Publication date: 2023-11-07
Anticipated expiration: 2043-10-07
Also published as: CN117009267B

Abstract

The application discloses a method for inserting time information in a source synchronous data stream, which relates to the technical field of signal processing, defines a fusion signal CLK_1PPS, and defines a source synchronous transmission interval and a time transmission interval; when the local real-time clock approaches 1 second and at least two source synchronous clock periods exist, if CLK_1PPS is high level, stopping jumping, setting and maintaining the signal, and when the local real-time clock reaches a 1 second boundary, resetting the signal, so that the CLK_1PPS signal generates high level pulses with the rising edge of more than two source synchronous clock periods, the rising edge of the pulses means that an interface signal enters a time transmission interval, and the falling edge means a boundary of 1 second in the absolute time; when the time transfer ends, clk_1pps is set for at least two clock cycles of the time transfer, and the interface returns to the source synchronous transfer interval. The application fuses the time interface into the source synchronous data stream to achieve the purpose of simplifying interface IO.

Description

Method for inserting time information in source synchronous data stream

Technical Field

The application relates to the technical field of signal processing, in particular to a method for inserting time information in a source synchronous data stream.

Background

Non-high-speed signal transmission inside electronic devices, inside boards or between boards often uses source synchronous interfaces, and a typical application scenario is between two programmable gate arrays FPGAs. The source synchronous interfaces are typically parallel buses. The source synchronous interface has the advantages that clocks at the two ends of the receiving and transmitting are homologous, and the data clocks are synchronous, so that transmission errors of data streams at the two ends of the bus can be avoided. The source synchronous interface is a parallel port, which has the disadvantage of occupying more bus input/output interfaces IO in the board. If time information needs to be transferred inside the device, such as from one chip to another, it is common practice to transfer time in the form of pulse-per-second + serial data. The second pulse 1PPS can precisely locate a boundary of one second in the absolute time, and the serial data is used to tell the receiving end the current absolute time value. The receiving end can completely synchronize the time information of the local real-time clock with the real-time clock of the transmitting end through the two signals. This approach requires the use of at least two IOs, one pulse per second signal, one (group) data signal. When we transmit source synchronous data stream and time information between two chips (such as FPGA), there is sometimes a scenario that the number of IOs is tight, i.e. there are not so many IOs to transmit all information, so we hope to have a scheme that can fuse time information into the source synchronous interface, so as to achieve the purpose of simplifying IOs.

Disclosure of Invention

The application aims to provide a method for inserting time information into a source synchronous data stream, which is used for solving the problem that IO resources are tensed when the source synchronous data stream and the time information are transmitted between FPGAs simultaneously in the prior art.

The application solves the problems by the following technical proposal:

a method of inserting time information in a source synchronous data stream, comprising:

step S1, defining a fusion signal CLK_1PPS of second pulse information and source synchronous clock information, defining a source synchronous transmission interval and a time transmission interval, wherein the source synchronous transmission interval refers to a source synchronous data stream transmitted by an interface, and the time transmission interval refers to current time information transmitted by the interface;

step S2, when the local real-time clock approaches 1 second and at least two source synchronous clock periods exist, if CLK_1PPS is high level, stopping jumping, setting and maintaining the signal, and when the local real-time clock reaches a 1 second boundary, resetting the signal, so that the CLK_1PPS signal generates a high level pulse which is more than two source synchronous clock periods, the rising edge of the pulse means that an interface signal enters a time transmission interval, and the falling edge means a boundary of 1 second in absolute time;

and step S3, setting the CLK_1PPS to at least two clock cycles of time transmission after the time transmission is finished, and returning the interface to the source synchronous transmission interval.

Further comprises: the receiving end normally checks the high level duration of 1PPS at high frequency, when the high level which lasts for more than 1 source synchronous clock period is found in the source synchronous transmission interval, the 1 second boundary which indicates the absolute time comes immediately, and when the signal is checked to be 0, the 1 second boundary which indicates the absolute time at the moment.

Compared with the prior art, the application has the following advantages:

(1) The application fuses the time interface into the source synchronous data stream to achieve the purpose of simplifying interface IO. And inserting time information into the source synchronous data stream through the fusion signal CLK_1PPS, informing the receiving end of synchronizing the local real clock, negotiating the receiving and transmitting ends to continue transmitting the original data stream after the time information is sent, and reducing the influence on the bandwidth of the source data stream to the minimum.

(2) In the source synchronous transmission interval, the data bus transmits source synchronous data; in the time transmission interval, the data bus transmits the current time information. In order to reduce the bandwidth impact on the bus source synchronous data, it is necessary to transmit time information to the receiving end as soon as possible, i.e. the shorter the time transmission interval is, the better the compression. The second boundary can be accurately known by clk_1pps. In the time transmission interval, clk_1pps hops according to the clock frequency of the agreed time transmission interval, and provides a time reference for bus value judgment.

Drawings

FIG. 1 is a schematic diagram of the present application;

FIG. 2 is a flow chart of the present application;

FIG. 3 is a schematic diagram of transmission codes according to the present application;

fig. 4 is a flow chart of a receiving end processing in the present application.

Detailed Description

The present application will be described in further detail with reference to examples, but embodiments of the present application are not limited thereto.

Example 1:

1. clock and second pulse

First we fuse the information of the second pulse with the source-synchronous clock information, we define this signal as the fused signal clk_1pps. At the same time we define two transmission intervals: a source synchronous transmission interval and a time transmission interval, wherein the source synchronous transmission interval refers to a source synchronous data stream transmitted by an interface; the time transmission interval refers to the time information transmitted by the interface.

As shown in fig. 1, for the transmitting end, when the local real-time clock is very close to one second, but there are at least two source synchronous clock cycles, if clk_1pps is high, the transition is stopped, it is set and maintained, and when the local real-time clock reaches the 1 second boundary, the signal is reset. The clk_1PPS signal will thus generate a high pulse of more than two source synchronous clock cycles, the rising edge of which means that the interface signal enters the time transmission interval and the falling edge means the boundary of one second in absolute time.

When the time transmission is finished, clk_1pps is set for at least two clock cycles of the time transmission, and the interface returns to the data stream transmission interval.

The processing flow of the transmitting end is shown in fig. 2, and the receiving end normally checks the high level duration of clk_1pps at high frequency. When a high level lasting more than 1 source synchronous clock period is found in the source synchronous transmission interval, a 1 second boundary indicating time is immediately arrived. When the signal is checked to be set to 0, this indicates that this time is the 1 second boundary of absolute time. At the end of the time transmission, clk_1pps sets two periods and returns to the source synchronous transmission interval.

2. Data bus

In the source synchronous transmission interval, the data bus transmits source synchronous data; in the time transmission interval, the data bus transmits the current time information. In order to reduce the bandwidth impact on the bus source synchronous data, it is necessary to transmit time information to the receiving end as soon as possible, i.e. the shorter the time transmission interval is, the better the compression.

The second boundary can be accurately known by clk_1pps. In the time transmission interval, clk_1pps hops according to the clock frequency of the agreed time transmission interval, and provides a time reference for bus value judgment.

In conventional processing, a high level on the data bus represents a 1, and a low level represents a 0. In the application, in order to compress the time transmission interval to the minimum, two judgment vectors of duty ratio and phase are introduced besides high and low levels. In one period of the time transmission interval, each transmission code is defined as shown in table 1 with reference to the period time of clk_1pps:

table 1 transmission coding table

The coding scheme is shown in fig. 3.

The processing flow of the receiving end is shown in fig. 4. The coding of the transmitting end is the same.

The information of year, month, day, time, minute and second is transmitted in the time transmission interval through the codes, so that the receiving end receives the absolute time information of the current moment, and the receiving end synchronizes the absolute time information to the local real clock in the next second.

Although the application has been described herein with reference to the above-described illustrative embodiments thereof, the foregoing embodiments are merely preferred embodiments of the present application, and it should be understood that the embodiments of the present application are not limited to the above-described embodiments, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure.

Claims

1. A method of inserting time information in a source synchronous data stream, comprising:

2. The method of inserting time information in a source synchronous data stream of claim 1, further comprising: the receiving end normally checks the high level duration of 1PPS at high frequency, when the high level which lasts for more than 1 source synchronous clock period is found in the source synchronous transmission interval, the 1 second boundary which indicates the absolute time comes immediately, and when the signal is checked to be 0, the 1 second boundary which indicates the absolute time at the moment.