CN117008567B - Switch machine control signal fault simulation system - Google Patents
Switch machine control signal fault simulation system Download PDFInfo
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- CN117008567B CN117008567B CN202310842809.8A CN202310842809A CN117008567B CN 117008567 B CN117008567 B CN 117008567B CN 202310842809 A CN202310842809 A CN 202310842809A CN 117008567 B CN117008567 B CN 117008567B
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- 238000004088 simulation Methods 0.000 title claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims description 25
- 230000002441 reversible effect Effects 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 claims 1
- 238000012423 maintenance Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0259—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the response to fault detection
- G05B23/0262—Confirmation of fault detection, e.g. extra checks to confirm that a failure has indeed occurred
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
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Abstract
The invention discloses a fault simulation system for control signals of a switch machine, which is characterized by comprising a signal output end, the switch machine and a simulation module, wherein the signal output end is connected with the switch machine and the simulation module, the switch machine is connected with the simulation module, the signal output end is used for outputting control signals, the switch machine is used for responding to the control signals and feeding back the completion signals when finishing actions, and the simulation module is used for simulating the states of the switch machine responding to the signals and feeding back the signals to perform fault simulation.
Description
Technical Field
The invention relates to the field of railway switch machine control signals, in particular to a fault simulation system for a switch machine control signal.
Background
In recent years, as railway reforms are advanced, the defects of equipment maintenance quality and personnel service level are becoming more and more obvious, and in order to better improve the skill level and maintenance quality of workers, the training of workers becomes the first thing, and the most frequent equipment point switches used as railway electric service are certainly the key points of training, but the prior art cannot simulate the control signals of the point switches and faults of the point switches when the point switches receive the control signals and act.
Disclosure of Invention
The invention aims to provide a fault simulation system for control signals of a switch machine, which comprises a signal output end, the switch machine and a simulation module, wherein the signal output end is connected with the switch machine and the simulation module, the switch machine is connected with the simulation module, the signal output end is used for outputting control signals, the switch machine is used for responding the control signals and feeding back completion signals when the action is completed, and the simulation module is used for performing fault simulation on the states of the response signals and the feedback signals of the switch machine.
Further, the analog module further comprises a first power supply V1, a first input terminal P1, a second input terminal P2, a first resistor R1, a second resistor R2, a first MOS transistor Q1, a second triode Q2, a third triode Q3 and a fourth MOS transistor Q4, wherein a source electrode of the first MOS transistor Q1 is connected with a base electrode of the second triode Q2, a drain electrode of the first MOS transistor Q1 is connected with the first power supply V1, a grid electrode of the first MOS transistor Q1 is connected with the first input terminal P1, a collector electrode of the second triode Q2 is connected with a base electrode of the third triode Q3, one end of the first resistor R1 is connected between the collector electrode of the second triode Q2 and the base electrode of the third triode Q3, one end of the second resistor R2 is connected with the first power supply V1, the other end of the second resistor R2 is connected with the collector electrode of the third triode Q3, a drain electrode of the fourth MOS transistor Q4 is connected with the source electrode of the first MOS transistor Q1 and the base electrode of the second triode Q2, a grid electrode of the fourth MOS transistor Q4 is connected with the base electrode of the second triode Q2, the fourth MOS transistor Q2 is connected with the base electrode of the third triode Q2, the second MOS transistor Q2 is connected with the feedback terminal P2, the signal feedback terminal P2 is connected with the first switch P2, the signal input terminal P is connected with the second switch P2, the signal feedback terminal P is connected with the second switch P, the signal meter, the signal input terminal P is finished, the signal input terminal P is connected with the signal switch P, and the signal switch P is finished, and the signal switch is connected to the signal input terminal P is connected to the signal terminal P and has the signal terminal P.
Further, the analog module further includes a first operational amplifier U1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fifth MOS transistor Q5, and a first capacitor C1, where one end of the third resistor R3 is connected to the first power supply V1, one end of the fourth resistor R4 is connected to the other end of the third resistor R3, a feedback signal is fed back between the third resistor R3 and the fourth resistor R4 from the inverting end of the first operational amplifier U1, an output end of the first operational amplifier U1 is connected to a gate of the fifth MOS transistor Q5, one end of the fifth resistor R5 is connected to the first power supply V1, a source of the fifth MOS transistor Q5 is connected to the other end of the fifth resistor R5, a drain of the fifth MOS transistor Q5 is connected to one end of the first capacitor C1, one end of the sixth resistor R6 is connected to a drain end of the fifth MOS transistor Q5, one end of the first capacitor C1, and another end of the fourth resistor R4, the sixth resistor R6, the other end of the first capacitor C1 is connected to the ground.
Further, the analog module further includes a second operational amplifier U2, a sixth MOS transistor Q6, a seventh triode Q7, a seventh resistor R7, and an eighth resistor R8, where the non-inverting terminal of the second operational amplifier U2 is connected to the first input terminal P1, the feedback signal of the inverting terminal of the second operational amplifier U2 is provided between the third resistor R3 and the fourth resistor R4, the output terminal of the second operational amplifier U2 is connected to the gate of the seventh triode Q7, the gate of the sixth MOS transistor Q6 is connected between the output terminal of the first operational amplifier U1 and the gate of the fifth MOS transistor Q5, the drain of the sixth MOS transistor Q6 is connected between the drain of the fifth MOS transistor Q5 and the first capacitor C1, one end of the seventh resistor R7 is connected to the first power supply V1, the source of the seventh triode Q7 is connected to the other end of the seventh resistor R7, the drain of the seventh triode Q7 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the ground.
Further, the analog module further includes a third operational amplifier U3, an eighth triode Q8, a ninth resistor R9, and a tenth resistor R10, where the in-phase end of the third operational amplifier U3 is connected between the collector of the second triode Q2 and the base of the third triode Q3, the feedback signal of the inverting end of the third operational amplifier U3 is provided between the third resistor R3 and the fourth resistor R4, the output end of the third operational amplifier U3 is connected with one end of R9, one end of the tenth resistor R10 is connected with the other end of the ninth resistor R9, the base of the eighth triode Q8 is connected between the ninth resistor R9 and the tenth resistor R10, the collector of the eighth triode Q8 is connected between the drain of the seventh triode Q7 and the eighth resistor R8, and the other end of the tenth resistor R10 is connected with the emitter of the eighth triode Q8 and the ground.
Furthermore, the analog module further comprises an eleventh resistor R11, one end of the eleventh resistor R11 is connected with the grid electrode of the fourth MOS tube Q4, and the other end of the eleventh resistor R11 is connected with the grounding end.
Furthermore, the analog module further comprises a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected to the gate end of the first MOS tube Q1, the source end of the sixth MOS tube Q6, the same-phase end of the second operational amplifier U2, and the other end of the thirteenth resistor R13 is connected to the ground end.
Further, the analog module further includes a twelfth resistor R12, one end of the twelfth resistor R12 is connected to the gate of the fifth MOS transistor Q5, and the other end of the twelfth resistor R12 is connected to the ground.
Furthermore, the analog module further includes a fourteenth resistor R14, one end of the fourteenth resistor R14 is connected between the gate of the seventh triode Q7 and the output end of the second operational amplifier U2, and the other end of the fourteenth resistor R14 is connected with the ground terminal.
Compared with the prior art, the invention has the beneficial effects that:
the invention can simulate faults after the switch machine responds to the control signal, and compares the time of the switch machine responding to the control signal with the time required by the switch machine to finish the action so as to reflect the current state of the switch machine.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the prior art and the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an overall structure provided by the present invention.
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
Referring to the drawings, the invention relates to a fault simulation system for control signals of a switch machine, which comprises a signal output end, the switch machine and a simulation module, wherein the signal output end is connected with the switch machine and the simulation module, the switch machine is connected with the simulation module, the signal output end is used for outputting control signals, the switch machine is used for responding the control signals and feeding back completion signals when finishing actions, and the simulation module is used for carrying out fault simulation on the states of the response signals and the feedback signals of the switch machine.
Specifically, the analog module further comprises a first power supply V1, a first input terminal P1, a second input terminal P2, a first resistor R1, a second resistor R2, a first MOS transistor Q1, a second triode Q2, a third triode Q3 and a fourth MOS transistor Q4, wherein a source electrode of the first MOS transistor Q1 is connected with a base electrode of the second triode Q2, a drain electrode of the first MOS transistor Q1 is connected with the first power supply V1, a grid electrode of the first MOS transistor Q1 is connected with the first input terminal P1, a collector electrode of the second triode Q2 is connected with a base electrode of the third triode Q3, one end of the first resistor R1 is connected between the collector electrode of the second triode Q2 and the base electrode of the third triode Q3, one end of the second resistor R2 is connected with the first power supply V1, the other end of the second resistor R2 is connected with the collector electrode of the third triode Q3, a drain electrode of the fourth MOS transistor Q4 is connected with the base electrode of the first MOS transistor Q1, a grid electrode of the fourth MOS transistor Q4 is connected with the base electrode of the second MOS transistor Q2, a grid electrode of the fourth MOS transistor Q2 is connected with the base electrode of the third triode Q2, a signal feedback terminal P2 is connected with the third triode Q2, and the signal feedback terminal P2 is connected with the third MOS transistor Q2, the signal feedback terminal P is connected with the first switch P2, the signal feedback terminal P is finished, and the signal is input to the signal meter, the signal is input to the signal meter P is finished, and the signal is input to the signal terminal P2 and the signal has the signal to the signal terminal P and the signal has the signal to the signal and the signal terminal P.
Specifically, the analog module further includes a first operational amplifier U1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fifth MOS transistor Q5, and a first capacitor C1, where one end of the third resistor R3 is connected to the first power supply V1, one end of the fourth resistor R4 is connected to the other end of the third resistor R3, a feedback signal is fed back between the third resistor R3 and the fourth resistor R4 at the inverting end of the first operational amplifier U1, an output end of the first operational amplifier U1 is connected to a gate of the fifth MOS transistor Q5, one end of the fifth resistor R5 is connected to the first power supply V1, a source of the fifth MOS transistor Q5 is connected to the other end of the fifth resistor R5, a drain of the fifth MOS transistor Q5 is connected to one end of the first capacitor C1, one end of the sixth resistor R6 is connected to the drain end of the fifth MOS transistor Q5, one end of the first capacitor C1, a drain end of the sixth MOS transistor Q6, and the other end of the fourth resistor R4, the fifth resistor R5, the other end of the first capacitor C1 is connected to the ground.
Specifically, the analog module further includes a second operational amplifier U2, a sixth MOS transistor Q6, a seventh triode Q7, a seventh resistor R7, and an eighth resistor R8, where the in-phase end of the second operational amplifier U2 is connected to the first input terminal P1, feedback signals of the inverting end of the second operational amplifier U2 are fed back between the third resistor R3 and the fourth resistor R4, the output end of the second operational amplifier U2 is connected to the gate of the seventh triode Q7, the gate of the sixth MOS transistor Q6 is connected between the output end of the first operational amplifier U1 and the gate of the fifth MOS transistor Q5, the drain of the sixth MOS transistor Q6 is connected between the drain of the fifth MOS transistor Q5 and the first capacitor C1, one end of the seventh resistor R7 is connected to the first power supply V1, the source of the seventh triode Q7 is connected to the other end of the seventh resistor R7, the drain of the seventh triode Q7 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the ground.
Specifically, the analog module further includes a third operational amplifier U3, an eighth triode Q8, a ninth resistor R9, and a tenth resistor R10, where the in-phase end of the third operational amplifier U3 is connected between the collector of the second triode Q2 and the base of the third triode Q3, the feedback signal of the inverting end of the third operational amplifier U3 is provided between the third resistor R3 and the fourth resistor R4, the output end of the third operational amplifier U3 is connected with one end of R9, one end of the tenth resistor R10 is connected with the other end of the ninth resistor R9, the base of the eighth triode Q8 is connected between the ninth resistor R9 and the tenth resistor R10, the collector of the eighth triode Q8 is connected between the drain of the seventh triode Q7 and the eighth resistor R8, and the other end of the tenth resistor R10 is connected with the emitter of the eighth triode Q8 and the ground.
Specifically, the analog module further includes an eleventh resistor R11, one end of the eleventh resistor R11 is connected to the gate of the fourth MOS transistor Q4, and the other end of the eleventh resistor R11 is connected to the ground.
Specifically, the analog module further includes a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected to the gate end of the first MOS transistor Q1, the source end of the sixth MOS transistor Q6, the in-phase end of the second operational amplifier U2, and the other end of the thirteenth resistor R13 is connected to the ground end.
Specifically, the analog module further includes a twelfth resistor R12, one end of the twelfth resistor R12 is connected to the gate of the fifth MOS transistor Q5, and the other end of the twelfth resistor R12 is connected to the ground.
Specifically, the analog module further includes a fourteenth resistor R14, one end of the fourteenth resistor R14 is connected between the gate of the seventh triode Q7 and the output end of the second operational amplifier U2, and the other end of the fourteenth resistor R14 is connected to the ground terminal.
The first input terminal P1 end obtains signals and then synchronously feeds back the signals to the grid electrode of the first MOS transistor Q1, the grid electrode of the first MOS transistor Q1 and the source electrode of the first MOS transistor Q1 reach conduction pressure difference, one path of power supply signals are fed back to the base electrode of the second triode Q2 through the drain electrode of the first MOS transistor Q1 and the source electrode of the first MOS transistor Q1, the base electrode of the second triode Q2 and the emitting electrode of the second triode Q2 generate forward bias, the collector electrode of the second triode Q2 amplifies signal currents, the collector electrode of the second triode Q2 feeds back to the base electrode of the third triode Q3, the base electrode of the third triode Q3 and the emitting electrode of the third triode Q3 generate forward bias, the first resistor R1 prevents the second triode Q2 from breakdown, the second resistor R2 prevents the third triode Q3 from breakdown, the current signals amplified by the collector electrode of the third triode Q3 feed back to the end of the first operational amplifier U1, the reverse end of the first operational amplifier U1 obtains signal feedback between the third resistor R3 and the fourth resistor R4, the signal feedback end of the second operational amplifier Q2 is obtained through the reverse MOS transistor Q4, the fourth MOS transistor Q4 receives signals and the signal feedback from the drain electrode of the fourth MOS transistor Q4, and the fourth MOS transistor Q4 receives signals from the fourth MOS transistor Q4, and the fourth MOS transistor Q4 reaches the conduction pressure difference is achieved, and the drain electrode of the fourth MOS transistor Q4 is started, and the drain electrode of the fourth MOS transistor Q is started, and the fourth MOS transistor Q1 is started, and the fourth MOS transistor Q is opened, and the fourth signal is opened.
Considering that the switch machine is in a fixed time from the start of the action to the end of the action, if the switch machine does not feed back a reverse action completion signal when the action time is exceeded, the switch machine can indicate the action fault of the switch machine, the action time of the switch machine needs to be set, fault simulation is convenient, a fifth resistor R5 is arranged to enable the source electrode of a fifth MOS tube Q5 to change the voltage amplitude, the potential of a first capacitor C1 in an initial state can not rise, the first operational amplifier U1 synchronously feeds back the signals to the grid electrode of the fifth MOS tube Q5 and the grid electrode of the sixth MOS tube Q6 when outputting the signals, meanwhile, the grid electrode of the fifth MOS tube Q5 and the source electrode of the fifth MOS tube Q5 can not reach a conduction pressure difference, the fifth MOS tube Q5 is cut off, meanwhile, the grid electrode of the sixth MOS tube Q6 and the source electrode of the sixth MOS tube Q6 reach a conduction pressure difference, one path of the output signals of the first operational amplifier U1 is connected to a ground loop through a twelfth resistor R12, the drain electrode of the sixth MOS tube Q6, the grid electrode of the sixth MOS tube Q6 and a thirteenth resistor R13 are connected to the ground loop, when the switch machine operates, a signal is fed back to the first input terminal P1, when the first input terminal P1 obtains the signal, the source voltage of the sixth MOS tube Q6 is changed to ensure that the source voltage of the sixth MOS tube Q6 and the grid electrode of the sixth MOS tube Q6 cannot reach the conduction pressure difference, the output signal of the first operational amplifier U1 is enabled to rise in potential of the first capacitor C1 after passing through the twelfth resistor R12 and the sixth resistor R6, when the switch machine finishes feeding back the signal to the first input terminal P1, one path of the first capacitor C1 release signal is fed back to the same phase end of the second operational amplifier U2 through the drain electrode of the sixth MOS tube Q6, the source electrode of the sixth MOS tube Q6 and the thirteenth resistor R13, the speed of the first capacitor C1 release signal is changed through adjusting the resistance value of the thirteenth resistor R13, the reverse phase end of the second operational amplifier U2 obtains a feedback signal through the third resistor R3 and the fourth resistor R4, the power signal is fed back to the grid electrode of the seventh triode Q7 through a seventh resistor R7, a source electrode of the seventh triode Q7, a drain electrode of the seventh triode Q7 and an eighth resistor R8 to a grounding end loop, a signal time table between the drain electrode of the seventh triode Q7 and the eighth resistor R8 is a positioning state indication signal, the fourteenth resistor R14 discharges parasitic capacitance voltage of the seventh triode Q7, a second operational amplifier U2 outputs a signal to feed back to the grid electrode of the seventh triode Q7, the grid electrode of the seventh triode Q7 and the source electrode of the seventh triode Q7 cannot reach a conducting pressure difference, so that simulation setting is carried out on the time of the indexing action after the control signal is obtained by the switcher, the positioning indication signal is removed when the switcher starts to act after responding to the signal, and the feedback of the signal is waited, when the signal amplitude of the first capacitor C1 is smaller than the voltage amplitude between the third resistor R3 and the fourth resistor R4, the second operational amplifier U2 is cut off, the positioning state indication signal is restored, the switcher is not finished in the indexing action setting time, and the switcher is in a fault state.
When the signal between the drain electrode of the first MOS transistor Q1 and the base electrode of the second triode Q2 is released, the power supply signal is fed back to the same phase end of the third operational amplifier U3 through the first resistor R1, one path of the output signal of the third operational amplifier U3 is fed back to the ground end loop through the ninth resistor R9 and the tenth resistor R10, the signal between the third operational amplifier U3 and the ninth resistor R9 is completed in the inversion action, the signal between the ninth resistor R9 and the tenth resistor R10 is fed back to the base electrode of the eighth triode Q8, the base electrode of the eighth triode Q8 and the emitter electrode of the eighth triode Q8 generate forward bias, the signal between the drain electrode of the seventh triode Q7 and the eighth resistor R8 is fed back to the ground end loop through the collector electrode of the eighth triode Q8, the emitter electrode of the eighth triode Q8 is removed in the stable state, the positioning state indication signal is removed, and when the switch finishes the inversion action within the set time of the inversion action, the switch is completed, and the switch has no fault.
Claims (1)
1. The fault simulation system for the control signal of the switch machine is characterized by comprising a signal output end, the switch machine and a simulation module, wherein the signal output end is connected with the switch machine and the simulation module, the switch machine is connected with the simulation module, the signal output end is used for outputting the control signal, the switch machine is used for responding to the control signal and feeding back a completion signal when the action is completed, and the simulation module performs fault simulation on the states of the response signal and the feedback signal of the switch machine;
The analog module further comprises a first power supply, a first input terminal, a second input terminal, a first resistor, a second resistor, a first MOS tube, a second triode, a third triode and a fourth MOS tube, wherein the source electrode of the first MOS tube is connected with the base electrode of the second triode, the drain electrode of the first MOS tube is connected with the first power supply, the grid electrode of the first MOS tube is connected with the first input terminal, the collector electrode of the second triode is connected with the base electrode of the third triode, one end of the first resistor is connected with the first power supply, the other end of the first resistor is connected between the collector electrode of the second triode and the base electrode of the third triode, one end of the second resistor is connected with the first power supply, the other end of the second resistor is connected with the collector electrode of the third triode, the drain electrode of the fourth MOS tube is connected between the source electrode of the first MOS tube and the base electrode of the second triode, the emitter electrode of the second MOS tube, the source electrode of the fourth MOS tube is connected with the ground terminal, the first input terminal end obtains feedback signal table for a switch to obtain feedback signal and starts to switch, and the switch is turned over, and the second input signal is completed by the switch;
The analog module further comprises a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a fifth MOS tube and a first capacitor, wherein one end of the third resistor is connected with a first power supply, one end of the fourth resistor is connected with the other end of the third resistor, feedback signals of an inverting end of the first operational amplifier are fed back between the third resistor and the fourth resistor, an output end of the first operational amplifier is connected with a grid electrode of the fifth MOS tube, one end of the fifth resistor is connected with the first power supply, a source electrode of the fifth MOS tube is connected with the other end of the fifth resistor, a drain electrode of the fifth MOS tube is connected with one end of the first capacitor, one end of the sixth resistor is connected with the drain end of the fifth MOS tube, one end of the first capacitor, the drain end of the sixth MOS tube is connected with the fourth resistor, the other end of the sixth resistor and the ground end of the first capacitor;
The analog module further comprises a second operational amplifier, a sixth MOS tube, a seventh triode, a seventh resistor and an eighth resistor, wherein the in-phase end of the second operational amplifier is connected with the first input terminal, feedback signals of the inverting end of the second operational amplifier are fed back between the third resistor and the fourth resistor, the output end of the second operational amplifier is connected with the grid electrode of the seventh triode, the grid electrode of the sixth MOS tube is connected between the output end of the first operational amplifier and the grid electrode of the fifth MOS tube, the drain electrode of the sixth MOS tube is connected between the drain electrode of the fifth MOS tube and the first capacitor, one end of the seventh resistor is connected with the first power supply, the source electrode of the seventh triode is connected with the other end of the seventh resistor, the drain electrode of the seventh triode is connected with one end of the eighth resistor, and the other end of the eighth resistor is connected with the grounding end;
The analog module further comprises a third operational amplifier, an eighth triode, a ninth resistor and a tenth resistor, wherein the in-phase end of the third operational amplifier is connected between the collector electrode of the seventh triode and the base electrode of the third triode, feedback signals of the inverting end of the third operational amplifier are fed back between the third resistor and the fourth resistor, the output end of the third operational amplifier is connected with one end of R9, one end of the tenth resistor is connected with the other end of the ninth resistor, the base electrode of the eighth triode is connected between the ninth resistor and the tenth resistor, the collector electrode of the eighth triode is connected between the drain electrode of the seventh triode and the eighth resistor, and the other end of the tenth resistor is connected with the emitter electrode of the eighth triode and the ground terminal;
the simulation module further comprises an eleventh resistor, one end of the eleventh resistor is connected with the grid electrode of the fourth MOS tube, and the other end of the eleventh resistor is connected with the grounding end;
The analog module further comprises a thirteenth resistor, one end of the thirteenth resistor is connected to the gate end of the first MOS tube, the source end of the sixth MOS tube and the same-phase end of the second operational amplifier, and the other end of the thirteenth resistor is connected with the grounding end;
the simulation module further comprises a twelfth resistor, one end of the twelfth resistor is connected with the grid electrode of the fifth MOS tube, and the other end of the twelfth resistor is connected with the grounding end;
The analog module further comprises a fourteenth resistor, one end of the fourteenth resistor is connected between the grid electrode of the seventh triode and the output end of the second operational amplifier, and the other end of the fourteenth resistor is connected with the grounding end;
The first input terminal P1 end obtains signals and then synchronously feeds back the signals to the grid electrode of the first MOS transistor Q1, the grid electrode of the first MOS transistor Q1 and the source electrode of the first MOS transistor Q1 reach conduction pressure difference, one path of power supply signals are fed back to the base electrode of the second triode Q2 through the drain electrode of the first MOS transistor Q1 and the source electrode of the first MOS transistor Q1, the base electrode of the second triode Q2 and the emitting electrode of the second triode Q2 generate forward bias, the collector electrode of the second triode Q2 amplifies signal currents, the collector electrode of the second triode Q2 feeds back to the base electrode of the third triode Q3, the base electrode of the third triode Q3 and the emitting electrode of the third triode Q3 generate forward bias, the first resistor R1 prevents the second triode Q2 from breakdown, the second resistor R2 prevents the third triode Q3 from breakdown, the current signals amplified by the collector electrode of the third triode Q3 feed back to the end of the first operational amplifier U1, the reverse end of the first operational amplifier U1 obtains signal feedback between the third resistor R3 and the fourth resistor R4, the signal feedback end of the second operational amplifier Q2 is obtained by the reverse MOS transistor Q4, the signal feedback end of the fourth MOS transistor Q4 is obtained, the fourth MOS transistor Q4 receives signals and the signal feedback between the grid electrode of the fourth MOS transistor Q4 and the fourth MOS transistor Q4, the signal is started to reach conduction pressure difference, and the fourth MOS signal is achieved, and the fourth MOS signal is started, and the fourth MOS signal is started, and the fourth signal is started to reach the fourth MOS signal stage and the fourth signal stage;
Setting a fifth resistor R5 to change the voltage amplitude of the source electrode of the fifth MOS tube Q5, enabling the potential of a first capacitor C1 in an initial state not to rise, synchronously feeding back to the grid electrode of the fifth MOS tube Q5 and the grid electrode of the sixth MOS tube Q6 when the first operational amplifier U1 outputs signals, enabling the grid electrode of the fifth MOS tube Q5 and the source electrode of the fifth MOS tube Q5 not to reach a conduction pressure difference, cutting off the fifth MOS tube Q5, enabling the grid electrode of the sixth MOS tube Q6 and the source electrode of the sixth MOS tube Q6 to reach a conduction pressure difference, enabling one path of signals output by the first operational amplifier U1 to pass through a twelfth resistor R12 to a grounding end loop, and the other path of signals to pass through a sixth resistor R6, a sixth MOS tube Q6 grid electrode, a thirteenth resistor R13 to a grounding end loop, feeding back a signal to a first input terminal P1 when the first input terminal P1 obtains signals, changing the source electrode voltage of the sixth MOS tube Q6 to enable the source electrode of the sixth MOS tube Q6 and the grid electrode of the sixth MOS tube Q6 not to reach the conduction pressure difference, when the switch finishes feeding back the signal of the first input terminal P1, one path of the released signal of the first capacitor C1 is fed back to the same-phase end of the second operational amplifier U2 through a drain electrode of a sixth MOS tube Q6, a source electrode of the sixth MOS tube Q6 and a thirteenth resistor R13 to a grounding end loop, the other path of the released signal of the first capacitor C1 is fed back to the same-phase end of the second operational amplifier U2, the speed of the released signal of the first capacitor C1 is changed by adjusting the resistance value of the thirteenth resistor R13, a feedback signal is obtained between a third resistor R3 and a fourth resistor R4 at the inverting end of the second operational amplifier U2, a power signal is fed back to the grounding end loop through a seventh resistor R7, a source electrode of a seventh triode Q7, a drain electrode of the seventh triode Q7 and an eighth resistor R8, a signal time table between the drain electrode of the seventh triode Q7 and the eighth resistor R8 is a positioning state indicating signal, the fourteenth resistor R14 discharges the parasitic capacitance voltage of the seventh triode Q7, the output signal of the second operational amplifier U2 is fed back to the grid electrode of the seventh triode Q7, the grid electrode of the seventh triode Q7 and the source electrode of the seventh triode Q7 cannot reach the conduction pressure difference, so that the time of the turning action after the control signal is acquired by the point switch is simulated and set, the point switch starts to act after responding to the signal, the positioning indication signal is removed in a transient state, the feedback of the completion signal is waited, when the signal amplitude of the first capacitor C1 is smaller than the voltage amplitude between the third resistor R3 and the fourth resistor R4, the second operational amplifier U2 is cut off, the positioning state indication signal is recovered, the point switch does not finish the turning action within the setting time of the turning action, and the point switch is in a fault state;
When the signal between the drain electrode of the first MOS transistor Q1 and the base electrode of the second triode Q2 is released, the power supply signal is fed back to the same phase end of the third operational amplifier U3 through the first resistor R1, one path of the output signal of the third operational amplifier U3 is fed back to the ground end loop through the ninth resistor R9 and the tenth resistor R10, the signal between the third operational amplifier U3 and the ninth resistor R9 is completed in the inversion action, the signal between the ninth resistor R9 and the tenth resistor R10 is fed back to the base electrode of the eighth triode Q8, the base electrode of the eighth triode Q8 and the emitter electrode of the eighth triode Q8 generate forward bias, the signal between the drain electrode of the seventh triode Q7 and the eighth resistor R8 is fed back to the ground end loop through the collector electrode of the eighth triode Q8, the emitter electrode of the eighth triode Q8 is removed in the stable state, the positioning state indication signal is removed, and when the switch finishes the inversion action within the set time of the inversion action, the switch is completed, and the switch has no fault.
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