CN116997878A - Power budget allocation method and related equipment - Google Patents

Abstract

The application discloses a power budget allocation method and related equipment, which are particularly used in the field of battery management, wherein the method comprises the following steps: determining a power consumption of at least one processor core included in each of the plurality of power domains during a first cycle; allocating a power budget to each power domain according to the power consumption of at least one processor core contained in each power domain in a first period, so that each power domain performs frequency adjustment in a second period based on the allocated power budget, wherein the second period is the next period of the first period; by using the method, the power budget can be fully utilized, higher power supply frequency is provided for the cores for data processing, the performance of each core is fully exerted, and the working speed and the working performance of the processor are improved.

Description

A power budget allocation method and related equipment Technical field

Embodiments of the present application relate to the field of power management, and in particular, to a power budget allocation method and related equipment.

Background technique

With the continuous development of electronic equipment configuration, multi-core processors have been widely used in computers and mobile phones. Multi-core processors refer to the integration of multiple computing engines (processor cores) in one processor, which can support multi-thread tasks; for single As for core processors, multi-core processors support decomposing the data to be processed into multiple parts and giving them to different core registers so that each arithmetic unit can work together to increase the operating speed of the processor.

Generally, multi-core processors are powered by multiple integrated voltage regulators (IVRs). That is, multi-core processors generally include multiple power domains. In order to ensure that the total power/current of multiple cores of the processor is not If the maximum supply power/current that the system design can withstand is exceeded, the power budget needs to be allocated between different power domains; in a multi-core processor that supports overclocking, the processor usually allocates the power budget evenly to the cores in the overclocked state. And based on the allocation results, the maximum frequency allowed for each core is determined, so that the power consumption of each core when running the heaviest load at the highest frequency does not exceed the power budget allocated by the processor, thus ensuring that the entire system stable operation.

Limited by the above maximum frequency, when the load running by each processor core is less than the heaviest load, the power consumption of a single processor core will be lower than its maximum allowable power consumption, and each processor core cannot fully Using the power budget allocated by the processor, the power consumption of all processor cores will also be lower than the maximum power consumption that the system can withstand. This will result in the inability to exert the maximum performance of the processor.

Contents of the invention

Embodiments of the present application provide a power budget allocation method and related equipment, which are used to allocate the power budget according to the status of the processor core corresponding to each power domain in the processor.

The first aspect of the embodiment of the present application provides a power budget allocation method, including:

When the processor is a multi-core processor, the processor contains multiple power domains, and each power domain supplies power to at least one processor core; first, it is necessary to determine the power of the processor core in each power domain in the first cycle. Power consumption, and then allocate the power budget to each power domain based on the obtained power consumption; it can be understood that the corresponding power consumption of each power domain in the first cycle can directly or indirectly reflect the processing in that power domain According to the status of the processor core, the power budget is allocated according to the power consumption, which can meet the needs of different processor cores, so that each power domain can adjust the frequency based on the allocated power budget.

In the above design, the frequency controller adjusts the power budget allocated to the processor core according to its power consumption, and then controls the frequency of the processor core according to the power budget, so that the power budget can be more reasonably allocated to meet different needs. processor core requirements. Furthermore, this method can also adjust the frequency according to the power budget. In this way, the adjusted processor core can be more consistent with its operating status and improve the working efficiency of the processor core.

In conjunction with the first aspect of the embodiments of the present application, in the first implementation manner of the first aspect of the embodiments of the present application:

The frequency controller may allocate the power budget based on the real-time power consumption of at least one processor core included in each power domain in the first cycle, or may allocate the power budget based on the real-time power consumption of at least one processor core included in each power domain in the first cycle. Allocate based on average power consumption; in this way, the frequency controller can sense the operating status of the processor core through multiple methods and provide multiple solutions for allocating the power budget.

In conjunction with the first implementation manner of the first aspect of the embodiments of the present application, in the second implementation manner of the first aspect of the embodiments of the present application:

When the frequency controller obtains the power consumption of at least one processor core included in each power domain in the first cycle, it can also calculate the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption. The load is then used as a reference for allocating the power budget according to the load. This provides a new solution for the frequency controller to allocate the budget.

Combined with the second implementation manner of the first aspect of the embodiments of the present application, in the third implementation manner of the first aspect of the embodiments of the present application:

When the frequency controller obtains the load of at least one processor core included in each power domain in the first cycle, it can also predict the predicted load of at least one processor core included in each power domain in the second cycle based on the load. The load is then used as a reference for allocating the power budget based on the predicted load; it can be understood that the predicted load of at least one processor core included in each power domain in the second cycle can directly reflect the power of the processor core in the second cycle. In this way, the frequency controller can allocate the power budget more reasonably and improve the performance of the processor core.

Combined with the third implementation manner of the first aspect of the embodiments of the present application, in the fourth implementation manner of the first aspect of the embodiments of the present application:

The frequency controller obtains the power consumption of at least one processor core included in each power domain in the first cycle, and the load of the at least one processor core included in each power domain in the first cycle, and the predicted load of at least one processor core included in each power domain in the second cycle, any one or more of them can be used as a reference for allocating power budget, so that more comprehensive perception processing can be achieved The operating status of the processor core can be used to allocate the power budget to each power domain more reasonably.

The second aspect of the embodiment of the present application provides a power budget allocation method, including:

When the processor is a multi-core processor, the processor contains multiple power domains, and each power domain supplies power to multiple processor cores. First, it is necessary to determine whether the multiple processor cores contained in each power domain are located in the first power domain. The number of active processor cores in one cycle, and then allocate the power budget to all processor cores contained in each power domain based on the number of active processor cores in the first cycle. Describe each power domain; it can be understood that the more the number of active cores in each power domain, the heavier the processor core's task of processing data, so more work margin should be allocated to it to increase its Frequency; allocating the power budget according to the number of active processor cores can meet the needs of different power domains, so that each power domain can adjust the frequency in the next cycle based on the allocated power budget.

In the above design, the frequency controller adjusts the power budget allocated to the multiple processor cores contained in each power domain according to the number of active processor cores in the first cycle, and then adjusts the power budget allocated to it according to the number of active processor cores in each power domain. Budget implementation controls the frequency of the processor core so that the power budget can be allocated more reasonably to meet the needs of different processor cores. Furthermore, this method can also adjust the frequency according to the power budget. In this way, the adjusted processor core can be more consistent with its operating status and improve the working efficiency of the processor core.

In conjunction with the second aspect of the embodiments of the present application, in the first implementation manner of the second aspect of the embodiments of the present application:

The frequency controller can also determine the power consumption of multiple processor cores included in each power domain in the first cycle, and then determine the power consumption of the multiple processor cores included in each power domain in the first cycle. The number of processor cores in the activated state and the power consumption of the multiple processor cores included in each of the multiple power domains in the first cycle, allocate the power budget to each of the power domains; In this way, the frequency controller can determine the number of processor cores that are activated in the first cycle according to the number of processor cores included in each power domain in the multiple power domains and the number of processor cores in each power domain in the multiple power domains. The power consumption of multiple processor cores included in the domain in the first cycle is used as a reference for allocating power budgets, allowing a more comprehensive perception of the operating status of the processor cores and a more reasonable allocation of power budgets for each power domain.

A third aspect of the embodiment of the present application provides a frequency controller, including:

a determining unit configured to determine the power consumption in the first cycle of at least one processor core included in each power domain of the plurality of power domains;

An allocation unit configured to allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle;

An adjustment unit, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In conjunction with the third aspect of the embodiments of the present application, in the first implementation manner of the third aspect of the embodiments of the present application:

The power consumption of the at least one processor core included in each power domain in the first cycle is the real-time power consumption or the average power consumption of the at least one processor core included in each power domain in the first cycle.

In combination with the first implementation manner of the third aspect of the embodiments of the present application, in the second implementation manner of the third aspect of the embodiments of the present application:

The frequency controller also includes a calculation unit;

The calculation unit is configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. cycle load.

Combined with the second implementation manner of the third aspect of the embodiments of the present application, in the third implementation manner of the third aspect of the embodiments of the present application:

The computing unit is further configured to predict, based on the load of at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the first period. Forecasted load over the second period.

In combination with the third implementation manner of the third aspect of the embodiments of the present application, in the fourth implementation manner of the third aspect of the embodiments of the present application:

The allocation unit is specifically configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of the at least one processor core included in each power domain in the first cycle. The power budget is allocated to each power domain based on any one of the load of the cycle and the predicted load of at least one processor core included in each power domain in the second cycle.

The fourth aspect of the embodiment of the present application provides a frequency controller, including:

a determining unit configured to determine the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain of the plurality of power domains;

An allocation unit configured to allocate the power budget to each power domain according to the number of processor cores in the activated state of the plurality of processor cores included in each power domain in the first cycle;

An adjustment unit, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In conjunction with the fourth aspect of the embodiments of the present application, in the first implementation manner of the fourth aspect of the embodiments of the present application:

The determining unit is also used to determine the power consumption in the first cycle of the multiple processor cores included in each of the multiple power domains;

The allocating unit is configured to determine the number of processor cores in the activated state within the first cycle of the multiple processor cores included in each power domain and the number of processor cores included in each power domain in the multiple power domains. Contains the power consumption of multiple processor cores in the first cycle, and allocates the power budget to each of the power domains.

A fifth aspect of the embodiment of the present application provides a processor, including:

The processor includes a processor core, a power consumption detector, a power consumption controller and a frequency regulator; the power consumption detector and the frequency regulator are respectively connected to the power consumption controller;

The power consumption detector is used to detect and determine the power consumption of at least one processor core included in each power domain in the plurality of power domains in the first cycle;

The power consumption controller is configured to allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle;

The frequency adjuster is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In conjunction with the fifth aspect of the embodiments of the present application, in the first implementation manner of the fifth aspect of the embodiments of the present application:

The power consumption of the at least one processor core included in each power domain in the first cycle is the real-time power consumption or the average power consumption of the at least one processor core included in each power domain in the first cycle.

In combination with the first implementation manner of the fifth aspect of the embodiments of the present application, in the second implementation manner of the fifth aspect of the embodiments of the present application:

The power consumption controller is also configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain. first cycle load.

Combined with the second implementation manner of the fifth aspect of the embodiments of the present application, in the third implementation manner of the fifth aspect of the embodiments of the present application:

The power consumption controller is further configured to predict, based on the load of at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the said first period. Forecasted load during the second period.

In combination with the third implementation manner of the fifth aspect of the embodiments of the present application, in the fourth implementation manner of the fifth aspect of the embodiments of the present application:

The power consumption controller is specifically configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of the at least one processor core included in each power domain in the first cycle. A power budget is allocated to each power domain based on any one of the load in one cycle and the predicted load in the second cycle of at least one processor core included in each power domain.

A sixth aspect of the embodiment of the present application provides a processor, including:

The processor includes a processor core, a power consumption controller and a frequency regulator; the frequency regulator is respectively connected to the power consumption controller;

The power consumption controller determines the number of processor cores that are active in the first cycle among the multiple processor cores contained in each power domain of the plurality of power domains; according to the number of processor cores contained in each power domain The number of processor cores in the active state of the multiple processor cores in the first cycle, and allocate the power budget to each power domain;

The frequency adjuster is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In conjunction with the sixth aspect of the embodiments of the present application, in the first implementation manner of the sixth aspect of the embodiments of the present application:

The processor also includes a power consumption detector, and the power consumption detector is connected to the power consumption controller;

The power consumption is used to determine the power consumption of multiple processor cores included in each of the multiple power domains in the first cycle;

The power consumption controller is specifically configured to determine the number of processor cores that are active in the first cycle and the number of processor cores included in each power domain. The power consumption in the first cycle of the multiple processor cores included in the power domain is allocated to each power domain.

A seventh aspect of the embodiments of the present application provides an electronic device, which includes the processor described in any of the fifth or sixth aspects.

The above aspects or other aspects of the present application will be specifically introduced in the following embodiments.

Description of the drawings

Figure 1 is a core power distribution table of a processor provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a multi-core processor provided by an embodiment of the present application;

Figure 3 is a schematic flowchart of a power margin allocation method provided by an embodiment of the present application;

Figure 4 is a schematic flow chart of another power margin allocation method provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of a frequency controller provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of another frequency controller provided by an embodiment of the present application;

Figure 7 is a schematic structural diagram of another frequency controller provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another frequency controller provided by an embodiment of the present application.

Detailed ways

Embodiments of the present application provide a power budget allocation method and related equipment, which are used to allocate the power budget according to the status of the processor core corresponding to each power domain in the processor.

The technical solutions in this application will be described in detail below with reference to the accompanying drawings in this application. Obviously, the described embodiments are only some of the embodiments of this application, rather than all of the embodiments.

Various embodiments disclosed in this application may be applied to electronic devices with overclocking functions. In some embodiments of the present application, the electronic device may be a computer device having a processor (such as a central processing unit (CPU)), such as a desktop computer. It should also be understood that in other embodiments of the present application, the electronic device may also be a portable electronic device with a processor, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), or a vehicle-mounted device. wait. Exemplary embodiments of portable electronic devices include, but are not limited to, carrying Or portable electronic devices with other operating systems.

Multi-core processor refers to the integration of two or more complete computing engines (processor cores) in one processor. At this time, the processor can support multiple processor cores on the system bus, and the bus controller provides all Bus control signals and command signals. As the performance requirements for processors to process data are getting higher and higher, if you only increase the speed of a single-core chip, too much heat will be generated due to the high operating frequency. At the same time, the development of semiconductor technology also limits the frequency of single-core chips. , so multi-core processors came into being. The architecture of multi-core processors embodies the concept of "divide and conquer", that is, dividing the tasks that need to be processed and assigning multiple divided tasks to multiple cores for processing. In this way, one processor can complete the task within a specific clock cycle. Perform more tasks. Multi-core technology allows the processor to process tasks in parallel, and the multi-core system is easier to expand. It can incorporate more powerful processing performance into a slimmer form factor, consume less power, and generate more heat. Few; multi-core processors have become an inevitable product of processor development.

Processor core overclocking technology (inter turbo boost) means that when a running program is started, the processor will automatically accelerate to an appropriate frequency to ensure that the program runs smoothly; when dealing with complex applications, the processor can automatically increase the running frequency to increase speed. , to process tasks with higher performance requirements; when switching tasks, the processor will immediately be in a power-saving state. This not only ensures the effective use of energy, but also greatly increases the program speed. Popularly understood as automatic overclocking, the processor will automatically adjust the processor frequency according to the current workload, so as to maximize performance during heavy tasks. The purpose of this technology is to maximize the performance potential of the processor without exceeding the maximum power.

When powering multi-core processors, regional independent power supply is usually adopted, that is, the processor is divided into multiple power domains, and each power domain supplies power independently. Overclocking turbo technology allows some processor cores to be powered , the power is added to other processor cores to allow individual processor cores to run at higher frequencies, as long as the total power/current consumed by the processor does not exceed the maximum power supply/current that the system design can withstand. Therefore, the power budget needs to be reasonably allocated among multiple power domains, and the highest frequency allowed for the core in the turbo state needs to be formulated based on the allocated power budget.

In the existing technology, the power budget is generally allocated equally to each power domain, that is, the power budget allocated to each power domain is the same, and then in the middle of each power domain, the power budget is allocated according to the heaviest load that each power domain can bear. Load, determine the maximum frequency of the processor core; it is understandable that the operating frequency of the processor core in each power domain is limited by the maximum frequency, that is, when the processor core is in an overclocked state, the increased operating frequency cannot exceed the maximum frequency.

Figure 1 provides a core power distribution table of a processor according to an embodiment of the present application. The processor includes 16 cores and 32 threads. It can be understood that in the first column, no processor core is in an overclocked state, and in the second column In the column, there is one processor core in the overclocking state, and so on; for example, in the ninth column of data, in this state, the power consumption of 8 processor cores in the turbo state is between 14W and 14.5W. Around 18.34W, which is significantly lower than the 18.34W power consumption of a single processor core in turbo in the second column of data. At the same time, when 8 processor cores are in turbo state, the total power consumption of the processor is 122.87W, which is significantly lower than the peak power consumption of 144.49W when 10 processor cores are in turbo state in the 11th column of data. Obviously, this way of allocating power margin means that each core in the turbo state is limited by the maximum frequency. In many cases, the power budget cannot be fully used, and the maximum performance of each core cannot be exerted. Therefore, it is necessary to reformulate the way of allocating power budget to improve the performance of turbo function.

In view of this, this application provides a power budget allocation method to adjust the power budget allocated to the processor core according to its power consumption, and then controls the frequency of the processor core according to the power budget, so that the power budget can Get a more reasonable allocation to meet the needs of different processor cores. Furthermore, this method can also adjust the frequency according to the power budget. In this way, the adjusted processor core can be more consistent with its operating status and improve the working efficiency of the processor core.

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention.

The terms "system" and "network" in the embodiments of this application may be used interchangeably. "At least one" means one or more, and "plurality" means two or more. "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the priority or importance of multiple objects. For example, the first moment and the second moment are just to distinguish different moments, but do not indicate the difference in priority or importance of the two moments.

FIG. 2 exemplarily shows a schematic structural diagram of a processor 200 provided by an embodiment of the present application. As shown in FIG. 2 , the processor 200 may include at least one processor core, such as processor core 20 , processor core 21 , processor core 22 and processor core 23 . The processor 200 may also include non-core components, such as general-purpose units (including counters, decoders, signal generators, etc.), accelerator units, input/output control units, interface units, internal memories, external buffers, etc. Among them, each processor core and non-core components can be connected through a communication bus (not shown in Figure 2) to realize data transmission operations.

It should be understood that the above-mentioned processor 200 may be a chip. For example, the processor 200 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), or It can be a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), or a microcontroller Unit, MCU), can also be a programmable logic device (PLD) or other integrated chip. It should be noted that the processor 200 in the embodiment of the present application may also be an integrated circuit chip with signal processing capabilities. For example, the above-mentioned processor 100 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, Discrete hardware components. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

It can be understood that the memory (such as internal memory and external cache) in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of illustration, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that memory for the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

In the embodiment of the present application, continuing to refer to FIG. 2 , the processor may further include a frequency controller 24 , and each processor core may also be provided with a frequency regulator. The frequency controller 24 may be connected to each processor core. frequency regulator communication connection. In this way, when controlling the overclocking adjustment of each processor core, the frequency controller 24 can send a frequency control instruction to the frequency adjuster of the processor core, so that the frequency adjuster of the processor core adjusts the processing according to the frequency control instruction. The frequency of the processor core, for example, is adjusted to be greater than the maximum frequency set by the manufacturer.

It should be noted that FIG. 2 is only an illustrative illustration. In other possible examples, the frequency regulator can also be set in only one or several processor cores. In this way, the frequency controller 24 can only be set for The frequency regulator controls the frequency of the processor core. Alternatively, a frequency adjuster can also be provided in a non-core component. In this way, the frequency controller 24 can not only control the frequency of the processor core, but also control the frequency of the non-core component. Of course, the non-core components mentioned here refer to components that work at a set frequency.

The power budget allocation method in this application will be introduced below by taking controlling the frequency of one processor core as an example. Controlling other processor cores or non-processor cores will not be described again.

Based on the processor shown in Figure 2, Figure 3 exemplarily shows a flow chart corresponding to a power budget allocation method provided by an embodiment of the present application. This method is suitable for a frequency controller, such as the frequency controller shown in Figure 2 twenty four. In the embodiment of the present application, the frequency controller can perform the power budget allocation method in a periodic manner. Figure 3 exemplarily introduces the primary frequency control process of the frequency controller. As shown in Figure 3, the method includes:

301. The frequency controller determines the power consumption in the first cycle of at least one processor core included in each power domain of the plurality of power domains.

In the embodiment of the present application, the power supply mode of the processor may be a pre-core power supply mode, that is, each power domain only includes one processor core, and each processor core is independently powered for it; it may also be a pre-core power supply mode. In the die power supply mode, each power domain includes multiple processor cores, and the processor supplies power to multiple processors belonging to the same power domain; in this way, the core working status is a reference. It can be known from the mathematical formula: Wi=Pi/(Fi Vi2); where Wi is the load, Pi is the power consumption, Fi is the power supply frequency corresponding to the core, and Vi is the power supply voltage corresponding to the voltage domain. That is, when the processor obtains the power consumption corresponding to the first cycle, it also needs to obtain the power supply voltage and power supply frequency of the power domain corresponding to each core in the first cycle. The processor can divide multiple power domains for multiple processor cores. , each power domain includes at least one processor core.

The frequency controller needs to predetermine the period to allocate the power budget; since evenly allocating a fixed power margin to each power domain will make the maximum frequency that each power domain can achieve be limited by the fixed power budget, and the maximum power supply The frequency will in turn result in the inability to fully utilize the maximum performance of each core; therefore, the frequency controller needs to make a more reasonable allocation of power margin according to the real-time status of each battery domain. For example, the processor can determine an allocated period. , monitor the status of each power domain in one cycle, and then allocate the allocation in the next cycle based on the status. It is understandable that the power budget can also be allocated once in multiple cycles, and there is no specific limit.

For example, the frequency controller can obtain the power consumption of each power domain through a power consumption detector, use the power consumption to sense the status of each power domain, and allocate a reasonable power budget to it; it is understandable that power consumption control The device can detect the average power consumption corresponding to each power domain within a cycle, and can also obtain real-time power consumption, with no specific limitations.

It can be understood that when a power domain only includes one processor core, the power consumption of each power domain obtained by the power consumption controller is the power consumption of the processor core; when a power domain includes multiple processor cores When , the power consumption of each power domain obtained by the power consumption controller is the total power consumption of all processor cores in the power domain.

302. The frequency controller calculates the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. load.

The frequency controller also uses the power consumption to determine the load of each power domain in the first cycle, uses the load as the processing rate, and then calculates the load of each core in the first cycle according to the above formula, and then uses this load as the The reference item for allocating the power budget in the second period.

303. The frequency controller predicts the load of at least one processor core included in each power domain in the second cycle based on the load of the at least one processor core included in each power domain in the second cycle. predicted load.

After the frequency controller determines the load of each power domain in the first cycle, it can also use the load to predict the predicted load of each power domain in the second cycle. The load can more directly reflect the operating frequency requirements of each power domain in the second cycle. Therefore, allocating the power budget in the second cycle based on the predicted load can make the allocated power budget more reasonable.

304. The frequency controller determines the load of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. , and any one or more of the predicted load of at least one processor core included in each power domain in the second period, allocate a power budget to each power domain.

In a first optional manner, the frequency controller can allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle; for example, the frequency controller can The power budget is allocated according to the following formula:

PB _i =(P _i /P _total )*PB _total

Among them, PB _i is the power margin allocated by the system to the i-th power domain, _Pi is the power consumption in the first cycle corresponding to the i-th power domain, P _total is the sum of power consumption corresponding to all power domains, PB _total is the total amount of power budget provided by the system; it can be understood that the higher the power consumption of the power domain in the first cycle, the greater the data processing workload performed by the power domain, and more data needs to be allocated to it. According to the power budget, the frequency of its internal processor core is increased, so that the processing speed of the processor core can be increased and the performance of the processor core can be fully utilized.

In a second optional manner, the frequency controller may allocate a power budget to each power domain based on the load of at least one processor core included in each power domain in the first cycle; for example, The power budget can be allocated according to the following formula:

PB _i =(A _i /A _total )*PB _total

Among them, PB _i is the power margin allocated by the system to the i-th power domain, A _i is the load in the first cycle corresponding to the i-th power domain, A _total is the total load corresponding to all power domains, and PB _total is the system The total amount of power budget provided; it can be understood that the greater the load corresponding to the power domain in the first cycle, the greater the data processing workload performed by the power domain, and more power budget needs to be allocated to it. Increasing the frequency of its internal processor core can increase the processing speed of the processor core and give full play to the performance of the processor core.

In a third optional manner, the frequency controller may allocate a power budget to each power domain based on the predicted load of at least one processor core included in each power domain during the second period; exemplary , the formula used is similar to the formula in the second optional method above, but A _i becomes the predicted load in the second cycle corresponding to the i-th power domain, and A _total is the sum of predicted loads corresponding to all power domains. , PB _total is the total power budget provided by the system; it can be understood that the predicted load can directly reflect the power demand of each power domain in the second cycle. The larger the predicted load corresponding to the power domain in the second cycle, the greater the predicted load. The greater the data processing workload that this power domain will perform, the more power budget needs to be allocated to it and the frequency of its internal processor core should be increased. This can increase the processing speed of the processor core and give full play to the capabilities of the processor core. performance.

In a fourth optional manner, the frequency controller may be based on the load of at least one processor core included in each power domain in the first cycle and the load of at least one processor core included in each power domain in the first period. The predicted load in the second cycle is used to allocate the power budget to each power domain. Specifically, the exponentially weighted moving average EWMA value of the two can be calculated, and the power budget is allocated based on the EWMA value corresponding to each power domain; this way Combined with the implementation status and predicted status of the processor core, the power budget is allocated more reasonably.

Specifically, the power consumption of at least one processor core included in each power domain in the first cycle, the load of at least one processor core included in each power domain in the first cycle, and the power consumption of at least one processor core included in each power domain in the first cycle. The predicted load of at least one processor core in the second period can be combined in any combination, and the frequency controller can arbitrarily select one or more items as the basis for allocating the power budget, and there is no specific limit.

305. The frequency controller adjusts the frequency of each power domain in the second cycle according to the allocated power budget.

It can be understood that the second period is the next period of the first period. After the frequency controller allocates power margin to each power domain, it adjusts the power supply voltage in the power domain corresponding to each processor core according to the allocated power margin, and then determines the core based on the power budget and power supply voltage. The corresponding maximum power supply frequency, and the corresponding operating frequency of the core is continuously adjusted according to the maximum power supply frequency.

This application provides a power budget allocation method to adjust the power budget allocated to the processor core according to its power consumption, and then controls the frequency of the processor core according to the power budget, so that the power budget can be more reasonable. Allocation to meet the needs of different processor cores. Furthermore, this method can also adjust the frequency according to the power budget. In this way, the adjusted processor core can be more consistent with its operating status and improve the working efficiency of the processor core.

Based on the processor shown in Figure 2, Figure 4 exemplarily shows a flow chart corresponding to another power budget allocation method provided by an embodiment of the present application. This method is suitable for a frequency controller, such as the frequency control shown in Figure 2 Device 24. In the embodiment of this application, the power supply mode of the processor is a pre-die power supply mode, that is, each power domain includes multiple processor cores, and the processor supplies power to multiple processors belonging to the same power domain; as shown in Figure 4 As shown, the method includes:

401. The frequency controller determines the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain of the multiple power domains.

In this embodiment, each power domain of the processor includes multiple processor cores, and the multiple processor cores are collectively powered. It can be understood that when the processor core is in an activated (overclocking) state, it is necessary to Increase the power supply frequency and improve the performance of the core. For example, the processor can allocate the power margin in the next cycle to each power domain according to the number of cores in the active state in each power domain in the current cycle. The number of cores in the power domain in the active state is The more, the more power margin needs to be allocated to that power domain.

402. The frequency controller determines the power consumption in the first cycle of the multiple processor cores included in each power domain of the multiple power domains.

It can be understood that the frequency controller can still use the power consumption of the multiple processor cores included in each power domain in the first cycle as a condition for allocating power margin. Specifically, this step is the same as the embodiment shown in Figure 3 Step 301 in is similar and is not specifically limited.

403. The frequency controller adjusts the frequency according to the number of processor cores that are activated in the first cycle among the multiple processor cores included in each power domain and/or the frequency of each power domain in the multiple power domains. Contains the power consumption of multiple processor cores in the first cycle, and allocates the power budget to each of the power domains.

For example, in the first implementation, the power budget can be allocated according to the following formula:

PB _i =(N _i /N _total )*PB _total

Among them, PB _i is the power margin allocated by the system to the i-th power domain, _Ni is the number of active processors in the i-th power domain, and N _total is the active processing corresponding to all power domains. The total number of processor cores, PB _total is the total power budget provided by the system. For example, in the second implementation, the frequency controller may adjust the frequency according to the number of processor cores that are active in the first cycle and the plurality of power supplies. The power consumption of multiple processor cores included in each power domain in the domain in the first cycle is used to allocate the power budget; that is, the power budget is divided into two parts: PB _totalA and PB _totalB , where PB _totalA is used to calculate the power budget according to the power domain. The power budget is allocated corresponding to the average power consumption. PB _totalB is used to allocate according to the number of active cores in the power domain. Finally, the power budgets allocated by the two are added together to obtain the final power allocated to the power domain. Budget.

Specifically, there are many formulas for calculating the power budget, as long as the power budget allocated to the power domain is positively correlated with the greater the power consumption corresponding to the power domain, or the greater the number of activated cores, the specific form is No restrictions.

404. The frequency controller adjusts the frequency of each power domain in the second cycle according to the allocated power budget.

It can be understood that this step is similar to step 305 in the embodiment shown in FIG. 3 and will not be described again.

According to the foregoing method, FIG. 5 is a schematic structural diagram of a frequency controller 500 provided by an embodiment of the present application. The frequency controller 500 may be a chip or a circuit, such as a chip or circuit that may be disposed in a processor. The frequency controller 500 may correspond to the frequency controller 24 in the above method. The frequency controller 500 can implement any one or any corresponding steps of the method shown in FIG. 3 . As shown in FIG. 5 , the frequency controller 500 may include a monitoring circuit 501 and a control circuit 502 . Further, the frequency controller 500 may also include a bus system, and the monitoring circuit 501 and the control circuit 502 may be connected through the bus system. Moreover, the monitoring circuit 501 can also be connected to the power consumption detector of each processor core through the bus system, and the control circuit 502 can also be connected to the frequency regulator of each processor core through the bus system.

In this embodiment of the present application, the monitoring circuit 501 may determine the power consumption of at least one processor core included in each of the multiple power domains in the first cycle, and send it to the control circuit 502 . Correspondingly, the control circuit 502 may allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle, and control the frequency according to the allocated power budget. The regulator performs frequency adjustment.

According to the foregoing method, FIG. 6 is a schematic structural diagram of another frequency controller 600 provided by an embodiment of the present application. The frequency controller 600 may be a chip or a circuit, such as a chip or circuit that may be disposed in a processor. The frequency controller 600 may correspond to the frequency controller 24 in the above method. The frequency controller 600 can implement any one or any number of corresponding method steps as shown in FIG. 4 . As shown in FIG. 6 , the frequency controller 600 may include a monitoring circuit 601 and a control circuit 602 . Further, the frequency controller 600 may also include a bus system, and the monitoring circuit 601 and the control circuit 602 may be connected through the bus system. Moreover, the monitoring circuit 601 can also be connected to the power consumption detector of each processor core through the bus system, and the control circuit 602 can also be connected to the frequency regulator of each processor core through the bus system.

In this embodiment of the present application, the monitoring circuit 601 may determine the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain in the multiple power domains, and send it to the control circuit. 602. Correspondingly, the control circuit 602 may allocate the power budget to each power domain according to the number of processor cores included in each power domain that are in the active state in the first cycle, and according to the allocation The power budget control frequency regulator performs frequency regulation.

According to the foregoing method, FIG. 7 is a schematic structural diagram of another frequency controller 700 provided by an embodiment of the present application. The frequency controller 700 may be a chip or a circuit, such as a chip or circuit that may be disposed in a processor. The frequency controller 700 may correspond to the frequency controller 24 in the above method. The frequency controller 700 can implement any one or any corresponding steps of the method shown in Figure 3 above. As shown in FIG. 7 , the frequency controller 700 may include a determination unit 701 , a distribution unit 702 and an adjustment unit 703 .

The determining unit 701 is used to determine the power consumption of at least one processor core included in each power domain in the plurality of power domains in the first cycle.

The allocation unit 702 is configured to allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle.

The adjustment unit 703 is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, and the second period is the next period of the first period.

In an optional implementation, the power consumption of at least one processor core included in each power domain in the first cycle is the power consumption of the at least one processor core included in each power domain in the first cycle. Real-time power consumption or average power consumption.

In an optional implementation, the frequency controller 700 further includes a calculation unit 704.

The calculation unit 704 is configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. one cycle of load.

In an optional implementation, the computing unit 704 is further configured to predict, based on the load of at least one processor core included in each power domain in the first cycle, that each power domain contains The predicted load of at least one processor core during the second period.

In an optional implementation, the allocating unit 702 is specifically configured to calculate the power consumption of at least one processor core included in each power domain according to the power consumption in the first cycle. The power budget is allocated to any one of the load of at least one processor core in the first period and the predicted load of at least one processor core included in each power domain in the second period. Describe each power domain.

It can be understood that the functions of each unit in the above frequency controller 700 can be implemented with reference to the corresponding method embodiment, and will not be described again here.

It should be understood that the above division of the units of the frequency controller 700 is only a division of logical functions. During actual implementation, it should be understood that the above division of the units of the frequency controller 700 is only a division of logical functions. In actual implementation, all of them can be or partially integrated into a physical entity, or physically separate. In this embodiment of the present application, the acquisition unit 701 can be implemented by the monitoring circuit 501 of FIG. 5 , and the determination unit 702 and the adjustment unit 703 can be implemented by the control circuit 502 of FIG. 5 .

According to the foregoing method, FIG. 8 is a schematic structural diagram of another frequency controller 800 provided by an embodiment of the present application. The frequency controller 800 may be a chip or a circuit, such as a chip or circuit that may be disposed in a processor. The frequency controller 800 may correspond to the frequency controller 24 in the above method. The frequency controller 800 can implement any one or more of the corresponding method steps shown in Figure 4 above. As shown in FIG. 8 , the frequency controller 800 may include a determination unit 801 , a distribution unit 802 and an adjustment unit 803 .

The determining unit 801 is used to determine the number of processor cores that are in an activated state in the first cycle among the multiple processor cores included in each power domain of the multiple power domains.

The allocation unit 802 is configured to allocate the power budget to each power supply domain according to the number of processor cores in the activated state of the plurality of processor cores included in each power supply domain in the first cycle.

The adjustment unit 803 is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, and the second period is the next period of the first period.

In an optional implementation, the determining unit 801 is also used to determine the power consumption in the first cycle of multiple processor cores included in each of the multiple power domains;

The allocating unit 802 is configured to calculate the number of processor cores that are activated in the first cycle according to the number of processor cores included in each power domain and each power domain in the multiple power domains. The power consumption of the included multiple processor cores in the first cycle is allocated to the power budget of each power domain.

It can be understood that the functions of each unit in the above frequency controller 800 can be implemented with reference to the corresponding method embodiment, and will not be described again here.

It should be understood that the above division of the units of the frequency controller 800 is only a division of logical functions. In actual implementation, they can be fully or partially integrated into a physical entity, or they can also be physically separated. In this embodiment of the present application, the acquisition unit 801 can be implemented by the monitoring circuit 601 of FIG. 6 , and the determination unit 802 and the adjustment unit 803 can be implemented by the control circuit 602 of FIG. 6 .

According to the method provided by the embodiment of the present application, the present application also provides a computer program product. The computer program product includes: computer program code. When the computer program code is run on a computer, it causes the computer to execute the steps shown in Figures 1 to 4. The method of any one of the embodiments is shown.

According to the method provided by the embodiment of the present application, the present application also provides a computer-readable storage medium. The computer-readable medium stores program code. When the program code is run on a computer, it causes the computer to execute Figures 1 to 5 The method of any of the embodiments shown.

The terms "component", "module", "system", etc. used in this specification are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, a thread of execution, a program and/or a computer running on a processor. Through the illustrations, both applications running on the computing device and the computing device may be components. One or more components can reside in a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. Additionally, these components can execute from various computer-readable media having various data structures stored thereon. A component may, for example, be based on a signal having one or more data packets (eg, data from two components interacting with another component, a local system, a distributed system, and/or a network, such as the Internet, which interacts with other systems via signals) Communicate through local and/or remote processes.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or a combination of computer software and electronic hardware. accomplish. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (22)

A power budget allocation method, characterized in that the method includes: Determine the power consumption in the first cycle of at least one processor core included in each power domain in the plurality of power domains; According to the power consumption of at least one processor core included in each power domain in the first cycle, the power budget is allocated to each power domain, so that each power domain in the second cycle is based on the allocation. Frequency adjustment is performed according to the obtained power budget, and the second period is the next period of the first period. The method of claim 1, wherein the power consumption of at least one processor core included in each power domain in the first cycle is Real-time power consumption or average power consumption in the first cycle. The method of claim 2, further comprising: Calculate the load of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. The method of claim 3, further comprising: According to the load of the at least one processor core included in each power domain in the first cycle, the predicted load of the at least one processor core included in each power domain in the second cycle is predicted. The method of claim 4, wherein the power budget is allocated to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle, include: According to the power consumption of at least one processor core included in each power domain in the first cycle, the load of the at least one processor core included in each power domain in the first cycle, and the Allocate a power budget to each power domain based on any one or more of the predicted loads of at least one processor core included in each power domain in the second period. A power budget allocation method, characterized in that the method includes: Determine the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain in the multiple power domains; According to the number of processor cores in the active state of the multiple processor cores included in each power domain in the first cycle, a power budget is allocated to each power domain such that each power supply domain The domain performs frequency adjustment based on the allocated power budget in a second period, which is a period next to the first period. The method of claim 6, further comprising: Determine the power consumption in the first cycle of multiple processor cores included in each of the multiple power domains; Allocating a power budget to each power domain based on the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain includes: According to the number of processor cores that are activated in the first cycle and the number of processor cores included in each of the multiple power domains. In the first cycle of power consumption, a power budget is allocated to each of the power domains. A frequency controller, characterized by including: Determining unit, used to determine the power consumption in the first cycle of at least one processor core included in each power domain in the plurality of power domains; An allocation unit configured to allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle; An adjustment unit, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period. The frequency controller according to claim 8, wherein the power consumption of at least one processor core included in each power domain in the first cycle is The real-time power consumption or average power consumption of the core in the first cycle. The frequency controller according to claim 9, characterized in that the frequency controller further includes a calculation unit; The calculation unit is configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle based on the power consumption of the at least one processor core included in each power domain in the first cycle. cycle load. The frequency controller according to claim 10, characterized in that: The computing unit is further configured to predict, based on the load of at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the first period. Forecasted load over the second period. The frequency controller according to any one of claims 8 to 11, characterized in that, The allocation unit is specifically configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of the at least one processor core included in each power domain in the first cycle. The power budget is allocated to each power domain based on any one of the load of the cycle and the predicted load of at least one processor core included in each power domain in the second cycle. A frequency controller, characterized in that the frequency controller includes: a determining unit configured to determine the number of processor cores that are active in the first cycle among the multiple processor cores included in each power domain of the plurality of power domains; An allocation unit configured to allocate the power budget to each power domain according to the number of processor cores in the activated state of the plurality of processor cores included in each power domain in the first cycle; An adjustment unit, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period. The frequency controller according to claim 13, characterized in that: The determining unit is also used to determine the power consumption in the first cycle of the multiple processor cores included in each of the multiple power domains; The allocating unit is configured to determine the number of processor cores in the activated state within the first cycle of the multiple processor cores included in each power domain and the number of processor cores included in each power domain in the multiple power domains. Contains the power consumption of multiple processor cores in the first cycle, and allocates the power budget to each of the power domains. A processor, characterized in that the processor includes a processor core, a power consumption detector, a power consumption controller and a frequency regulator; the power consumption detector and the frequency regulator are respectively located in the power consumption The controller is connected; The power consumption detector is used to detect and determine the power consumption of at least one processor core included in each power domain in the plurality of power domains in the first cycle; The power consumption controller is configured to allocate a power budget to each power domain based on the power consumption of at least one processor core included in each power domain in the first cycle; The frequency adjuster is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period. The processor of claim 15, wherein the power consumption of the at least one processor core included in each power domain in the first cycle is Real-time power consumption or average power consumption in the first cycle. The processor according to claim 16, wherein the power consumption controller is further configured to calculate the power consumption of each processor core according to the power consumption of at least one processor core included in each power domain in the first cycle. The load of at least one processor core included in each power domain during the first cycle. The processor of claim 17, wherein the power consumption controller is further configured to predict the power consumption of the at least one processor core included in each power domain in the first cycle. The predicted load of at least one processor core included in each power domain during the second period. The processor according to claim 17, characterized in that the power consumption controller is specifically configured to calculate each power consumption according to the power consumption of at least one processor core included in each power domain in the first cycle. Any one of the load of at least one processor core included in the power domain in the first cycle and the predicted load of at least one processor core included in each power domain in the second cycle will be A power budget is allocated to each power domain. A processor, characterized in that the processor includes a processor core, a power consumption controller and a frequency regulator; the frequency regulator is respectively connected to the power consumption controller; The power consumption controller determines the number of processor cores that are active in the first cycle among the multiple processor cores contained in each power domain of the plurality of power domains; according to the number of processor cores contained in each power domain The number of processor cores in the active state of the multiple processor cores in the first cycle, and allocate the power budget to each power domain; The frequency adjuster is configured to adjust the frequency of each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period. The processor according to claim 20, wherein the processor further includes a power consumption detector, and the power consumption detector is connected to the power consumption controller; The power consumption is used to determine the power consumption of multiple processor cores included in each of the multiple power domains in the first cycle; The power consumption controller is specifically configured to determine the number of processor cores that are active in the first cycle and the number of processor cores included in each power domain. The power consumption in the first cycle of the multiple processor cores included in the power domain is allocated to each power domain. An electronic device, characterized by comprising the processor according to any one of claims 15 to 21.