CN116997878A - Power budget allocation method and related equipment - Google Patents

Power budget allocation method and related equipment Download PDF

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Publication number
CN116997878A
CN116997878A CN202080103358.0A CN202080103358A CN116997878A CN 116997878 A CN116997878 A CN 116997878A CN 202080103358 A CN202080103358 A CN 202080103358A CN 116997878 A CN116997878 A CN 116997878A
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Prior art keywords
power
period
processor
power consumption
processor core
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CN202080103358.0A
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Inventor
胡荻
郭东之
李继明
刘臻
王哲
库特拉德米特罗
马里亚什尤里
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The application discloses a power budget allocation method and related equipment, which are particularly used in the field of battery management, wherein the method comprises the following steps: determining a power consumption of at least one processor core included in each of the plurality of power domains during a first cycle; allocating a power budget to each power domain according to the power consumption of at least one processor core contained in each power domain in a first period, so that each power domain performs frequency adjustment in a second period based on the allocated power budget, wherein the second period is the next period of the first period; by using the method, the power budget can be fully utilized, higher power supply frequency is provided for the cores for data processing, the performance of each core is fully exerted, and the working speed and the working performance of the processor are improved.

Description

Power budget allocation method and related equipment Technical Field
The embodiment of the application relates to the field of power management, in particular to a power budget allocation method and related equipment.
Background
With the continuous development of electronic equipment configuration, a multi-core processor is widely applied to the fields of computers and mobile phones, wherein the multi-core processor is used for integrating a plurality of computing engines (processor cores) in one processor and can support multi-line tasks; for a single-core processor, the multi-core processor supports the decomposition of data to be processed into a plurality of parts, and different core registers are respectively given to enable all arithmetic units to jointly operate, so that the running speed of the processor is improved.
Generally, the multi-core processor is powered by a plurality of integrated circuit voltage-stabilized power supplies (integrated voltage regulator, IVR), that is, the multi-core processor generally comprises a plurality of power domains, and in order to ensure that the total power/current of a plurality of cores of the processor does not exceed the maximum power/current which can be born by the system design, power budgets need to be allocated among different power domains; in a multi-core processor supporting an over-frequency function, a power budget is generally allocated to cores in an over-frequency state by the processor, and the highest frequency allowed to be reached by each core is determined according to an allocation result, so that power consumption generated when each core operates the heaviest load in the highest frequency state does not exceed the power budget allocated to the processor, and stable operation of the whole system is ensured.
With the limitation of the highest frequency, when the load operated by each processor core is smaller than the heaviest load, the power consumption of the single processor core will be lower than the maximum power consumption allowed by the single processor core, each processor core cannot fully utilize the power budget allocated by the processor, and the power consumption of all the processor cores will be lower than the maximum power consumption that can be born by the system, thus, the maximum performance of the processor cannot be exerted.
Disclosure of Invention
The embodiment of the application provides a power budget allocation method and related equipment, which are used for allocating power budgets according to the states of processor cores corresponding to power domains in a processor.
A first aspect of an embodiment of the present application provides a method for allocating a power budget, including:
when the processor is a multi-core processor, the processor comprises a plurality of power domains, and each power domain supplies power for at least one processor core; first, it is necessary to determine the power consumption of the processor core in each power domain in a first period, and then allocate a power budget to each power domain based on the obtained power consumption; it may be appreciated that the power consumption of each power domain in the first period may directly or indirectly reflect the state of the processor core in the power domain, allocate a power budget according to the power consumption, and may satisfy the requirements of different processor cores, so that each power domain may perform frequency adjustment based on the allocated power budget.
In the design, the frequency controller adjusts the power budget allocated to the processor core according to the power consumption of the processor core, and then controls the frequency of the processor core according to the power budget, so that the power budget can be more reasonably allocated, and the requirements of different processor cores are met. Furthermore, the mode can also carry out frequency adjustment according to the power budget, so that the adjusted processor core can be more in line with the running state of the processor core, and the working efficiency of the processor core is improved.
In combination with the first aspect of the embodiment of the present application, in a first implementation manner of the first aspect of the embodiment of the present application:
the frequency controller may allocate the power budget according to the real-time power consumption of the at least one processor core included in each power domain in the first period, or may allocate the power budget according to the average power consumption of the at least one processor core included in each power domain in the first period; in this way, the frequency controller may sense the operating state of the processor core in a variety of ways, providing a variety of schemes for its allocation of power budgets.
With reference to the first implementation manner of the first aspect of the embodiment of the present application, in a second implementation manner of the first aspect of the embodiment of the present application:
the frequency controller can calculate the load of at least one processor core in each power domain in the first period according to the power consumption when the power consumption of at least one processor core in each power domain in the first period is obtained, and then the load is used as a reference for distributing the power budget according to the load, so that a new scheme is provided for distributing the budget for the frequency controller.
With reference to the second implementation manner of the first aspect of the embodiment of the present application, in a third implementation manner of the first aspect of the embodiment of the present application:
The frequency controller may further predict a predicted load of at least one processor core included in each power domain in a second period according to the load when obtaining the load of the at least one processor core included in each power domain in the first period, and then use the predicted load as a reference for allocating the power budget; it can be appreciated that the predicted load of at least one processor core in the second period included in each power domain can directly reflect the power demand of the processor core in the second period, so that the frequency controller can more reasonably allocate power budget for the frequency controller, and improve the working performance of the processor core.
With reference to the third implementation manner of the first aspect of the embodiment of the present application, in a fourth implementation manner of the first aspect of the embodiment of the present application:
after obtaining the power consumption of at least one processor core contained in each power domain in the first period, the load of at least one processor core contained in each power domain in the first period and the predicted load of at least one processor core contained in each power domain in the second period, the frequency controller can be used as a reference for distributing power budget according to any one or more of the load and the predicted load, so that the running state of the processor core can be more comprehensively perceived, and the power budget can be more reasonably distributed for each power domain.
A second aspect of an embodiment of the present application provides a method for allocating a power budget, including:
when the processor is a multi-core processor, the processor comprises a plurality of power domains, and each power domain supplies power for a plurality of processor cores; firstly, determining the number of processor cores of which the plurality of processor cores are in an activated state in a first period, which are contained in each power domain, and then distributing power budget to each power domain according to the number of the processor cores of which the plurality of processor cores are in the activated state in the first period; it can be appreciated that the more cores in each power domain are active, the heavier the task of processing data by the processor core is, so that more working margin is allocated to the processor core, and the frequency is increased; the power budget is allocated according to the number of the processor cores in the active state, so that the requirements of different power domains can be met, and each power domain can perform frequency adjustment in the next period based on the allocated power budget.
In the above design, the frequency controller adjusts the power budget allocated to the processor cores according to the number of the processor cores in the active state in the first period, which are included in each power domain, and then controls the frequency of the processor cores according to the power budget, so that the power budget can be more reasonably allocated, and the requirements of different processor cores are met. Furthermore, the mode can also carry out frequency adjustment according to the power budget, so that the adjusted processor core can be more in line with the running state of the processor core, and the working efficiency of the processor core is improved.
In combination with the second aspect of the embodiment of the present application, in a first implementation of the second aspect of the embodiment of the present application:
the frequency controller may further determine power consumption of the plurality of processor cores included in each of the plurality of power domains in a first period, and then allocate a power budget to each of the plurality of power domains according to the number of processor cores included in each of the plurality of power domains that are in an active state during the first period and the power consumption of the plurality of processor cores included in each of the plurality of power domains in the first period; in this way, the frequency controller can more comprehensively sense the running state of the processor cores according to the number of the processor cores in the active state in the first period and the power consumption of the processor cores in the first period, which are included in each power domain, of the power domains, and more reasonably allocate the power budget for each power domain.
A third aspect of an embodiment of the present application provides a frequency controller, including:
a determining unit configured to determine power consumption of at least one processor core included in each of the plurality of power domains in a first cycle;
An allocation unit, configured to allocate a power budget to each power domain according to power consumption of at least one processor core included in each power domain in a first period;
and the adjusting unit is used for carrying out frequency adjustment on each power domain in a second period according to the allocated power budget, wherein the second period is the next period of the first period.
With reference to the third aspect of the embodiment of the present application, in a first implementation manner of the third aspect of the embodiment of the present application:
the power consumption of the at least one processor core contained in each power domain in the first period is real-time power consumption or average power consumption of the at least one processor core contained in each power domain in the first period.
With reference to the first implementation manner of the third aspect of the embodiment of the present application, in a second implementation manner of the third aspect of the embodiment of the present application:
the frequency controller further comprises a calculation unit;
the computing unit is configured to compute a load of at least one processor core included in each power domain in a first cycle according to power consumption of the at least one processor core included in each power domain in the first cycle.
With reference to the second implementation manner of the third aspect of the embodiment of the present application, in a third implementation manner of the third aspect of the embodiment of the present application:
the computing unit is further configured to predict a predicted load of the at least one processor core included in each power domain in the second cycle according to a load of the at least one processor core included in each power domain in the first cycle.
With reference to the third implementation manner of the third aspect of the embodiment of the present application, in a fourth implementation manner of the third aspect of the embodiment of the present application:
the allocation unit is specifically configured to allocate a power budget to each power domain according to any one of a power consumption of at least one processor core included in each power domain in a first period, a load of at least one processor core included in each power domain in the first period, and a predicted load of at least one processor core included in each power domain in the second period.
A fourth aspect of an embodiment of the present application provides a frequency controller, including:
a determining unit, configured to determine the number of processor cores that are in an active state in a first period, where the number of processor cores is included in each of the plurality of power domains;
An allocation unit, configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first period, where the number of processor cores is included in each power domain;
and the adjusting unit is used for carrying out frequency adjustment on each power domain in a second period according to the allocated power budget, wherein the second period is the next period of the first period.
With reference to the fourth aspect of the embodiment of the present application, in a first implementation manner of the fourth aspect of the embodiment of the present application:
the determining unit is further configured to determine power consumption of a plurality of processor cores included in each of the plurality of power domains in a first period;
the allocation unit is configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first cycle and the power consumption of the plurality of processor cores in the first cycle.
A fifth aspect of an embodiment of the present application provides a processor, including:
the processor comprises a processor core, a power consumption detector, a power consumption controller and a frequency regulator; the power consumption detector and the frequency regulator are respectively connected with the power consumption controller;
The power consumption detector is used for detecting and determining the power consumption of at least one processor core contained in each power domain in a plurality of power domains in a first period;
the power consumption controller is configured to allocate a power budget to each power domain according to power consumption of at least one processor core included in each power domain in a first period;
the frequency adjustor is configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
With reference to the fifth aspect of the embodiment of the present application, in a first implementation manner of the fifth aspect of the embodiment of the present application:
the power consumption of the at least one processor core contained in each power domain in the first period is real-time power consumption or average power consumption of the at least one processor core contained in each power domain in the first period.
With reference to the first implementation manner of the fifth aspect of the embodiment of the present application, in a second implementation manner of the fifth aspect of the embodiment of the present application:
the power consumption controller is further configured to calculate a load of at least one processor core included in each power domain in a first period according to power consumption of the at least one processor core included in each power domain in the first period.
With reference to the second implementation manner of the fifth aspect of the embodiment of the present application, in a third implementation manner of the fifth aspect of the embodiment of the present application:
the power consumption controller is further configured to predict a predicted load of the at least one processor core included in each power domain in the second cycle according to a load of the at least one processor core included in each power domain in the first cycle.
With reference to the third implementation manner of the fifth aspect of the embodiment of the present application, in a fourth implementation manner of the fifth aspect of the embodiment of the present application:
the power consumption controller is specifically configured to allocate a power budget to each power domain according to any one of a power consumption of at least one processor core included in each power domain in a first period, a load of at least one processor core included in each power domain in the first period, and a predicted load of at least one processor core included in each power domain in the second period.
A sixth aspect of an embodiment of the present application provides a processor, including:
the processor comprises a processor core, a power consumption controller and a frequency regulator; the frequency regulator is respectively connected with the power consumption controller;
The power consumption controller determines the number of the processor cores in the activated state in a first period, wherein the processor cores are contained in each power domain in the power domains; distributing power budget to each power domain according to the number of the processor cores in the active state of the plurality of processor cores in the first period;
the frequency adjustor is configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
With reference to the sixth aspect of the embodiment of the present application, in a first implementation manner of the sixth aspect of the embodiment of the present application:
the processor also comprises a power consumption detector, and the power consumption detector is connected with the power consumption controller;
the power consumption is used for determining the power consumption of a plurality of processor cores in a first period, wherein the power consumption is contained in each power domain in the plurality of power domains;
the power consumption controller is specifically configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first cycle and the power consumption of the plurality of processor cores in the first cycle.
A seventh aspect of an embodiment of the application provides an electronic device comprising a processor as set forth in any of the fifth or sixth aspects above.
The above aspects and other aspects of the present application will be specifically described in the following embodiments.
Drawings
FIG. 1 is a table of core power distribution for a processor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a multi-core processor according to an embodiment of the present application;
FIG. 3 is a flow chart illustrating a power margin allocation method according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating another power margin allocation method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a frequency controller according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of another frequency controller according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of another frequency controller according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of another frequency controller according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a power budget allocation method and related equipment, which are used for allocating power budgets according to the states of processor cores corresponding to power domains in a processor.
The following detailed description of the present application refers to the accompanying drawings, which illustrate only some, but not all, embodiments of the application.
The embodiments disclosed by the application can be applied to electronic equipment with an over-frequency function. In some embodiments of the application, the electronic device may be a computer device, such as a desktop computer, having a processor, such as a central processing unit (central processing unit, CPU). It should also be appreciated that in other embodiments of the present application, the electronic device may also be a portable electronic device having a processor, such as a cell phone, tablet computer, wearable device (e.g., smart watch) with wireless communication capabilities, vehicle-mounted device, etc. Exemplary embodiments of portable electronic devices include, but are not limited to, piggy-backOr other operating system.
A multi-core processor refers to a processor that has two or more complete compute engines (processor cores) integrated into one processor, where the processor can support multiple processor cores on a system bus, and all bus control signals and command signals are provided by a bus controller. With the increasing performance requirements for processing data of a processor, if the speed of a single-core chip is simply increased, excessive heat is generated due to the excessively high working frequency, and meanwhile, the development of semiconductor technology also limits the provision of the single-core chip frequency, so that a multi-core processor is generated. The architecture of the multi-core processor embodies the concept of a divide-and-conquer method, namely, the tasks to be processed are divided, and the divided tasks are arranged to a plurality of cores for processing, so that one processor can execute more tasks in a specific clock period, the multi-core technology can enable the processors to process the tasks in parallel, the multi-core system is easier to expand, stronger processing performance can be integrated in a more delicate shape, and the power consumption is lower and the heat generated by the power consumption is less; multicore processors have become an integral product of processor development.
The processor core over-clocking technique (inter turbo boost) refers to that after an operation program is started, the processor automatically accelerates to a proper frequency so as to ensure the smooth operation of the program; when the method is applied to complex applications, the processor can automatically improve the running main frequency to speed up, and process tasks with higher performance requirements; when the task switch is made, the processor is immediately in a power saving state. Thus, not only the effective utilization of energy is ensured, but also the program speed is greatly improved. Colloquially, the processor can automatically adjust the main frequency of the processor according to the current task amount by automatically overtaking, so that the maximum performance is exerted when the task is retried. The gist of this technique is to exploit the performance potential of the processor as much as possible without exceeding the maximum power.
When power is supplied to a multi-core processor, a regional independent power supply mode is generally adopted, namely the processor is divided into a plurality of power domains, each power domain supplies power independently, and the super-frequency turbo technology allows power of some processor cores to be added to other processor cores, so that the individual processor cores operate at a higher frequency, and the total power/current consumed by the processor is ensured not to exceed the maximum power/current which can be born by the system design. There is a need to reasonably allocate power budgets among the power domains and to formulate the highest frequency allowed to be reached by the cores in turbo state based on the allocated power budgets.
In the prior art, power budget is generally distributed to each power domain in average, that is, the power budget distributed to each power domain is the same, then the maximum frequency of the processor core is determined in the middle of each power domain according to the heaviest load bearable by each power domain; it will be appreciated that the processor core operating frequency in each power domain is limited by the maximum frequency that the boosted operating frequency should not exceed when the processor core is in an over-clocking state.
FIG. 1 is a table of core power distribution for a processor including 16 cores and 32 threads according to an embodiment of the present application; it will be appreciated that in the first column, no processor core is in an over-clocking state, in the second column, one processor core is in an over-clocking state, and so on; illustratively, in the ninth column of data, in this state, the power consumption of 8 processor cores in the turbo state is around 14W to 14.5W, which is significantly lower than the power consumption of 18.34W when a single processor core in the second column of data is turbo. Meanwhile, when the 8 processor cores are in the turbo state, the total power consumption of the processor is 122.87W, and is obviously lower than the peak power consumption 144.49W of the processor when the 10 processor cores in the turbo state in the 11 th column data. Obviously, this way of allocating power margin makes it impossible to fully use the power budget in many cases, nor to exert the maximum performance of each core, because each core in turbo state is limited by the maximum frequency. There is a need to re-formulate ways to allocate power budgets to improve the performance of the turbo function.
In view of the above, the present application provides a power budget allocation method for adjusting the power budget allocated to a processor core according to the power consumption of the processor core, and then controlling the frequency of the processor core according to the power budget, so that the power budget can be more reasonably allocated to meet the demands of different processor cores. Furthermore, the mode can also carry out frequency adjustment according to the power budget, so that the adjusted processor core can be more in line with the running state of the processor core, and the working efficiency of the processor core is improved.
The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.
The terms "system" and "network" in embodiments of the application may be used interchangeably. "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
And, unless otherwise specified, references to "first," "second," etc. ordinal words of embodiments of the present application are used for distinguishing between multiple objects and are not used for limiting the priority or importance of the multiple objects. For example, the first time and the second time are only for distinguishing between different times, and are not indicative of the difference in priority, importance, or the like between the two times.
Fig. 2 schematically illustrates a structure of a processor 200 according to an embodiment of the present application. As shown in fig. 2, processor 200 may include at least one processor core, such as processor core 20, processor core 21, processor core 22, and processor core 23. Non-core components such as general purpose units (including counters, decoders, signal generators, etc.), accelerator units, input/output control units, interface units, internal memory, external buffers, etc. may also be included in the processor 200. Wherein the respective processor cores and the non-core components may be connected by a communication bus (not illustrated in fig. 2) to implement a data transmission operation.
It should be appreciated that the processor 200 may be a chip. For example, the processor 200 may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processor unit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip. It should be noted that the processor 200 in the embodiment of the present application may also be an integrated circuit chip with signal processing capability. For example, the processor 100 described above may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be appreciated that the memory (e.g., internal memory and external buffers) in embodiments of the application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In an embodiment of the present application, and with continued reference to fig. 2, a frequency controller 24 may be further included in the processor, and a frequency adjustor may be further disposed in each processor core, where the frequency controller 24 may be communicatively coupled to the frequency adjustor in each processor core. In this manner, in controlling the over-clocking of each processor core, the frequency controller 24 may send frequency control instructions to the frequency adjustor of that processor core to cause the frequency adjustor of that processor core to tune the frequency of that processor core in accordance with the frequency control instructions, e.g., to be greater than a manufacturer-set maximum frequency.
It should be noted that fig. 2 is only an exemplary illustration, and in other possible examples, the frequency adjustor may be provided in only one or a few processor cores, so that the frequency controller 24 may only control the frequency of the processor core in which the frequency adjustor is provided. Alternatively, a frequency adjustor may be provided in the non-core component, such that the frequency controller 24 may control not only the frequency of the processor core but also the frequency of the non-core component. Of course, the non-core component described herein refers to a component that operates at a set frequency.
The power budget allocation method of the present application is described below by taking the frequency of controlling one processor core as an example, and the description of controlling other processor cores or non-processor cores will not be repeated.
Based on the processor illustrated in fig. 2, fig. 3 schematically illustrates a flow chart corresponding to a power budget allocation method according to an embodiment of the present application, where the method is applicable to a frequency controller, such as the frequency controller 24 illustrated in fig. 2. In an embodiment of the present application, the frequency controller may perform a power budget allocation method in a periodic manner, and fig. 3 exemplarily illustrates a primary frequency control procedure of the frequency controller, as shown in fig. 3, where the method includes:
301. the frequency controller determines a power consumption of at least one processor core included in each of the plurality of power domains during a first cycle.
In the embodiment of the application, the power supply mode of the processor can be a pre-core power supply mode, namely each power domain only comprises one processor core, and each processor core independently supplies power to the processor core; the system can also be a pre-die power supply mode, wherein each power domain comprises a plurality of processor cores, and the processors supply power for a plurality of processors belonging to the same power domain; thus, a reference to the core operating state. From the mathematical formula it can be known that: wi=pi/(Fi Vi 2); wi is a load, pi is power consumption, fi is power supply frequency corresponding to the kernel, and Vi is power supply voltage corresponding to the voltage domain. When the processor acquires the power consumption corresponding to the first period, the power supply voltage of the power supply domain corresponding to each core in the first period and the power supply frequency processor need to be acquired at the same time, so that the power supply domains can be divided for the processor cores, and each power supply domain comprises at least one processor core.
The frequency controller needs a predetermined period to allocate a power budget; since the average allocation of a fixed power margin for each power domain would cause the maximum frequency achievable by each power domain to be limited by the fixed power budget, the maximum power frequency would in turn result in an inability to fully exploit the maximum performance of each core; the frequency controller may be configured to allocate power margin more reasonably based on the real-time status of each battery domain, and the processor may determine an allocated period, monitor the status of each power domain in one period, and allocate allocation in the next period based on the status.
By way of example, the frequency controller may obtain the power consumption of each power domain through a power consumption detector, and use the power consumption to sense the state of each power domain and allocate a reasonable power budget for the power domain; it can be understood that the power consumption controller may detect average power consumption corresponding to each power domain in one period, or may obtain real-time power consumption, which is not limited in particular.
It can be understood that, when one power domain includes only one processor core, the power consumption of each power domain obtained by the power consumption controller is the power consumption of the processor core; when one power domain includes a plurality of processor cores, the power consumption of each power domain obtained by the power consumption controller is the total power consumption of all the processor cores in the power domain.
302. And the frequency controller calculates the load of at least one processor core contained in each power domain in the first period according to the power consumption of the at least one processor core contained in each power domain in the first period.
The frequency controller also uses the power consumption to determine the load of each power domain in the first period, uses the load as a processing rate, then calculates the load of each core in the first period according to the above formula, and uses the load as a reference item for distributing the power budget in the second period.
303. The frequency controller predicts the predicted load of the at least one processor core contained in each power domain in the second period according to the load of the at least one processor core contained in each power domain in the first period.
After the load of each power domain in the first period is determined, the frequency controller can also predict the predicted load of each power domain in the second period by using the load, and the predicted load of each power domain in the second period can more directly reflect the working frequency requirement of each power domain in the second period, so that the power budget in the second period is distributed according to the predicted load, and the distributed power budget can be more reasonable.
304. The frequency controller allocates a power budget to each power domain based on any one or more of a power consumption of at least one processor core included in each power domain during a first period, a load of at least one processor core included in each power domain during the first period, and a predicted load of at least one processor core included in each power domain during the second period.
In a first alternative, the frequency controller may allocate a power budget for each power domain based on the power consumption of at least one processor core contained in each power domain during a first period; by way of example, allocation of the power budget may be made according to the following equation:
PB i ＝(P i /P total )*PB total
wherein PB i Power margin allocated to the system for the ith power domain, P i For the power consumption in the first period corresponding to the ith power domain, P total PB is the sum of power consumption corresponding to all power domains total The total amount of power budget provided for the system; it can be understood that the higher the power consumption of the power domain in the first period, the larger the data processing workload performed by the power domain, more power budget needs to be allocated to the power domain, and the frequency of the internal processor core is increased, so that the processing speed of the processor core can be increased, and the performance of the processor core can be fully exerted.
In a second alternative, the frequency controller may allocate a power budget for each power domain based on the load of at least one processor core contained in each power domain during the first period; by way of example, allocation of the power budget may be made according to the following equation:
PB i ＝(A i /A total )*PB total
wherein PB i A power margin allocated to the system for the ith power domain i For the load in the first period corresponding to the ith power domain, A total PB is the sum of loads corresponding to all power domains total The total amount of power budget provided for the system; it can be understood that the larger the corresponding load of the power domain in the first period, the larger the data processing workload performed by the power domain is, the more power budget needs to be allocated to the power domain, so as to increase the frequency of the internal processor core, thus increasing the processing speed of the processor core and fully playing the performance of the processor core.
In a third alternative, the frequency controller may allocate a power budget for each power domain based on a predicted load of at least one processor core contained by each power domain during the second period; the formula used is similar to that in the second alternative, but A i Then become a pre-power in the second period corresponding to the ith power domainLoad measurement, A total PB is the sum of the predicted loads corresponding to all power domains total The total amount of power budget provided for the system; it can be understood that the predicted load can directly reflect the power requirement of each power domain in the second period, and the larger the corresponding predicted load of the power domain in the second period, the larger the data processing workload to be performed by the power domain is, the more power budget needs to be allocated to the power domain, and the frequency of the internal processor core is improved, so that the processing speed of the processor core can be improved, and the performance of the processor core can be fully exerted.
In a fourth alternative manner, the frequency controller may allocate a power budget for each power domain according to the load of at least one processor core included in each power domain in the first period and the predicted load of at least one processor core included in each power domain in the second period, and specifically may calculate an exponentially weighted moving average value EWMA value of the two, and allocate the power budget according to the EWMA value corresponding to each power domain; this allows for a more rational allocation of power budget in combination with the implementation state and the predicted state of the processor core.
Specifically, the power consumption of at least one processor core included in each power domain in the first period, the load of at least one processor core included in each power domain in the first period, and the predicted load of at least one processor core included in each power domain in the second period may be arbitrarily combined, and the frequency controller may arbitrarily select one or more terms as the basis for allocating the power budget, which is not specifically limited.
305. The frequency controller frequency adjusts said each power domain during a second period according to the allocated power budget.
It will be appreciated that the second period is the next period to the first period. After the frequency controller distributes power allowance for each power domain, the power supply voltage in the power domain corresponding to each processor core is adjusted according to the distributed power allowance, then the maximum power supply frequency corresponding to the core is determined according to the power budget and the power supply voltage, and meanwhile the working frequency corresponding to the core is continuously adjusted according to the maximum power supply frequency.
The application provides a power budget allocation method, which is used for adjusting the power budget allocated to a processor core according to the power consumption of the processor core, and then controlling the frequency of the processor core according to the power budget implementation, so that the power budget can be allocated more reasonably, and the requirements of different processor cores are met. Furthermore, the mode can also carry out frequency adjustment according to the power budget, so that the adjusted processor core can be more in line with the running state of the processor core, and the working efficiency of the processor core is improved.
Based on the processor shown in fig. 2, fig. 4 schematically illustrates a flow chart corresponding to another power budget allocation method provided by an embodiment of the present application, where the method is applicable to a frequency controller, such as the frequency controller 24 illustrated in fig. 2. In the embodiment of the application, the power supply mode of the processor is a pre-die power supply mode, namely, each power domain comprises a plurality of processor cores, and the processor supplies power for a plurality of processors belonging to the same power domain together; as shown in fig. 4, the method includes:
401. the frequency controller determines a number of processor cores of each of the plurality of power domains that include a plurality of processor cores that are in an active state during a first period.
In this embodiment, each power domain of the processor includes a plurality of processor cores, the plurality of processor cores being collectively powered; it will be appreciated that when the processor core is in an active (over-clocking) state, it is desirable to increase the power frequency for it to increase the performance of the core. For example, the processor may allocate a power margin in a next cycle to each power domain according to the number of cores that each power domain is in an active state in a current cycle, and the more the number of cores that are in an active state in a power domain, the more power margins that the power domain needs to allocate.
402. The frequency controller determines a power consumption of a plurality of processor cores included in each of the plurality of power domains during a first cycle.
It will be appreciated that the frequency controller may still use the power consumption of the plurality of processor cores in the first cycle included in each power domain as a condition for allocating a power margin, and this step is similar to step 301 in the embodiment shown in fig. 3, and is not specifically limited.
403. And the frequency controller distributes power budget to each power domain according to the number of the processor cores in the active state in the first period and/or the power consumption of the processor cores in the first period.
Illustratively, in a first embodiment, the allocation of the power budget may be made according to the following formula:
PB i ＝(N i /N total )*PB total
wherein PB i Power margin allocated to the system for the ith power domain, N i N is the number of processors in active state in the ith power domain total PB is the sum of the numbers of the processor cores in the active state corresponding to all power domains total The total amount of power budget provided for the system. For example, in the second embodiment, the frequency controller may allocate the power budget according to the number of processor cores that are in the active state in the first cycle of the plurality of processor cores included in each power domain and the power consumption of the plurality of processor cores in the first cycle of each power domain; i.e. dividing the power budget into two parts PB totalA And PB totalB Wherein PB is totalA For power budget allocation according to average power consumption of power domains, PB totalB And the power budgets allocated to the power domain are obtained by adding the power budgets allocated to the active cores in the power domain.
Specifically, the calculation formulas of the power budget may be various, as long as the power budget allocated to the power domain is satisfied, the larger the power consumption corresponding to the power domain is, or the more cores in the active state are positively correlated, and the specific form is not limited.
404. The frequency controller frequency adjusts said each power domain during a second period according to the allocated power budget.
It will be appreciated that this step is similar to step 305 in the embodiment shown in fig. 3 and will not be described in detail herein.
According to the foregoing method, fig. 5 is a schematic structural diagram of a frequency controller 500 according to an embodiment of the present application, where the frequency controller 500 may be a chip or a circuit, such as a chip or a circuit that may be disposed in a processor. The frequency controller 500 may correspond to the frequency controller 24 in the above-described method. The frequency controller 500 may implement the steps of any one or more of the corresponding methods as shown in fig. 3. As shown in fig. 5, the frequency controller 500 may include a monitoring circuit 501 and a control circuit 502. Further, the frequency controller 500 may further comprise a bus system, through which the monitoring circuit 501 and the control circuit 502 may be connected. The monitor circuit 501 may be further connected to a power consumption detector of each processor core through a bus system, and the control circuit 502 may be further connected to a frequency regulator of each processor core through a bus system.
In an embodiment of the present application, the monitoring circuit 501 may determine the power consumption of at least one processor core included in each of the plurality of power domains during the first period, and send the power consumption to the control circuit 502. Correspondingly, the control circuit 502 may allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first period, and control the frequency adjustor to perform frequency adjustment according to the allocated power budget.
According to the foregoing method, fig. 6 is a schematic structural diagram of another frequency controller 600 according to an embodiment of the present application, where the frequency controller 600 may be a chip or a circuit, such as a chip or a circuit that may be disposed in a processor. The frequency controller 600 may correspond to the frequency controller 24 in the above-described method. The frequency controller 600 may implement the steps of any one or more of the corresponding methods as shown in fig. 4. As shown in fig. 6, the frequency controller 600 may include a monitoring circuit 601 and a control circuit 602. Further, the frequency controller 600 may further comprise a bus system, through which the monitoring circuit 601 and the control circuit 602 may be connected. The monitor circuit 601 may also be connected to a power consumption detector of each processor core through a bus system, and the control circuit 602 may also be connected to a frequency regulator of each processor core through a bus system.
In an embodiment of the present application, the monitoring circuit 601 may determine the number of processor cores that determine that a plurality of processor cores included in each of the plurality of power domains are in an active state in the first period, and send the number of processor cores to the control circuit 602. Correspondingly, the control circuit 602 may allocate a power budget to each power domain according to the number of processor cores that are active in the first period and control the frequency adjustor to perform frequency adjustment according to the allocated power budget.
According to the foregoing method, fig. 7 is a schematic structural diagram of another frequency controller 700 according to an embodiment of the present application, where the frequency controller 700 may be a chip or a circuit, such as a chip or a circuit that may be disposed in a processor. The frequency controller 700 may correspond to the frequency controller 24 in the above-described method. The frequency controller 700 may implement the steps of any one or more of the corresponding methods as shown in fig. 3 above. As shown in fig. 7, the frequency controller 700 may include a determining unit 701, an allocating unit 702, and an adjusting unit 703.
A determining unit 701, configured to determine power consumption of at least one processor core included in each of the plurality of power domains in a first cycle.
An allocation unit 702, configured to allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first period.
An adjusting unit 703, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
In an alternative embodiment, the power consumption of the at least one processor core included in each power domain in the first period is real-time power consumption or average power consumption of the at least one processor core included in each power domain in the first period.
In an alternative embodiment, the frequency controller 700 further comprises a computing unit 704.
The calculating unit 704 is configured to calculate a load of at least one processor core included in each power domain in the first cycle according to power consumption of the at least one processor core included in each power domain in the first cycle.
In an alternative embodiment, the calculating unit 704 is further configured to predict, according to a load of the at least one processor core included in each power domain in the first cycle, a predicted load of the at least one processor core included in each power domain in the second cycle.
In an alternative embodiment, the allocating unit 702 is specifically configured to allocate a power budget to each power domain according to any one of a power consumption of at least one processor core included in each power domain in a first period, a load of at least one processor core included in each power domain in the first period, and a predicted load of at least one processor core included in each power domain in the second period.
It can be appreciated that the functions of the respective units in the frequency controller 700 may refer to the implementation of the corresponding method embodiments, which are not described herein.
It should be understood that the above division of the units of the frequency controller 700 is only a division of a logic function, and it should be understood that the above division of the units of the frequency controller 700 is only a division of a logic function in actual implementation, and may be fully or partially integrated into a physical entity or may be physically separated. In the embodiment of the present application, the acquisition unit 701 may be implemented by the monitoring circuit 501 of fig. 5, and the determining unit 702 and the adjusting unit 703 may be implemented by the control circuit 502 of fig. 5.
According to the foregoing method, fig. 8 is a schematic structural diagram of another frequency controller 800 according to an embodiment of the present application, and the frequency controller 800 may be a chip or a circuit, for example, a chip or a circuit that may be disposed in a processor. The frequency controller 800 may correspond to the frequency controller 24 in the above-described method. The frequency controller 800 may implement the steps of any one or more of the corresponding methods as shown in fig. 4 above. As shown in fig. 8, the frequency controller 800 may include a determining unit 801, an allocating unit 802, and an adjusting unit 803.
A determining unit 801, configured to determine the number of processor cores that are in an active state in a first period, where the processor cores are included in each of the plurality of power domains.
An allocation unit 802, configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in the first period and the number of processor cores that are included in each power domain.
And an adjusting unit 803, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
In an optional implementation manner, the determining unit 801 is further configured to determine power consumption of a plurality of processor cores in a first cycle, where the plurality of processor cores are included in each of the plurality of power domains;
the allocating unit 802 is configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first cycle and the power consumption of the plurality of processor cores in the first cycle.
It can be appreciated that the functions of the respective units in the frequency controller 800 may refer to the implementation of the corresponding method embodiments, which are not described herein.
It should be understood that the above division of the units of the frequency controller 800 is merely a division of a logic function, and may be fully or partially integrated into a physical entity or may be physically separated. In the embodiment of the present application, the obtaining unit 801 may be implemented by the monitoring circuit 601 of fig. 6, and the determining unit 802 and the adjusting unit 803 may be implemented by the control circuit 602 of fig. 6.
According to a method provided by an embodiment of the present application, the present application also provides a computer program product, including: computer program code which, when run on a computer, causes the computer to perform the method of any of the embodiments shown in fig. 1 to 4.
According to the method provided by the embodiment of the present application, the present application further provides a computer readable storage medium storing a program code, which when executed on a computer, causes the computer to perform the method of any one of the embodiments shown in fig. 1 to 5.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (22)

  1. A method of allocating a power budget, the method comprising:
    determining a power consumption of at least one processor core included in each of the plurality of power domains during a first cycle;
    and distributing power budgets to each power domain according to the power consumption of at least one processor core in a first period, wherein the power consumption is contained in each power domain, so that each power domain carries out frequency adjustment in a second period based on the distributed power budgets, and the second period is the next period of the first period.
  2. The method of claim 1, wherein the power consumption of the at least one processor core included in each power domain during the first period is real-time power consumption or average power consumption of the at least one processor core included in each power domain during the first period.
  3. The method according to claim 2, wherein the method further comprises:
    and calculating the load of at least one processor core contained in each power domain in the first period according to the power consumption of the at least one processor core in the first period.
  4. A method according to claim 3, characterized in that the method further comprises:
    and predicting the predicted load of the at least one processor core contained in each power domain in the second period according to the load of the at least one processor core contained in each power domain in the first period.
  5. The method of claim 4, wherein allocating a power budget to each power domain based on power consumption of at least one processor core included in said each power domain during a first cycle comprises:
    and allocating a power budget to each power domain according to any one or more of the power consumption of at least one processor core contained in each power domain in a first period, the load of at least one processor core contained in each power domain in the first period and the predicted load of at least one processor core contained in each power domain in the second period.
  6. A method of allocating a power budget, the method comprising:
    determining the number of processor cores in an activated state in a first period, wherein the processor cores are contained in each of the power domains;
    and distributing power budgets to each power domain according to the number of the processor cores which are in the active state in a first period and are contained in each power domain, so that each power domain carries out frequency adjustment in a second period based on the distributed power budgets, and the second period is the next period of the first period.
  7. The method of claim 6, wherein the method further comprises:
    determining power consumption of a plurality of processor cores contained in each of the plurality of power domains during a first cycle;
    the allocating the power budget to each power domain according to the number of the processor cores of the plurality of processor cores in the active state in the first period, includes:
    and distributing the power budget to each power domain according to the number of the processor cores in the active state of the plurality of processor cores in the first period and the power consumption of the plurality of processor cores in the first period.
  8. A frequency controller, comprising:
    a determining unit configured to determine power consumption of at least one processor core included in each of the plurality of power domains in a first cycle;
    an allocation unit, configured to allocate a power budget to each power domain according to power consumption of at least one processor core included in each power domain in a first period;
    and the adjusting unit is used for carrying out frequency adjustment on each power domain in a second period according to the allocated power budget, wherein the second period is the next period of the first period.
  9. The frequency controller of claim 8, wherein the power consumption of the at least one processor core included in each power domain during the first period is real-time power consumption or average power consumption of the at least one processor core included in each power domain during the first period.
  10. The frequency controller according to claim 9, further comprising a calculation unit;
    the computing unit is configured to compute a load of at least one processor core included in each power domain in a first cycle according to power consumption of the at least one processor core included in each power domain in the first cycle.
  11. The frequency controller according to claim 10, wherein,
    the computing unit is further configured to predict a predicted load of the at least one processor core included in each power domain in the second cycle according to a load of the at least one processor core included in each power domain in the first cycle.
  12. A frequency controller according to any one of claims 8 to 11,
    the allocation unit is specifically configured to allocate a power budget to each power domain according to any one of a power consumption of at least one processor core included in each power domain in a first period, a load of at least one processor core included in each power domain in the first period, and a predicted load of at least one processor core included in each power domain in the second period.
  13. A frequency controller, the frequency controller comprising:
    a determining unit, configured to determine the number of processor cores that are in an active state in a first period, where the number of processor cores is included in each of the plurality of power domains;
    an allocation unit, configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first period, where the number of processor cores is included in each power domain;
    And the adjusting unit is used for carrying out frequency adjustment on each power domain in a second period according to the allocated power budget, wherein the second period is the next period of the first period.
  14. The frequency controller according to claim 13, wherein,
    the determining unit is further configured to determine power consumption of a plurality of processor cores included in each of the plurality of power domains in a first period;
    the allocation unit is configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first cycle and the power consumption of the plurality of processor cores in the first cycle.
  15. A processor, the processor comprising a processor core, a power consumption detector, a power consumption controller, and a frequency adjustor; the power consumption detector and the frequency regulator are respectively connected with the power consumption controller;
    the power consumption detector is used for detecting and determining the power consumption of at least one processor core contained in each power domain in a plurality of power domains in a first period;
    the power consumption controller is configured to allocate a power budget to each power domain according to power consumption of at least one processor core included in each power domain in a first period;
    The frequency adjustor is configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
  16. The processor of claim 15, wherein the power consumption of the at least one processor core included in each power domain during the first period is real-time power consumption or average power consumption of the at least one processor core included in each power domain during the first period.
  17. The processor of claim 16, wherein the power consumption controller is further configured to calculate a load of the at least one processor core included in each power domain during the first cycle based on power consumption of the at least one processor core included in each power domain during the first cycle.
  18. The processor of claim 17, wherein the power consumption controller is further configured to predict a predicted load of the at least one processor core included in each power domain during the second period based on a load of the at least one processor core included in each power domain during the first period.
  19. The processor of claim 17, wherein the power consumption controller is configured to allocate a power budget to each power domain based on any of a power consumption of at least one processor core included in each power domain during a first period, a load of at least one processor core included in each power domain during the first period, and a predicted load of at least one processor core included in each power domain during the second period.
  20. A processor, the processor comprising a processor core, a power consumption controller, and a frequency adjustor; the frequency regulator is respectively connected with the power consumption controller;
    the power consumption controller determines the number of the processor cores in the activated state in a first period, wherein the processor cores are contained in each power domain in the power domains; distributing power budget to each power domain according to the number of the processor cores in the active state of the plurality of processor cores in the first period;
    the frequency adjustor is configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
  21. The processor of claim 20, further comprising a power consumption detector coupled to the power consumption controller;
    the power consumption is used for determining the power consumption of a plurality of processor cores in a first period, wherein the power consumption is contained in each power domain in the plurality of power domains;
    the power consumption controller is specifically configured to allocate a power budget to each power domain according to the number of processor cores that are in an active state in a first cycle and the power consumption of the plurality of processor cores in the first cycle.
  22. An electronic device comprising a processor according to any one of claims 15 to 21.
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US8984313B2 (en) * 2012-08-31 2015-03-17 Intel Corporation Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator
US9360906B2 (en) * 2013-05-01 2016-06-07 Advanced Micro Devices, Inc. Power management for multiple compute units
US9625971B2 (en) * 2014-01-10 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. System and method of adaptive voltage frequency scaling
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