WO2022041251A1

WO2022041251A1 - Power budget allocation method and related device

Info

Publication number: WO2022041251A1
Application number: PCT/CN2020/112688
Authority: WO
Inventors: 胡荻; 郭东之; 李继明; 刘臻; 王哲; 库特拉德米特罗; 马里亚什尤里
Original assignee: 华为技术有限公司
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-03-03
Also published as: CN116997878A

Abstract

The present application is specifically used in the field of battery management. Disclosed are a power budget allocation method and a related device. The method comprises: determining power consumption of at least one processor core comprised in each of a plurality of power domains in a first period; and allocating a power budget to each power domain according to the power consumption of the at least one processor core comprised in each power domain in the first period, such that each power domain performs frequency adjustment in a second period on the basis of the allocated power budget, wherein the second period is a period next to the first period. The method can fully utilize power budgets to provide higher power supply frequencies for cores for data processing, thus fully exerting the performance of each core and improving working rates and working performance of processors.

Description

A power budget allocation method and related equipment

technical field

The embodiments of the present application relate to the field of power management, and in particular, to a power budget allocation method and related equipment.

Background technique

With the continuous development of electronic equipment configuration, multi-core processors have been widely used in the field of computers and mobile phones. Multi-core processors refer to the integration of multiple computing engines (processor cores) in one processor, which can support multi-threaded tasks; In terms of core processors, multi-core processors support dividing the data to be processed into multiple parts and assign them to different core registers, so that each operator can operate together to improve the running speed of the processor.

Generally, multi-core processors are powered by multiple integrated voltage regulators (IVRs), that is, multi-core processors generally include multiple power domains. Exceeding the maximum power supply power/current that the system design can bear, it is necessary to allocate the power budget between different power domains; in a multi-core processor that supports overclocking, the processor usually allocates the power budget equally to the cores in the overclocked state. And according to the allocation result, the maximum frequency allowed by each core is determined, so that the power consumption of each core when running the heaviest load at the highest frequency state does not exceed the power budget allocated by the processor, thus ensuring that the entire system is stable operation.

Restricted by the above maximum frequency, when the load of each processor core is less than the heaviest load, the power consumption of a single processor core will be lower than the maximum power consumption it can allow, and each processor core cannot fully Using the power budget allocated by the processor, the power consumption of all processor cores will also be lower than the maximum power consumption that the system can bear, which will result in the inability to exert the maximum performance of the processor.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a power budget allocation method and related devices, which are used to allocate the power budget according to the states of the processor cores corresponding to each power supply domain in the processor.

A first aspect of the embodiments of the present application provides a method for allocating a power budget, including:

When the processor is a multi-core processor, the processor contains multiple power domains, and each power domain supplies power to at least one processor core; first, it is necessary to determine the power consumption of the processor cores in each power domain in the first cycle. power consumption, and then allocate the power budget to each power domain according to the obtained power consumption; it is understandable that the corresponding power consumption of each power domain in the first cycle can directly or indirectly reflect the processing in the power domain According to the state of the processor core, the power budget is allocated according to the power consumption, which can meet the needs of different processor cores, so that each power domain can perform frequency adjustment based on the allocated power budget.

In the above design, the frequency controller adjusts the power budget allocated to the processor core according to the power consumption of the processor core, and then controls the frequency of the processor core according to the power budget, so that the power budget can be allocated more reasonably to meet different requirements. processor core requirements. Furthermore, in this way, the frequency can also be adjusted according to the power budget, so that the adjusted processor core can be more in line with its operating state and improve the working efficiency of the processor core.

In conjunction with the first aspect of the embodiments of the present application, in the first implementation of the first aspect of the embodiments of the present application:

The frequency controller can allocate the power budget according to the real-time power consumption of at least one processor core included in each power domain in the first cycle, or according to the real-time power consumption of at least one processor core included in each power domain during the first cycle. The average power consumption is allocated; in this way, the frequency controller can sense the operating state of the processor core in various ways, and provide various schemes for allocating the power budget.

With reference to the first implementation of the first aspect of the embodiments of the present application, in the second implementation of the first aspect of the embodiments of the present application:

When obtaining the power consumption of at least one processor core included in each power domain in the first cycle, the frequency controller can also calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption. The load is then used as a reference for allocating the power budget according to the load, so that a new scheme is provided for the frequency controller to allocate the budget.

With reference to the second implementation of the first aspect of the embodiments of the present application, in the third implementation of the first aspect of the embodiments of the present application:

When obtaining the load of at least one processor core included in each power domain in the first cycle, the frequency controller can also predict the prediction of at least one processor core included in each power domain in the second cycle according to the load. load, and then use the predicted load as a reference for allocating the power budget; it is understandable that the predicted load of at least one processor core included in each power domain in the second cycle can directly reflect the power of the processor core in the second cycle. In this way, the frequency controller can be more reasonably allocated power budget to improve the working performance of the processor core.

In conjunction with the third implementation of the first aspect of the embodiments of the present application, in the fourth implementation of the first aspect of the embodiments of the present application:

The frequency controller obtains the power consumption of the at least one processor core included in each power domain in the first cycle, and the load of the at least one processor core included in each power domain during the first cycle, and the predicted load of at least one processor core included in each power domain in the second cycle, any one or more of them can be used as a reference for allocating a power budget, so that a more comprehensive perception and processing can be achieved. The operating state of the core is more reasonable to allocate the power budget to each power domain.

A second aspect of the embodiments of the present application provides a method for allocating a power budget, including:

When the processor is a multi-core processor, the processor contains multiple power domains, and each power domain supplies power to multiple processor cores; first, it is necessary to determine the number of processor cores included in each power domain in the The number of active processor cores in a cycle, and then allocate the power budget to the Describe each power domain; it is understandable that the more the number of active cores in each power domain, the heavier the task of the processor core to process data, so it is necessary to allocate more work margins to improve its performance. Frequency: The power budget is allocated according to the number of active processor cores, which can meet the needs of different power domains, so that each power domain can perform frequency adjustment in the next cycle based on the allocated power budget.

In the above design, the frequency controller adjusts the power budget allocated to each power domain according to the number of processor cores that are active in the first cycle of the multiple processor cores contained in each power domain, and then according to the power Budget implementation controls the frequency of the processor cores so that the power budget can be allocated more reasonably to meet the needs of different processor cores. Furthermore, in this manner, the frequency can also be adjusted according to the power budget, so that the adjusted processor core can be more in line with its operating state and improve the working efficiency of the processor core.

In conjunction with the second aspect of the embodiments of the present application, in the first implementation manner of the second aspect of the embodiments of the present application:

The frequency controller can also determine the power consumption of the plurality of processor cores contained in each power domain in the first cycle, and then according to the plurality of processor cores contained in each power domain in the first cycle the number of active processor cores and the power consumption of the plurality of processor cores included in each of the plurality of power domains in the first cycle, and allocate a power budget to each of the power domains; In this way, the frequency controller can be based on the number of processor cores that are in the active state in the first cycle and the number of each power supply in the multiple power supply domains The power consumption of the multiple processor cores included in the domain in the first cycle is used as a reference for allocating the power budget, so that the running state of the processor cores can be more comprehensively sensed, and the power budget can be allocated to each power domain more reasonably.

A third aspect of the embodiments of the present application provides a frequency controller, including:

a determining unit, configured to determine the power consumption of at least one processor core included in each of the multiple power domains in the first cycle;

an allocation unit, configured to allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle;

An adjustment unit, configured to adjust the frequency of each power supply domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

With reference to the third aspect of the embodiments of the present application, in the first implementation of the third aspect of the embodiments of the present application:

The power consumption of the at least one processor core included in each power domain in the first cycle is the real-time power consumption or average power consumption of the at least one processor core included in each power domain in the first cycle.

In conjunction with the first implementation of the third aspect of the embodiments of the present application, in the second implementation of the third aspect of the embodiments of the present application:

The frequency controller further includes a calculation unit;

The computing unit is configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of at least one processor core included in each power domain. cycle load.

With reference to the second implementation of the third aspect of the embodiments of the present application, in the third implementation of the third aspect of the embodiments of the present application:

The computing unit is further configured to predict, according to the load of at least one processor core included in each power domain in the first cycle, that the at least one processor core included in each power domain will perform in the first cycle. Predicted load for two cycles.

With reference to the third implementation of the third aspect of the embodiments of the present application, in the fourth implementation of the third aspect of the embodiments of the present application:

The allocating unit is specifically configured to, according to the power consumption of at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the first cycle. A power budget is allocated to each power domain according to the load of the cycle, and any one of the predicted load of at least one processor core included in each power domain during the second cycle.

A fourth aspect of the embodiments of the present application provides a frequency controller, including:

a determining unit, configured to determine the number of processor cores that are in an active state in the first cycle of the multiple processor cores included in each power supply domain in the multiple power supply domains;

an allocation unit, configured to allocate a power budget to each of the power domains according to the number of processor cores in the active state of the plurality of processor cores included in each of the power domains;

With reference to the fourth aspect of the embodiments of the present application, in the first implementation of the fourth aspect of the embodiments of the present application:

The determining unit is further configured to determine the power consumption in the first cycle of the multiple processor cores included in each of the multiple power supply domains;

The allocating unit is configured to, according to the number of processor cores in the active state of the plurality of processor cores included in each power supply domain and the number of processor cores in each power supply domain in the plurality of power supply domains The power consumption of the plurality of processor cores included in the first cycle, with a power budget allocated to each of the power domains.

A fifth aspect of the embodiments of the present application provides a processor, including:

The processor includes a processor core, a power consumption detector, a power consumption controller and a frequency regulator; the power consumption detector and the frequency regulator are respectively connected to the power consumption controller;

the power consumption detector, configured to detect and determine the power consumption of at least one processor core included in each of the multiple power domains in the first cycle;

the power consumption controller, configured to allocate a power budget to each power supply domain according to the power consumption of at least one processor core included in each power supply domain in the first cycle;

The frequency regulator is configured to perform frequency regulation on each power domain in a second cycle according to the allocated power budget, where the second cycle is a next cycle of the first cycle.

With reference to the fifth aspect of the embodiments of the present application, in the first implementation manner of the fifth aspect of the embodiments of the present application:

With reference to the first implementation of the fifth aspect of the embodiments of the present application, in the second implementation of the fifth aspect of the embodiments of the present application:

The power consumption controller is further configured to calculate the power consumption of the at least one processor core included in each power domain in the first cycle according to the power consumption of the at least one processor core included in each power domain. load for the first cycle.

In conjunction with the second implementation of the fifth aspect of the embodiments of the present application, in the third implementation of the fifth aspect of the embodiments of the present application:

The power consumption controller is further configured to predict, according to the load of the at least one processor core included in each power domain in the first cycle, that the at least one processor core included in each power domain will be in the first cycle. Predicted load for the second period.

In conjunction with the third implementation of the fifth aspect of the embodiments of the present application, in the fourth implementation of the fifth aspect of the embodiments of the present application:

The power consumption controller is specifically configured to, according to the power consumption of the at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the first cycle. A power budget is allocated to each power domain, and any one of the load for one cycle and the predicted load of at least one processor core included in each power domain during the second cycle.

A sixth aspect of the embodiments of the present application provides a processor, including:

The processor includes a processor core, a power consumption controller and a frequency regulator; the frequency regulators are respectively connected to the power consumption controller;

The power consumption controller determines the number of processor cores that are in an active state in the first cycle of multiple processor cores included in each power supply domain in the multiple power supply domains; the number of processor cores in the active state of the plurality of processor cores in the first cycle, allocating a power budget to each power domain;

With reference to the sixth aspect of the embodiments of the present application, in the first implementation of the sixth aspect of the embodiments of the present application:

The processor further includes a power consumption detector connected to the power consumption controller;

The power consumption is used to determine the power consumption of the multiple processor cores included in each of the multiple power domains in the first cycle;

The power consumption controller is specifically configured to, according to the number of processor cores in the active state of the multiple processor cores included in each power supply domain in the first cycle and the number of each of the multiple power supply domains The power consumption of the plurality of processor cores included in the power domain in the first cycle, and the power budget is allocated to each power domain.

A seventh aspect of the embodiments of the present application provides an electronic device, where the electronic device includes the processor described in any of the fifth aspect or the sixth aspect.

The above aspects or other aspects of the present application will be specifically introduced in the following embodiments.

Description of drawings

FIG. 1 is a core power distribution table of a processor provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a multi-core processor according to an embodiment of the present application;

FIG. 3 is a schematic flowchart of a power headroom allocation method provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart of another power headroom allocation method provided by an embodiment of the present application;

5 is a schematic structural diagram of a frequency controller according to an embodiment of the present application;

6 is a schematic structural diagram of another frequency controller provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another frequency controller provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another frequency controller according to an embodiment of the present application.

detailed description

The technical solutions in the present application will be described in detail below with reference to the drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Various embodiments disclosed in this application may be applied to electronic devices with overclocking functions. In some embodiments of the present application, the electronic device may be a computer device having a processor (such as a central processing unit (CPU)), such as a desktop computer. It should also be understood that, in some other embodiments of the present application, the electronic device may also be a portable electronic device with a processor, such as a mobile phone, a tablet computer, a wearable device (such as a smart watch) with a wireless communication function, a vehicle-mounted device Wait. Exemplary embodiments of portable electronic devices include, but are not limited to, carry-on

Or portable electronic devices with other operating systems.

A multi-core processor means that two or more complete computing engines (processor cores) are integrated into one processor. At this time, the processor can support multiple processor cores on the system bus, and the bus controller provides all the Bus control signals and command signals. As the performance requirements of processors for processing data become higher and higher, if the speed of single-core chips is only increased, excessive heat will be generated due to the high operating frequency. At the same time, the development of semiconductor technology also limits the availability of single-core chip frequencies. , so multi-core processors came into being. The architecture of multi-core processors embodies the concept of "divide and conquer", that is, the tasks that need to be processed are divided, and the divided tasks are arranged to multiple cores for processing, so that a processor can be processed within a specific clock cycle. Execute more tasks, multi-core technology enables processors to process tasks in parallel, and multi-core systems are easier to expand, and more powerful processing performance can be packed into a smaller form factor, using less power and generating more heat. Less; multi-core processors have become an inevitable product of processor development.

Processor core overclocking technology (inter turbo boost) means that when a running program is started, the processor will automatically accelerate to an appropriate frequency to ensure smooth operation of the program; when dealing with complex applications, the processor can automatically increase the operating frequency to speed up , to process tasks with higher performance requirements; when switching between work tasks, the processor will immediately be in a power-saving state. This not only ensures the efficient use of energy, but also greatly improves the program speed. Commonly understood as automatic overclocking, the processor will automatically adjust the main frequency of the processor according to the current amount of tasks, so as to maximize the performance of heavy tasks. The main purpose of this technology is to maximize the performance potential of the processor without exceeding the maximum power.

When supplying power to multi-core processors, regional independent power supply is usually adopted, that is, the processor is divided into multiple power domains, and each power domain supplies power independently. Overclocking turbo technology allows some processor cores to be powered , add the power to other processor cores to allow individual processor cores to run at a higher frequency, as long as the total power/current consumed by the processor does not exceed the maximum power supply power/current that the system is designed to withstand. Therefore, the power budget needs to be properly distributed among the multiple power domains, and the maximum frequency allowed by the core in the turbo state needs to be determined according to the allocated power budget.

In the prior art, the power budget is generally allocated to each power domain evenly, that is, the power budget allocated to each power domain is the same, and then in the middle of each power domain, according to the heaviest load that each power domain can bear. Load, determine the maximum frequency of the processor core; it is understandable that the operating frequency of the processor core in each power domain is limited by the maximum frequency, that is, when the processor core is in an overclocked state, the increased operating frequency cannot exceed the maximum frequency.

FIG. 1 provides a core power distribution table of a processor for an embodiment of the present application, wherein the processor includes 16 cores and 32 threads; it can be understood that in the first column, no processor core is in an overclocked state, and the second In the column, one processor core is in the overclocking state, and so on; for example, in the ninth column of data, in this state, there are 8 processor cores in the turbo state, and the power consumption is between 14W and 14.5W , which is significantly lower than the power consumption of 18.34W when a single processor core is in turbo in the second column of data. At the same time, when 8 processor cores are in turbo state, the total power consumption of the processor is 122.87W, which is significantly lower than the peak power consumption of 144.49W when 10 processor cores are in turbo state in the 11th column data. Obviously, this way of allocating the power margin makes each core in the turbo state unable to fully utilize the power budget in many cases due to the limitation of the maximum frequency, nor to exert the maximum performance of each core. Therefore, it is necessary to reformulate the way to allocate the power budget to improve the performance of the turbo function.

In view of this, the present application provides a power budget allocation method to adjust the power budget allocated to the processor core according to the power consumption of the processor core, and then control the frequency of the processor core according to the power budget, so that the power budget can be Get a more reasonable allocation to meet the needs of different processor cores. Furthermore, in this way, the frequency can also be adjusted according to the power budget, so that the adjusted processor core can be more in line with its operating state and improve the working efficiency of the processor core.

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

The terms "system" and "network" in the embodiments of the present application may be used interchangeably. "At least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one item (a) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple .

And, unless otherwise specified, ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the priority or importance of multiple objects. For example, the first moment and the second moment are only for distinguishing different moments, and do not indicate the difference in priority or importance of the two moments.

FIG. 2 exemplarily shows a schematic structural diagram of a processor 200 provided by an embodiment of the present application. As shown in FIG. 2 , the processor 200 may include at least one processor core, such as a processor core 20 , a processor core 21 , a processor core 22 and a processor core 23 . The processor 200 may also include non-core components, such as general-purpose units (including counters, decoders, signal generators, etc.), accelerator units, input/output control units, interface units, internal memory, and external buffers. Wherein, each processor core and non-core components can be connected through a communication bus (not shown in FIG. 2 ), so as to realize the data transmission operation.

It should be understood that the above-mentioned processor 200 may be a chip. For example, the processor 200 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), or a system on chip (SoC). It can be a central processing unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), or a microcontroller (microcontroller). unit, MCU), it can also be a programmable logic device (PLD) or other integrated chips. It should be noted that the processor 200 in this embodiment of the present application may also be an integrated circuit chip, which has a signal processing capability. For example, the processor 100 described above may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, Discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It can be understood that the memory (for example, the internal memory and the external buffer) in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory may be random access memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the methods described herein is intended to include, but not be limited to, these and any other suitable types of memory.

In this embodiment of the present application, with continued reference to FIG. 2 , the processor may further include a frequency controller 24, and each processor core may also be provided with a frequency regulator, and the frequency controller 24 may be associated with each processor core. the frequency regulator communication connection. In this way, when controlling the overclocking adjustment of each processor core, the frequency controller 24 may send a frequency control instruction to the frequency adjuster of the processor core, so that the frequency adjuster of the processor core adjusts the processing according to the frequency control instruction The frequency of the processor core, for example, is adjusted to be greater than the maximum frequency set by the manufacturer.

It should be noted that FIG. 2 is only an exemplary illustration. In other possible examples, the frequency regulator may be set only in one or several processor cores. In this way, the frequency controller 24 may The frequency regulator controls the frequency of the processor core. Alternatively, a frequency regulator may also be set in the non-core components, so that the frequency controller 24 can not only control the frequency of the processor core, but also control the frequency of the non-core components. Of course, the non-core components mentioned here refer to the components that work according to the set frequency.

The following takes controlling the frequency of one processor core as an example to introduce the power budget allocation method in the present application, and will not go into details for controlling other processor cores or non-processor cores.

Based on the processor shown in FIG. 2 , FIG. 3 exemplarily shows a schematic flowchart corresponding to a method for allocating a power budget provided by an embodiment of the present application. The method is applicable to a frequency controller, such as the frequency controller shown in FIG. 2 . twenty four. In this embodiment of the present application, the frequency controller may execute the power budget allocation method in a periodic manner. FIG. 3 exemplarily introduces the primary frequency control process of the frequency controller. As shown in FIG. 3 , the method includes:

301. The frequency controller determines the power consumption of at least one processor core included in each of the multiple power domains in the first cycle.

In this embodiment of the present application, the power supply mode of the processor may be a pre-core power supply mode, that is, each power supply domain includes only one processor core, and each processor core is independently powered; it may also be a pre-core power supply mode. In the die power supply mode, each power supply domain includes multiple processor cores, and the processor supplies power to multiple processors belonging to the same power supply domain. It can be known from the mathematical formula: Wi=Pi/(Fi Vi2); where Wi is the load, Pi is the power consumption, Fi is the power supply frequency corresponding to the core, and Vi is the power supply voltage corresponding to the voltage domain. That is, when the processor obtains the power consumption corresponding to the first cycle, it also needs to obtain the power supply voltage and power supply frequency of the power supply domain corresponding to each core in the first cycle. The processor can divide multiple power supply domains for multiple processor cores. , each power domain includes at least one processor core.

The frequency controller needs to pre-determine the cycle to allocate the power budget; since the average allocation of a fixed power margin to each power domain will make the maximum frequency that each power domain can achieve is limited by the fixed power budget, while the maximum power supply The frequency will in turn lead to the inability to fully utilize the maximum performance of each core; therefore, the frequency controller needs to allocate the power margin more reasonably according to the real-time status of each battery domain. Exemplarily, the processor can determine an allocated cycle , monitor the state of each power domain in one cycle, and then allocate the allocation in the next cycle according to the state. It is understandable that the power budget can also be allocated once in multiple cycles, which is not specifically limited.

Exemplarily, the frequency controller can obtain the power consumption of each power domain through the power consumption detector, use the power consumption to sense the state of each power domain, and allocate a reasonable power budget to it; it can be understood that the power consumption control The controller can detect the average power consumption corresponding to each power domain in a cycle, and can also obtain the real-time power consumption, which is not limited in detail.

It is understandable that when a power domain includes only one processor core, the power consumption of each power domain obtained by the power consumption controller is the power consumption of the processor core; when a power domain includes multiple processor cores When , the power consumption of each power domain obtained by the power consumption controller is the total power consumption of all processor cores in the power domain.

302. The frequency controller calculates the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of at least one processor core included in each power domain in the first cycle. load.

The frequency controller also uses the power consumption to determine the load of each power domain in the first cycle, uses the load as the processing rate, and then calculates the load of each core in the first cycle according to the above formula, and then uses the load as the pair. The reference term for the allocation of the power budget in the second cycle.

303. The frequency controller predicts, according to the load of at least one processor core included in each power domain in the first cycle, that at least one processor core included in each power domain will be included in the second cycle predicted load.

After determining the load of each power domain in the first cycle, the frequency controller can also use the load to predict the predicted load of each power domain in the second cycle. The load can more directly reflect the operating frequency requirement of each power domain in the second cycle. Therefore, allocating the power budget in the second cycle according to the predicted load can make the allocated power budget more reasonable.

304. The frequency controller calculates, according to the power consumption of the at least one processor core included in each power domain in the first cycle, the load of the at least one processor core included in each power domain during the first cycle , and any one or more of the predicted loads of at least one processor core included in each power supply domain within the second cycle, allocating a power budget to each power supply domain.

In a first optional manner, the frequency controller may allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle; The power budget is allocated according to the following formula:

PB _i =(P _i /P _total )*PB _total

Among them, PB _i is the power margin allocated by the system for the ith power domain, Pi is the power consumption in the first cycle corresponding to the _ith power domain, P _total is the sum of the power consumption corresponding to all power domains, PB _total is the total amount of power budget provided by the system; it can be understood that the higher the power consumption of the power domain in the first cycle, the greater the data processing workload of the power domain, and the more it needs to be allocated. increase the frequency of its internal processor core, so as to improve the processing speed of the processor core and give full play to the performance of the processor core.

In a second optional manner, the frequency controller may allocate a power budget to each power domain according to the load of at least one processor core included in each power domain in the first cycle; for example, The power budget can be allocated according to the following formula:

PB _i =(A _i /A _total )*PB _total

Among them, PB _i is the power margin allocated by the system for the ith power domain, A _i is the load in the first cycle corresponding to the ith power domain, A _total is the sum of the loads corresponding to all power domains, and PB _total is the system The total amount of power budget provided; it can be understood that the larger the corresponding load of the power domain in the first cycle, the greater the data processing workload of the power domain, the more power budget needs to be allocated, Increase the frequency of its internal processor core, so that the processing speed of the processor core can be increased and the performance of the processor core can be fully utilized.

In a third optional manner, the frequency controller may allocate a power budget to each power domain according to the predicted load of at least one processor core included in each power domain in the second cycle; an exemplary , the formula used is similar to the formula in the second optional method above, but A _i becomes the predicted load in the second cycle corresponding to the i-th power domain, and A _total is the sum of the predicted loads corresponding to all power domains , PB _total is the total power budget provided by the system; it is understandable that the predicted load can directly reflect the power demand of each power domain in the second cycle, and the larger the predicted load corresponding to the power domain in the second cycle, the The larger the data processing workload will be in this power domain, the more power budget needs to be allocated to it, and the frequency of its internal processor core needs to be increased. performance.

In a fourth optional manner, the frequency controller may be based on the load of at least one processor core included in each power domain in the first cycle and the load of at least one processor core included in each power domain in the first cycle The predicted load in the second cycle is used to allocate the power budget for each power domain. Specifically, the exponentially weighted moving average EWMA value of the two can be calculated, and the power budget can be allocated according to the EWMA value corresponding to each power domain; Combine the implementation state and predicted state of the processor core to allocate the power budget more reasonably.

Specifically, the power consumption of at least one processor core included in each power domain in the first cycle, the load of at least one processor core included in each power domain in the first cycle, and the The predicted loads of the at least one processor core in the second cycle can be combined arbitrarily, and the frequency controller can arbitrarily select one or more items as the basis for allocating the power budget, which is not specifically limited.

305. The frequency controller performs frequency adjustment on each power domain in the second cycle according to the allocated power budget.

It can be understood that the second period is the next period of the first period. After the frequency controller allocates a power margin for each power domain, it adjusts the power supply voltage in the power domain corresponding to each processor core according to the allocated power margin, and then determines the core according to the power budget and power supply voltage. The corresponding maximum power supply frequency, and the operating frequency corresponding to the core is continuously adjusted according to the maximum power supply frequency.

The present application provides a method for allocating a power budget, which is used to adjust the power budget allocated to a processor core according to the power consumption of the processor core, and then control the frequency of the processor core according to the power budget, so that the power budget can be more reasonable. Allocate to meet the needs of different processor cores. Furthermore, in this way, the frequency can also be adjusted according to the power budget, so that the adjusted processor core can be more in line with its operating state and improve the working efficiency of the processor core.

Based on the processor shown in FIG. 2 , FIG. 4 exemplarily shows a schematic flowchart corresponding to another method for allocating a power budget provided by an embodiment of the present application. The method is applicable to a frequency controller, such as the frequency control shown in FIG. 2 . device 24. In the embodiment of the present application, the power supply mode of the processor is a pre-die power supply mode, that is, each power supply domain includes multiple processor cores, and the processor supplies power to multiple processors belonging to the same power supply domain; as shown in Figure 4 As shown, the method includes:

401. The frequency controller determines the number of processor cores that are in an active state in the first cycle and that are included in each of the multiple power supply domains.

In this embodiment, each power domain of the processor includes multiple processor cores, and the multiple processor cores are collectively powered; it can be understood that when the processor core is in an activated (overclocked) state, it needs to Increase the power supply frequency and improve the performance of the core. Exemplarily, the processor may allocate a power margin for each power domain in the next cycle according to the number of cores that are active in the current cycle for each power domain, and the number of active cores in the power domain. The more, the more power headroom that needs to be allocated for that power domain.

402. The frequency controller determines the power consumption of the multiple processor cores included in each of the multiple power domains in the first cycle.

It can be understood that the frequency controller can still use the power consumption of the multiple processor cores included in each power domain in the first cycle as the condition for allocating the power margin. Specifically, this step is the same as the embodiment shown in FIG. 3 . Step 301 in is similar, which is not specifically limited.

403. The frequency controller is based on the number of processor cores that are in the active state in the first cycle and/or the number of processor cores included in each power supply domain and/or the number of each power supply domain in the multiple power supply domains. The power consumption of the plurality of processor cores included in the first cycle, with a power budget allocated to each of the power domains.

Exemplarily, in the first embodiment, the power budget can be allocated according to the following formula:

PB _i =(N _i /N _total )*PB _total

Among them, PB _i is the power margin allocated by the system for the ith power domain, Ni is the number of active processors in the _ith power domain, and N _total is the active processing corresponding to all power domains PB _total is the total power budget provided by the system. Exemplarily, in the second implementation manner, the frequency controller may be based on the number of processor cores that are active in the first cycle and the plurality of power sources according to the plurality of processor cores included in each power supply domain. The power consumption of multiple processor cores contained in each power domain in the domain in the first cycle is used to allocate the power budget; that is, the power budget is divided into two parts, PB _totalA and PB _totalB , where PB _totalA is used according to the power domain. The power budget is allocated according to the average power consumption. PB _totalB is used to allocate according to the number of active cores in the power domain. Finally, the power budget allocated by the two is added to obtain the power finally allocated to the power domain. budget.

Specifically, there can be various formulas for calculating the power budget, as long as the power budget allocated to the power domain is positively correlated with the power consumption corresponding to the power domain, or the number of cores in the active state is positively correlated. Not limited.

404. The frequency controller performs frequency adjustment on each power domain in the second cycle according to the allocated power budget.

It can be understood that this step is similar to step 305 in the embodiment shown in FIG. 3 , and details are not described here.

According to the foregoing method, FIG. 5 is a schematic structural diagram of a frequency controller 500 provided by an embodiment of the present application. The frequency controller 500 may be a chip or a circuit, such as a chip or a circuit that may be provided in a processor. The frequency controller 500 may correspond to the frequency controller 24 in the above method. The frequency controller 500 may implement any one or more of the corresponding method steps as shown in FIG. 3 . As shown in FIG. 5 , the frequency controller 500 may include a monitoring circuit 501 and a control circuit 502 . Further, the frequency controller 500 may further include a bus system, and the monitoring circuit 501 and the control circuit 502 may be connected through the bus system. Moreover, the monitoring circuit 501 can also be connected to the power consumption detector of each processor core through the bus system, and the control circuit 502 can also be connected to the frequency regulator of each processor core through the bus system.

In this embodiment of the present application, the monitoring circuit 501 may determine the power consumption of at least one processor core included in each of the multiple power supply domains in the first cycle, and send the power consumption to the control circuit 502 . Correspondingly, the control circuit 502 may allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle, and control the frequency according to the allocated power budget. The regulator performs frequency adjustment.

According to the foregoing method, FIG. 6 is a schematic structural diagram of another frequency controller 600 provided by an embodiment of the present application. The frequency controller 600 may be a chip or a circuit, such as a chip or a circuit that may be provided in a processor. The frequency controller 600 may correspond to the frequency controller 24 in the above method. The frequency controller 600 may implement any one or more of the corresponding method steps as shown in FIG. 4 . As shown in FIG. 6 , the frequency controller 600 may include a monitoring circuit 601 and a control circuit 602 . Further, the frequency controller 600 may also include a bus system, and the monitoring circuit 601 and the control circuit 602 may be connected through the bus system. Moreover, the monitoring circuit 601 can also be connected to the power consumption detector of each processor core through the bus system, and the control circuit 602 can also be connected to the frequency regulator of each processor core through the bus system.

In this embodiment of the present application, the monitoring circuit 601 may determine the number of processor cores that are in the active state in the first cycle and that are included in each power supply domain in the multiple power supply domains, and send them to the control circuit 602. Correspondingly, the control circuit 602 can allocate the power budget to each power domain according to the number of the processor cores in the active state of the plurality of processor cores included in each power domain, and according to the allocation The power budget controls the frequency regulator for frequency regulation.

According to the foregoing method, FIG. 7 is a schematic structural diagram of another frequency controller 700 according to an embodiment of the present application. The frequency controller 700 may be a chip or a circuit, such as a chip or circuit that may be provided in a processor. The frequency controller 700 may correspond to the frequency controller 24 in the above method. The frequency controller 700 may implement any one or more of the corresponding method steps shown in FIG. 3 above. As shown in FIG. 7 , the frequency controller 700 may include a determination unit 701 , an allocation unit 702 and an adjustment unit 703 .

The determining unit 701 is configured to determine the power consumption in the first cycle of at least one processor core included in each power supply domain of the multiple power supply domains.

The allocating unit 702 is configured to allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle.

An adjustment unit 703, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In an optional implementation manner, the power consumption of at least one processor core included in each power domain in the first cycle is the power consumption of at least one processor core included in each power domain in the first cycle Real-time power consumption or average power consumption.

In an optional embodiment, the frequency controller 700 further includes a calculation unit 704 .

The computing unit 704 is configured to calculate the power consumption of the at least one processor core included in each power domain in the first cycle according to the power consumption of the at least one processor core included in each power domain. one cycle load.

In an optional implementation manner, the computing unit 704 is further configured to predict, according to the load of at least one processor core included in each power domain in the first cycle, that each power domain contains The predicted load of the at least one processor core in the second cycle.

In an optional implementation manner, the allocating unit 702 is specifically configured to, according to the power consumption of at least one processor core included in each power domain in the first cycle, the Any one of the load of at least one processor core during the first cycle and the predicted load of at least one processor core included in each power domain during the second cycle, allocating a power budget to all for each power domain.

It can be understood that, the functions of each unit in the above-mentioned frequency controller 700 may refer to the implementation of the corresponding method embodiments, which will not be repeated here.

It should be understood that the above division of the units of the frequency controller 700 is only a division of a logical function. In actual implementation, it should be understood that the division of the above units of the frequency controller 700 is only a division of a logical function, and in actual implementation, all Or partially integrated into one physical entity, or physically separate. In this embodiment of the present application, the acquiring unit 701 may be implemented by the monitoring circuit 501 in FIG. 5 above, and the determining unit 702 and the adjusting unit 703 may be implemented by the control circuit 502 in FIG. 5 above.

According to the foregoing method, FIG. 8 is a schematic structural diagram of another frequency controller 800 provided by an embodiment of the present application. The frequency controller 800 may be a chip or a circuit, such as a chip or a circuit that may be provided in a processor. The frequency controller 800 may correspond to the frequency controller 24 in the above method. The frequency controller 800 may implement any one or more of the corresponding method steps shown in FIG. 4 above. As shown in FIG. 8 , the frequency controller 800 may include a determination unit 801 , an allocation unit 802 and an adjustment unit 803 .

The determining unit 801 is configured to determine the number of the processor cores that are in an active state in the first cycle and included in each power supply domain in the multiple power supply domains.

The allocating unit 802 is configured to allocate a power budget to each power supply domain according to the number of the processor cores in the active state in the first cycle included in each power supply domain.

An adjustment unit 803, configured to perform frequency adjustment on each power domain in a second period according to the allocated power budget, where the second period is the next period of the first period.

In an optional implementation manner, the determining unit 801 is further configured to determine the power consumption in the first cycle of the multiple processor cores included in each of the multiple power supply domains;

The allocating unit 802 is configured to calculate the number of processor cores that are in an active state in the first cycle and each power domain in the plurality of power domains according to the number of processor cores included in each power domain. The power consumption of the included plurality of processor cores in the first cycle, with a power budget allocated to each of the power domains.

It can be understood that, the functions of each unit in the above-mentioned frequency controller 800 may refer to the implementation of the corresponding method embodiments, which will not be repeated here.

It should be understood that the above division of the units of the frequency controller 800 is only a division of logical functions, and in actual implementation, all or part of them may be integrated into one physical entity, or may be physically separated. In this embodiment of the present application, the obtaining unit 801 may be implemented by the monitoring circuit 601 in FIG. 6 above, and the determining unit 802 and the adjusting unit 803 may be implemented by the control circuit 602 in FIG. 6 above.

According to the method provided by the embodiment of the present application, the present application also provides a computer program product, the computer program product includes: computer program code, when the computer program code is run on a computer, the computer is made to execute the steps shown in FIG. 1 to FIG. 4 . The method of any one of the illustrated embodiments.

According to the method provided by the embodiment of the present application, the present application further provides a computer-readable storage medium, where the computer-readable storage medium stores program codes, and when the program codes are run on a computer, the computer is made to execute FIG. 1 to FIG. 5 . The method of any one of the illustrated embodiments.

The terms "component", "module", "system" and the like are used in this specification to refer to a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be components. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. A component may, for example, be based on a signal having one or more data packets (eg, data from two components interacting with another component between a local system, a distributed system, and/or a network, such as the Internet interacting with other systems via signals) Communicate through local and/or remote processes.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware accomplish. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A method for allocating a power budget, wherein the method comprises:

determining the power consumption of at least one processor core included in each of the multiple power domains in the first cycle;

Allocate a power budget to each power domain according to the power consumption of at least one processor core included in the each power domain in the first cycle, so that each power domain is based on the allocation in the second cycle Frequency adjustment is performed on the obtained power budget, and the second period is the next period of the first period.
The method according to claim 1, wherein the power consumption of the at least one processor core included in each power domain in the first cycle is equal to the power consumption of the at least one processor core included in each power domain in the first cycle Real-time or average power consumption for the first cycle.
The method according to claim 2, wherein the method further comprises:

According to the power consumption of at least one processor core included in each power domain in the first cycle, the load of at least one processor core included in each power domain in the first cycle is calculated.
The method according to claim 3, wherein the method further comprises:

According to the load of at least one processor core included in each power domain in the first cycle, the predicted load of at least one processor core included in each power domain in the second cycle is predicted.
The method according to claim 4, wherein the power budget is allocated to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle, include:

According to the power consumption of at least one processor core included in each power domain in the first cycle, the load of at least one processor core included in each power domain during the first cycle, and the Allocating a power budget to each of the power domains for any one or more of the predicted loads of at least one processor core included in the plurality of power domains in the second cycle.
A method for allocating a power budget, wherein the method comprises:

determining the number of processor cores that are active in the first cycle of multiple processor cores included in each of the multiple power domains;

Allocate a power budget to each power supply domain according to the number of processor cores in the active state of the plurality of processor cores included in each power supply domain, so that each power supply The domain performs frequency adjustment based on the allocated power budget during a second period, the second period being the next period of the first period.
The method according to claim 6, wherein the method further comprises:

determining the power consumption of the plurality of processor cores included in each of the plurality of power domains in the first cycle;

The allocating a power budget to each power domain according to the number of processor cores in the active state of the plurality of processor cores included in each power domain, including:

According to the number of processor cores that are active in the first cycle and the number of processor cores included in each power domain in the multiple power domains During the first cycle of power consumption, a power budget is allocated to each of the power domains.
A frequency controller, characterized in that it includes:

a determining unit, configured to determine the power consumption of at least one processor core included in each of the multiple power domains in the first cycle;

an allocation unit, configured to allocate a power budget to each power domain according to the power consumption of at least one processor core included in each power domain in the first cycle;

An adjustment unit, configured to adjust the frequency of each power domain in a second period according to the allocated power budget, where the second period is a period next to the first period.
The frequency controller according to claim 8, wherein the power consumption of at least one processor core included in each power domain in the first cycle is the same as that of at least one processor included in each power domain The real-time or average power consumption of the core in the first cycle.
The frequency controller according to claim 9, wherein the frequency controller further comprises a calculation unit;

The computing unit is configured to calculate the power consumption of at least one processor core included in each power domain in the first cycle according to the power consumption of at least one processor core included in each power domain. cycle load.
The frequency controller of claim 10, wherein:

The computing unit is further configured to predict, according to the load of at least one processor core included in each power domain in the first cycle, that the at least one processor core included in each power domain will perform in the first cycle. Predicted load for two cycles.
The frequency controller according to any one of claims 8 to 11, wherein:

The allocating unit is specifically configured to, according to the power consumption of at least one processor core included in each power domain in the first cycle, the at least one processor core included in each power domain in the first cycle. A power budget is allocated to each power domain according to the load of the cycle, and any one of the predicted load of at least one processor core included in each power domain during the second cycle.
A frequency controller, characterized in that the frequency controller comprises:

a determining unit, configured to determine the number of processor cores that are in an active state in the first cycle of the multiple processor cores included in each power supply domain in the multiple power supply domains;

an allocation unit, configured to allocate a power budget to each of the power domains according to the number of processor cores in the active state of the plurality of processor cores included in each of the power domains;

An adjustment unit, configured to adjust the frequency of each power supply domain in a second period according to the allocated power budget, where the second period is the next period of the first period.
The frequency controller of claim 13, wherein:

The determining unit is further configured to determine the power consumption in the first cycle of the multiple processor cores included in each of the multiple power supply domains;

The allocating unit is configured to, according to the number of processor cores in the active state of the plurality of processor cores included in each power supply domain and the number of processor cores in each power supply domain in the plurality of power supply domains The power consumption of the plurality of processor cores included in the first cycle, with a power budget allocated to each of the power domains.
A processor, characterized in that the processor includes a processor core, a power consumption detector, a power consumption controller and a frequency regulator; the power consumption detector and the frequency regulator are connected to the controller;

the power consumption detector, configured to detect and determine the power consumption of at least one processor core included in each of the multiple power domains in the first cycle;

the power consumption controller, configured to allocate a power budget to each power supply domain according to the power consumption of at least one processor core included in each power supply domain in the first cycle;

The frequency regulator is configured to perform frequency regulation on each power domain in a second cycle according to the allocated power budget, where the second cycle is a next cycle of the first cycle.
The processor according to claim 15, wherein the power consumption of the at least one processor core included in each power domain in the first cycle is the same as that of the at least one processor core included in each power domain The real-time power consumption or average power consumption during the first cycle.
The processor according to claim 16, wherein the power consumption controller is further configured to calculate the power consumption of each power supply domain according to the power consumption of at least one processor core included in each power supply domain in the first cycle. The load of at least one processor core included in each power domain during the first cycle.
The processor according to claim 17, wherein the power consumption controller is further configured to predict the load according to the load of at least one processor core included in each power domain in the first cycle The predicted load of at least one processor core included in each power domain during the second cycle.
The processor according to claim 17, wherein the power consumption controller is specifically configured to, according to the power consumption of at least one processor core included in each power domain in the first cycle, each Any one of the load of at least one processor core included in the power domain in the first cycle and the predicted load of at least one processor core included in each power domain during the second cycle, will be A power budget is allocated to each of the power domains.
A processor, characterized in that the processor includes a processor core, a power consumption controller and a frequency regulator; the frequency regulators are respectively connected to the power consumption controller;

The power consumption controller determines the number of processor cores that are in an active state in the first cycle of multiple processor cores included in each power supply domain in the multiple power supply domains; the number of processor cores in the active state of the plurality of processor cores in the first cycle, allocating a power budget to each power domain;

The frequency regulator is configured to perform frequency regulation on each power domain in a second cycle according to the allocated power budget, where the second cycle is a next cycle of the first cycle.
The processor of claim 20, wherein the processor further comprises a power consumption detector, the power consumption detector is connected to the power consumption controller;

The power consumption is used to determine the power consumption of the multiple processor cores included in each of the multiple power domains in the first cycle;

The power consumption controller is specifically configured to, according to the number of processor cores in the active state of the multiple processor cores included in each power supply domain in the first cycle and the number of each of the multiple power supply domains The power consumption of the plurality of processor cores included in the power domain in the first cycle, and the power budget is allocated to each power domain.
An electronic device, characterized by comprising the processor according to any one of claims 15 to 21.