CN116994624A - Memory chip, memory, electronic device, and control method of memory - Google Patents

Abstract

The embodiment of the application discloses a memory chip, a memory, an electronic device and a control method of the memory, wherein the memory chip comprises: the instruction analysis module is used for analyzing the instruction to obtain a corresponding operation mode and an operation target and forming a corresponding control signal; and the non-target termination module is used for responding to the control signal, providing a non-target termination resistance value under a corresponding operation mode for the data transmission path when the memory chip is a non-operation target, and transmitting data by the memory chip and the instruction sender through the data transmission path.

Description

Memory chip, memory, electronic device, and control method of memory

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, but not limited to a memory chip, a memory, an electronic device, and a method for controlling the memory.

Background

According to the low power memory standard protocol set by the joint electronic equipment engineering council (Joint Electron Device Engineering Council, JEDEC) 209B, once the resistance value of the Non-Target termination module (NT-ODT) is set by the Mode Register (MR), the NT-ODT uses the same resistance value at the time of both Read operation and Write operation. In practice, the read operation and the write operation cannot simultaneously meet the requirements of the read operation and the write operation by using the same NT-ODT resistance value at present due to different signal transmission directions.

Disclosure of Invention

The embodiment of the application provides a memory chip, a memory, an electronic device and a control method of the memory.

The technical scheme of the application is realized as follows:

a memory chip, comprising:

the instruction analysis module is used for analyzing the instruction to obtain a corresponding operation mode and an operation target and forming a corresponding control signal;

and the non-target termination module is used for responding to the control signal, providing a non-target termination resistance value under a corresponding operation mode for the data transmission path when the memory chip is a non-operation target, and transmitting data by the memory chip and the instruction sender through the data transmission path.

A memory comprising a plurality of memory chips as described above, the memory comprising:

the first connecting end is used for connecting with the instruction sender to receive the instruction;

the second connecting end is used for being connected with the instruction sender and transmitting data signals;

the plurality of memory chips are simultaneously connected to the first connection terminal and the second connection terminal.

An electronic device, comprising the memory, further comprising:

the instruction sender is connected to the memory and used for outputting the instruction and transmitting the data signal corresponding to the instruction.

A method of controlling a memory including a plurality of memory chips, comprising:

analyzing the instruction to obtain a corresponding operation mode and an operation target, and forming a corresponding control signal;

responding to the control signal, and providing a non-target termination resistance value in a corresponding operation mode for the data transmission path when the memory chip is a non-operation target; wherein the memory chip and the instruction sender transmit data via a data transmission path.

A computer storage medium storing one or more programs executable by one or more processors to implement the steps of a control method for controlling a memory as described above.

The embodiment of the application provides a memory chip, a memory, an electronic device and a control method of the memory, wherein the memory chip comprises: the instruction analysis module is used for analyzing the instruction to obtain a corresponding operation mode and an operation target and forming a corresponding control signal; the non-target termination module is used for responding to the control signal, providing a non-target termination resistance value under a corresponding operation mode for the data transmission channel when the memory chip is a non-operation target, and transmitting data by the memory chip and the instruction sender through the data transmission channel; the application changes the structure of the memory chip, dynamically provides non-target termination resistance values effective on the data transmission path, for example, provides non-target termination resistance values in a read operation mode, thus optimizing the signal quality of the read operation; in the write mode, providing a non-target termination resistance value in the write mode, so that the signal quality of the write operation can be optimized; thereby obtaining a better eye pattern.

Drawings

FIG. 1 is a schematic diagram of the operational state definition of the JEDEC for NT-ODT during read and write operations;

FIG. 2 is a schematic diagram of a memory chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a second embodiment of a memory chip;

fig. 4 is a schematic diagram of a memory chip according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a memory chip according to an embodiment of the present application;

fig. 6 is a schematic diagram of a memory chip according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 9 is a flow chart of a method for controlling a memory according to an embodiment of the application;

FIG. 10 is a diagram illustrating a comparison of eye patterns according to an embodiment of the present application;

fig. 11 is a diagram illustrating an eye diagram comparison according to an embodiment of the application.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

According to JEDEC209B specifications, NT-ODT was introduced, taking LPDDR5/5x as an example. The LPDDR5/5X nature is also a block of Synchronous Dynamic Random Access Memory (SDRAM), commonly referred to as DDR SDRAM, S (synchronous) denotes synchronous, D (dynamic) denotes dynamic memory, and static memory (SRAM) as a distinction, DDR means that both rising and falling edges of a clock can transfer data. Illustratively, the LPDDR5/5X protocol specifies that once the resistance value of the NT-ODT is set by a Mode Register (MR), the NT-ODT uses the same resistance value during both Read operations and Write operations.

The working state definition of the JEDEC for NT-ODT at the time of read operation and write operation is shown in FIG. 1. As can be seen in connection with FIG. 1, in FIG. 1, D1 is in an operational state, such as in a read mode of operation, whereby D1 may be referred to as an operational target T-D; while D2 is in a non-operating state, whereby D2 may be referred to as a non-operating target NT-D. The application processor (Application Processor, AP) is accordingly also in operation. It is to be understood that the operational targets T-D and the non-operational targets NT-D may vary.

In the read operation mode shown in fig. 1, the reception terminal Rx in the operation target T-D is in a non-operating state, and the transmission terminal Tx is in an operating state. In fig. 1, the input terminal and the output terminal in the non-operating state are set in bold. The transmitting terminal Tx in the AP is in a non-operating state, and the receiving terminal Rx in the AP is in an operating state. In the non-operation target NT-D, both the transmission terminal Tx and the reception terminal Rx thereof are in a non-operation state. In the read mode, the termination resistor (T-ODT) in the operational target T-D is turned off, which can also be understood as having an infinite resistance value, while the SoC-ODT in the system-on-chip AP is in an operational state.

In FIG. 1, D1 is in an operational state, such as in a write mode of operation, where die D1 is still referred to as an operational target T-D; and D2 is in a non-operating state, whereby D2 will still be referred to as non-operational target NT-D. The AP is accordingly also in operation.

In the write operation mode shown in fig. 1, the reception terminal Rx in the operation target T-D is in an operating state, and the transmission terminal Tx is in a non-operating state, as shown in bold black. The transmitting terminal Tx in the AP is in an operating state, and the receiving terminal Rx in the AP is in a non-operating state. In the non-operation target NT-D, both the transmission terminal Tx and the reception terminal Rx thereof are in a non-operation state. Further, as shown in fig. 1, in the write operation mode, the termination resistor (T-ODT) in the operation target T-D is closed, and the SoC-ODT in the system-on-chip AP is opened to be in a non-operating state.

As can be seen from FIG. 1, the non-target termination resistances NT-ODT of the non-operational targets NT-D all use the same resistance value and are unchanged as a result of the combination of the read operation mode and the write operation mode described above.

In practice, the read and write operations cannot simultaneously satisfy the requirements of the read and write operations using the same NT-ODT resistance values as shown in fig. 1 due to the different signal transmission directions.

In some scenarios, the switching of the Non-Target ODT can also be achieved by configuring the register in the MR to set the NT-ODT resistance value before each read operation and write operation, respectively, to optimize the signal quality of the read operation, and by configuring the MR once at the time of the write operation and the read operation, respectively, at the time of the actual operation. And each time the read operation is switched to the write operation or the write operation is switched to the read operation, the write MR operation is performed on the memory chip. This way of configuring the registers in the MR to set the NT-ODT resistance value prior to each read or write operation can introduce a significant delay, e.g., the time overhead (latency) of MR per write operation is equal to 2CK+Max (14 ns,5 nCK). This latency corresponds to the time required for 135 data transfers when LPDDR5X is operating at 8533 Mbps. It can be seen that this way of optimizing the eye pattern introduces additional time overhead, reducing performance.

Fig. 2 is a schematic structural diagram of a memory chip 10 according to an embodiment of the present application, where the memory chip 10 includes:

the instruction parsing module 20 is configured to parse the instruction to obtain a corresponding operation mode and an operation target, and form a corresponding control signal;

in an embodiment of the application, the instructions include instructions of a command/address (CA) bus. The operation modes include a read operation mode and a write operation mode. Of course, with other instructions and other modes, reasonable extensions can be made, which is not specifically described in the present application. The data transferred by the CA bus is different when the memory chip is read and written.

And a non-target termination module 30 for providing a non-target termination resistance value in a corresponding operation mode to the data transmission path when the memory chip 10 is a non-operation target in response to the control signal, the memory chip 10 and the instruction sender transmitting data via the data transmission path.

In the embodiment of the present application, when the memory chip 10 is the operation target, it is disconnected from the data transmission path.

It will be appreciated that a memory typically includes a plurality of memory chips therein, the memory chip selected by a signal having a first logic level of the chip select signals being referred to as an operation target; the memory chip that is not selected by the signal having the second logic level among the chip selection signals is referred to as a non-operation target.

In an embodiment of the application, the instruction sender includes a processor. When the memory chip 10 is a non-operation target, in the read operation mode, the non-target termination module 30 provides the data transmission path with a non-target termination resistance value in the read operation mode, so that the signal quality of the read operation on the data transmission path can be optimized, and the influence of the memory chip 10 as the non-operation target on the read signals of other memory chips as the operation target can be reduced; in the write operation mode, the non-target termination module 30 provides the data transmission path with the non-target termination resistance value in the write operation mode, so that the signal quality of the write operation on the data transmission path can be optimized, and the influence of the write signal of the memory chip 10 as the non-operation target on the other memory chips as the operation target can be reduced; thereby obtaining a better eye pattern.

According to the application, when the memory chip 10 is a non-operation target, the non-target terminating resistance value effective on the data transmission path is dynamically provided, and the non-target terminating resistance value corresponding to the writing operation and the non-target terminating resistance value corresponding to the reading operation are automatically switched, so that the signal quality of the reading operation can be optimized when the non-target terminating resistance value corresponding to the reading operation is switched, and the signal quality of the writing operation can be optimized when the non-target terminating resistance value corresponding to the writing operation is switched, and a better eye diagram is obtained. Moreover, the method of dynamically providing the non-target termination resistance value effective for the data transmission path avoids the problems that the waiting time is increased and the effective bandwidth is reduced when the register of NT-ODT is set each time the register is switched from the read operation to the write operation or from the write operation to the read operation.

The memory chip provided by the embodiment of the application comprises: the instruction analysis module is used for analyzing the instruction to obtain a corresponding operation mode and an operation target and forming a corresponding control signal; the non-target termination module is used for responding to the control signal, providing a non-target termination resistance value under a corresponding operation mode for the data transmission channel when the memory chip is a non-operation target, and transmitting data by the memory chip and the instruction sender through the data transmission channel; the application changes the structure of the memory chip, dynamically provides non-target termination resistance values effective on the data transmission path, for example, provides non-target termination resistance values in a read operation mode, thus optimizing the signal quality of the read operation; in the write mode, providing a non-target termination resistance value in the write mode, so that the signal quality of the write operation can be optimized; thereby obtaining a better eye pattern.

In some embodiments of the present application, referring to FIG. 3, a non-target termination module 30 in a memory chip 10 includes: a switching unit 301 and a resistance unit 302. Here, taking two modes as an example, including a first mode and a second mode, one of the two modes is a read operation mode, and the other is a write operation mode; of course, in the case of other modes, reasonable expansion can be performed, and the mode resistance corresponding to the other modes is set, which is not particularly limited in the application;

the resistor unit 302 includes a first mode resistor 3021 and a second mode resistor 3022;

a switching unit 301 that connects the first mode resistor 3021 and the second mode resistor 3022;

a switching unit 301 for turning on the connection of the first mode resistor 3021 to the data transmission path during the first mode and turning off the connection of the second mode resistor 3022 to the data transmission path in response to the control signal;

fig. 3 exemplarily shows a connection relationship during the first mode during which the switching unit 301 turns on the connection of the first mode resistor 3021 to the data transmission path, as shown bolded in fig. 3, and turns off the connection of the second mode resistor 3022 to the data transmission path in response to the control signal.

VTT in the figure represents the termination power supply required for the memory chip 10, the voltage of which is the voltage required for the corresponding memory chip 10; or 0V, which corresponds to ground.

During the second mode (not shown in fig. 3), the switching unit 301 is further configured to switch on the connection of the second mode resistor 3022 to the data transmission path and to switch off the connection of the first mode resistor 3021 to the data transmission path during the second mode in response to the control signal.

The switching unit 301 is further configured to disconnect the second mode resistor 3022 from the data transmission path and disconnect the first mode resistor 3021 from the data transmission path when the memory chip 10 is the operation target (not shown in fig. 3) in response to the control signal.

That is, only if the memory chip 10 is not selected, the corresponding pattern resistance during the corresponding pattern is connected, thereby automatically switching between the non-target termination resistance value corresponding to the write operation and the non-target termination resistance value corresponding to the read operation.

In some embodiments of the present application, referring to fig. 4, the memory chip 10 includes a plurality of first pins 101 for receiving data signals with different bits, respectively;

the memory chip 10 includes a plurality of non-target termination modules 30, which are respectively connected to the plurality of first pins 101 in a one-to-one correspondence manner, and respectively provide corresponding non-target termination resistance values for the data signals of each bit;

the memory chip 10 further includes a second pin 102 connected to the instruction parsing module 20, and the second pin is configured to receive an instruction.

FIG. 4 illustrates a memory chip 10 including 8 first pins 101 for receiving 8-bit data signals of one BYTE (BYTE), respectively, the 8-bit data signals being different in corresponding data signal lines (Lane), such as DQ_BUS01_DQ_BUS08 in FIG. 4; at this time, one memory chip 10 includes 8 non-target termination modules 30, and each non-target termination module 30 is connected to a corresponding first pin 101 to provide a corresponding non-target termination resistance value for the data signal of each bit, so that each data signal line can be guaranteed to have the best signal quality.

It can be appreciated that the number of the first pins 101 and the number of the non-target termination modules 30 included in the memory chip 10 are not particularly limited in the present application, so that in the case that the memory chip 10 includes a plurality of non-target termination modules 30, the non-target termination modules are respectively connected to the plurality of first pins 101 in a one-to-one correspondence manner, and a corresponding non-target termination resistance value is respectively provided for the data signal of each bit, that is, each data line is connected to one non-target termination module 30, so that the eye pattern quality of each data line is improved.

For example, referring to FIG. 4, the non-target termination module 30 may include resistor units that are resistor arrays (DQ NT-ODT arrays) each including two resistors R1 and R2.

In some embodiments of the present application, referring to fig. 5, the memory chip 10 further includes a target termination module 40 for providing a target termination resistance value when the memory chip 10 is the instructed operation target.

In the embodiment of the present application, each memory chip 10 includes a Target termination module 40, where a corresponding MR (not shown in the figure) is set, and a value of the Target termination module 40 (Target ODT) dedicated to each data signal line is configured as a plurality of values, for example, a plurality of binary numbers, each corresponding to a resistance value.

In an embodiment of the present application, referring to fig. 6, during a WRITE operation, a non-target termination resistor (NT-ODT-WRITE) corresponding to the WRITE operation provides a non-target termination resistor value in a corresponding operation mode to a data transmission path. The target termination module 40 in fig. 5 provides the data transmission path with a corresponding target termination resistance value for the corresponding write operation.

In some embodiments of the present application, the non-target termination module 30 further includes a configuration unit (not shown) for configuring the resistances of the first mode resistor and the second mode resistor.

In the embodiment of the present application, the configuration unit includes MRs, for example, two MRs are selected: MRx and MRy. Taking the first mode resistor R1 as a non-target termination resistor (NT-ODT-READ) corresponding to a READ operation, taking the second mode resistor R2 as a non-target termination resistor (NT-ODT-WRITE) corresponding to a WRITE operation as an example, the value of R1 is configured by a corresponding MRx, and the value of R2 is configured by a corresponding MRy. As can be seen, MRx is dedicated to setting the resistance of NT-ODT-READ and MRy is dedicated to setting the resistance of NT-ODT-WRITE.

TABLE 1 MRx configured values of R1

As can be seen from table 1, when the values in MRx are configured as a plurality of values, such as a plurality of binary numbers, each binary number corresponds to a resistance value; n is a positive integer. One or more MRx can be arranged for the NT-ODT-READ, and R1 has a plurality of resistance values Rx 0-Rxn; thus, a plurality of binary numbers can be configured according to actual requirements; the more binary numbers the MRx corresponding to the NT-ODT-READ can be configured, the larger the selectable range of values of the resistance of the NT-ODT-READ, thereby ensuring that, in response to a control signal, a more finely controlled non-target termination resistance value in a READ mode of operation is provided in the READ mode of operation, and a better eye diagram is provided without increasing time overhead.

TABLE 2 values of R2 for MRy configuration

As can be seen from table 2, when the values in MRy are configured as a plurality of values, for example, a plurality of binary numbers, each binary number corresponds to one resistance value; n is a positive integer. One or more MRy can be arranged for the NT-ODT-WRITE, and R2 has a plurality of resistance values Ry 0-Ryn; thus, a plurality of binary numbers can be configured according to actual requirements; the more binary numbers the MRy corresponding to the NT-ODT-WRITE can configure, the larger the selectable value range of the resistance value of the NT-ODT-WRITE, so that the non-target termination resistance value in a WRITE operation mode with finer control is provided in the WRITE operation mode when responding to a control signal, and a better eye diagram is provided under the condition of not increasing time expenditure.

In some embodiments of the present application, referring to fig. 5, the memory chip 10 further includes a plurality of receiving units 50 for receiving each input data signal, comparing each input data signal with a corresponding reference data signal, and outputting an output data signal of each path.

In an embodiment of the present application, as shown in fig. 5, the memory chip 10 further includes a plurality of receiving units 50, each receiving unit 50 includes one or more MRs (not shown in the figure), and each receiving unit 50 includes an MR dedicated to setting a reference data signal, such as a reference voltage Vref, associated with a corresponding one of the input data signals. That is, the reference data signals corresponding to each path are configured independently, and the numerical configuration range of the reference data signals can be flexibly selected according to the number of the MRs corresponding to each path, so that all the data signal lines can obtain the optimal timing margin. That is, when the respective data signal lines are set to different reference voltages, improvement in eye width of the data signal lines whose eye patterns are poor is remarkable.

It should be noted that, according to JEDEC209B specifications, LPDDR5/LPDDR5x DRAMs share one reference voltage setting for one byte (data signal including 8 bits). However, since the data signal lines are generally different in one byte, this results in that one byte shares one reference voltage and thus cannot obtain an optimal timing margin for all the data signal lines.

In view of the foregoing, the number of the first pins 101, the number of the non-target termination modules 30, and the number of the receiving units 50 included in the memory chip 10 according to the present application may be the same, so that each first pin 101 receives a data signal with one bit, and a separate reference voltage is set for the data signal with each bit, so that each data signal line can have the maximum eye width, and similarly, each data path with each bit can be configured with NT-ODT, so that each data signal line can have the best signal quality.

In some embodiments of the present application, referring to fig. 7, the present application provides a memory 60 including a plurality of memory chips 10, the memory 60 including:

a first connection end 601, configured to connect with an instruction sender to receive an instruction;

a second connection 602, configured to connect to an instruction sender, and configured to transmit a data signal;

a plurality of memory chips 10 are simultaneously connected to the first connection terminal 601 and the second connection terminal 602.

In the embodiment of the present application, different memory chips 10 are regarded as different ranks, and each Rank, for example Rank0, rank1, is connected to the instruction sender through the first connection end 601 to receive the instruction; rank0, rank1 are connected to the instruction sender through a second connection 602, and are used for transmitting data signals. The non-target termination module 30 of each Rank is connected to the first pin 101 of the corresponding Rank, and the second pin 102 of each Rank is connected to the instruction parsing module 20.

In the embodiment of the application, CA_BUS represents an LPDDR system command address BUS (command and address BUS), and the transmitted signals comprise all commands and address signals possibly used by the LPDDR system. DQ_BUS represents the LPDDR system Data Queue (DQ) data BUS, and the transmitted signal contains all possible data signals used by the LPDDR system.

In an embodiment of the application, the memory includes, but is not limited to, a semiconductor memory, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM).

In some embodiments of the present application, referring to fig. 8, the present application provides an electronic device 80, including a memory 60, further including:

the instruction sender 70 is connected to the memory 60, and is configured to output an instruction and transmit a data signal corresponding to the instruction.

In an embodiment of the present application, the instruction sender 70 includes, but is not limited to, a System-on-a-chip (SOC), and the instruction parsing module (CA bus decoder) in the memory 60 can automatically identify whether the operation of the port physical layer (Port Physical Layer, PHY) of the SOC on the memory 60 is Read or Write, and then automatically switch between NT-ODT-Read and NT-ODT-Write.

Fig. 9 is a flow chart of a method for controlling a memory according to an embodiment of the present application, which is applied to the foregoing memory chip, memory or electronic device, and includes:

and 101, analyzing the instruction, obtaining a corresponding operation mode and an operation target, and forming a corresponding control signal.

In the embodiment of the application, the memory chip analyzes the command of the command address bus through the command analysis module and judges whether the current command corresponds to a read operation mode or a write operation mode; and determines the operation target and forms corresponding control signals. For example, CA [2:0] =001 determines that the currently performed instruction corresponds to a read operation mode; CA [2:0] = 110 determines that the currently executing instruction corresponds to a write operation mode.

Step 102, responding to the control signal, and providing a non-target termination resistance value in a corresponding operation mode for the data transmission path when the memory chip is a non-operation target.

Wherein the memory chip and the instruction sender transmit data via a data transmission path.

In the embodiment of the application, the memory chip responds to the control signal through a switch unit such as a multiplexer switch (Multiplexer switch) included in the non-target termination module, and when the memory chip is a non-operation target, the non-target termination resistance value in the corresponding operation mode is provided for the data transmission path, namely, the switching between different NT-ODT resistance values is realized through the multiplexer switch.

Here, if the result parsed by the CA bus decoder is a Read command, the multiplexer switch turns on the NT-ODT-Read resistor and turns off the other NT-ODT resistors; if the result analyzed by the command analysis module is a Write command, the multiplexer switch turns on the NT-ODT-WRITE resistor and turns off other NT-ODT resistors; thus, the non-target termination resistance value effective on the data transmission path is dynamically provided, the NT-ODT-READ resistance value in the READ operation mode is provided in the READ operation mode, and the signal quality of the READ operation can be optimized; in the WRITE operation mode, providing the resistance value of the NT-ODT-WRITE in the WRITE operation mode, so that the signal quality of the WRITE operation can be optimized; thereby obtaining a better eye pattern.

In the embodiment of the application, the value of MRx corresponding to NT-ODT-READ and the value of MRy corresponding to NT-ODT-WRITE are written into the memory chip or the memory by SOC (PHY) when the memory chip or the memory is initialized. The specific values of NT-ODT-READ and NT-ODT-WRITE may be determined by signal integrity (SIGNAL INTEGRITY, SI) simulation or training (training) of the entire link.

In some embodiments of the present application, the number of data transmission paths is plural, and each data transmission path is provided with a corresponding non-target termination resistance value. In the application, the number of data transmission paths is the same as the number of bits of the data signals of a plurality of bits, and each bit corresponds to one data signal line.

In the embodiment of the application, each data signal line has independent ODT/NT-ODT configuration, and each data signal line can have the best signal quality.

In the embodiment of the application, the parts of the drawings, such as Multiplexer switch, DQ NT-ODT, DQ Target-ODT, vref and the like, only show a circuit schematic diagram of one signal in the DQ_BUS, and the representation shows that any signal in the DQ_BUS has the same structure. I.e., each data signal line has an independent DQ NT-ODT, DQ Target-ODT, vref.

Referring to FIG. 6, the Non-Target ODT corresponding to the WRITE operation in the present application is NT-ODT-WRITE; the Non-Target ODT corresponding to the READ operation is NT-ODT-READ; unlike the related art in which Read/write operation Non-Target ODT corresponds only to NT-ODT; by way of example, applying the topology provided by the present application to scenario one, referring to FIG. 10, the best eye diagram is obtained by setting NT-ODT to 240 Ω during a write operation, while the best eye diagram is obtained by setting NT-ODT to 80 Ω during a read operation.

Still another exemplary application of the topology provided by the present application to scenario two is shown with reference to FIG. 11, where NT-ODT is set to 120Ω and the best eye is obtained during a write operation, and where NT-ODT is set to off and the best eye is obtained during a read operation.

From the above, it is apparent that the improvement of the eye pattern of the data signal lines with a poor eye pattern is apparent when the respective data signal lines of the present application are set to different ODT. Under the condition of not increasing time expenditure, the topological structure provided by the application has a better eye pattern; the ODT matching on the PHY side is maintained during the read operation, and the eye height is adjusted. Each data signal line has an independent reference voltage configuration, so that each data signal line can have the maximum eye width (timing margin).

The description of the electronic device embodiments above is similar to that of the method embodiments above, with similar benefits as the method embodiments. For technical details not disclosed in the embodiments of the apparatus of the present application, please refer to the description of the embodiments of the method of the present application.

Embodiments of the present application provide a storage medium storing executable instructions, the storage medium storing one or more programs executable by one or more processors to implement the steps of: analyzing the instruction to obtain a corresponding operation mode and an operation target, and forming a corresponding control signal;

responding to the control signal, and providing a non-target termination resistance value in a corresponding operation mode for the data transmission path when the memory chip is a non-operation target; wherein the memory chip and the instruction sender transmit data via a data transmission path.

The application provides a storage medium: analyzing the instruction to obtain a corresponding operation mode and an operation target, and forming a corresponding control signal; responding to the control signal, when the memory chip is a non-operation target, providing a non-target termination resistance value under a corresponding operation mode for the data transmission channel, and transmitting data by the memory chip and the instruction sender through the data transmission channel; the application changes the structure of the memory chip, dynamically provides non-target termination resistance values effective on the data transmission path, for example, provides non-target termination resistance values in a read operation mode, thus optimizing the signal quality of the read operation; in the write mode, providing a non-target termination resistance value in the write mode, so that the signal quality of the write operation can be optimized; thereby obtaining a better eye pattern.

In some embodiments of the application, the one or more programs are executable by the one or more processors to perform the steps of:

the number of the data transmission paths is plural, and a corresponding non-target termination resistance value is provided for each data transmission path.

Embodiments of the present application provide a computer-readable storage medium storing one or more programs executable by one or more processors to implement a control process in a control method for controlling a memory as provided in the corresponding embodiment of fig. 9, which will not be described herein.

The computer storage medium/Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable programmable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic random access Memory (Ferromagnetic Random Access Memory, FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Read Only optical disk (Compact Disc Read-Only Memory, CD-ROM); but may also be various terminals such as mobile phones, computers, tablet devices, personal digital assistants, etc., that include one or any combination of the above-mentioned memories.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment of the present application" or "the foregoing embodiments" or "some implementations" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "an embodiment of the application" or "the foregoing embodiment" or "some embodiments" or "some implementations" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of units is only one logical function division, and there may be other divisions in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

The methods disclosed in the method embodiments provided by the application can be arbitrarily combined under the condition of no conflict to obtain a new method embodiment.

The features disclosed in the several product embodiments provided by the application can be combined arbitrarily under the condition of no conflict to obtain new product embodiments.

The features disclosed in the embodiments of the method or the apparatus provided by the application can be arbitrarily combined without conflict to obtain new embodiments of the method or the apparatus.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.

Alternatively, the above-described integrated units of the present application may be stored in a computer-readable storage medium if implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present application may be embodied essentially or in a part contributing to the related art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

It should be noted that the drawings in the embodiments of the present application are only for illustrating schematic positions of respective devices on the terminal device, and do not represent actual positions in the terminal device, the actual positions of respective devices or respective areas may be changed or shifted according to actual situations (for example, structures of the terminal device), and proportions of different parts in the terminal device in the drawings do not represent actual proportions.

The foregoing is merely an embodiment of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A memory chip, comprising:

the instruction analysis module is used for analyzing the instruction to obtain a corresponding operation mode and an operation target and forming a corresponding control signal;

and the non-target termination module is used for responding to the control signal, providing a non-target termination resistance value under the corresponding operation mode for a data transmission channel when the memory chip is a non-operation target, and transmitting data by the memory chip and an instruction sender through the data transmission channel.

2. The memory chip of claim 1, wherein the non-target termination module comprises: a switching unit and a resistance unit;

the resistance unit comprises a first mode resistance and a second mode resistance;

the switch unit is connected with the first mode resistor and the second mode resistor;

the switching unit is used for responding to the control signal, connecting the first mode resistor with the data transmission path during a first mode, and disconnecting the second mode resistor with the data transmission path;

the switching unit is further configured to switch on a connection of the second mode resistor to the data transmission path during a second mode and to switch off a connection of the first mode resistor to the data transmission path in response to the control signal.

3. The memory chip of claim 1, wherein the memory chip comprises a plurality of first pins for receiving data signals of different bits, respectively;

the memory chip comprises a plurality of non-target termination modules which are respectively connected with the plurality of first pins in a one-to-one correspondence manner, and respectively provide corresponding non-target termination resistance values for the data signals of each bit;

the memory chip further comprises a second pin connected to the instruction analysis module, and the second pin is used for receiving the instruction.

4. The memory chip of claim 1, wherein the memory chip further comprises a target termination module for providing a target termination resistance value when the memory chip is an operational target of the instruction.

5. The memory chip of claim 3, wherein the non-target termination module further comprises a configuration unit for configuring resistance values of the first mode resistance and the second mode resistance.

6. The memory chip of claim 1, wherein the memory chip further comprises a plurality of receiving units for receiving each input data signal, comparing the each input data signal with a corresponding reference data signal, and outputting an output data signal for each path.

7. A memory comprising a plurality of memory chips as defined in any one of claims 1 to 6, the memory comprising:

the first connecting end is used for connecting with the instruction sender to receive the instruction;

the second connecting end is used for being connected with the instruction sender and transmitting the data signal;

a plurality of memory chips are simultaneously connected to the first connection terminal and the second connection terminal.

8. An electronic device comprising the memory of claim 7, further comprising:

and the instruction sender is connected to the memory and used for outputting the instruction and transmitting a data signal corresponding to the instruction.

9. A method of controlling a memory, the memory including a plurality of memory chips, comprising:

analyzing the instruction to obtain a corresponding operation mode and an operation target, and forming a corresponding control signal;

responding to the control signal, and providing a non-target termination resistance value in the corresponding operation mode for a data transmission path when the memory chip is a non-operation target; wherein the memory chip and the instruction sender transmit data via the data transmission path.

10. The control method according to claim 9, wherein the number of the data transmission paths is plural, and a corresponding non-target termination resistance value is provided for each data transmission path, respectively.