CN210123555U - Conversion equipment of signal interface and communication system - Google Patents

Abstract

The application discloses a conversion device of a signal interface and a communication system. Wherein, this equipment includes: the conversion chip is provided with an original signal interface and a plurality of expanded target signal interfaces, and is used for converting the original signal received by the original signal interface into a target signal and outputting the target signal through the plurality of target signal interfaces; and the control circuit is connected with the conversion chip and used for detecting the interface type of the external module accessed to the target signal interface and controlling the interface type of the target signal interface to be matched with the interface type of the external module. The PCIe conversion equipment solves the technical problems that the data path of a downlink port cannot be adaptively increased or reduced due to the fact that the existing PCIe conversion equipment cannot achieve the purpose of micro-control auxiliary control by means of a single chip microcomputer and the like.

Description

Conversion equipment of signal interface and communication system

Technical Field

The application relates to the field of signal interface extension, in particular to conversion equipment of a signal interface and a communication system.

Background

The PCIe (peripheral Component Interconnect express) bus is a high-speed serial computer expansion bus standard, and is mainly used for connecting external devices in a processor system. With the rapid development of information technology and internet, people have higher and higher requirements on the functions of devices, and the devices are required to simultaneously provide support for multiple functions, particularly in some gateway systems, a plurality of high-speed network cards are required to be simultaneously connected. Each high-speed network card needs the support of an independent PCIe link, one PCIe link can only be connected with one device, the number of PCIe signal interfaces provided by the conventional chipset is limited, and the PCIe signal interfaces need to be expanded in order to break through the limitation.

The existing PCIe switching devices mainly include the following three types: the PCIe link switching card with the switch switching function is used for switching PCIe link interfaces or interface positions, and has a driver signal relay function.

With the rapid development of information technology and internet, the demand of various high-speed cards for PCIe interfaces is continuously expanding, and the existing PCIe adapter card implementation method has disadvantages, for example:

each port of the PCIe adapter card is relatively stable, the self-adaption increase or decrease of the port cannot be realized, the highest number of data paths of each port is kept unchanged, and the number cannot be changed in a self-adaption mode in cooperation with the change of the number of the ports; a few PCIe adapter cards have the number of self-adaptive ports and the highest lane number of each port, but need to be controlled by a microcontroller such as a single chip microcomputer or an FPGA (field programmable gate array); with the increase of the number of the downstream ports of the PCIe adapter card, the adapter card cannot provide sufficient power to each downstream port, and multiple downstream ports cannot be fully loaded at the same time.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

The embodiment of the application provides a conversion device of a signal interface and a communication system, and aims to at least solve the technical problems that the existing PCIe conversion device cannot realize the self-adaptive increase or decrease of data paths of downlink ports, and needs to be controlled by micro-control assistance such as a single chip microcomputer.

According to an aspect of an embodiment of the present application, there is provided a signal interface conversion apparatus including: the conversion chip is provided with an original signal interface and a plurality of expanded target signal interfaces, and is used for converting the original signal received by the original signal interface into a target signal and outputting the target signal through the plurality of target signal interfaces; and the control circuit is connected with the conversion chip and used for detecting the interface type of the external module accessed to the target signal interface and controlling the interface type of the target signal interface to be matched with the interface type of the external module.

Optionally, the interface types include: the interface comprises a first interface type and a second interface type, wherein a target signal interface of which the type is the first interface type comprises a port, all data paths are positioned in the port, and the data paths are used for transmitting target signals; the target signal interface with the type of the second interface comprises two ports, and all data paths are evenly distributed in the two ports

Optionally, the number of data paths included in any one of the target signal interfaces is the same as the number of data paths included in the original signal interface.

Optionally, the conversion chip includes a first port group and a second port group, where the first port group includes: the first port is connected with the original signal interface and used for receiving an original signal; the second port is used for outputting a target signal corresponding to the target signal interface of the first interface type or outputting one half of a target signal corresponding to the target signal interface of the second interface type; when the second port is used for outputting one half of a target signal corresponding to a target signal interface of the second interface type, the third port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; the fourth port is in an idle state; the second port set includes: the fifth port is used for outputting a target signal corresponding to the target signal interface of the first interface type; the sixth port is used for outputting a target signal corresponding to the target signal interface of the first interface type or outputting one half of a target signal corresponding to the target signal interface of the second interface type; when the sixth port is used for outputting one half of a target signal corresponding to the target signal interface of the second interface type, the seventh port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; the eighth port is in an idle state.

Optionally, the first port group and the second port group respectively include a first flag bit and a second flag bit, where the first flag bit of the first port group is in a low level state, and when the second flag bit of the first port group is in a high level state, the second port is configured to output a target signal corresponding to a target signal interface of the first interface type; when the first flag bit of the first port group is in a high-impedance state and the second flag bit of the first port group is in a low-level state, the second port is used for outputting one half of a target signal corresponding to a target signal interface of the second interface type, and at the moment, the third port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; when the first zone bit of the second port group is in a low level state and the second zone bit of the second port group is in a high level state, the sixth port is used for outputting a target signal corresponding to the target signal interface of the first interface type; when the first flag bit of the second port group is in a high-impedance state and the second flag bit of the second port group is in a low-level state, the sixth port is configured to output one half of the target signal corresponding to the target signal interface of the second interface type, and at this time, the seventh port is configured to output the other half of the target signal corresponding to the target signal interface of the second interface type.

Optionally, the control circuit comprises: the first control circuit is used for controlling the state of a first zone bit of the first port group, and the first control circuit is used for controlling the first zone bit of the first port group to be in a low level state when the interface type of the external module is detected to be the first interface type; the first control circuit is also used for controlling the first flag bit of the first port group to be in a high-impedance state when the interface type of the external module is detected to be a second interface type; the second control circuit is used for controlling the state of a second zone bit of the first port group, wherein the second control circuit is used for controlling the second zone bit of the first port group to be in a high level state when the interface type of the external module is detected to be the first interface type; the second control circuit is also used for controlling a second zone bit of the first port group to be in a low level state when the interface type of the external module is detected to be the second interface type; the third control circuit is used for controlling the state of the first zone bit of the second port group, wherein the third control circuit is used for controlling the first zone bit of the second port group to be in a low level state when the interface type of the external module is detected to be the first interface type; the third control circuit is also used for controlling the first flag bit of the second port group to be in a high-impedance state when the interface type of the external module is detected to be the second interface type; the fourth control circuit is used for controlling the state of a second zone bit of the second port group, wherein the fourth control circuit is used for controlling the second zone bit of the second port group to be in a high level state when the interface type of the external module is detected to be the first interface type; the fourth control circuit is further configured to control the second flag bit of the second port group to be in a low level state when the interface type of the external module is detected to be the second interface type.

Optionally, the first control circuit and the third control circuit both include a first field effect transistor and a second field effect transistor, wherein a drain D of the first field effect transistor is connected to the power supply, a source S of the first field effect transistor is connected to a drain D of the second field effect transistor, a source S of the second field effect transistor is grounded, and a gate G of the first field effect transistor is connected to a gate G of the second field effect transistor; a source S of a first field effect transistor and a drain D of a second field effect transistor of the first control circuit are connected with the first port group, and a source S of the first field effect transistor and a drain D of the second field effect transistor of the third control circuit are connected with the second port group; the second control circuit and the fourth control circuit respectively comprise a third field effect tube and a fourth field effect tube, wherein a drain electrode D of the third field effect tube is connected with a power supply and a grid electrode G of the fourth field effect tube, a source electrode S of the third field effect tube is grounded, a drain electrode D of the fourth field effect tube is connected with the power supply, a source electrode S of the fourth field effect tube is grounded, and a drain electrode D of the fourth field effect tube is connected with the source electrode S of the fourth field effect tube through a resistor with a preset resistance value; and a drain D of a fourth field effect transistor of the second control circuit and a source S of the fourth field effect transistor are connected with the first port group, and a drain D of the fourth field effect transistor of the fourth control circuit and a source S of the fourth field effect transistor are connected with the second port group.

Optionally, the conversion apparatus further comprises: the reset circuit is connected with the conversion chip and is used for resetting the target signal interfaces; the reset circuit corresponding to any one of the target signal interfaces comprises two Schmitt triggers which are connected in series.

Optionally, the conversion apparatus further comprises: the power supply chip is connected with a power supply of the case where the conversion equipment is located and used for converting the power supply into at least one type of power supply with a preset voltage value; and the power supply chip is started when the power of the external module accessed to the target signal interface is larger than a preset threshold value, otherwise, the power supply chip refuses to be started.

According to another aspect of the embodiments of the present application, there is also provided a communication system, including the above conversion device; an external device connected to the conversion device; and the conversion equipment is used for detecting the interface type of the external module and providing a signal interface matched with the interface type.

In an embodiment of the present application, there is provided a conversion device of a signal interface, including: the conversion chip is provided with an original signal interface and a plurality of expanded target signal interfaces, and is used for converting the original signal received by the original signal interface into a target signal and outputting the target signal through the plurality of target signal interfaces; the control circuit is connected with the conversion chip and used for detecting the interface type of an external module accessed to a target signal interface and controlling the interface type of the target signal interface to be matched with the interface type of the external module, the control circuit is built by adopting an independent element, and then the control circuit is utilized to control the data path of the downlink port of the PCIe conversion equipment to realize self-adaptive increase or decrease, so that the technical effect that the PCIe conversion equipment can increase or decrease the number of the data paths lan of the downlink port according to the number of the data paths lan of the accessed external module is realized, and the technical problems that the data path of the downlink port can not be increased or decreased in a self-adaptive manner by the conventional PCIe conversion equipment and micro-control auxiliary control such as a single chip microcomputer is needed are solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a block diagram of a conversion apparatus of a signal interface according to an embodiment of the present application;

FIG. 2 is a block diagram of a PCIe multi-port translation device in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of an allocation of ports of a switch chip according to an embodiment of the present application;

FIGS. 4 a-4 d are circuit diagrams of configuration conversion chip ports;

FIG. 5 is a circuit diagram of a reset circuit according to an embodiment of the present application;

FIG. 6 is a timing diagram of a power supply according to an embodiment of the present application;

fig. 7 is a block diagram of a communication system according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In accordance with an embodiment of the present application, there is provided an embodiment of a signal interface translation device, it should be noted that the steps shown in the flowchart of the figure can be executed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

Fig. 1 is a block diagram of a conversion apparatus of a signal interface according to an embodiment of the present application, as shown in fig. 1, the apparatus including:

the conversion chip 10 is provided with an original signal interface and a plurality of expanded target signal interfaces, and is configured to convert an original signal received by the original signal interface into a target signal and output the target signal through the plurality of target signal interfaces.

In an optional embodiment of the present application, the conversion chip 10 is specifically a PCIe expansion card, and is disposed in a 2U chassis, and is disposed at a lower layer of the chassis together with a motherboard, and fig. 2 is a schematic structural diagram of a PCIe multi-port conversion device according to an embodiment of the present application, as shown in fig. 2, because an internal space of the chassis is compact, a hard disk and other modules need to be disposed at an upper layer of the chassis, and the PCIe expansion card expands a data path lan interface on the motherboard for transmitting one path × 8PCIe signal into three physical sockets (slots), where two slots are a data path lan interface of one path × 8 or a data path lan interface of two paths × 4, and another is a data path lan interface of one path × 8.

As shown in fig. 2, the maximum usable area inside the switching device is 147mm × 147mmm, and the height of the switching device is limited to 3mm at the right side, so that the place where the heat dissipation fins of the Switch switching chip can be put down is only the left area. The upper left part is fixedly provided with a slot for PCIe 16, and the upper middle part is provided with a horizontal slot for PCIe 16. If the Switch conversion chip is placed in the upper area on the left side, firstly, routing of PCIe signals is difficult, and secondly, the heat dissipation fins of the Switch conversion chip are difficult to place. Finally, according to the scheme, the Switch conversion chip is placed at the lower left corner, and the shortest distance between the data paths and lanes of the PCIe signals can be guaranteed to the maximum extent at the position.

Preferably, the conversion chip 10 may employ a PEX8732Switch chip.

And the control circuit 12 is connected with the conversion chip 10 and is used for detecting the interface type of the external module accessed to the target signal interface and controlling the interface type of the target signal interface to be matched with the interface type of the external module.

In some alternative embodiments of the present application, the control circuit 12 is built using discrete components, with respect to the integrated circuit, and one diode and one transistor are referred to as discrete components.

Compared with microcontrollers such as a single chip microcomputer, the control circuit is built by adopting independent elements and has the following advantages: a program is not required to be written, a programming interface is omitted, programming by a programmer is omitted, and a program verification step is omitted; the cost of the discrete components such as the triode, the resistor, the capacitor and the like used in the scheme is lower than that of the microcontroller such as a single chip microcomputer and an FPGA; the participation of the program is reduced, the risk of the control circuit failure caused by the program run-off is reduced, and the reliability of the circuit is improved.

It should be noted that, the control circuit 12 controlling the interface type of the target signal interface to match the interface type of the external module means controlling the lane type of the downlink port of the conversion chip 10 to match the interface type of the external module, for example, the external module is a path of 8 lanes, and the downlink port of the conversion chip 10 is automatically switched to a path of 8 lanes; the external module is a port of two paths of 4 lanes, and the downlink port of the conversion chip 10 is automatically switched to an interface of two paths of 4 lanes. That is, the adaptive switching between the two paths of 4 lane ports and the one path of 8 lane ports is realized in the same physical slot of the downlink port of the control conversion chip 10.

Through the equipment, the self-adaptive control circuit is built by adopting the independent element, and then the control circuit is utilized to control the data path of the downlink port of the PCIe switching equipment to realize self-adaptive increase or decrease, so that the technical effect that the PCIe switching equipment adaptively increases or decreases the number of the data path of the downlink port of the PCIe switching equipment according to the change of PCIe signals is realized.

According to an alternative embodiment of the present application, the interface types include: the interface comprises a first interface type and a second interface type, wherein a target signal interface of which the type is the first interface type comprises a port, all data paths are positioned in the port, and the data paths are used for transmitting target signals; the target signal interface of the second interface type includes two ports, and all data paths are evenly distributed in the two ports.

According to an optional embodiment of the present application, the first interface type refers to that the target signal interface is a PCIe signal interface with one path of 1 × 8, where 1 × 8 refers to the number of prot ports and lane data paths, 1 × 8 includes 1 port, and each port is 8 lanes; similarly, the second interface type is a PCIe signal interface with a target signal interface of two paths 2 × 4, where 2 × 4 means that the target signal interface includes 2 ports, and each port is 4 lanes.

Optionally, the number of data paths included in any one of the target signal interfaces is the same as the number of data paths included in the original signal interface.

According to an alternative embodiment of the present application, the original signal interface of the conversion chip 10 is a 1 × 8PCIe interface, and the plurality of target signal interfaces includes a 1 × 8PCIe interface and a 2 × 4 PCIe interface, that is, the number of data lanes in any one target signal interface is equal to the number of data lanes in the original signal interface.

In an alternative embodiment of the present application, the conversion chip 10 includes a first port group and a second port group, wherein the first port group includes: the first port is connected with the original signal interface and used for receiving an original signal; the second port is used for outputting a target signal corresponding to the target signal interface of the first interface type or outputting one half of a target signal corresponding to the target signal interface of the second interface type; when the second port is used for outputting one half of a target signal corresponding to a target signal interface of the second interface type, the third port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; the fourth port is in an idle state; the second port set includes: the fifth port is used for outputting a target signal corresponding to the target signal interface of the first interface type; the sixth port is used for outputting a target signal corresponding to the target signal interface of the first interface type or outputting one half of a target signal corresponding to the target signal interface of the second interface type; when the sixth port is used for outputting one half of a target signal corresponding to the target signal interface of the second interface type, the seventh port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; the eighth port is in an idle state.

According to an optional embodiment of the present application, the first port group and the second port group respectively include a first flag bit and a second flag bit, where the first flag bit of the first port group is in a low level state, and when the second flag bit of the first port group is in a high level state, the second port is configured to output a target signal corresponding to a target signal interface of the first interface type; when the first flag bit of the first port group is in a high-impedance state and the second flag bit of the first port group is in a low-level state, the second port is used for outputting one half of a target signal corresponding to a target signal interface of the second interface type, and at the moment, the third port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; when the first zone bit of the second port group is in a low level state and the second zone bit of the second port group is in a high level state, the sixth port is used for outputting a target signal corresponding to the target signal interface of the first interface type; when the first flag bit of the second port group is in a high-impedance state and the second flag bit of the second port group is in a low-level state, the sixth port is configured to output one half of the target signal corresponding to the target signal interface of the second interface type, and at this time, the seventh port is configured to output the other half of the target signal corresponding to the target signal interface of the second interface type.

Fig. 3 is a schematic diagram illustrating the port allocation of a conversion chip according to an embodiment of the present application, in which PEX8732 is taken as the conversion chip, and PEX8732 is taken as an example for description below.

The PEX8732 resource is up to 32 data lanes (lane), 8 ports (port). These 32 lanes and 8 ports are divided into two groups (stations), each station having 16 lanes and 4 ports, as shown in fig. 3, station0 manages 16 lanes including lane0 to lane15, and station1 manages 16 lanes including lane16 to lane 31. The scheme at most comprises 6 ports, one of the 6 ports is an uplink port of 8 lanes, 5 downlink ports are provided, one of the 6 ports is 8 lanes, the rest of the downlink ports are 4 lanes, and at least comprises 3 ports, one of the ports is an uplink port of 8 lanes, and the rest of the ports are downlink ports of 8 lanes.

The PCIe Switch conversion chip has more and more ports and more flexible port setting, and in order to solve the problem that a few configuration pins can be configured with a plurality of working modes, a high-resistance state is also incorporated into pin configuration.

As shown in table 1, the station0 resource in PEX8732 includes 4 ports and 16 lanes, and the 4 ports include: port0, port1, port2, port3, 16 lanes comprising: from lane0 to lane 15. Self-adaptive switching is carried out on ports of two paths of 4 lanes and one path of 8 lanes, and the configuration shown in the table 1 is selected: when STN0(1:0) is 01, station0 is divided into two ports (port0 and port1), each port being assigned 8 lanes; when STN (1:0) ═ Z0, station0 is divided into 3 ports (port0, port1, and port2), with port0 assigned 8 lanes and port1 and port2 both assigned 4 lanes.

Table 1 station0 port configuration table

As shown in table 2, the station1 resource in PEX8732 also includes 4 ports and 16 lanes, and the 4 ports include: port8, port9, port10, port11, 16 lanes comprising: from lane16 to lane 31. The scheme of the invention totally has two physical downlink ports to make two ports of 4 lanes and 8 lanes to make self-adaptive switching, has made one port of 4 lanes and 8 lanes to make self-adaptive switching in station0, and also needs to make two ports of 4 lanes and 8 lanes to make self-adaptive switching in station 1. The configuration shown in table 2 was selected: when STN1(1:0) is 01, station1 is divided into two ports (port8 and port9), each port being assigned 8 lanes; when STN (1:0) ═ Z0, station1 is divided into 3 ports (port8, port9, and port10), with port8 assigned 8 lanes and port9 and port10 both assigned 4 lanes.

Table 2 station1 port configuration table

In some alternative embodiments of the present application, the control circuit 12 comprises: the first control circuit is used for controlling the state of a first zone bit of the first port group, and the first control circuit is used for controlling the first zone bit of the first port group to be in a low level state when the interface type of the external module is detected to be the first interface type; the first control circuit is also used for controlling the first flag bit of the first port group to be in a high-impedance state when the interface type of the external module is detected to be a second interface type; the second control circuit is used for controlling the state of a second zone bit of the first port group, wherein the second control circuit is used for controlling the second zone bit of the first port group to be in a high level state when the interface type of the external module is detected to be the first interface type; the second control circuit is also used for controlling a second zone bit of the first port group to be in a low level state when the interface type of the external module is detected to be the second interface type; the third control circuit is used for controlling the state of the first zone bit of the second port group, wherein the third control circuit is used for controlling the first zone bit of the second port group to be in a low level state when the interface type of the external module is detected to be the first interface type; the third control circuit is also used for controlling the first flag bit of the second port group to be in a high-impedance state when the interface type of the external module is detected to be the second interface type; the fourth control circuit is used for controlling the state of a second zone bit of the second port group, wherein the fourth control circuit is used for controlling the second zone bit of the second port group to be in a high level state when the interface type of the external module is detected to be the first interface type; the fourth control circuit is further configured to control the second flag bit of the second port group to be in a low level state when the interface type of the external module is detected to be the second interface type.

According to an optional embodiment of the present application, each of the first control circuit and the third control circuit comprises a first fet and a second fet, wherein a drain D of the first fet is connected to a power supply, a source S of the first fet is connected to a drain D of the second fet, a source S of the second fet is grounded, and a gate G of the first fet is connected to a gate G of the second fet; a source S of a first field effect transistor and a drain D of a second field effect transistor of the first control circuit are connected with the first port group, and a source S of the first field effect transistor and a drain D of the second field effect transistor of the third control circuit are connected with the second port group; the second control circuit and the fourth control circuit respectively comprise a third field effect tube and a fourth field effect tube, wherein a drain electrode D of the third field effect tube is connected with a power supply and a grid electrode G of the fourth field effect tube, a source electrode S of the third field effect tube is grounded, a drain electrode D of the fourth field effect tube is connected with the power supply, a source electrode S of the fourth field effect tube is grounded, and a drain electrode D of the fourth field effect tube is connected with the source electrode S of the fourth field effect tube through a resistor with a preset resistance value; and a drain D of a fourth field effect transistor of the second control circuit and a source S of the fourth field effect transistor are connected with the first port group, and a drain D of the fourth field effect transistor of the fourth control circuit and a source S of the fourth field effect transistor are connected with the second port group.

Fig. 4a is a circuit diagram of the first circuit, which is a circuit for configuring STN0[1], in order to implement adaptive switching between two lanes of 4 lanes and one lane of 8 lanes in the same physical slot, a pin needs to be set in a module connected to a downlink PORT to identify whether the module is a lane of 4 lanes or a lane of 8 lanes, and in this scheme, the identification of the collected downlink module is transmitted to PORT1_8X _4X # shown in fig. 4 a. The settings of PORT1_8X _4X # are: the downlink module is a PORT of 8 lanes, and PORT1_8X _4X # is high; the downstream module is two PORTs of two paths of 4 lanes, and the PORT1_8X _4X # is low. As shown in table 1, when the downlink module is two ports of two paths of 4 lanes, STN0[1] ═ Z needs to be set, that is, STRAP _ STN0_ G1 in fig. 4a is high impedance; when the downlink module is a port of one path of 8 lanes, STN0[1] needs to be set to 0, that is, STRAP _ STN0_ G1 in fig. 4a is low. The above logic is built by using discrete elements, as shown in fig. 4a, when PORT1_8X _4X # is high, both MOS transistors are turned on, and STRAP _ STN0_ G1 is clamped to ground; when the PORT1_8X _4X # is low, both MOS transistors are turned off, the STRAP _ STN0_ G1 is connected to the PN junctions of the two non-conducting MOS transistors, and when the currents of the drain D and the source S of the selected MOS transistor are very small, the MOS transistor is equivalently high-impedance, and the MOS transistor is selected as BSS138 in the scheme.

Fig. 4b is a circuit diagram of the second circuit, which is a circuit for configuring STN0[0], and as shown in table 1, when the downlink module is two ports of two lanes of 4 lanes, it is necessary to set STN0[0] to 0, that is, strp _ STN0_ G0 in fig. 4b is low; when the downlink module is a port of one path of 8 lanes, STN0[0] needs to be set to 1, that is, STRAP _ STN0_ G0 in fig. 4b is high. Building the above logic by using discrete elements, as shown in fig. 4b, when PORT1_8X _4X # is high, the left MOS transistor is turned on, the right MOS transistor GATE is clamped to the ground, the left MOS transistor is turned off, the trap _ STN0_ G0 is pulled up to be high, and the configured IO voltage of PEX8732 is 1.8V through the partial voltage of 10K and 12K; when PORT1_8X _4X # is low, the left MOS transistor is off, the right MOS transistor GATE is pulled up high, the right MOS transistor is on, and STRAP _ STN0_ G0 is clamped to ground.

Fig. 4c is a circuit diagram of the third circuit, which is a circuit for configuring STN1[1], and as shown in table 2, when a downlink module is two ports of two lanes of 4 lanes, STN1[1] ═ z is required to be set, that is, strp _ STN1_ G1 in fig. 4c is high impedance; when the downlink module is a port of one path of 8 lanes, STN1[1] needs to be set to 0, that is, STRAP _ STN1_ G1 in fig. 4c is low. The above logic is built by using discrete elements, as shown in fig. 4c, when PORT2_8X _4X # is high, both MOS transistors are turned on, and STRAP _ STN1_ G1 is clamped to ground; when the PORT2_8X _4X # is low, both MOS transistors are turned off, the STRAP _ STN1_ G1 is connected to the PN junction of two non-conducting MOS transistors, and the STRAP _ STN1_ G1 is equivalently high impedance.

Fig. 4d is a circuit diagram of the third circuit, which is a circuit for configuring STN1[0], and as shown in table 2, when the downlink module is two ports of two lanes of 4 lanes, it is necessary to set STN1[0] to 0, that is, strp _ STN1_ G0 in fig. 4d is low; when the downlink module is a port of one path of 8 lanes, STN1[0] needs to be set to 1, that is, STRAP _ STN1_ G0 in fig. 4d is high. Building the above logic using discrete components, as shown in fig. 4d, when PORT2_8X _4X # is high, the left MOS transistor is turned on, the right MOS transistor GATE is clamped to ground, the left MOS transistor is turned off, STRAP _ STN1_ G0 is pulled up, where the divided voltage by 10K and 12K is 1.8V, and STRAP _ STN1_ G0 is high; when PORT1_8X _4X # is low, the left MOS transistor is off, the right MOS transistor GATE is pulled up high, the right MOS transistor is on, and STRAP _ STN1_ G0 is clamped to ground.

According to an alternative embodiment of the present application, the above conversion apparatus further comprises: the reset circuit is connected with the conversion chip 10 and is used for resetting the target signal interfaces; the reset circuit corresponding to any one of the target signal interfaces comprises two Schmitt triggers which are connected in series.

Fig. 5 is a circuit diagram of a reset circuit according to an embodiment of the present application, and as shown in fig. 5, a schmitt trigger 74LVC14APWR is selected, each path of a 6-path trigger is inverted, two-stage triggering is adopted, reset levels are consistent, an uplink port can reset each downlink port and PEX8732, resetting of a downlink port cannot affect the uplink port nor other downlink ports, and both effective execution of resetting and safety of resetting are ensured.

In some optional embodiments of the present application, the conversion apparatus further comprises: the power supply chip is connected with a power supply of the case where the conversion equipment is located and used for converting the power supply into at least one type of power supply with a preset voltage value; and the power supply chip is started when the power of the external module accessed to the target signal interface is larger than a preset threshold value, otherwise, the power supply chip refuses to be started.

In the embodiment provided by the application, one uplink port expands three downlink ports, and the downlink ports are applied to a high-speed card, and the 12V and 3.3V required by all the downlink ports are far from being supplied by a high-speed connector, and in the embodiment of the application, an ATX power connector is adopted to directly introduce 12V from a chassis power supply, so that the sufficient power supply of the conversion equipment is ensured. Fig. 6 is a timing diagram of power supply of a power supply according to an embodiment of the present application, as shown in fig. 6, after a 12V power supply is introduced, the power supply is converted into different power supplies of 3.3V, 0.9V, and 1.8V, and the power-on sequence is 3.3V, 0.9V, and 1.8V, where the time interval parameters are as follows:

0ms<t1<1ms

0ms<t2<0.5ms

the 3.3V power supply supplies power to 3 PCIe slots, the sum of the sufficient power supply and the redundancy is 8A, the RT8202M is selected as the power supply chip, and in order to reduce the pressure of pulling the ground mos tube, the asymmetric design of pulling 1 mos tube and pulling 2 mos tubes is adopted.

The 0.9V power supply is the core voltage of the PEX8732, the power supply chip selects RT8202M according to the requirement of the chip and the sum of redundancy 12A, the inductor selects 1uH18A, and the mos tube adopts a symmetrical design of pulling up 1 and pulling down 1.

12V introduced by ATX of the 4 pins is connected with 12V introduced by the slot of the uplink port in parallel, and if only one downlink port is connected or the power of a module of the three downlink ports does not exceed 30W, a 12V power supply introduced by ATX of the external 4 pins is not needed; if the power of the three downlink port modules exceeds 30W, a 12V power supply introduced by an external 4-pin ATX is needed, and the power of the downlink port power supply is ensured.

With the above device, by placing the PEX8732 on the patch panel, PCIe is extended and chassis layout pressure is reduced. Its downstream port can be applied to all products of both PCIe1 × 8 and PCIe2 × 4 families. The scheme provides a new application solution of the PCIe GEN3 adapter card based on PEX8732 with high reliability and high efficiency, and is widely applied to various industries of network communication.

Fig. 7 is a block diagram of a communication system according to an embodiment of the present application, as shown in fig. 7, the system including:

an external device 70 connected to the conversion device 72;

according to an alternative embodiment of the present application, the external device 70 is an external device that accesses the translation device 72 through a PCIe bus.

And a conversion device 72 for detecting the interface type of the external module 70 and providing a signal interface matching the interface type.

It should be noted that, a preferred embodiment of the conversion device 72 in fig. 7 may refer to the conversion device described in any one of fig. 1 to fig. 6, and details are not repeated here.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims (10)

1. A signal interface conversion apparatus, comprising:

the conversion chip is provided with an original signal interface and a plurality of expanded target signal interfaces, and is used for converting an original signal received by the original signal interface into a target signal and outputting the target signal through the target signal interfaces;

and the control circuit is connected with the conversion chip and used for detecting the interface type of an external module accessed to the target signal interface and controlling the interface type of the target signal interface to be matched with the interface type of the external module.

2. The translation device according to claim 1, wherein the interface types include: a first interface type and a second interface type, wherein,

the target signal interface with the type of the first interface comprises a port, all data paths are positioned in the port, and the data paths are used for transmitting the target signals;

the target signal interface of the type of the second interface comprises two ports, and all data paths are evenly distributed in the two ports.

3. The conversion apparatus of claim 2, wherein any one of the plurality of destination signal interfaces comprises the same number of data lanes as the original signal interface.

4. The translation device of claim 2, wherein the translation chip includes a first port set and a second port set, wherein,

the first port set includes: the first port is connected with the original signal interface and used for receiving the original signal; the second port is used for outputting a target signal corresponding to the target signal interface of the first interface type or outputting one half of a target signal corresponding to the target signal interface of the second interface type; when the second port is used for outputting one half of a target signal corresponding to the target signal interface of the second interface type, the third port is used for outputting the other half of the target signal corresponding to the target signal interface of the second interface type; the fourth port is in an idle state;

the second port set includes: the first port is used for outputting a target signal corresponding to a target signal interface of the first interface type; the sixth port is configured to output a target signal corresponding to the target signal interface of the first interface type or output one half of a target signal corresponding to the target signal interface of the second interface type; when the sixth port is configured to output one-half of the target signal corresponding to the target signal interface of the second interface type, the seventh port is configured to output the other one-half of the target signal corresponding to the target signal interface of the second interface type; the eighth port is in an idle state.

5. The translation device of claim 4, wherein the first port set and the second port set comprise a first flag bit and a second flag bit, respectively, wherein,

when the first flag bit of the first port group is in a low level state and the second flag bit of the first port group is in a high level state, the second port is used for outputting a target signal corresponding to a target signal interface of the first interface type;

when the first flag bit of the first port group is in a high-impedance state and the second flag bit of the first port group is in a low-level state, the second port is configured to output one half of a target signal corresponding to a target signal interface of the second interface type, and at this time, the third port is configured to output the other half of the target signal corresponding to the target signal interface of the second interface type;

when the first flag bit of the second port group is in a low level state and the second flag bit of the second port group is in a high level state, the sixth port is configured to output a target signal corresponding to a target signal interface of the first interface type;

when the first flag bit of the second port group is in a high-impedance state and the second flag bit of the second port group is in a low-level state, the sixth port is configured to output one half of the target signal corresponding to the target signal interface of the second interface type, and at this time, the seventh port is configured to output the other half of the target signal corresponding to the target signal interface of the second interface type.

6. The conversion apparatus according to claim 5, wherein the control circuit comprises: a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit, wherein,

the first control circuit is configured to control a state of a first flag bit of the first port group, where the first control circuit is configured to control the first flag bit of the first port group to be in a low level state when detecting that the interface type of the external module is the first interface type; the first control circuit is further configured to control a first flag bit of the first port group to be in a high-impedance state when detecting that the interface type of the external module is the second interface type;

the second control circuit is configured to control a state of a second flag bit of the first port group, where the second control circuit is configured to control the second flag bit of the first port group to be in a high level state when detecting that the interface type of the external module is the first interface type; the second control circuit is further configured to control a second flag bit of the first port group to be in a low level state when detecting that the interface type of the external module is the second interface type;

the third control circuit is configured to control a state of a first flag bit of the second port group, where the third control circuit is configured to control the first flag bit of the second port group to be in a low level state when it is detected that the interface type of the external module is the first interface type; the third control circuit is further configured to control the first flag of the second port group to be in a high-impedance state when the interface type of the external module is detected to be the second interface type;

the fourth control circuit is configured to control a state of a second flag bit of the second port group, where the fourth control circuit is configured to control the second flag bit of the second port group to be in a high level state when it is detected that the interface type of the external module is the first interface type; the fourth control circuit is further configured to control the second flag bit of the second port group to be in a low level state when it is detected that the interface type of the external module is the second interface type.

7. The conversion apparatus according to claim 6,

the first control circuit and the third control circuit both comprise a first field effect transistor and a second field effect transistor, wherein a drain electrode D of the first field effect transistor is connected with a power supply, a source electrode S of the first field effect transistor is connected with a drain electrode D of the second field effect transistor, a source electrode S of the second field effect transistor is grounded, and a grid electrode G of the first field effect transistor is connected with a grid electrode G of the second field effect transistor;

a source electrode S of a first field effect transistor of the first control circuit and a drain electrode D of the second field effect transistor of the third control circuit are connected with the first port group;

the second control circuit and the fourth control circuit both comprise a third field effect transistor and a fourth field effect transistor, wherein a drain electrode D of the third field effect transistor is connected with a power supply and a grid electrode G of the fourth field effect transistor, a source electrode S of the third field effect transistor is grounded, a drain electrode D of the fourth field effect transistor is connected with the power supply, a source electrode S of the fourth field effect transistor is grounded, and a drain electrode D of the fourth field effect transistor is connected with the source electrode S of the fourth field effect transistor through a resistor with a preset resistance value;

and a drain electrode D of a fourth field effect transistor of the second control circuit and a source electrode S of the fourth field effect transistor are connected with the first port group, and a drain electrode D of the fourth field effect transistor of the fourth control circuit and a source electrode S of the fourth field effect transistor are connected with the second port group.

8. The transition device defined in claim 1, further comprising:

the reset circuit is connected with the conversion chip and is used for resetting the target signal interfaces;

the reset circuit corresponding to any one of the target signal interfaces comprises two Schmitt triggers which are connected in series.

9. The transition device defined in claim 1, further comprising:

the power supply chip is connected with a power supply of the case where the conversion equipment is located and used for converting the power supply into at least one type of power supply with a preset voltage value;

and the power supply chip is started when the power of the external module accessed to the target signal interface is greater than a preset threshold value, otherwise, the power supply chip refuses to be started.

10. A communication system, comprising:

the conversion apparatus of any one of claims 1 to 9;

an external device connected to the conversion device;

the conversion equipment is used for detecting the interface type of the external module and providing a signal interface matched with the interface type.

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