CN116994522A

CN116994522A - Display panel and control method thereof

Info

Publication number: CN116994522A
Application number: CN202311069548.7A
Authority: CN
Inventors: 王玉青; 孙志松; 王宁波; 许骥
Original assignee: Vicino Technology Co ltd
Current assignee: Vicino Technology Co ltd
Priority date: 2023-08-23
Filing date: 2023-08-23
Publication date: 2023-11-03

Abstract

The embodiment of the invention discloses a display panel and a control method thereof, wherein the control method comprises the following steps: in the process of switching the refresh frequency of the first display partition, a plurality of transition frames are arranged, the refresh frequency of the first display partition in the plurality of transition frames is between the refresh frequency before switching and the refresh frequency after switching of the first display partition, so that the display brightness of the boundary line position in the frequency switching process is slowly changed, and the problem that abnormal boundary line display is caused by overlarge brightness change in the process of switching display pictures with different refresh frequencies is avoided. And/or in the process of switching the refresh frequency of the first display partition, setting the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition to be different in a plurality of transition frames so as to balance the brightness difference of the boundary line between the first display partition and the second display partition under the plurality of transition frames, thereby improving the problem of abnormal boundary display.

Description

Display panel and control method thereof

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a control method thereof.

Background

With the development of display technology, the requirements of display quality of display panels are increasing.

At present, the existing display panel has the phenomenon of uneven display brightness, presents a visual effect of uneven display, and seriously reduces the display quality.

Disclosure of Invention

The embodiment of the invention provides a display panel and a control method thereof, which are used for improving the display quality.

According to an aspect of the present invention, there is provided a control method of a display panel including at least two display sections including a first display section and a second display section adjacent to each other and having different refresh frequencies, the display panel including:

a plurality of pixel circuits arranged in an array;

the control method of the display panel comprises the following steps:

setting a plurality of transition frames in the process of switching the refresh frequency of the first display partition, wherein the refresh frequency of the first display partition in the transition frames is between the refresh frequency of the first display partition before switching and the refresh frequency after switching; and/or in the transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

Optionally, the refresh frequency of the first display partition in the plurality of transition frames gradually increases or gradually decreases, and is between the refresh frequency of the first display partition before switching and the refresh frequency after switching;

Optionally, the display panel further includes:

at least one driving circuit including a scanning circuit including a multi-stage shift unit, a gate module, and a gate signal line;

the plurality of transition frames includes a first type refresh frame and a second type refresh frame;

the gating module responds to the signal on the gating signal line, does not enable the shifting unit to output a scanning signal to the pixel circuit of the first display partition when in a first type refreshing frame, and enables the shifting unit to output the scanning signal to the pixel circuit of the first display partition when in a second type refreshing frame;

in the process of switching the refresh frequency of the first display partition, a first type refresh frame is inserted among a plurality of second type refresh frames, and the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased or gradually decreased; and/or in at least two transition frames, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different;

optionally, in at least two refresh frames of the first type, the row positions of the pixel circuits corresponding to the boundaries of the first display partition adjacent to the second display partition are different;

optionally, in a plurality of first type refresh frames between two adjacent second type refresh frames, row positions of pixel circuits corresponding to adjacent boundaries of the first display partition and the second display partition are the same or different;

Optionally, when the refresh frequency before the switching of the first display partition is greater than the refresh frequency after the switching, the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased in the process of switching the refresh frequency of the first display partition; the refresh frequency of the first display partition gradually decreases;

and/or when the refresh frequency before the first display partition is switched is smaller than the refresh frequency after the first display partition is switched, gradually reducing the number of first type refresh frames inserted between two adjacent second type refresh frames in the process of switching the refresh frequency of the first display partition; the refresh frequency of the first display partition is gradually increased;

optionally, in at least two transition frames, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition change in a line number increasing manner or a line number decreasing manner, or change in a line number increasing and then decreasing manner, or change in a line number decreasing and then increasing manner, or change randomly;

optionally, in any two transition frames, the variation of the line position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition is less than or equal to 20 lines;

Optionally, in the process of switching the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition changes according to the fixed row number each time;

optionally, in the process of switching the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition is changed along with the change of the refresh frequency of the first display partition according to the fixed row number.

Optionally, the strobe module is responsive to the signal on the strobe signal line to cause the shift unit to output the scan signal to the pixel circuit of the second display partition, and not cause the shift unit to output the scan signal to the pixel circuit of the first display partition, in the first type refresh frame; when the second type refreshing frame is used, the shifting unit is enabled to output scanning signals to the pixel circuits of the first display partition and the second display partition;

in the process of switching the refresh frequency of the first display partition, a first type refresh frame is inserted among a plurality of second type refresh frames, and the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased or gradually decreased; and/or in at least two refresh frames of the first type, the row positions of the pixel circuits corresponding to the boundaries of the first display partition adjacent to the second display partition are different.

Optionally, in the process of switching the refresh frequency of the first display partition, in the first type refresh frame, the signal on the gate signal line is the pulse width of the self active level, which is smaller than the pulse width of the signal on the gate signal line in the second type refresh frame;

optionally, in the process of switching the refresh frequency of the first display partition, in at least two refresh frames of the first type, the transition time of the signal on the strobe signal line in the refresh frame of the first type is changed; the jump time of the signal on the gating signal line in the first type refreshing frame corresponds to the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition;

optionally, in the process of switching the refresh frequency of the first display partition, in at least two refresh frames of the first type, the transition time of the signal on the strobe signal line in the refresh frame of the first type changes in an increasing manner or in a decreasing manner, or changes in a manner of increasing first and then decreasing, or changes in a manner of decreasing first and then increasing, or changes randomly;

optionally, in any two first-type refresh frames, the variation of the transition time of the signal on the strobe signal line in the first-type refresh frames is less than or equal to 20 rows of pixel circuit scanning time;

Optionally, in the process of switching the refresh frequency of the first display partition, a transition time of the signal on the gate signal line in the first type refresh frame varies with a change of the refresh frequency of the first display partition.

Optionally, the display panel further includes a third display partition, the first display partition, the second display partition and the third display partition are sequentially adjacent, and refresh frequencies of two adjacent display partitions in the first display partition, the second display partition and the third display partition are different;

in the process of switching the refresh frequency of the third display partition, the refresh frequency of the third display partition in the plurality of transition frames is between the refresh frequency of the third display partition before switching and the refresh frequency after switching; and/or in the plurality of transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the third display partition and the second display partition are different;

the display panel further includes:

the refresh frequency of the first display partition is the same as that of the third display partition, and the refresh frequency of the first display partition is smaller than that of the second display partition, and the display driving method further comprises the following steps:

The gating module responds to the signals on the gating signal lines, and enables the shifting unit to output scanning signals to the pixel circuits of the second display partition when the first type refreshing frame is performed, and does not enable the shifting unit to output the scanning signals to the pixel circuits of the first display partition and the third display partition; when the second type refreshing frame is used, the shifting unit is enabled to output scanning signals to pixel circuits of the first display partition, the second display partition and the third display partition;

or the refresh frequency of the first display partition and the refresh frequency of the third display partition are the same, and the refresh frequency of the first display partition is greater than the refresh frequency of the second display partition, and the display driving method further comprises:

the gating module responds to the signals on the gating signal lines, and does not enable the shifting unit to output scanning signals to the pixel circuits of the second display partition when the first type refreshing frame is performed, so that the shifting unit outputs the scanning signals to the pixel circuits of the first display partition and the third display partition; and in the second type refreshing frame, enabling the shifting unit to output scanning signals to pixel circuits of the first display partition, the second display partition and the third display partition.

Optionally, before the refresh frequencies of the first display partition and the third display partition are switched, the first display partition corresponds to the 1 st to W th row of pixel circuits, the second display partition corresponds to the w+1 th to J th row of pixel circuits, the third display partition corresponds to the j+1 th to Z th row of pixel circuits, and W, J, Z are all positive integers which are larger than 1 and are mutually different; the gating module responds to signals on the gating signal lines in the process of switching the refreshing frequencies of the first display partition and the third display partition;

When at least one first type refreshing frame is performed, the shifting unit is not enabled to output scanning signals to the pixel circuits of the 1 st to W+P+n rows and the pixel circuits of the J+P+n to 1 st to Z rows, and is enabled to output scanning signals to the pixel circuits of the W+P+n to 1 st to J+P+n rows;

when the second type refreshing frame is used, the shifting unit is enabled to output scanning signals to the pixel circuits of the 1 st to Z th rows; wherein P is a positive integer, and n is a positive integer or a negative integer.

Optionally, the gating module includes a plurality of gating units, each stage of shifting unit is connected with the pixel circuits of the corresponding row through the gating unit, and control ends of the plurality of gating units are connected with the gating signal lines;

optionally, when the first type refresh frame is used, and when the shift unit corresponding to the pixel circuit of the second display partition outputs the scanning signal, the signal on the gating signal line is the self effective level, and the gating unit is controlled to be conducted so as to control the shift unit to output the scanning signal to a part of the pixel circuits of the second display area;

when the second type refreshing frame is generated, when the shifting units corresponding to the pixel circuits of the first display partition and the second display partition output scanning signals, the signals on the gating signal lines jump to the self effective level, and the gating units are controlled to be conducted so as to control the shifting units to output the scanning signals to the pixel circuits of the first display partition and the second display partition.

Optionally, the display panel further includes: at least one driving circuit, the driving circuit includes scanning circuit, at least two clock signal lines, gating module and gating signal line, the scanning circuit includes multistage shift unit;

the control method of the display panel further comprises the following steps:

the gating module responds to signals on the gating signal lines and controls the shifting units to output scanning signals to corresponding pixel circuits so as to realize different refresh frequencies corresponding to at least two display partitions; the transition edges of the signal on the strobe signal line are aligned in time with the transition edges of the clock signal on one of the at least two clock signal lines, or differ by less than or equal to 2 crystal oscillator periods, wherein the crystal oscillator is disposed in a clock circuit for generating the clock signal.

Optionally, the clock signal on one of the at least two clock signal lines is used as an effective clock signal of a corresponding shift unit, and the transition time when the scanning signal output by the shift unit transitions to the effective level is determined by the corresponding effective clock signal, and the effective clock signals corresponding to the adjacent two shift units are clock signals on different clock signal lines;

optionally, the time when the signal on the gating signal line jumps to the self effective level is the same as the time when the effective clock signal of the shift unit corresponding to the pixel circuit to be refreshed on the first row jumps to the self effective level;

Optionally, the shift unit includes a first output transistor, the first output transistor is connected between a carry signal output end of the shift unit and a first clock signal end, and in the adjacent two-stage shift units, the carry signal output end of the previous-stage shift unit is electrically connected with the input end of the next-stage shift unit; in the adjacent two-stage shifting units, the first clock signal end of the previous-stage shifting unit and the first clock signal end of the next-stage shifting unit are electrically connected to different clock signal lines, and the clock signal on the clock signal line electrically connected with the first clock signal end of the shifting unit is used as an effective clock signal.

Optionally, the at least two clock signal lines include a first clock signal line and a second clock signal line; the clock signals on the first clock signal line and the second clock signal line have the same frequency and opposite phases;

when the shifting unit corresponding to the pixel circuit to be refreshed in the first row is an odd-level shifting unit, the jump edge of the signal on the gating signal line is aligned with the jump edge of the clock signal on the second clock signal line;

and/or when the shift unit corresponding to the pixel circuit to be refreshed in the first row is the even-numbered stage shift unit, the jump edge of the signal on the gating signal line is aligned with the jump edge of the clock signal on the first clock signal line;

Optionally, the at least one driving circuit includes a first driving circuit, the R rows of pixel circuits correspond to a same shift unit in the first driving circuit, and R is an integer greater than or equal to 2;

and/or, the at least one driving circuit comprises a second driving circuit, one row of pixel circuits corresponds to one shifting unit in the second driving circuit, and different rows of pixel circuits correspond to different shifting units in the second driving circuit;

and/or, the at least one driving circuit comprises a third driving circuit, the K rows of pixel circuits correspond to the same shifting unit in the third driving circuit, and K is an integer greater than or equal to 2.

Optionally, the pixel circuit includes a driving module, a data writing module and a threshold compensation module, the data writing module is connected between the data line and a first end of the driving module, a control end of the data writing module is electrically connected with the second driving circuit, the threshold compensation module is connected between a second end of the driving module and the control end, and a control end of the threshold compensation module is electrically connected with the first driving circuit;

optionally, the pixel circuit further includes a first initialization module, the first initialization module is connected between the first initialization signal line and the control end of the driving module, and the control end of the first initialization module is electrically connected with the third driving circuit;

Optionally, the data writing module comprises a P-type transistor, the threshold compensation module comprises an N-type transistor, and the first initialization module comprises an N-type transistor;

optionally, in the process of switching the refresh frequency of the first display partition, in the plurality of transition frames, the change amount of the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition is an integer multiple of R rows.

According to another aspect of the present invention, there is provided a control method of a display panel including at least two display partitions including a first display partition and a second display partition adjacent to each other and having different refresh frequencies; the display panel includes: a plurality of pixel circuits arranged in an array; the driving circuit comprises a scanning circuit, at least two clock signal lines, a gating module and a gating signal line, wherein the scanning circuit comprises a multistage shift unit, and the scanning circuit is connected with the at least two clock signal lines;

the control method of the display panel comprises the following steps:

the gating module responds to signals on the gating signal lines, so that the shifting unit outputs scanning signals to the corresponding pixel circuits to realize different refresh frequencies corresponding to at least two display partitions; the transition edges of the signal on the strobe signal line are aligned in time with the transition edges of the clock signal on one of the at least two clock signal lines, or differ by less than or equal to 2 crystal oscillator periods, wherein the crystal oscillator is disposed in a clock circuit for generating the clock signal.

the signal on the gating signal line jumps to the jump time of the self effective level, which is the same as the jump time of the effective clock signal of the shifting unit corresponding to the pixel circuit which needs to be refreshed in the first line;

optionally, the shift unit includes a first output transistor, the first output transistor is connected between a carry signal output end of the shift unit and a first clock signal end, and in the adjacent two-stage shift units, the carry signal output end of the previous-stage shift unit is electrically connected with the input end of the next-stage shift unit; in the adjacent two-stage shifting units, a first clock signal end of a shifting unit of a previous stage and a first clock signal end of a shifting unit of a next stage are electrically connected to different clock signal lines, and clock signals on the clock signal lines electrically connected with the first clock signal ends of the shifting units are used as effective clock signals;

Optionally, the shift unit is controlled to output a scan signal to the pixel circuits of the second display area in the first type refresh frame, and the shift unit is controlled to output a scan signal to the pixel circuits of the first display area and the second display area in the second type refresh frame.

Optionally, the at least two clock signal lines include a first clock signal line and a second clock signal line; the first clock signal line and the second clock signal line have the same frequency and opposite phases;

when the shifting unit corresponding to the pixel circuit to be refreshed in the first row is an odd-level shifting unit, the jump edge of the signal on the gating signal line is aligned with the jump edge of the clock signal on the first clock signal line;

and/or when the shift unit corresponding to the pixel circuit to be refreshed in the first row is the even-numbered stage shift unit, the jump edge of the signal on the gating signal line is aligned with the jump edge of the clock signal on the second clock signal line.

According to another aspect of the present invention, there is provided a display panel controlled by the control method of the display panel provided by any of the embodiments of the present invention.

According to the technical scheme provided by the embodiment of the invention, the plurality of transition frames are arranged in the process of switching the refresh frequency of the first display partition, and the refresh frequency of the first display partition in the plurality of transition frames is between the refresh frequency before switching and the refresh frequency after switching of the first display partition, so that the display brightness of the boundary line position in the frequency switching process is slowly changed, and the problem that abnormal boundary line display is caused by overlarge brightness change in the process of switching display pictures with different refresh frequencies is avoided. And/or in the process of switching the refresh frequency of the first display partition, in the plurality of transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different, for example, the positions are changed along with time change, so that the brightness difference of the boundary between the first display partition and the second display partition under the plurality of transition frames is balanced, and the problem of abnormal boundary display is solved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 3 is a flowchart of a control method of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

Fig. 7 is a schematic timing diagram of a strobe signal on a strobe signal line in a time domain according to an embodiment of the present invention;

fig. 8 is a schematic timing diagram of a strobe signal on a strobe signal line in a time domain according to another embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display panel corresponding to a display panel airspace adjustment method according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a driving timing sequence of a scan signal in a frequency switching process according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a driving timing of a scan signal in a frequency switching process according to another embodiment of the present invention;

FIG. 12 is a flowchart of another control method of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a shift unit according to an embodiment of the present invention;

fig. 14 is a schematic diagram of a driving timing of a shift unit according to the present embodiment;

FIG. 15 is a schematic diagram of another shift unit according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a driving timing of another shift unit according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 19 is a schematic diagram showing a driving timing of another shift unit according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of another display panel according to an embodiment of the invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device includes a display panel 11 and a display driving module 300, and the display driving module 300 may be a driving chip. The display panel 11 may include a display area AA, which may include a plurality of pixel circuits PX arranged in an array, and a non-display area NAA. The display panel 11 may further include a plurality of scan lines GL1 and a driving circuit 12, the plurality of scan lines GL1 extending along the X direction and being sequentially arranged along the Y direction, each of the scan lines GL1 being connected to a corresponding row of pixel circuits PX. The driving circuit 12 is connected to the corresponding scanning line GL1, and the driving circuit 12 is located in the non-display area NAA. The display panel 11 further includes a plurality of data lines DL extending in the Y direction and arranged in the X direction, and each data line DL is connected to a corresponding column of pixel circuits PX. The X-direction (which may be the row direction) and the Y-direction (which may be the column direction) intersect, for example, vertically.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 1 and 2, a display area AA of a display panel 11 provided in this embodiment includes at least two display partitions, for example, a first display partition AA1 and a second display partition AA2 that are adjacent to each other, and refresh frequencies corresponding to the first display partition AA1 and the second display partition AA2 are different. For example, the first display partition AA1 corresponds to a low refresh rate and the second display partition AA2 corresponds to a high refresh rate; alternatively, the first display partition AA1 corresponds to a high refresh rate and the second display partition AA2 corresponds to a low refresh rate. The first display area AA1 and the second display area AA2 may be arranged in the Y direction.

Fig. 3 is a flowchart of a control method of a display panel according to an embodiment of the present invention, and referring to fig. 1 to fig. 3, the control method of a display panel according to the embodiment includes:

s120, setting a plurality of transition frames in the process of switching the refresh frequency of the first display partition, wherein the refresh frequency of the first display partition in the transition frames is between the refresh frequency of the first display partition before switching and the refresh frequency after switching; and/or in the transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

The refresh frequency at which different display sections are switched by the display panel 11 during display is not necessarily the same. The refresh rate of the first display partition AA1 in the plurality of transition frames may be greater than the smaller of the refresh rate of the first display partition AA1 before switching and the refresh rate after switching and less than the larger of the refresh rate of the first display partition AA1 before switching and the refresh rate after switching.

Taking the example that the display panel 11 shown in fig. 2 includes the first display area AA1 and the second display area AA2, for example, the refresh frequency before the switching of the first display area AA1 is 60Hz, and the refresh frequency to be switched of the first display area AA1 is 30Hz, then a transition frame with the refresh frequency of 40Hz may be inserted in the refresh frequency switching process of the first display area AA 1. In other words, in the refresh rate switching process of the first display area AA1, the refresh rate of the first display area AA1 may be switched to 40Hz and then switched from 40Hz to 30Hz, so as to reduce the brightness difference every time the refresh rate is switched. Compared with a mode of directly switching from the current refresh frequency (60 Hz) to the target refresh frequency (30 Hz), the scheme adopts a mode of inserting transition frames to gradually transition the refresh frequency of the first display partition to the target refresh frequency to be switched, so that the display brightness of the boundary line position in the frequency switching process is slowly changed, and the problem of abnormal boundary line display caused by overlarge brightness change in the process of switching display pictures with different refresh frequencies is avoided.

In an embodiment, the number of transition frames may be set to be greater than 1, and the refresh frequency of the sequentially inserted transition frames is sequentially increased or decreased during the refresh frequency switching process of the first display area AA1, so as to improve the brightness difference during the refresh frequency switching process. The number of transition frames may be determined based on the difference between the refresh frequencies before and after switching of the display partition. If the difference between the refresh frequencies before and after switching is too large, the gradient of the transition frame can be reduced, thereby increasing the number of transition frames; if the difference between the refresh frequencies before and after switching is small, the gradient of the transition frame can be appropriately increased, thereby reducing the number of transition frames. Here, the gradient of a transition frame characterizes the difference in refresh frequency between two adjacent transition frames.

Optionally, in the plurality of transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed. That is, in the plurality of transition frames, the positions of the pixel circuits corresponding to the boundaries where the first display area AA1 and the second display area AA2 are adjacent are different. That is, the position of the boundary line between the first display area AA1 and the second display area AA2 is adjustable. Illustratively, in the refresh frequency switching process of the first display area AA1, in the first transition frame, the adjacent boundary between the first display area AA1 and the second display area AA2 corresponds to the pixel circuit of the Q-th row, and in the second transition frame, the adjacent boundary between the first display area AA1 and the second display area AA2 corresponds to the pixel circuit of the q±q-th row, wherein Q and Q are both positive integers. Similarly, in other transition frames, the number of lines of pixel circuits corresponding to the boundary between the first display area AA1 and the second display area AA2 is different from the positions of the boundary lines in the first transition frame and the second transition frame. The positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed in each transition frame, so that the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed with time in space, and the brightness difference of the boundary lines between the first display area AA1 and the second display area AA2 under a plurality of transition frames is balanced, so that the problem of abnormal boundary line display is improved. In the refresh rate switching process of the first display area AA1, 1 to 255 transition frames may be set, or, the transition frame at each transition refresh rate may be greater than or equal to 1 frame and less than or equal to 255 frames. During the refresh frequency switching of the first display partition AA1, the transition frame may comprise one or more of the following: at least a portion of the frames at the pre-switch frequency, at least a portion of the frames at the post-switch frequency, and transition frames at frequencies between the pre-switch and post-switch frequencies. And switching the refresh frequency of the first display partition AA1 when the refresh frequency switching condition of the first display partition AA1 is met or a refresh frequency switching instruction of the first display partition AA1 is received.

Optionally, in this embodiment, the refresh frequency of the first display partition AA1 in the plurality of transition frames gradually increases or gradually decreases, and is between the refresh frequency before switching and the refresh frequency after switching of the first display partition AA 1. That is, the refresh frequencies corresponding to the transition frames are gradually changed according to the forward gradient or the reverse gradient, so that the first display area AA1 is gradually switched from the current refresh frequency to the refresh frequency to be switched in a stepwise manner, so that the brightness difference caused by the refresh frequency switched each time in the transition frames is regularly changed, and the brightness change at the boundary position is not easily perceived by human eyes.

For example, when the refresh frequency of the first display area AA1 before switching is 1Hz and the refresh frequency of the first display area AA1 after switching is 60Hz, transition frames corresponding to the transition refresh frequencies of 12Hz, 15Hz, 20Hz, 24Hz, 30Hz and 40Hz are sequentially inserted when the refresh frequency of the first display area AA1 is switched from 1Hz to 60Hz, and the brightness of the display screen corresponding to the transition frames at each transition refresh frequency gradually and slowly changes (e.g., increases or decreases), which is beneficial to improving the display problem caused by the brightness difference at the dividing line position when the first display area AA1 is switched from 1Hz to 60 Hz. On the contrary, when the refresh frequency before the switching of the first display area AA1 is 60Hz and the refresh frequency after the switching is 1Hz, when the refresh frequency of the first display area AA1 is switched from 60Hz to 1Hz, transition frames corresponding to the transition refresh frequencies of 40Hz, 30Hz, 24Hz, 20Hz, 15Hz and 12Hz are sequentially inserted, and the brightness of the display picture corresponding to the transition frame under each transition refresh frequency gradually and slowly decreases. The number and gradient of transition refresh frequencies can be set as desired.

With continued reference to fig. 1 and 2, the driving circuit 12 includes a scan circuit 100, a gate module 200, and a gate signal line SE1, wherein the scan circuit 100 includes a multi-stage shift unit 10. The carry signal output CR (IN some embodiments, the output O1 may also be multiplexed) of the stage shift unit 10 is connected to the input IN of the next stage shift unit 10, and the shift unit 10 is configured to output the scan signal step by step according to the first clock signal and/or the second clock signal. Illustratively, among the plurality of cascaded shift units 10, the first clock signal SCK2 accessed by the odd-numbered stage shift unit 10 and the second clock signal SCK1 accessed by the even-numbered stage shift unit 10 are both supplied by the first clock signal line CLK1, and the second clock signal SCK1 accessed by the odd-numbered stage shift unit 10 and the first clock signal SCK2 accessed by the even-numbered stage shift unit 10 are both supplied by the second clock signal line CLK 2. For example, in the adjacent two-stage shift unit 10, the first clock signal terminal CK2 of the shift unit 10 of the present stage is connected to the first clock signal line CLK1, the second clock signal terminal CK1 is connected to the second clock signal line CLK2, the first clock signal terminal CK2 of the shift unit 10 of the next stage is connected to the second clock signal line CLK2, and the second clock signal terminal CK1 is connected to the first clock signal line CLK1 to realize shift output of the scan circuit 100.

Alternatively, the output terminal of the scan circuit 100 is connected to the gate module 200, for example, the gate module 200 includes a plurality of gate units 20, the output terminal O1 of each shift unit 10 is connected to one gate unit 20, and the control terminal of the gate unit 20 is connected to the gate signal line SE1, wherein each gate unit 20 may be connected to the same gate signal line SE1. The output terminal O2 of the gate unit 20 is connected to the scanning line GL1 of the corresponding row, that is, to the pixel circuit PX of the corresponding row. The gating unit 20 is used for gating whether the scanning signal output by the stage shifting unit 10 is transmitted to the corresponding scanning line GL 1. Alternatively, the gating unit 20 may include a logic gate circuit.

Alternatively, the gate unit 20 may include a first transistor having a first terminal connected to the output terminal O1 of the corresponding shift unit 10 and a second transistor having a second terminal connected to a second terminal of the second transistor, the first terminal of the second transistor being connected to a first power signal line (the voltage of which may be an inactive level of the scan signal). The control terminal of the first transistor and the control terminal of the second transistor may be connected to the same gate signal line, and channel types of the first transistor and the second transistor are the same. The control terminal of the first transistor and the control terminal of the second transistor may be connected to different gate signal lines, and channel types of the first transistor and the second transistor are different. The first transistor is turned on, and the second transistor is turned off, so that the scan signal output by the shift unit 10 is transmitted to the corresponding pixel circuit PX. The first transistor is turned off, and the second transistor is turned on, so that the scan signal output by the shift unit 10 cannot be transmitted to the corresponding pixel circuit PX.

Alternatively, the gate unit 20 may include a cascade control switch for controlling whether the carry signal output from the carry signal output terminal of the previous stage shift unit 10 is output to the input terminal of the next stage shift unit 10, thereby disabling the next stage shift unit 10 from generating the scan signal. The cascade control switch may be connected between the carry signal output terminal of the previous stage shift unit 10 and the input terminal of the next stage shift unit 10 of the adjacent two stage shift units 10. The specific structure of the gating unit 20 may be set as needed, and the embodiment of the present invention is not limited thereto.

In this embodiment, the plurality of transition frames includes a first type refresh frame and a second type refresh frame. The gating module 200 is used to turn on or off in response to a signal on the gating signal line SE 1. The display area AA of the display panel 11 includes at least a first display area AA1 and a second display area AA2, and the strobe module 200 is configured to respond to the signal on the strobe signal line SE1, and not to make the shift unit 10 output the scan signal to the pixel circuit PX corresponding to the first display area AA1 in the first type refresh frame. Wherein, not causing the shift unit 10 to output the scan signal to the corresponding pixel circuit PX may include: the shift unit generates a scan signal, which is blocked by the gate module 200 in the off state (e.g., including a logic gate circuit) and cannot be transmitted to the corresponding pixel circuit PX, or the shift unit 10 cannot generate a scan signal under the effect of the gate module 200 in the off state (e.g., including a cascade control switch), and further, no scan signal is transmitted to the corresponding pixel circuit PX.

The strobe block 200 is configured to, in response to a signal on the strobe signal line SE1, cause the shift unit 10 to output a scan signal to the pixel circuit PX corresponding to the first display section AA1 in the second type refresh frame. The gate module 200 is in an on state, which corresponds to an enable state, so that the shift unit 10 generates a scan signal and transmits the scan signal to the pixel circuit PX corresponding to the first display partition AA 1. The pixel circuit PX for causing the shift unit 10 to output the scan signal to the first display section AA1 includes: the scan signal output by the shift unit 10 is directly transmitted to the pixel circuit PX corresponding to the first display partition AA1, or the scan signal output by the shift unit 10 in the earlier stage is passed through the gate module 200 to obtain a final scan signal, and then transmitted to the pixel circuit PX corresponding to the first display partition AA 1.

In this embodiment, in the refresh frequency switching process of the first display area AA1, the first type refresh frame is inserted between the plurality of second type refresh frames, and the number of the first type refresh frames between the adjacent two second type refresh frames is gradually increased or gradually decreased.

The refresh frequency before the switching of the first display partition AA1 is larger than the refresh frequency after the switching, and the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased in the process of switching the refresh frequency of the first display partition AA 1; the refresh frequency of the first display area AA1 gradually decreases. For example, the refresh frequency before the first display area AA1 is switched is 60Hz, and the refresh frequency after the switching is 1Hz, so that transition frames corresponding to the transition refresh frequencies of 40Hz, 30Hz, 24Hz, 20Hz, 15Hz and 12Hz may be sequentially inserted in the refresh frequency switching process of the first display area AA1, and since the first type refresh frame does not refresh the first display area AA1, the number of first type refresh frames in the plurality of transition frames is sequentially increased, so as to reduce the refresh frequency of the first display area AA1, thereby meeting the requirement of the refresh frequency of the first display area AA1 and the second display area AA 2.

Optionally, in at least two transition frames, the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are located at different row positions. In the above transition frames, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be different, or the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be different only in some transition frames of the transition frames.

Optionally, in at least two refresh frames of the first type, the row positions of the pixel circuits corresponding to the boundaries of the first display area AA1 adjacent to the second display area AA2 are different. Optionally, in at least two refresh frames of the second type, the row positions of the pixel circuits corresponding to the boundaries of the first display area AA1 adjacent to the second display area AA2 are different. Optionally, in at least one first type refresh frame and at least one second type refresh frame, the row positions of the pixel circuits corresponding to the boundaries of the first display area AA1 adjacent to the second display area AA2 are different.

Specifically, in at least two transition frames, the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 may be changed in an increasing manner, for example, in a transition frame in which the transition refresh frequency is 40Hz when the refresh frequency of the first display partition AA1 is switched from 60Hz to 1Hz, the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are n+6 lines, in a transition frame in which the transition refresh frequency is 30Hz, the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are n+2 lines, in a transition frame in which the transition refresh frequency is 24Hz, the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are n+4 lines, in a transition frame in which the transition frequency is 20Hz, the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are n+6, and the line positions of the pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are n+2, and the line positions of the pixel circuits corresponding to the adjacent boundary of the first display partition AA2 are n+2.

Alternatively, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be changed in a manner of decreasing the row numbers. For example, when the refresh rate of the first display area AA1 is switched from 60Hz to 1Hz, in a transition frame in which the transition refresh rate is 40Hz, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the nth line, in a transition frame in which the transition refresh rate is 30Hz, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the nth-2 line, in a transition frame in which the transition refresh rate is 24Hz, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the nth-4 line, in a transition frame in which the transition refresh rate is 20Hz, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the nth-6 line, in a transition frame in which the transition refresh rate is 15Hz, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the nth-8 line, and the line positions of the transition frame in which the transition rate is 12Hz, and the line positions of the adjacent boundaries of the first display area AA2 are the first display area and the adjacent to the first display area AA2 are the nth-10 line.

Alternatively, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be changed in such a manner that the line numbers are increased and then decreased, or in such a manner that the line numbers are decreased and then increased. For example, when the refresh rate of the first display area AA1 is switched from 60Hz to 1Hz, in a transition frame in which the transition refresh rate is 40Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth line, in a transition frame in which the transition refresh rate is 30Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-2 line, in a transition frame in which the transition refresh rate is 24Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-4 line, in a transition frame in which the transition refresh rate is 20Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-6 line, in a transition frame in which the transition refresh rate is 15Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-4 line, and the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA2 in the transition frame in which the transition frequency is the first display area AA2 is the adjacent to the nth-12 Hz.

Alternatively, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be randomly changed, and the changing conditions may be specifically set according to actual requirements. For example, when the refresh rate of the first display area AA1 is switched from 60Hz to 1Hz, in a transition frame in which the transition refresh rate is 40Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth line, in a transition frame in which the transition refresh rate is 30Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-2 line, in a transition frame in which the transition refresh rate is 24Hz, the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-6 line, in a transition frame in which the transition refresh rate is 20Hz, in a transition frame in which the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth-4 line, in a transition frame in which the transition refresh rate is 15Hz, in which the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is the nth line, and in which the transition frequency is 12Hz, and in which the line position of the pixel circuit corresponding to the adjacent boundary of the first display area AA2 is the first display area and the adjacent to the second display area AA2 is the nth line.

In some embodiments, in the process of switching the refresh frequency of the first display area AA1, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed according to the fixed number of rows each time. For example, in the process of switching the refresh frequency of the first display area AA1, a plurality of transition frames are set, and under each transition frame, the row positions of the pixel circuits corresponding to the adjacent boundaries of the display areas are all fixedly changed according to 2 rows, or fixedly changed according to a multiple of 2.

Optionally, in the process of switching the refresh frequency of the first display partition AA1, a plurality of transition frames are set, and in the plurality of transition frames, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 are changed, where the refresh frequency of the transition frames is the refresh frequency before switching or the refresh frequency after switching. For example, the refresh frequency before the first display area AA1 is switched is 1Hz, and the refresh frequency after the switching is 60Hz, so when the refresh frequency of the first display area AA1 is switched from 1Hz to 60Hz, a display period of the first display area AA1 may include 120 frames, for example, 119 first type refresh frames and 1 second type refresh frames, and when the refresh frequency of the first display area AA1 is switched, at least part of 120 frames of the last display period with the refresh frequency before the switching is 1Hz is a transition frame, and at least part of the transition frames are in a transition frame, where the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed. And/or, when the refresh frequency of the first display area AA1 is switched from 1Hz to 60Hz, a display period of the first display area AA1 may include 2 frames, for example, corresponding to 1 first type refresh frame and 1 second type refresh frame, and when the refresh frequency of the first display area AA1 is switched, 2 frames of the first display period and 2 frames of the second display period, in which the refresh frequency is switched to 60Hz, are transition frames, and in the plurality of transition frames, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed. And/or at least part of 120 frames of the last display period with the refresh frequency of 1Hz before switching is a transition frame, at least part of 2 frames of the first display period with the refresh frequency of 60Hz after switching is a transition frame, and the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition AA1 and the second display partition AA2 are changed (i.e. different) in a plurality of transition frames.

Optionally, in the process of switching the refresh frequency of the first display partition AA1, a plurality of transition frames are set, the refresh frequency of the first display partition AA1 in the plurality of transition frames is between the refresh frequency before switching and the refresh frequency after switching of the first display partition AA1, the refresh frequency is gradually increased or decreased, and the positions of pixel circuits corresponding to adjacent boundaries of the first display partition AA1 and the second display partition AA2 are fixed.

As an alternative technical solution provided in this embodiment, in the process of switching the refresh frequency of the first display partition AA1, the row position of the pixel circuit corresponding to the adjacent boundary between the first display partition AA1 and the second display partition AA2 changes along with the change of the refresh frequency of the first display partition AA1, for example, changes according to a fixed line number. That is, in the process of switching the refresh frequency of the first display area AA1, the transition refresh frequency of the plurality of transition frames is controlled, and at the same time, the row positions of the pixel circuits corresponding to the adjacent boundaries of the display area are controlled to synchronously change according to the refresh frequency of the transition frames, and each time, the row positions are changed according to the fixed row number or the non-fixed row number.

In this embodiment, the purpose of setting the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 to change according to the fixed number of rows is to ensure the uniformity of the change of the boundary positions of the display areas in the plurality of transition frames, so as to improve the uniformity of the display brightness at the boundary positions, and to be beneficial to improving the color cast problem at the boundary positions.

Alternatively, with continued reference to fig. 2, in another embodiment, the strobe module 200, in response to the signal on the strobe signal line SE1, causes the shift unit 10 to output the scan signal to the pixel circuit of the second display area AA2, and does not cause the shift unit 10 to output the scan signal to the pixel circuit of the first display area AA1, at the time of the first type of refresh frame; in the second type refresh frame, the shift unit 10 is caused to output a scan signal to the pixel circuits of the first display area AA1 and the second display area AA 2. In other words, the second display area AA2 is in the refresh state regardless of the first type refresh frame or the second type refresh frame, and the first display area AA1 is refreshed only in the second type refresh frame, that is, the second display area AA2 is in the high-brush state, the first display area AA1 is in the low-brush state, and the refresh frequency of the first display area AA1 is smaller than the refresh frequency of the second display area AA 2.

Alternatively, in the above technical solutions, the refresh frequency switching may be performed by the second display partition AA2, or the refresh frequency switching may be performed by both the first display partition AA1 and the second display partition AA 2.

Optionally, in any two transition frames, the variation of the line position of the pixel circuit PX corresponding to the adjacent boundary between the first display area AA1 and the second display area AA2 is less than or equal to 20 lines, so as to ensure that the effect that the normal human eye can not subjectively perceive the position variation of the boundary under the premise of improving the abnormal brightness of the time division in the frequency switching, thereby preventing the human eye from perceiving the position variation of the boundary due to the overlarge variation of the boundary position in the process of switching the refresh frequency. Optionally, in any two transition frames, the variation of the row position of the pixel circuit PX corresponding to the adjacent boundary of the first display area AA1 and the second display area AA2 is less than or equal to 10 rows. In the frequency switching process, the position change range of the boundary line cannot be too large or too small, otherwise the effect of improving the brightness abnormality of the boundary line and the visual effect of the human eye on the position change of the boundary line cannot be balanced.

Optionally, in a plurality of refresh frames of the first type (for example, may be partial refresh frames) between two adjacent refresh frames of the second type (for example, may be full refresh frames), the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are the same or different. That is, in the transition frames corresponding to the same refresh frequency, for the inserted first type refresh frames, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be the same, that is, the positions of the boundaries of the display areas are not changed in the first type refresh frames; alternatively, the row positions of the pixel circuits corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 may be different, that is, the positions of the boundary lines of the display areas are changed while the first type refresh frame is inserted in the plurality of first type refresh frames, so as to further improve the abnormal display condition at the boundary line positions.

Of course, in other embodiments, the refresh frequency before the switching of the first display partition AA1 is smaller than the refresh frequency after the switching, and in the process of switching the refresh frequency of the first display partition AA1, the number of first type refresh frames inserted between two adjacent second type refresh frames gradually decreases; the refresh frequency of the first display area AA1 gradually increases. In this embodiment, the specific control method of the display panel is opposite to the control method that the refresh frequency before the switching of the first display area AA1 is greater than the refresh frequency after the switching, and specific reference may be made to the related description in the above embodiment, which is not repeated.

Fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and referring to fig. 4, the pixel circuit includes a driving module, a data writing module and a threshold compensation module, the data writing module is connected between a data line and a first end of the driving module, a control end of the data writing module is electrically connected with a second driving circuit, the threshold compensation module is connected between a second end of the driving module and the control end, and a control end of the threshold compensation module is electrically connected with the first driving circuit. The effective level of the scan signal SN1 output by the first driving circuit may be the on level of the compensation module. The active level of the scan signal SP1 output by the second driving circuit may be the on level of the data writing module.

Optionally, the pixel circuit further includes a first initialization module, where the first initialization module is connected between the first initialization signal line Vref2 and a control terminal of the driving module, and the control terminal of the first initialization module is electrically connected to the third driving circuit. The effective level of the scan signal SN2 output by the third driving circuit may be the on level of the first initialization module.

Specifically, the driving module includes a driving transistor M3, the data writing module includes a data writing transistor M4, the threshold compensation module includes a threshold compensation transistor M5, and the first initialization module includes a third initialization transistor M6.

Optionally, the data writing module comprises a P-type transistor. Optionally, the threshold compensation module comprises an N-type transistor. Optionally, the first initialization module includes an N-type transistor.

Optionally, the pixel circuit further includes a first initialization transistor M1, a second initialization transistor M2, a storage capacitor C, a first light emission control transistor M7, and a second light emission control transistor M8, wherein the first initialization transistor M1 is connected between the second initialization signal line Vref1 and the first pole of the light emitting diode D1, the second initialization transistor M2 is connected between the third initialization signal line Vcom and the first pole S (or the second pole D) of the third transistor M3, the storage capacitor C is connected between the first power line L1 and the gate G of the driving transistor M3, the first light emission control transistor M7 is connected between the first power line L1 and the first pole S of the driving transistor M3, the second light emission control transistor M8 is connected between the second pole D of the driving transistor M3 and the first pole of the light emitting diode D1, and the second pole of the light emitting diode D1 is connected to the second power line L2. Alternatively, the gate of the first initializing transistor M1 and the gate of the second initializing transistor M2 are connected to the fourth driving circuit, and the active level of the scan signal SP2 output by the fourth driving circuit may be the on level, e.g., low level, of the first initializing transistor M1 and the second initializing transistor M2. The gates of the first and second light emission control transistors M7 and M8 may be connected to a fifth driving circuit, and the effective level of the scan signal EM output from the fifth driving circuit may be the on level, e.g., high level, of the first and second light emission control transistors M7 and M8.

Alternatively, the scan line GL1 may be connected to a gate of the data writing transistor M4 in the pixel circuit PX for controlling a switching state of the data writing transistor M4. In the display process of the picture, the scanning signal SP1 is provided to the scanning line GL1 in each row of the pixel circuits PX in a progressive scanning manner, and the data voltage on the data line DL is transmitted to the corresponding pixel circuit PX in the duration of the on pulse of the corresponding scanning signal SP1 (the duration of the active level of the scanning signal SP 1), so as to realize data writing, so as to refresh the sub-pixels in the display area AA.

Optionally, the threshold compensation transistor M5 is an N-type transistor. Optionally, the third initialization transistor M6 is an N-type transistor.

The technical scheme provided by the embodiment is also applicable to panel structures with more than two display areas. Fig. 5 is a schematic structural diagram of another display panel according to the embodiment of the present invention, and referring to fig. 5, based on the above technical solutions, optionally, the display area AA further includes a third display area AA3, where the first display area AA1, the second display area AA2, and the third display area AA3 are sequentially adjacent, and refresh frequencies of two adjacent display areas in the first display area AA1, the second display area AA2, and the third display area AA3 are different.

Optionally, in the process of switching the refresh frequency of the third display partition AA3, setting a plurality of transition frames, where the refresh frequency of the third display partition AA3 in the plurality of transition frames is between the refresh frequency of the third display partition AA3 before switching and the refresh frequency after switching; and/or, in the transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the third display area AA3 and the second display area AA2 are different, for example, are changed. The refresh rate switching process of the third display area AA3 is the same as or similar to the refresh rate switching process of the first display area AA1, and will not be described here.

The pixel circuits corresponding to the adjacent boundaries of the first display area AA1, the second display area AA2 and the third display area AA3 are adjustable, so as to greatly change the area and/or the position of at least one display area, for example, when receiving an operation instruction that a user wants to adjust the window size or the position of the display area. The first, second and third display areas AA1, AA2 and AA3 may be arranged in the Y direction.

Optionally, the refresh rate of the first display area AA1 is less than the refresh rate of the second display area AA2, and the refresh rate of the third display area AA3 is less than the refresh rate of the second display area AA 2. Optionally, the refresh frequency of the first display area AA1 and the third display area AA3 is the same. Namely, the first display area AA1 and the third display area AA3 are low frequency areas, and the second display area AA2 is a high frequency area.

During the refresh frequency switching process of the first display area AA1 and the third display area AA3, the strobe module 200, in response to the signal on the strobe signal line SE1, causes the shift unit 10 to output the scan signal to the pixel circuit PX of the second display area AA2 during the first type refresh frame, and does not cause the shift unit 10 to output the scan signal to the pixel circuits PX of the first display area AA1 and the third display area AA 3; at the time of the second type refresh frame, the shift unit 10 is caused to output the scan signals to the pixel circuits PX of the first, second and third display partitions AA1, AA2 and AA 3.

Fig. 6 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention, which is applicable to the pixel circuit shown in fig. 4, referring to fig. 6, a display period of the pixel circuit PX includes a writing frame and a holding frame, and in the writing frame, the shift unit 10 provides a scan signal SP1 to the pixel circuit PX, and a data voltage is written into the pixel circuit PX; in the holding frame, the shift unit 10 does not supply the scan signal SP1 to the pixel circuit PX, and the data voltage cannot be written to the pixel circuit PX. The refresh frequency can be understood as the number of write frames included per unit time. Illustratively, the refresh frequency is 120Hz and the display panel includes 120 frames within 1s, which 120 frames are all write frames. When the refresh frequency is reduced to 60Hz, 1 holding frame is inserted between two adjacent writing frames, and then 60 writing frames are included in 1s, and the remaining 60 frames are holding frames, so that the refresh frequency is reduced to 60Hz. In the first type refresh frame, the pixel circuit PX of the first display partition AA1 may operate in the hold frame, and the pixel circuit PX of the second display partition AA2 may operate in the write frame. In the second type refresh frame, the pixel circuit PX of the first display partition AA1 may operate in the write frame, and the pixel circuit PX of the second display partition AA2 may operate in the write frame.

Fig. 7 is a schematic time-domain timing diagram of a strobe signal on a strobe signal line according to an embodiment of the present invention, fig. 8 is a schematic time-domain timing diagram of a strobe signal on another strobe signal line according to an embodiment of the present invention, where the timing shown in fig. 7 is a separate timing diagram under each transition frame, and fig. 8 is a sequential timing diagram under a plurality of transition frames. Fig. 7 and 8 illustrate an example in which the active level of the strobe signal on the strobe signal line SE1 is high. Referring to fig. 7 and 8, based on the above technical solution, taking the refresh frequency before switching of the first display area AA1 and the third display area AA3 as an example, the refresh frequency of the second display area AA2 is 120Hz, and the refresh frequency after switching of the first display area AA1 and the third display area AA3 is 1Hz.

Specifically, in the refresh frequency switching process of the first display partition AA1 and the third display partition AA3, at 60Hz, when the second type refresh frame F2 is performed, the signal on the strobe signal line SE1 is at its own active level when scanning the first display partition AA1, the second display partition AA2 and the third display partition AA3, and the strobe unit 20 is controlled to be turned on, so that the shift units 10 corresponding to the pixel circuits PX of the first display partition AA1, the second display partition AA2 and the third display partition AA3 output scanning signals to the pixel circuits PX of the first display partition AA1, the second display partition AA2 and the third display partition AA3, and the pixel circuits PX of the first display partition AA1, the second display partition AA2 and the third display partition AA3 perform data writing. In the first type refresh frame F1, the signal on the strobe signal line SE1 is at its active level during the period corresponding to the second display area AA2 is scanned, and the strobe unit 20 is controlled to be turned on, so that the shift unit 10 corresponding to the pixel circuit PX of the second display area AA2 outputs the scanning signal to the pixel circuit PX of the second display area AA2, and the pixel circuit corresponding to the second display area AA2 performs data writing. The signal on the strobe signal line SE1 is at an inactive level when scanning the time periods corresponding to the first display area AA1 and the third display area AA3, and controls the strobe unit 20 to turn off, so that the shift unit 10 does not output the scanning signal to the corresponding pixel circuits PX of the first display area AA1 and the third display area AA3, and the corresponding pixel circuits PX of the first display area AA1 and the third display area AA3 do not perform data writing. Thus, for the first display partition AA1 and the third display partition AA3, the first type refresh frame is a hold frame and the second type refresh frame is a write frame. For the second display partition AA2, both the second type refresh frame and the first type refresh frame are write frames.

At 60Hz, 1 frame of the first type refresh frame F1 is inserted between two adjacent second type refresh frames F2. For the first display area AA1 and the third display area AA3, the 1-frame second-type refresh frame F2 is a write frame, and the 1-frame first-type refresh frame F1 is a hold frame. For the second display area AA2, both the 1 frame second type refresh frame F2 and the 1 frame first type refresh frame F1 are write frames. The refresh frequency of the three display areas is 60Hz-120Hz-60Hz in sequence.

In the case of 1Hz, 119 frames of refresh frames F1 of the first type are inserted between two adjacent refresh frames F2 of the second type. For the first display area AA1 and the third display area AA3,1 frame of the second type refresh frame F2 is a write frame, and 119 frames of the first type refresh frame F1 are hold frames. For the second display area AA2,1 frame of the second type refresh frame F2 and 119 frames of the first type refresh frame F1 are both write frames.

In the switching process of the refresh frequencies of the first display area AA1 and the third display area AA3, transitional refresh frequencies are set to be corresponding to 40Hz, 30Hz, 24Hz, 20Hz, 15Hz and 12Hz so as to gradually switch the refresh frequencies of the first display area AA1 and the third display area AA3 from 60Hz to 1Hz.

In the transition frame with the transition refresh frequency of 40Hz, 2 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 2 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 40Hz. The refresh frequency of the three display areas is 40Hz-120Hz-40Hz in sequence. Optionally, during the frequency switching process, at 40Hz, the positions of the dividing lines of the first display area AA1 and the second display area AA2 are changed or unchanged for 2 frames of the first type refresh frame F1.

In the transition frame with the transition refresh frequency of 30Hz, 3 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 3 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 30Hz. The refresh frequency of the three display areas is sequentially 30Hz-120Hz-30Hz. Optionally, during the frequency switching process, at least part of the frames in the 3 frames of the first type refresh frame F1 are changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 30Hz.

In the transition frame with the transition refresh frequency of 24Hz, 4 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 4 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 24Hz. The refresh frequency of the three display areas is 24Hz-120Hz-24Hz in sequence. Optionally, during the frequency switching process, at least part of the frames in the 4 frames of the first type refresh frame F1 are changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 24Hz.

In the transition frame with the transition refresh frequency of 20Hz, 5 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 5 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 20Hz. The refresh frequency of the three display areas is sequentially 20Hz-120Hz-20Hz. Optionally, during the frequency switching, at least part of the frames in the 5 frames of the first type refresh frame F1 are changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 20Hz.

In the transition frame with the transition refresh frequency of 15Hz, 7 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 7 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 15Hz. The refresh frequency of the three display areas is sequentially 15Hz-120Hz-15Hz. Optionally, during the frequency switching process, at least part of the 7 frames of the first type refresh frame F1 is changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 15Hz.

In a transition frame with a transition refresh frequency of 12Hz, 9 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of the 9 first-type refresh frames F1, the shift unit 10 is caused to output scanning signals to the pixel circuits PX corresponding to the second display partition AA2, and the shift unit 10 is not caused to output scanning signals to the pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, so that the first display partition AA1 and the third display partition AA3 meet the refresh frequency of 12Hz. The refresh frequency of the three display areas is sequentially 12Hz-120Hz-12Hz. Optionally, during the frequency switching process, at least part of the 9 frames of the first type refresh frame F1 is changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 12Hz.

In the transition frame with the refresh frequency of 1Hz, 119 first-type refresh frames F1 are inserted between two adjacent second-type refresh frames F2, and in the second-type refresh frames F2, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the first display partition AA1, the second display partition AA2 and the third display partition AA3, and in each frame of 119 first-type refresh frames F1, the shift unit 10 is controlled to output scanning signals to pixel circuits PX corresponding to the second display partition AA2, so that the shift unit 10 does not output scanning signals to pixel circuits PX corresponding to the first display partition AA1 and the third display partition AA3, and the first display partition AA1 and the third display partition AA3 are realized to satisfy the refresh frequency of 1Hz. The refresh frequency of the three display areas is sequentially 1Hz-120Hz-1Hz. Optionally, during the frequency switching process, at least part of the 119 frames of the first type refresh frame F1 is changed or unchanged in the position of the boundary between the first display area AA1 and the second display area AA2 at 1Hz.

In the present embodiment, the number of the first-type refresh frames F1 interposed between the adjacent two second-type refresh frames F2 is gradually increased among the plurality of transition frames.

Fig. 9 is a schematic structural diagram of a display panel corresponding to a display panel airspace adjustment method according to an embodiment of the present invention, and referring to fig. 9, optionally, in a switching process of refresh frequencies of a first display partition AA1 and a third display partition AA3, in a corresponding transition frame, a row position of a pixel circuit PX corresponding to a dividing line between adjacent display partitions is adjusted, so that the row positions of pixel circuits PX corresponding to dividing lines between adjacent display partitions in different transition frames are different.

Referring to fig. 5 and 9, before or after the refresh frequency of at least one display partition (e.g., one or more of the first, second, and third display partitions AA1, AA2, and AA 3) is switched, the first display partition AA1 corresponds to the 1 st to W row pixel circuits PX, the second display partition AA2 corresponds to the w+1 th to J row pixel circuits PX, and the third display partition AA3 corresponds to the j+1 th to Z row pixel circuits PX, W, J, Z are positive integers that are greater than 1 and are different from each other. W, J, Z increases in sequence. In the process of switching the refresh frequencies of the first display area AA1 and the third display area AA3, the strobe module 200 does not make the shift unit 10 output the scan signal to the 1 st to w+p×n row pixel circuits PX and the j+p×n+1 st to Z row pixel circuits PX and makes the shift unit 10 output the scan signal to the w+p×n+1 st to j+p×n row pixel circuits PX in response to the signal on the strobe signal line SE1 during the first type refresh frame F1; and when at least one second type refreshing frame is performed, enabling the shifting unit to output scanning signals to the pixel circuits of the 1 st to Z th rows. Wherein P is a positive integer, e.g., a fixed step size, and n is a positive integer or a negative integer; during the switching of the refresh frequencies of the first display area AA1 and the third display area AA3, the values of P x n in at least two refresh frames F1 of the first type are not equal.

For example, before the refresh frequency of the first display area AA1 and the third display area AA3 is switched, the row position of the pixel circuit PX corresponding to the first display area AA1 is 1 to 786H (H represents: row), the row position of the pixel circuit PX corresponding to the second display area AA2 is 787 to 2014H, and the row position of the pixel circuit PX corresponding to the third display area AA3 is the row position after 2014H.

Specifically, in the transition frame with the transition refresh frequency of 40Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 789 to 2012H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 788H (786+2x1=788) pixel circuits PX and 2013 (2015-2*1 =2013) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the transition refresh frequency of 30Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 791 to 2010H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 790H (788+2×1=790) pixel circuits and 2011 (2013-2*1 =2011) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the transition refresh frequency of 24Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 793 to 2008H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 792H (790+2×1=792) pixel circuits PX and 2009 (2011-2*1 =2009) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the transition refresh frequency of 20Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 795 to 2006H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 794H (792+2×1=794) pixel circuits PX and 2007 (2009-2*1 =2007) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the transition refresh frequency of 15Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 797 to 2004H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 796H (794+2×1=796) pixel circuits PX and 2005 (2007-2*1 =2005) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the transition refresh frequency of 12Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 799 to 2002H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 798H (796+2×1=798) pixel circuits PX and 2003 (2005-2*1 =2003) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F1, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

In the transition frame with the refresh frequency of 1Hz, at the time of the first type refresh frame F1, the shift unit 10 is caused to output the scan signal to the 801 to 2000H pixel circuits PX, and the shift unit 10 is not caused to output the scan signal to the 1 st to 800H (798+2×1=800) pixel circuits PX and 2001 (2003-2*1 =2001) to ZH pixel circuits PX (for example, Z may be 2800). In the second type refresh frame F2, the shift unit 10 is caused to output the scanning signal to the 1 st to ZH pixel circuits PX.

For the convenience of understanding the present solution, fig. 10 is a schematic diagram of driving timing sequence of scan signals in the frequency switching process according to the embodiment of the present invention, taking the refresh frequency of 1Hz in fig. 9 as an example, in the second type refresh frame F2, the strobe signal CSP on the strobe signal line SE1 in the second driving circuit is at an active level, for example, a low level, and rows 1 to 2800 all output scan signals SP1 (i.e., SP1-1 to SP 1-2800) to pixel circuits corresponding to the first display area AA1, the second display area AA2, and the third display area AA3, and the pixel circuits PX corresponding to the first display area AA1, the second display area AA2, and the third display area AA3 are all written with the scan signals SP1. At the time of the first type refresh frame F1, the strobe signal CSP1 on the strobe signal line SE1 transitions to an active level at the time tp corresponding to the scan to the 801 th line and transitions to an inactive level, for example, a high level, at the time tp' corresponding to the scan to the 2000 th line, and therefore, the shift unit 10 outputs the scan signal to the pixel circuits PX of 801 to 2000 lines.

Fig. 11 is a schematic diagram of a driving timing sequence of a scan signal in a frequency switching process according to another embodiment of the present invention. Taking the refresh frequency of 1Hz in fig. 9 as an example, in the second refresh frame F2, the strobe signal CSN1 on the strobe signal line SE1 in the first driving circuit is at an active level, for example, a high level, and the rows 1 to 2800 output the scan signals SN1 (i.e., SN1-1 to SN 1-2800) to the pixel circuits PX corresponding to the first display area AA1, the second display area AA2, and the third display area AA3, and the pixel circuits PX corresponding to the first display area AA1, the second display area AA2, and the third display area AA3 are all written with the scan signals SN1. At the time of the first type refresh frame F1, the gate signal CSN1 on the gate signal line SE1 transitions to an active level at the time tn corresponding to the scan to the 801 th row and transitions to an inactive level, for example, a low level, at the time tn' corresponding to the scan to the 2000 th row, and thus the shift unit 10 outputs the scan signal to the 801 to 2000 rows of the pixel circuits PX.

With continued reference to fig. 10 and 11, during the refresh frequency switching of the first display partition AA1, in the first type refresh frame F1, the pulse width TP1 (or TN 1) at which the signal on the gate signal line SE1 is at its own active level is smaller than the pulse width TP2 (or TN 2) at which the signal on the gate signal line SE1 is at its own active level in the second type refresh frame F2. That is, TP1< TP2, TN1< TN2.

Optionally, with continued reference to fig. 10, during the refresh frequency switching of the first display partition AA1, in at least two refresh frames F1 of the first type, the transition time tp (or tn) of the signal CSP1 (or CSN 1) on the strobe signal line SE1 in the refresh frame F1 of the first type is varied. Specifically, the transition time tp (or tn) of the signal on the strobe signal line SE1 in the first type refresh frame F1 corresponds to the row position of the pixel circuit corresponding to the boundary of the first display area AA1 adjacent to the second display area AA 2. The position of the boundary between the first display area AA1 and the second display area AA2 changes, and the transition time tp (or tn) of the signal on the strobe signal line SE1 in the first type refresh frame F1 changes.

As can be seen from fig. 9 to 11, in the refresh frequency switching process of the first display area AA1, the effective clock signal of the shift unit 10 corresponding to the pixel circuit PX at the tp corresponding to the 799 th row at 12Hz transitions to the transition edge of the self-effective level, and the effective clock signal of the shift unit 10 corresponding to the pixel circuit PX at the tp corresponding to the 797 th row at 15Hz transitions to the transition edge of the self-effective level, so that the positions of tp at 12Hz and tp at 15Hz in the respective first type refresh frames F1 are different, which is equivalent to a change. Similarly, tn at 12Hz and tn at 15Hz are different in the respective first type refresh frame F1, which corresponds to a change.

Optionally, in the transition frame with the refresh frequency of 1Hz, in 119 first-type refresh frames F1 between two adjacent second-type refresh frames F2, the transition timings tp (or tn) of the signals on the strobe signal line SE1 in the 119 first-type refresh frames F1 are all changed, that is, the positions of tp (or tn) at 1Hz in the first-type refresh frames F1 are all different.

During the switching of the refresh frequency of the first display partition AA1, in at least two refresh frames F1 of the first type, the transition time tp (or tn) of the signal on the strobe signal line SE1 in the refresh frame F1 of the first type changes in an increasing manner or in a decreasing manner, or in a first increasing and then decreasing manner, or in a first decreasing and then increasing manner, or in a random manner. The transition time tp (or tn) is the same or similar to the change of the row position of the pixel circuit PX corresponding to the boundary between the display sections.

In any two first-type refresh frames F1, the amount of change in the transition timing tp (or tn) of the signal on the strobe signal line SE1 in the first-type refresh frame F1 is less than or equal to 20 rows of pixel circuit scan times.

Optionally, during the refresh frequency switching of the first display area AA1, the transition time tp (or tn) of the signal on the strobe signal line SE1 in the first type refresh frame varies with the refresh frequency of the first display area AA1, for example, the transition time tp (or tn) varies with the refresh frequency of the first display area AA1 at fixed time intervals. The fixed time interval may be equal to an integer multiple of the scanning time of the R-row pixel circuits PX.

In summary, in the process of switching the first display area AA1 and the third display area AA3 from 60Hz to 1Hz, the row positions of the pixel circuits PX corresponding to the adjacent boundaries of the first display area AA1 and the second display area AA2 are changed in a manner of increasing the row numbers, and the row positions of the pixel circuits PX corresponding to the adjacent boundaries of the third display area AA3 and the second display area AA2 are changed in a manner of decreasing the row numbers, where the number of rows changed each time is p×n. Here, P may be determined by a driving architecture of the scanning circuit 100, for example, if the driving architecture of the scanning circuit 100 is that one shift unit 10 drives two rows of pixel circuits PX simultaneously, then p=2; if the driving architecture of the scanning circuit 100 is that one shift unit 10 drives one row of pixel circuits PX, p=1.

Of course, in other embodiments, the change condition of the row position of the pixel circuit PX corresponding to the boundary position between the adjacent display partitions may also be changed in other manners, and the description of the display area AA including the first display partition AA1 and the second display partition AA2 may be referred to, which is not repeated.

Fig. 12 is a flowchart of another method for controlling a display panel according to an embodiment of the present invention, and referring to fig. 12, the method for controlling a display panel includes:

S210, enabling the shifting unit to output scanning signals to corresponding pixel circuits in response to signals on the gating signal lines by the gating module so as to realize different refresh frequencies corresponding to at least two display partitions; the transition edges of the signal on the strobe signal line are aligned in time with the transition edges of the clock signal on one of the at least two clock signal lines, or differ by less than or equal to 2 crystal oscillator periods, wherein the crystal oscillator is disposed in a clock circuit for generating the clock signal.

Specifically, the turn-on timing of the gating module 200 is associated with the occurrence timing of the turn-on pulse of the scan signal outputted from the shift unit 10, and thus, the alignment of the transition edges of the signal on the gating signal line SE1, which controls the turn-on of the gating module 20, also affects the display effect of the display partition boundary position. In this embodiment, the alignment of the transition edge of the signal on the strobe signal line SE1 is associated with the clock signal (at least including the first clock signal and the second clock signal) corresponding to the current stage shift unit 10, so that the transition edge of the signal on the strobe signal line SE1 is controlled to be aligned with the transition edge of one of the at least two clock signals in time, or the phase difference is less than or equal to 2 crystal oscillator periods, so as to realize the precise time sequence control of different display partitions, and thus, the brightness abnormality phenomenon of the boundary line of each display partition during the frequency cutting is improved.

Optionally, the transition edge of the signal on the strobe signal line SE1, which transitions to its active level, is aligned in time with the transition edge of the clock signal on one of the at least two clock signal lines, which transitions to its active level, or differs by less than or equal to 2 crystal oscillator periods.

Optionally, the clock signal on one of the at least two clock signal lines is used as an effective clock signal corresponding to the shift unit 10, and the transition time when the scan signal output by the shift unit 10 transitions to its own effective level is determined by the corresponding effective clock signal, where the effective clock signals corresponding to the adjacent two shift units 10 are clock signals on different clock signal lines. The transition time when the scan signal outputted by the shift unit 10 transitions to its own active level is determined by the transition time when the corresponding active clock signal transitions to its own active level.

Fig. 13 is a schematic structural diagram of a shift unit according to an embodiment of the present invention, optionally, the shift unit includes a first output transistor M15, where the first output transistor M15 is connected between a carry signal output end CR of the shift unit and a first clock signal end CK2 (for transmitting a first clock signal SCK 2), and IN two adjacent shift units 10, the carry signal output end CR of a previous shift unit 10 is electrically connected to an input end IN (SINP IN fig. 13) of a next shift unit 10; in the adjacent two-stage shift units 10, the first clock signal terminal CK2 of the previous-stage shift unit 10 and the first clock signal terminal CK2 of the next-stage shift unit 10 are electrically connected to different clock signal lines, and the clock signal on the clock signal line to which the first clock signal terminal CK2 of the shift unit 10 is electrically connected serves as an effective clock signal.

When the first output transistor M15 is turned on, the valid pulse of the valid clock signal connected to the first clock signal terminal CK2 may be output to the carry signal output terminal CR (which may be multiplexed into the output terminal O1), which corresponds to the scan signal.

Fig. 13 specifically illustrates a case where the shift unit 10 is a PScan circuit, and referring to fig. 13, the shift unit 10 may include a first input transistor M9, a second input transistor M10, a third input transistor M11, a first output control transistor M12, a second output control transistor M13, a first output transistor M15, a second output transistor M14, a protection transistor M16, a first capacitor C1, and a second capacitor C2. The first pole of the first input transistor M9 is connected to the first potential signal line VGH, the second pole of the first input transistor M9 is connected to the second pole of the third input transistor M11 through the second input transistor M10, the first pole of the third input transistor M11 is connected to the input terminal SINP of the shift unit 10, the gate of the third input transistor M11 is connected to the second clock signal terminal CK1, and the gate of the second input transistor M10 is connected to the first clock signal terminal CK 2. A first pole of the first output control transistor M12 is connected to the second clock signal terminal CK1, a second pole of the first output control transistor M12 is connected to the gate of the first input transistor M9, and a gate of the first output control transistor M12 is connected to the second pole of the third input transistor M11; the first pole of the second output control transistor M13 is connected to the second potential signal line VGL, the second pole of the second output control transistor M13 is connected to the gate of the second output transistor M14, and the gate of the second output control transistor M13 is connected to the second clock signal terminal CK 1. The first pole of the first output transistor M15 is connected to the first clock signal terminal CK2, the gate of the first output transistor M15 is connected to the second pole of the third output transistor M11 via the protection transistor M16, and the second pole of the second output transistor M14 and the second pole of the first output transistor M15 are both connected to the output terminal O1 (which may be multiplexed as the carry signal output terminal CR) of the shift unit 10. A first pole of the second output transistor M14 may be connected to the first potential signal line VGH, and a gate of the protection transistor M16 may be connected to the second potential signal line VGL. The first capacitor C1 is connected between the gate of the first output transistor M15 and the output terminal O1 (which may be multiplexed as the carry signal output terminal CR) of the shift unit 10, and the second capacitor C2 is connected to the gate of the second output transistor M14 and the first potential signal line VGH. The structure, operation and principle of the circuit of fig. 13 are the same as or similar to those of the related art, and will not be repeated here.

Fig. 14 is a schematic diagram of a driving timing sequence of a shift unit according to the present embodiment, and with reference to fig. 13 and 14, at least two clock signal lines include a first clock signal line CLK1 and a second clock signal line CLK2, and the clock signals transmitted on the first clock signal line CLK1 and the second clock signal line CLK2 have the same frequency and opposite phases.

Taking the clock signal on the second clock signal line CLK2 as an example of the active clock signal SCK2 of the shift unit 10 as shown in fig. 13 and 14, the transition time when the scan signal SP1 outputted from the shift unit 10 transitions to its active level (e.g., low level) is determined by the corresponding active clock signal SCK2, that is, the transition time when the scan signal SP1 transitions to the active level is the same as the transition time when the first clock signal SCK2, or differs by less than or equal to 2 crystal oscillator periods.

With continued reference to fig. 14, the transition timing (e.g., tp) at which the signal (e.g., CSP 1) on the strobe signal line SE1 transitions to its own active level is the same as the transition timing at which the active clock signal SCK2 of the shift unit 10 corresponding to the pixel circuit to be refreshed in the first line (e.g., the pixel circuit PX to be refreshed in the first line of the entire display panel, or the first line pixel circuit PX of the display partition to be refreshed adjacent to the display partition not to be refreshed in the front, e.g., the pixel circuit PX of the 801 st line at 1Hz in fig. 9 and 10) transitions to its own active level. In other words, taking the clock signal on the second clock signal line CLK2 as the active clock signal of the odd-numbered stage shift unit 10 as an example, the transition timing of the active level of the scan signal outputted by the shift unit 10 corresponding to the pixel circuit to be refreshed in the first line is determined by the transition timing of the active clock signal of the shift unit 10 to its own active level, for example, the transition timing of the active level of the scan signal is determined by the transition timing of the first clock signal SCK2, the clock signal is an input signal, the scan signal is an output signal, and there is a certain delay in the output signal response to the input signal, so that the transition timing of the active clock signal (the first clock signal SCK 2) of the shift unit 10 corresponding to the pixel circuit to be refreshed in the first line transitions to its own active level (e.g., low level) is determined by the transition timing of the signal on the gate signal line SE1, and compared with the transition timing of the scan signal outputted by the output terminal O1 as the timing of the signal on the gate signal line SE 1.

In the first type refresh frame F1, the first row pixel circuit PX of the second display partition AA2 may be regarded as a pixel circuit PX of which the first row needs to be refreshed, for example, the 801 th row pixel circuit PX at 1Hz in fig. 9 and 10. In the second type refresh frame F2, the first row pixel circuit PX of the first display partition AA1 may be regarded as a pixel circuit PX of which the first row needs to be refreshed, for example, a1 st row pixel circuit PX at 1Hz as in fig. 9 and 10. If the side of the first display partition AA1 far from the second display partition AA2 is further provided with other display partitions, the refresh regions of the refresh frames of various types and the first row refresh position of the display panel can be set as required, which is not limited by the present invention. The more the number of display partitions is, the more types of refresh frames are displayed in the same refresh frame, and the more the transition edges that the signal on the strobe signal line SE1 transitions to the self-active level are, the more the signal on the strobe signal line SE1 transitions to the self-active level, so the setting mode of other transition edges that the signal on the strobe signal line SE1 transitions to the self-active level is the same as or similar to the setting mode that the signal on the strobe signal line SE1 transitions to the self-active level for the first time.

In other embodiments, because the period, precision, and other parameters of the clock signal are related to the crystal oscillator of the clock circuit, the transition time when the signal on the strobe signal line SE1 transitions to its own active level may differ by 1-2 crystal oscillator periods from the transition time when the active clock signal of the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row transitions to its own active level, so as to ensure accurate timing control.

Alternatively, when the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row is the odd-numbered stage shift unit, the transition edge (for example, the transition edge that transitions to its active level) of the signal on the strobe signal line SE1 is aligned with the transition edge (for example, the transition edge that transitions to its active level) of the clock signal on the second clock signal line CLK2, or the phase difference is less than or equal to 2 crystal oscillator periods. The clock signal on the second clock signal line CLK2 may be the effective clock signal of the odd-numbered stage shift cell.

And/or, when the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row is the even-numbered stage shift unit, the transition edge (for example, the transition edge that transitions to its own active level) of the signal on the strobe signal line SE1 is aligned with the transition edge (for example, the transition edge that transitions to its own active level) of the clock signal on the first clock signal line CLK1, or the phase difference is less than or equal to 2 crystal oscillator periods. The clock signal on the first clock signal line CLK1 may be the effective clock signal of the even-numbered stage shift cell.

In which the transition edge specifically includes a rising edge and a falling edge, in the control method, whether the transition edge of the signal on the strobe signal line SE1 is aligned with the rising edge of the clock signal or with the falling edge of the clock signal may be determined by at least one of a specific circuit principle and structure of the shift unit 10, a driving architecture of the scan circuit 100, and a driving type of the scan signal outputted from the scan circuit 100.

The driving structure of the scanning circuit 100 includes "one driving one", "two driving one", "three driving one", and the like, wherein "one driving one" indicates that one shift unit 10 in the scanning circuit 100 and the scanning line GL1 are in a one-to-one correspondence, that is, one shift unit 10 drives one row of pixel circuits; "one-driving-two" indicates that the same shift unit 10 in the scan circuit 100 corresponds to two scan lines GL1, i.e., one shift unit 10 drives two rows of pixel circuits, and "one-driving-three" indicates that the same shift unit 10 in the scan circuit 100 corresponds to three scan lines GL1, i.e., one shift unit 10 drives three rows of pixel circuits.

The driving type of the scan signal is determined by the type of the scan circuit 100, and if the scan circuit 100 is an nsan circuit, it can be electrically connected to the gate of the N-type transistor in the pixel circuit PX to control the on or off of the N-type transistor, the scan signal is a high-level active signal (the high level is the on level of the N-type transistor connected to the nsan circuit); if the scanning circuit 100 is a PScan circuit, it can be electrically connected to the gate of the P-type transistor in the pixel circuit PX to control the on or off of the P-type transistor, the scanning signal is a low-level active signal (the low level is the on level of the P-type transistor connected to the PScan circuit).

With continued reference to fig. 13 and 14, fig. 14 specifically illustrates that the scan circuit 100 is a PScan circuit, and the driving architecture is a driving timing under "one driving", and the PScan circuit may be electrically connected to the gate of the data writing transistor M4, as shown in fig. 14, the scan circuit 100 includes the shift unit 10 having the input signal SINP with a low level being an active signal, the scan signal SP1 with a low level being an on level or an active level, the pulse width of the scan signal SP1 being the same as the pulse width of the second clock signal SCK2, and the low level of the signal CSP1 on the strobe signal line SE1 being an on signal or an active level, so as to control the falling edge of the signal CSP1 on the strobe signal line SE1 to be aligned with the falling edge of the first clock signal SCK 2. Half of the period of the clock signal on the clock signal line to which the PScan circuit is connected may be equal to the scan time required for scanning one row of pixel circuits PX. If the nsan circuit is a one-drive two-configuration, the dividing lines of the first display area AA1 and the second display area AA2 are changed according to the 2-row pixel circuits PX, and the PScan circuit is a one-drive one-configuration, the first-row pixel circuit PX corresponding to the dividing lines of the first display area AA1 and the second display area AA2 is always an odd-row pixel circuit PX, corresponding to the odd-level shift unit 10, and the falling edge (corresponding time tp) of the signal CSP1 on the strobe signal line SE1 is aligned with the falling edge of the clock signal on the same clock signal line, but the corresponding clock signal line is not changed according to the change of the dividing lines of the first display area AA1 and the second display area AA 2.

If the scanning circuit 100 is an nsan circuit, the high level of the signal on the gate signal line SE1 is an on signal or an active level. The high level of the scan signal S1 is on level or active level, and when m=rm+1 and M is even, the shift unit corresponding to the pixel circuit PX to be refreshed in the first row is the even-level shift unit 10, and the rising edge of the signal on the gate signal line SE1 is controlled to be aligned with the rising edge or the falling edge of the clock signal on the first clock signal line CLK 1; if m is an odd number, the shift unit corresponding to the pixel circuit PX to be refreshed in the first row is the odd-level shift unit 10, and the rising edge of the signal on the control gate signal line SE1 is aligned with the rising edge or the falling edge of the clock signal on the second clock signal line CLK 2. Illustratively, the 0 th stage shift unit 10 corresponds to a first row of pixel circuits PX and a second row of pixel circuits PX, the 1 st stage shift unit 10 corresponds to a third row of pixel circuits PX and a fourth row of pixel circuits PX, and so on. For example, it is also possible that the 1 st stage shift unit 10 corresponds to the first row pixel circuit PX and the second row pixel circuit PX, the 2 nd stage shift unit 10 corresponds to the third row pixel circuit PX and the fourth row pixel circuit PX, and so on.

Where M is the corresponding number of rows of the first row pixel circuits of the refreshed display partition, M is the number of stages of the shift unit 10, and R is the number of rows of the pixel circuits PX driven by one shift unit.

In the present embodiment, whether the rising edge of the signal on the strobe signal line SE1 is aligned with the rising edge of the clock signal or the falling edge of the clock signal may be determined according to the active level of the signal SIN (e.g., SIN n 1) at the input terminal of the shift unit 10.

Fig. 15 is a schematic diagram of another shift unit according to an embodiment of the present invention, specifically illustrates a case where the shift unit 10 is an nsan circuit, fig. 16 is a schematic diagram of a driving timing of another shift unit according to an embodiment of the present invention, and specifically illustrates a driving timing of a reverse nsan circuit under a "one-drive-two" driving architecture of the scan circuit 100, which is applicable to the nsan circuit shown in fig. 15. Wherein the low level of the input signal SINN1 of the shift unit 10 is an active level. Since the scanning circuit 100 is a two-drive architecture, one shift unit 10 is correspondingly connected to two rows of pixel circuits, i.e., r=2. The circuit of fig. 15 is equivalent to adding an inverter circuit to the circuit of fig. 13, and the inverter circuit may include a third output transistor M17 and a fourth output transistor M18. The third output transistor M17 is connected between the first potential signal line VGH and the output terminal O1, and the fourth output transistor M18 is connected between the second potential signal line VGL and the output terminal O1. The gate of the third output transistor M17 and the gate of the fourth output transistor M18 are electrically connected to the carry signal output terminal CR. The circuit of fig. 15 has the same or similar structure and operation principle as the circuit of fig. 13, and the scan signal at the output terminal O1 of the circuit of fig. 15 is obtained by inverting the scan signal at the output terminal O1 of the circuit of fig. 13.

Fig. 17 is a schematic structural diagram of another display panel provided IN the embodiment of the present invention, specifically illustrating a situation IN which the shift units shown IN fig. 15 are cascaded, and referring to fig. 15 and 17, the shift unit 10 includes a first output transistor M15, where the first output transistor M15 is connected between a carry signal output end CR of the shift unit 10 and a first clock signal end CK2, and IN the adjacent two-stage shift units 10, the carry signal output end CR of the previous stage shift unit 10 is electrically connected with an input end IN (SINN 1) of the next stage shift unit 10; in the adjacent two-stage shift units 10, the first clock signal terminal CK2 of the previous-stage shift unit 10 and the first clock signal terminal CK2 of the next-stage shift unit 10 are electrically connected to different clock signal lines, and the clock signal on the clock signal line to which the first clock signal terminal CK2 of the shift unit 10 is electrically connected serves as an effective clock signal.

As shown in fig. 16, when the high level of the scan signal SN1 is the on level or the active level, if the low level of the input signal SINN1 of the shift unit 10 is the active level, the rising edge of the signal CSN1 on the control gate signal line SE1 is aligned with the falling edge of the clock signal on the first clock signal line CLK1 or the clock signal on the second clock signal line CLK 2. The scan circuit 100 may be a first nsan circuit electrically connected to the gate of the threshold compensation transistor M5 in the pixel circuit.

Taking the first type refresh frame F1 as an example, if the first row pixel circuit PX of the second display partition AA2 needs to be refreshed is the 677 th row, as can be seen from 677=m=2m+1, m=338, M is an even number, and the shift unit 10 corresponding to the pixel circuit PX of the first row needs to be refreshed is an even number level shift unit, so that the rising edge (for example, corresponding time tn) of the signal CSN1 on the control strobe signal line SE1 is aligned with the falling edge of the clock signal on the first clock signal line CLK1 (as shown by the solid line portion of the signal CSN1 in fig. 16).

Taking the first row pixel circuit to be refreshed in the second display area AA2 as an example in the first type refresh frame F1, if the first row pixel circuit PX in the second display area AA2 is the 675 th row, as can be seen from 675 m=2m+1, m=337, M is an odd number, and the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row is an odd number shift unit, so that the rising edge (for example, corresponding to time tn ") of the signal CSN1 on the gate signal line SE1 is controlled to be aligned with the falling edge of the clock signal on the second clock signal line CLK2 (as shown by the dotted line portion of the signal CSN1 in fig. 16).

In both examples shown in fig. 16, the line number of the first line pixel circuit PX of the second display section AA2 in the latter example is 2 larger than the line number of the first line pixel circuit PX of the former second display section AA2, and therefore, the time interval T is equal to two line scanning times, which corresponds to t=tn "-tn. Half of the period of the signal of the clock on the clock signal line to which the nsan circuit is connected may be equal to the scanning time required to scan the two rows of pixel circuits PX. Alternatively, in the case where the high level of the input signal SIN of the shift unit 10 is the active level, the rising edge of the signal CS1 on the strobe signal line SE1 is aligned in the opposite manner to that shown in fig. 16.

Fig. 18 is a schematic structural diagram of another display panel according to an embodiment of the present invention, specifically illustrating a case where the shift units 10 are nsan circuits, where each stage of shift unit 10 is connected to one clock signal line, an effective clock signal of the shift unit 10 is a clock signal on the clock signal line connected to the shift unit, and clock signal lines connected to adjacent two stages of shift units 10 are different. Fig. 19 is a schematic diagram of a driving timing of another shift unit according to an embodiment of the present invention, and specifically illustrates a driving timing of a second nsan circuit in a "one-drive two" driving architecture of the scan circuit 100, wherein a high level of an input signal SIN of the shift unit 10 is an active level, and a rising edge of a signal CSN2 on the strobe signal line SE1 is aligned with a rising edge of a clock signal. Specifically, as shown in fig. 19, in the case where the high level of the scan signal SN2 is the on level or the active level, if the high level of the input signal SIN (for example, SIN n 2) of the shift unit 10 is the active level, the rising edge of the signal CSN2 on the control gate signal line SE1 is aligned with the rising edge of the clock signal on the first clock signal line CLK1 or the second clock signal line CLK 2. The scan circuit 100 may be a second nsan circuit electrically connected to the gate of the third initialization transistor M6 in the pixel circuit.

Referring to fig. 19, for example, taking the first row pixel circuit PX of the second display partition AA2 to be refreshed when the first type refresh frame F1 is taken as an example, if the first row pixel circuit of the second display partition AA2 is the 677 th row, as known from m=2m+1, m=338, M is an even number, and the shift unit 10 corresponding to the pixel circuit PX of the first row to be refreshed is an even number stage shift unit, thereby controlling the rising edge (corresponding to tn time) of the signal CSN2 on the gate signal line SE1 to be aligned with the rising edge of the clock signal on the first clock signal line CLK1 (as shown by the solid line portion of the signal CSN2 on the gate signal line SE1 in fig. 17).

Taking the first-row pixel circuit PX of the second display partition AA2 that needs to be refreshed as an example in the first-type refresh frame F1, if the first-row pixel circuit of the second display partition AA2 is the 679 th row, as can be seen from m=2m+1, m=339, M is an odd number, and the shift unit 10 corresponding to the first-row pixel circuit PX that needs to be refreshed is an odd number shift unit, so that the rising edge (corresponding to tn″ time) of the signal CSN2 on the control gate signal line SE1 is aligned with the rising edge (shown as the dotted line portion of the signal CSN2 on the gate signal line SE1 in fig. 19) of the clock signal on the second clock signal line CLK 2.

Alternatively, the rising edge of the clock signal on the second clock signal line CLK2 is aligned with the falling edge of the clock signal on the first clock signal line CLK 1. Alternatively, the falling edge of the clock signal on the second clock signal line CLK2 is aligned with the rising edge of the clock signal on the first clock signal line CLK 1. Alternatively, m is an even number, and the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row is an even-numbered stage shift unit, and the rising edge (corresponding to tn) of the signal CSN2 on the control gate signal line SE1 is aligned with the falling edge of the clock signal on the second clock signal line CLK 2. Alternatively, m is an odd number, and the shift unit 10 corresponding to the pixel circuit PX to be refreshed in the first row is an odd-level shift unit, and the rising edge (corresponding to tn″ time) of the signal CSN2 on the control gate signal line SE1 is aligned with the falling edge of the clock signal on the first clock signal line CLK 1.

Alternatively, the rising edge of the clock signal on the second clock signal line CLK2 and the falling edge of the clock signal on the first clock signal line CLK1 are not aligned. Alternatively, the falling edge of the clock signal on the second clock signal line CLK2 and the rising edge of the clock signal on the first clock signal line CLK1 are not aligned.

In the above embodiments, when the number of rows corresponding to the first row pixel circuit of the second display area AA2 changes, for example, the row number increases, and in fig. 16 (or fig. 19), the signal CSN1 or CSN2 on the strobe signal line SE1 changes to the timing indicated by the dotted line, and when the time is shifted by T, the scan signal SN1 or SN2 of the shift unit of the present stage is not output to the corresponding pixel circuit PX, and the scan signal SN1 or SN2 of the shift unit of the subsequent stage is output to the corresponding pixel circuit PX.

According to the scheme, through the alignment mode of the jump edge of the signal CSP, CSN1 or CSN2 on the strobe signal line SE1 and the jump edge of the corresponding clock signal, the signals and the scanning signals on the strobe signal line SE1 are synchronized, so that the accurate control of the refresh frequency of a plurality of display partitions is facilitated, the abnormal display problem of the boundary line position in the multi-display partition switching refresh frequency is solved, and the power consumption is reduced.

Fig. 20 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 20, optionally, at least one driving circuit includes a first driving circuit 121, the first driving circuit 121 includes a first scanning circuit and a first gate module, and the first scanning circuit includes a plurality of stages of first shift units. The R row pixel circuits PX correspond to the same first shift unit in the first driving circuit 121, where R is an integer greater than or equal to 2. When r=2, the number of first shift units 11 is Z/2. Only the connection between the first-stage first shift unit and the last-stage first shift unit and the pixel circuits PX is shown in the figure, specifically, the first-stage first shift unit correspondingly drives the first-row pixel circuits PX and the second-row pixel circuits PX, and the last-stage first shift unit correspondingly drives the Z-th (last-row) pixel circuits PX and the Z-1-th (penultimate) pixel circuits PX.

And/or, the at least one driving circuit includes a second driving circuit 122, the second driving circuit 122 includes a second scan circuit and a second gate module, and the second scan circuit includes a multi-stage second shift unit. One row of pixel circuits PX corresponds to one second shift unit in the second driving circuit 122, and a different row of pixel circuits PX corresponds to a different second shift unit in the second driving circuit 122. The number of second shift units 12 is Z.

And/or, the at least one driving circuit includes a third driving circuit 123, the third driving circuit 123 includes a third scan circuit and a third gate module, and the third scan circuit includes a multi-stage third shift unit. The K rows of pixel circuits PX correspond to the same shift unit in the third driving circuit 123, where K is an integer greater than or equal to 2. When k=2, the number of the third shift units is Z/2, and the specific connection manner thereof may refer to the connection of the first driving circuit 121. Alternatively, r=k.

The input terminal IN of the first shift unit IN the different scan circuits is connected to different input signals (e.g., SIN1, SIN2, SIN 3). The pixel circuit SP1 has an input terminal for the scan signal SP1, the SN1 terminal is an input terminal for the scan signal SN1, and the SN2 terminal is an input terminal for the scan signal SN 2.

Alternatively, in conjunction with the pixel circuit shown in fig. 4, the second driving circuit 122 may be configured to provide the scan signal SP1 to the data writing transistor M4, the first driving circuit 121 may be configured to provide the scan signal SN1 to the threshold compensation transistor M5, and the third driving circuit 123 may be configured to provide the scan signal SN2 to the third initialization transistor M6.

The first gating module, the second gating module and the third gating module are respectively connected with different gating signal lines, the clock signal lines correspondingly connected with different driving circuits are different, namely, each driving circuit is connected with the corresponding first clock signal line CLK1 and second clock signal line CLK2, and the corresponding signals on the gating signal lines can be set in an alignment mode in the technical schemes.

By individually controlling the timing of the transition edge of the signal on the gate signal line to be aligned with the transition edge of the clock signal on one of the at least two clock signal lines, the problem of abnormal display of the display partition boundary position can also be solved.

Alternatively, in the technical solutions provided in the foregoing embodiments, the shift unit 10 may be a shift register, and may be an 8T2C architecture, and reference may be made to the description of the shift register in the related technical solutions. The gating module 200 may be formed of a transistor or a logic gate circuit, and may be capable of implementing a gating function.

Optionally, the embodiment of the invention further provides a display panel, and the display panel can be controlled by the control method of the display panel provided by any embodiment of the invention. The display panel not only can be a mobile phone panel, but also can be a display panel in a tablet, a mobile phone, a watch, a wearable device, an electronic device such as a vehicle-mounted display, a camera display, a television, a computer screen and the like. The display panel is controlled by the control method of the display panel provided by any embodiment of the invention, so the display panel provided by the embodiment of the invention also has the beneficial effects described by any embodiment of the invention.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A control method of a display panel, wherein the display panel includes at least two display partitions, the at least two display partitions include a first display partition and a second display partition that are adjacent and have different refresh frequencies, the display panel includes: a plurality of pixel circuits arranged in an array;

the control method of the display panel comprises the following steps:

setting a plurality of transition frames in the process of switching the refresh frequency of the first display partition, wherein the refresh frequency of the first display partition in the transition frames is between the refresh frequency before switching and the refresh frequency after switching of the first display partition; and/or in the transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition are different.

2. The method for controlling a display panel according to claim 1, wherein,

the refresh frequency of the first display partition in the transition frames is gradually increased or gradually decreased, and the refresh frequency is between the refresh frequency of the first display partition before switching and the refresh frequency after switching;

preferably, the display panel further includes:

At least one driving circuit including a scanning circuit including a multistage shift unit, a gate module, and a gate signal line;

the strobe module is responsive to a signal on the strobe signal line to cause the shift unit not to output a scan signal to the pixel circuit of the first display partition in the first type refresh frame, and to cause the shift unit to output a scan signal to the pixel circuit of the first display partition in the second type refresh frame;

preferably, in at least two refresh frames of the first type, the row positions of pixel circuits corresponding to the boundaries of the first display partition adjacent to the second display partition are different;

Preferably, in a plurality of refresh frames of the first type between two adjacent refresh frames of the second type, row positions of pixel circuits corresponding to adjacent boundaries of the first display partition and the second display partition are the same or different;

preferably, when the refresh frequency before switching the first display partition is greater than the refresh frequency after switching, the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased in the process of switching the refresh frequency of the first display partition; the refresh frequency of the first display partition gradually decreases;

and/or when the refresh frequency before the first display partition is switched is smaller than the refresh frequency after the first display partition is switched, gradually reducing the number of the first type refresh frames inserted between two adjacent second type refresh frames in the process of switching the refresh frequency of the first display partition; the refresh frequency of the first display partition is gradually increased;

preferably, in at least two transition frames, the line positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition change in a line number increasing manner or a line number decreasing manner, or change in a line number increasing and then decreasing manner, or change in a line number decreasing and then increasing manner, or change randomly;

Preferably, in any two transition frames, the variation of the line position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition is less than or equal to 20 lines;

preferably, in the process of switching the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition changes according to a fixed row number each time;

preferably, in the process of switching the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition changes along with the change of the refresh frequency of the first display partition;

preferably, in the process of switching the refresh frequency of the first display partition, the row position of the pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition is changed along with the change of the refresh frequency of the first display partition according to the fixed row number.

3. The control method of a display panel according to claim 2, wherein the gate module causes the shift unit to output a scan signal to the pixel circuit of the second display section at the time of the first type refresh frame in response to a signal on the gate signal line, and does not cause the shift unit to output a scan signal to the pixel circuit of the first display section; causing the shift unit to output a scan signal to the pixel circuits of the first display section and the second display section at the time of the second type refresh frame;

In the process of switching the refresh frequency of the first display partition, inserting the first type refresh frame among a plurality of second type refresh frames, wherein the number of the first type refresh frames inserted between two adjacent second type refresh frames is gradually increased or gradually decreased; and/or in at least two refresh frames of the first type, the row positions of pixel circuits corresponding to the boundaries of the first display partition adjacent to the second display partition are different;

preferably, in the process of switching the refresh frequency of the first display partition, in the first type refresh frame, the signal on the gate signal line is the pulse width of the self active level, which is smaller than the pulse width of the self active level in the second type refresh frame;

preferably, in the process of switching the refresh frequency of the first display partition, in at least two refresh frames of the first type, the transition time of the signal on the strobe signal line in the refresh frame of the first type is changed; the jump time of the signal on the gating signal line in the first type refreshing frame corresponds to the row position of a pixel circuit corresponding to the adjacent boundary of the first display partition and the second display partition;

Preferably, in the process of switching the refresh frequency of the first display partition, in at least two refresh frames of the first type, the transition time of the signal on the strobe signal line in the refresh frame of the first type changes in an increasing manner or a decreasing manner, or changes in a manner of increasing first and then decreasing first, or changes in a manner of decreasing first and then increasing first, or changes randomly;

preferably, in any two first-type refresh frames, the variation of the transition time of the signal on the gating signal line in the first-type refresh frames is less than or equal to 20 rows of pixel circuit scanning time;

preferably, in the process of switching the refresh frequency of the first display partition, the transition time of the signal on the gate signal line in the first type refresh frame varies with the change of the refresh frequency of the first display partition.

4. The method of claim 1, wherein the display panel further comprises a third display partition, the first display partition, the second display partition, and the third display partition are sequentially adjacent, refresh frequencies of adjacent two display partitions of the first display partition, the second display partition, and the third display partition are different,

In the process of switching the refresh frequency of the third display partition, the refresh frequency of the third display partition in a plurality of transition frames is between the refresh frequency of the third display partition before switching and the refresh frequency after switching; and/or in the transition frames, the positions of the pixel circuits corresponding to the adjacent boundaries of the third display partition and the second display partition are different;

preferably, the display panel further includes:

the refresh frequency of the first display partition is the same as that of the third display partition, and the refresh frequency of the first display partition is smaller than that of the second display partition, and the display driving method further comprises:

the strobe module, in response to a signal on the strobe signal line, causes the shift unit to output a scan signal to the pixel circuits of the second display partition, and does not cause the shift unit to output a scan signal to the pixel circuits of the first display partition and the third display partition at the time of the first type refresh frame; causing the shift unit to output a scan signal to the pixel circuits of the first, second, and third display partitions at the time of the second type refresh frame;

the strobe module is responsive to a signal on the strobe signal line, and does not cause the shift unit to output a scan signal to the pixel circuits of the second display partition, and causes the shift unit to output a scan signal to the pixel circuits of the first display partition and the third display partition when the first type refresh frame is performed; and when the second type refreshing frame is generated, the shifting unit is enabled to output scanning signals to the pixel circuits of the first display partition, the second display partition and the third display partition.

5. The method according to claim 4, wherein before switching refresh frequencies of the first display section and the third display section, the first display section corresponds to 1 st to W th row pixel circuits, the second display section corresponds to w+1 th to J th row pixel circuits, and the third display section corresponds to j+1 th to Z th row pixel circuits, and W, J, Z are positive integers which are larger than 1 and are different from each other;

In the process of switching the refresh frequencies of the first display partition and the third display partition, the gating module responds to signals on the gating signal lines, and when at least one first type of refresh frame is performed, the shifting unit is not enabled to output scanning signals to the pixel circuits of the 1 st to W+P x n rows and the pixel circuits of the J+P x n+1 st to Z rows, and is enabled to output scanning signals to the pixel circuits of the W+P x n+1 st to J+P x n rows; when the second type refreshing frame is used, the shifting unit is enabled to output scanning signals to the pixel circuits from the 1 st row to the Z th row; wherein P is a positive integer, and n is a positive integer or a negative integer.

6. The control method of a display panel according to claim 2, wherein the gate module includes a plurality of gate units, each stage of the shift unit is connected to the pixel circuits of the corresponding row through the gate units, and control ends of the plurality of gate units are connected to the gate signal lines;

preferably, when the first type refresh frame is used, and the shift unit corresponding to the pixel circuit of the second display partition outputs a scanning signal, the signal on the gating signal line is at an active level, and the gating unit is controlled to be turned on so as to control the shift unit to output the scanning signal to the pixel circuit of the second display partition;

7. The method of controlling a display panel according to claim 1, wherein the display panel further comprises:

at least one driving circuit including a scanning circuit including a multi-stage shift unit, at least two clock signal lines, a gate module, and a gate signal line;

the control method of the display panel further comprises the following steps:

the gating module responds to the signals on the gating signal lines and controls the shifting units to output scanning signals to the corresponding pixel circuits so as to realize different refresh frequencies corresponding to at least two display partitions; the transition edges of the signal on the strobe signal line are aligned in time with the transition edges of the clock signal on one of the at least two clock signal lines, or differ by less than or equal to 2 crystal oscillator periods, wherein the crystal oscillator is disposed in a clock circuit for generating the clock signal.

8. The method for controlling a display panel according to claim 7, wherein,

the clock signal on one of the at least two clock signal lines is used as an effective clock signal corresponding to the shifting unit, the transition time when the scanning signal output by the shifting unit is hopped to the self effective level is determined by the corresponding effective clock signal, and the effective clock signals corresponding to the adjacent two stages of shifting units are different clock signals on the clock signal lines;

the jump time when the signal on the gating signal line jumps to the self effective level is the same as the jump time when the effective clock signal of the shifting unit corresponding to the pixel circuit which needs to be refreshed at the first line jumps to the self effective level;

preferably, the shift unit includes a first output transistor connected between a carry signal output end and a first clock signal end of the shift unit, and in two adjacent stages of the shift units, the carry signal output end of the shift unit of a previous stage is electrically connected with the input end of the shift unit of a subsequent stage; in the adjacent two stages of shift units, a first clock signal end of the shift unit of the previous stage and a first clock signal end of the shift unit of the next stage are electrically connected to different clock signal lines, and a clock signal on the clock signal line electrically connected with the first clock signal end of the shift unit is used as an effective clock signal.

9. The control method of a display panel according to claim 7, wherein the at least two clock signal lines include a first clock signal line and a second clock signal line; the frequency and the phase of the clock signals on the first clock signal line and the second clock signal line are the same, and the phases are opposite;

preferably, the at least one driving circuit includes a first driving circuit, R rows of the pixel circuits correspond to the same shift unit in the first driving circuit, and R is an integer greater than or equal to 2;

and/or at least one driving circuit comprises a second driving circuit, one row of the pixel circuits corresponds to one shifting unit in the second driving circuit, and different rows of the pixel circuits correspond to different shifting units in the second driving circuit;

And/or, the at least one driving circuit comprises a third driving circuit, K rows of pixel circuits correspond to the same shifting unit in the third driving circuit, and K is an integer greater than or equal to 2;

preferably, the pixel circuit includes a driving module, a data writing module, and a threshold compensation module, where the data writing module is connected between a data line and a first end of the driving module, a control end of the data writing module is electrically connected with the second driving circuit, the threshold compensation module is connected between a second end of the driving module and the control end, and a control end of the threshold compensation module is electrically connected with the first driving circuit;

preferably, the pixel circuit further includes a first initialization module, the first initialization module is connected between a first initialization signal line and a control end of the driving module, and the control end of the first initialization module is electrically connected with the third driving circuit;

preferably, the data writing module comprises a P-type transistor, the threshold compensation module comprises an N-type transistor, and the first initializing module comprises an N-type transistor;

preferably, in the process of switching the refresh frequency of the first display partition, in the transition frames, the change amount of the positions of the pixel circuits corresponding to the adjacent boundaries of the first display partition and the second display partition is an integer multiple of R rows.

10. The control method of the display panel is characterized in that the display panel comprises at least two display partitions, and the at least two display partitions comprise a first display partition and a second display partition which are adjacent and have different refreshing frequencies; the display panel includes:

a plurality of pixel circuits arranged in an array;

the driving circuit comprises a scanning circuit, at least two clock signal lines, a gating module and a gating signal line, wherein the scanning circuit comprises a multistage shift unit, and the scanning circuit is connected with the at least two clock signal lines;

the control method of the display panel comprises the following steps:

the gating module responds to signals on the gating signal lines, so that the shifting unit outputs scanning signals to the corresponding pixel circuits, and the refresh frequencies corresponding to at least two display partitions are different; the transition edges of the signal on the strobe signal line are aligned in time with the transition edges of the clock signal on one of the at least two clock signal lines, or differ by less than or equal to 2 crystal oscillator periods, wherein the crystal oscillator is disposed in a clock circuit for generating the clock signal.

11. The method for controlling a display panel according to claim 10, wherein,

preferably, the shift unit includes a first output transistor connected between a carry signal output end and a first clock signal end of the shift unit, and in two adjacent stages of the shift units, the carry signal output end of the shift unit of a previous stage is electrically connected with the input end of the shift unit of a subsequent stage; in the adjacent two stages of shift units, a first clock signal end of the shift unit of the previous stage and a first clock signal end of the shift unit of the next stage are electrically connected to different clock signal lines, and a clock signal on the clock signal line electrically connected with the first clock signal end of the shift unit is used as an effective clock signal;

Preferably, the shift unit is controlled to output a scan signal to the pixel circuits of the second display partition in a first type refresh frame, and the shift unit is controlled to output a scan signal to the pixel circuits of the first display partition and the second display partition in a second type refresh frame.

12. The control method of a display panel according to claim 10, wherein the at least two clock signal lines include a first clock signal line and a second clock signal line; the first clock signal line and the second clock signal line have the same frequency and opposite phases;

13. A display panel characterized by being controlled by a control method of a display panel according to any one of claims 1-9.