CN116991482B - Instruction transmitting method, processor and related equipment - Google Patents
Instruction transmitting method, processor and related equipment Download PDFInfo
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- CN116991482B CN116991482B CN202311132914.9A CN202311132914A CN116991482B CN 116991482 B CN116991482 B CN 116991482B CN 202311132914 A CN202311132914 A CN 202311132914A CN 116991482 B CN116991482 B CN 116991482B
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000005540 biological transmission Effects 0.000 claims description 9
- 230000015654 memory Effects 0.000 description 18
- 238000004590 computer program Methods 0.000 description 5
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- 230000002093 peripheral effect Effects 0.000 description 2
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- 238000004458 analytical method Methods 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The application discloses an instruction transmitting method, a processor and related equipment, wherein the instruction transmitting method comprises the following steps: before the first instruction is transmitted, data information corresponding to the first instruction is acquired, whether all second instructions to be transmitted have second instructions which conflict with the data of the first instruction or not is predicted based on the data information corresponding to the first instruction and the data information corresponding to all second instructions to be transmitted, if the second instructions which conflict with the data of the first instruction exist, the first instruction is controlled to be transmitted after the second instructions are transmitted, so that the first instruction is controlled to be executed after the second instructions are executed, the problem of data conflict between part of the first instructions and the second instructions can be solved, instruction delay caused by pipeline refreshing and the like can be reduced, and the performance of a processor can be improved.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to an instruction transmitting method, a processor, and related devices.
Background
Currently, the execution mode of an instruction pipeline by a processor is mainly divided into two modes of sequential execution and out-of-order execution (or look-ahead execution). Although out-of-order execution may increase the processing efficiency of the instruction pipeline, it is prone to data conflict (or data correlation) issues between instructions. One way to solve the problem of data collision is to allow the instruction to execute out of order, if other instructions with data collision are found after the instruction is executed, the pipeline is flushed from the other instructions, and the instruction is fetched and executed again from the other instructions, however, this causes a large delay of the instructions and affects the performance of the processor.
Disclosure of Invention
The application discloses an instruction transmitting method, a processor and related equipment, which are used for reducing the delay of instructions and improving the performance of the processor.
In a first aspect, the present application discloses an instruction transmitting method, including: before a first instruction is transmitted, acquiring data information corresponding to the first instruction; predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on the data information corresponding to the first instructions and the data information corresponding to all second instructions to be transmitted; and if the second instruction which conflicts with the first instruction data exists, controlling the first instruction to be transmitted after the second instruction is transmitted so as to control the first instruction to be executed after the second instruction is executed.
In some optional examples, the predicting whether the second instructions to be transmitted have second instructions that collide with the first instruction data based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted includes: acquiring data information corresponding to all second instructions to be transmitted based on the data information record table; and predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on the data information corresponding to the first instructions and the obtained data information corresponding to all second instructions to be transmitted.
In some alternative examples, further comprising: and after any second instruction is decoded, acquiring the data information corresponding to the second instruction, and recording the data information corresponding to the second instruction in the data information recording table.
In some alternative examples, further comprising: and after any second instruction is transmitted, deleting the data information corresponding to the second instruction in the data information record table.
In some optional examples, the data information includes a data address and an address register number, and the predicting, based on the data information corresponding to the first instruction and the data information corresponding to all second instructions to be transmitted, whether there is a second instruction that conflicts with the first instruction data in all the second instructions to be transmitted includes: and predicting whether all second instructions to be transmitted have second instructions which conflict with the data of the first instructions based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all second instructions to be transmitted and whether the address register numbers corresponding to the first instructions are the same as the address register numbers corresponding to all second instructions to be transmitted.
In some optional examples, the data information includes a data address and data, and the predicting, based on the data information corresponding to the first instruction and the data information corresponding to all second instructions to be transmitted, whether there is a second instruction that conflicts with the first instruction data in all the second instructions to be transmitted includes: and predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all second instructions to be transmitted or not and whether the data corresponding to the first instructions are overlapped with the data corresponding to all second instructions to be transmitted or not.
In some alternative examples, if there are multiple second instructions that collide with the first instruction data, the controlling the first instruction to be transmitted after the second instruction to be transmitted includes: if the data corresponding to one second instruction in the plurality of second instructions comprises all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the one second instruction is transmitted; and if the data corresponding to at least two second instructions in the plurality of second instructions form all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the at least two second instructions are transmitted.
In some alternative examples, the controlling the first instruction to be transmitted after the second instruction to be transmitted includes: acquiring an instruction identifier of the second instruction; determining whether the second instruction is transmitted according to the instruction identification of the second instruction; and if the second instruction is transmitted, transmitting the first instruction.
In some alternative examples, the first instruction comprises a load instruction and the second instruction comprises a store instruction.
In a second aspect, the present application discloses a processor configured to perform the method of instruction transmission as claimed in any one of the preceding claims.
In a third aspect, the application discloses an electronic device comprising a processor as described above.
In a fourth aspect, the present application discloses a computer-readable storage medium having stored thereon instructions for performing the instruction transmitting method according to any one of the above.
According to the instruction transmitting method, the processor and the related equipment disclosed by the application, before the first instruction is transmitted, the data information corresponding to the first instruction is acquired, based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted, whether the second instructions which conflict with the data of the first instruction exist in all the second instructions to be transmitted or not is predicted, if the second instructions which conflict with the data of the first instruction exist, the first instruction is controlled to be transmitted after the second instruction is transmitted, so that the first instruction is controlled to be executed after the second instruction is executed, the problem of data conflict between part of the first instruction and the second instruction can be solved, the instruction delay caused by pipeline refreshing and the like can be reduced, and the performance of the processor can be further improved.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
Fig. 1 is a flowchart of a method for transmitting instructions according to an embodiment of the present application.
Fig. 2 is a flowchart of an instruction transmitting method according to another embodiment of the present application.
Fig. 3 is a schematic diagram of a data relationship between a first instruction and a plurality of second instructions according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a data relationship between a first instruction and a plurality of second instructions according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a data relationship between a first instruction and a plurality of second instructions according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a processor according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Currently, the instruction pipeline of a processor can be divided into five stages: the system comprises a fetch stage, a decoding stage, an execution stage, a memory access stage and a write-back stage. The execution mode of the processor for the instruction pipeline is mainly divided into two modes of sequential execution and out-of-order execution. In the sequential execution process, the processor executes fetched instructions one by one on one instruction pipeline according to the instruction fetch sequence. In out-of-order execution, the processor allows multiple instructions to be developed to each corresponding execution unit for processing rather than in instruction fetch order. That is, the processor may send the instruction capable of being executed in advance to the corresponding execution unit in advance according to the state of each execution unit and the analysis result of whether each instruction can be executed in advance. Then, the instruction execution results are rearranged by the instruction submitting unit according to the instruction fetching sequence.
Although out-of-order execution may increase the processing efficiency of the instruction pipeline, it is prone to data collision problems between instructions. The data collision problem can be classified into a read-after-write problem, a write-after-read problem, and a write-after-write problem. Taking the read-after-write problem as an example, a write operation of a write instruction modifies the value of a register or memory location within a certain clock cycle, and the next read instruction attempts to read the modified value, resulting in a data collision.
One way to solve the problem of data collision is to take the same read-after-write problem as an example, allow the write instruction to execute first, check if there is a read instruction older than the write instruction after the write instruction is executed, and if so, store the write instruction in a register. When executing the read instruction, checking the corresponding register, if the write instruction with the same address is found to be stored in the register, refreshing the pipeline from the read instruction, and restarting the instruction fetching and executing from the read instruction. Although this approach can solve the problem of data collision such as read after write, the process of brushing lines, re-fetching and executing will take a long time, resulting in a large delay of instructions and affecting the performance of the processor.
Based on the above, the application discloses an instruction transmitting scheme, which predicts whether the second instructions to be transmitted have instructions conflicted with the data before transmitting the first instructions, and if yes, controls the first instructions to be transmitted after the second instructions are transmitted, so as to reduce instruction delay caused by pipeline refreshing and the like while solving the conflict between part of the first instructions and the data of the second instructions, and improve the performance of a processor.
As an optional implementation of the present disclosure, an embodiment of the present disclosure discloses an instruction transmitting method, as shown in fig. 1, where the method includes:
s101: before transmitting a first instruction, acquiring data information corresponding to the first instruction;
in the application, after the instruction is fetched and decoded, the first instruction enters the instruction transmitting queue and is transmitted to the corresponding execution unit from the instruction transmitting queue for execution. However, before the first instruction is transmitted, data information corresponding to the first instruction is acquired, where the data information is used to determine whether there is a data collision between the first instruction and the second instruction.
S102: predicting whether all second instructions to be transmitted have second instructions which conflict with the data of the first instructions or not based on the data information corresponding to the first instructions and the data information corresponding to all second instructions to be transmitted;
after the data information corresponding to the first instruction is obtained, the data information corresponding to the first instruction is compared with the data information corresponding to all the second instructions to be transmitted or not, and whether the second instructions which conflict with the data of the first instruction exist in all the second instructions to be transmitted or not is predicted according to the comparison result.
It will be appreciated that all second instructions to be issued or not issued in the present application are ordered in the instruction issue queue after the first instruction. The data information corresponding to all the second instructions to be transmitted may be obtained in advance, or the data information corresponding to all the second instructions to be transmitted or not transmitted may be obtained at the same time when the data information corresponding to the first instruction is obtained, which is not described herein.
S103: if the second instruction conflicts with the first instruction data, the first instruction is controlled to be transmitted after the second instruction is transmitted, so that the first instruction is controlled to be executed after the second instruction is executed.
If it is predicted that all the second instructions to be transmitted have the second instruction which conflicts with the first instruction data, the first instruction is controlled to be transmitted after the second instruction is transmitted, that is, the first instruction enters an instruction transmission queue, but the first instruction is not transmitted temporarily, other instructions after the first instruction are transmitted first until the transmission of the second instruction which conflicts with the first instruction data is completed, and then the transmission of the first instruction is performed, so that the first instruction is executed after the execution of the second instruction which conflicts with the first instruction data, or the second instruction which conflicts with the first instruction data is executed first, and the problem of the data conflict between the first instruction and the second instruction can be solved.
On this basis, as shown in fig. 2, the instruction transmitting method further includes: s104: and if the second instruction which conflicts with the first instruction data does not exist, sending the first instruction to a corresponding execution unit for execution. That is, if it is predicted that there is no second instruction that conflicts with the first instruction data in all the second instructions to be issued, the first instruction is sent to the instruction issue queue, and is directly issued from the instruction issue queue to the corresponding execution unit for execution.
In the application, before the first instruction and the second instruction are transmitted or executed, whether the first instruction and the second instruction have data conflict is predicted, and when the first instruction and the second instruction are predicted to have data conflict, the transmitting sequence of the first instruction and the second instruction is adjusted, so that not only can the data conflict between partial instructions in an instruction pipeline be solved, but also the instruction delay caused by pipeline refreshing and the like can be reduced, that is, the instruction delay of the data conflict solving mode in the application is smaller, and the performance of a processor can be improved.
It can be understood that the execution mode of the instruction pipeline in the present application is still an out-of-order execution mode, but the transmission order of the first instruction and the second instruction is adjusted when the first instruction and the second instruction are predicted to have data collision.
In some embodiments of the present application, the first instruction comprises a load instruction (or a read instruction) and the second instruction comprises a store instruction (or a write instruction), and the data collision problem between the first instruction and the second instruction is a read-after-write problem. Of course, the present application is not limited in this regard, and in other embodiments, the first instruction comprises a store instruction (or write instruction) and the second instruction comprises a load instruction (or read instruction), and the problem of data collision between the first instruction and the second instruction is a write-after-read problem. In other embodiments, the first instruction comprises a store instruction (or a write instruction) and the second instruction comprises a store instruction (or a write instruction), the data conflict problem between the first instruction and the second instruction being a write-after-write problem.
It will be appreciated that a load instruction (or read instruction) is used to read data from a peripheral such as a memory into a processor or processor core, and a store instruction (or write instruction) is used to write data from a processor or processor core into a peripheral such as a memory.
In some embodiments of the present application, the obtained data information corresponding to all the second instructions to be transmitted may be stored in a data information record table, and the data information record table may be stored in a register, and before any first instruction is transmitted, whether all the second instructions to be transmitted have the second instruction that conflicts with the data of the first instruction may be predicted based on the data information corresponding to the first instruction and the data information record table.
In some optional examples, predicting whether all second instructions to be transmitted have second instructions that collide with the first instruction data based on the data information corresponding to the first instruction and the data information corresponding to all second instructions to be transmitted includes: acquiring data information corresponding to all second instructions to be transmitted based on the data information record table; based on the data information corresponding to the first instruction and the obtained data information corresponding to all the second instructions to be transmitted, predicting whether the second instructions to be transmitted have the second instructions which conflict with the data of the first instruction or not.
For example, after the data information corresponding to the first instruction is acquired, it may be predicted whether all the second instructions to be transmitted have the second instruction that conflicts with the data of the first instruction by looking up the data information record table. Specifically, the data information corresponding to the first instruction may be compared with the data information corresponding to all the second instructions to be transmitted, which are recorded in the data information recording table, and whether the second instructions to be transmitted have the second instruction in conflict with the first instruction data or not is predicted according to the comparison result.
In some alternative examples, the instruction transmitting method further includes: after any second instruction is decoded, the data information corresponding to the second instruction is acquired, and the data information corresponding to the second instruction is recorded in a data information recording table, so that more data information corresponding to the second instruction to be transmitted is acquired as much as possible.
In some alternative examples, the instruction transmitting method further includes: after any second instruction is transmitted, deleting the data information corresponding to the second instruction in the data information record table so as not to influence the prediction of the subsequent instruction, and causing the prediction error of the subsequent instruction.
In some embodiments of the present application, the data information includes a data address and an address register number, that is, the data information corresponding to the second instruction recorded in the data information recording table includes a data address corresponding to the second instruction and an address register number corresponding to the second instruction, where the address register number includes an address calculation related register number.
Based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted, predicting whether the second instructions to be transmitted have the second instructions which conflict with the data of the first instruction or not comprises the following steps: and predicting whether all the second instructions to be transmitted have the second instructions which conflict with the data of the first instructions based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all the second instructions to be transmitted and whether the address register numbers corresponding to the first instructions are the same as the address register numbers corresponding to all the second instructions to be transmitted.
Specifically, the data addresses corresponding to the first instruction are compared with the data addresses corresponding to all the second instructions to be transmitted, and after the address register numbers corresponding to the first instruction are compared with the address register numbers corresponding to all the second instructions to be transmitted, if the data addresses corresponding to the first instruction are at least partially overlapped with the data addresses corresponding to one second instruction, and the address register numbers corresponding to the first instruction are the same as the address register numbers corresponding to the same second instruction, the prediction result of the data conflict between the first instruction and the second instruction can be obtained.
Of course, the present application is not limited thereto, and in other embodiments, the data information further includes a data address and data, on the basis of which the data information corresponding to the second instruction recorded in the data information recording table may include the data address corresponding to the second instruction, and before comparing the data information corresponding to the first instruction with the data information corresponding to the second instruction, the data corresponding to the first instruction may be obtained according to the data address corresponding to the first instruction, and the data corresponding to the second instruction may be obtained according to the data address corresponding to the second instruction.
Based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted, predicting whether the second instructions to be transmitted have the second instructions which conflict with the data of the first instruction or not comprises the following steps: and predicting whether the second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all the second instructions to be transmitted or not and whether the data corresponding to the first instructions are overlapped with the data corresponding to all the second instructions to be transmitted or not.
Specifically, comparing the data address corresponding to the first instruction with the data addresses corresponding to all the second instructions to be transmitted, and after comparing the data corresponding to the first instruction with the data corresponding to all the second instructions to be transmitted, if the data address corresponding to the first instruction at least partially overlaps with the data address corresponding to one second instruction and the data of the first instruction at least partially overlaps with the data of the same second instruction, then the prediction result of the collision between the data of the first instruction and the data of the second instruction can be obtained.
It should be noted that, when the corresponding data is stored in the register corresponding to the instruction, the prediction result may be obtained by adopting a manner based on whether the data address corresponding to the first instruction overlaps with the data addresses corresponding to all the second instructions to be transmitted and whether the data corresponding to the first instruction overlaps with the data corresponding to all the second instructions to be transmitted, or by adopting a manner based on whether the data address corresponding to the first instruction overlaps with the data addresses corresponding to all the second instructions to be transmitted and whether the address register number corresponding to the first instruction is the same as the address register number corresponding to all the second instructions to be transmitted.
However, in the case where the corresponding data is not stored in the register corresponding to the instruction, the prediction result can only be obtained in a manner based on whether the data address corresponding to the first instruction overlaps with the data addresses corresponding to all the second instructions to be transmitted and whether the address register number corresponding to the first instruction is the same as the address register number corresponding to all the second instructions to be transmitted.
It should be further noted that, when the data is stored in a memory such as a memory, each byte has a unique address, based on this, in some embodiments, the data byte size corresponding to the first instruction may be compared with the data byte size corresponding to the second instruction, so as to assist in determining whether the data address corresponding to the first instruction overlaps with the data addresses corresponding to all the second instructions to be transmitted.
In some embodiments of the present application, if one second instruction that conflicts with the first instruction data exists in all the second instructions to be issued, the first instruction is controlled to issue after the one second instruction is issued, so as to control the first instruction to execute after the one second instruction is executed.
In other embodiments, if there are a plurality of second instructions that collide with the first instruction data, controlling the first instruction to be issued after the second instruction issued includes: if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions comprises all data corresponding to the first instruction, controlling the first instruction to be transmitted after the one second instruction is transmitted; and if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions does not comprise all the data corresponding to the first instruction, but at least part of the data corresponding to at least two second instructions closest to the first instruction can form all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the at least two second instructions are transmitted.
That is, in some embodiments, if all the second instructions to be transmitted have a plurality of second instructions that collide with the first instruction data, and the data corresponding to one second instruction closest to the first instruction among the plurality of second instructions includes all the data corresponding to the first instruction, the first instruction is controlled to be transmitted after the one second instruction is transmitted, so as to control the first instruction to be executed after the one second instruction is executed. Wherein, a second instruction closest to the first instruction refers to a second instruction whose transmission time or transmission sequence number is closest to the first instruction.
As shown in fig. 3, the plurality of second instructions that collide with the data of the first instruction are the 1 st second instruction and the 2 nd second instruction … nth second instruction, and the data corresponding to the nth second instruction closest to the first instruction includes all the data corresponding to the first instruction, the first instruction is controlled to be transmitted after the nth second instruction is transmitted, so as to control the first instruction to be executed after the nth second instruction is executed.
In other embodiments, if all the second instructions to be transmitted have a plurality of second instructions that collide with the first instruction data, the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions does not include all the data corresponding to the first instruction, but the data corresponding to at least two second instructions closest to the first instruction may form all the data corresponding to the first instruction, the first instruction is controlled to be transmitted after the at least two second instructions are transmitted, so as to control the first instruction to be executed after the at least two second instructions are executed.
As shown in fig. 4, the plurality of second instructions having data collision with the first instruction are the 1 st second instruction and the 2 nd second instruction, and at least part of the data corresponding to the 1 st second instruction and the 2 nd second instruction can form all the data corresponding to the first instruction, the first instruction is controlled to be transmitted after the 1 st second instruction and the 2 nd second instruction are transmitted, so that the first instruction is controlled to be executed after the 1 st second instruction and the 2 nd second instruction are executed.
Alternatively, as shown in fig. 5, the plurality of second instructions having data collision with the first instruction are the 1 st second instruction, the 2 nd second instruction, the 3 rd second instruction and the 4 th second instruction, respectively, and at least part of data corresponding to the 1 st second instruction, the 2 nd second instruction, the 3 rd second instruction and the 4 th second instruction may form all data corresponding to the first instruction, the first instruction is controlled to be transmitted after the 1 st second instruction, the 2 nd second instruction, the 3 rd second instruction and the 4 th second instruction are transmitted, so as to control the first instruction to be executed after the 1 st second instruction, the 2 nd second instruction, the 3 rd second instruction and the 4 th second instruction are executed.
In some embodiments of the present application, when it is predicted that all second instructions to be transmitted have second instructions that conflict with the data of the first instruction, the first instruction may be marked as an instruction that needs to wait for the second instruction that conflicts with the data of the first instruction to be transmitted and then transmitted, and the instruction identifier of the second instruction that conflicts with the data of the first instruction is saved, so as to determine whether the second instruction is transmitted according to the instruction identifier of the second instruction, so as to wake up and transmit the first instruction after the second instruction is transmitted.
Based on this, in some embodiments of the application, controlling the first instruction to be transmitted after the second instruction is transmitted includes: acquiring an instruction identification of a second instruction which conflicts with the first instruction data; determining whether the second instruction is transmitted according to the instruction identification of the second instruction; if the second instruction has been issued, issuing the first instruction.
For example, as shown in fig. 3, the instruction identifier of the nth second instruction is acquired, and after determining that the nth second instruction has been transmitted according to the instruction identifier of the nth second instruction, the first instruction is transmitted. Alternatively, as shown in fig. 4, the instruction identifiers of the 1 st second instruction and the 2 nd second instruction are obtained, and after the 1 st second instruction and the 2 nd second instruction are determined according to the instruction identifiers of the 1 st second instruction and the 2 nd second instruction, the first instruction is transmitted.
Wherein the instruction identification of the second instruction may also be stored in the data information record table. Specifically, after any second instruction is decoded, the instruction identifier of the second instruction may be obtained, and the instruction identifier of the second instruction is stored in the data information record table as data information corresponding to the second instruction.
As an alternative implementation of the present disclosure, an embodiment of the present disclosure discloses a processor configured to perform the method of transmitting instructions as disclosed in any of the above embodiments. Alternatively, a processor includes at least one processor core configured to perform the instruction issue method as disclosed in any of the embodiments above.
In some embodiments of the present application, as shown in FIG. 6, the processor may include a decode unit 30, a dispatch unit 31, and an execution unit 32. Wherein, the decoding unit 30 is used for fetching and decoding the first instruction and the second instruction; the dispatch unit 31 is configured to obtain data information corresponding to a first instruction before the first instruction is transmitted, predict whether all second instructions to be transmitted have a second instruction that conflicts with the first instruction data based on the data information corresponding to the first instruction and the data information corresponding to all second instructions to be transmitted, and if the second instructions have a second instruction that conflicts with the first instruction data, control the first instruction to be transmitted after the second instruction is transmitted, so as to control the first instruction to be executed after the second instruction is executed; the execution unit 32 is configured to execute a first instruction and a second instruction.
In some embodiments of the present application, the dispatch unit 31 predicts whether the second instructions to be transmitted have the second instructions that collide with the first instruction data based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted, and includes: acquiring data information corresponding to all second instructions to be transmitted based on the data information record table; based on the data information corresponding to the first instruction and the obtained data information corresponding to all the second instructions to be transmitted, predicting whether the second instructions to be transmitted have the second instructions which conflict with the data of the first instruction or not.
In some embodiments of the present application, the dispatch unit 31 is further configured to obtain the data information corresponding to the second instruction after decoding any of the second instructions, and record the data information corresponding to the second instruction in the data information record table.
In some embodiments of the present application, the dispatch unit 31 is further configured to delete the data information corresponding to the second instruction in the data information record table after any of the second instructions is transmitted.
In some embodiments of the present application, the data information includes a data address and an address register number, and the dispatching unit 31 predicts whether the second instructions to be transmitted have second instructions that collide with the data of the first instructions based on the data information corresponding to the first instructions and the data information corresponding to the second instructions to be transmitted, including: and predicting whether all the second instructions to be transmitted have the second instructions which conflict with the data of the first instructions based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all the second instructions to be transmitted and whether the address register numbers corresponding to the first instructions are the same as the address register numbers corresponding to all the second instructions to be transmitted.
In some embodiments of the present application, the data information includes a data address and data, and the dispatch unit 31 predicts whether the second instructions to be transmitted have the second instructions that collide with the data of the first instructions based on the data information corresponding to the first instructions and the data information corresponding to the second instructions to be transmitted, including: predicting whether the second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all the second instructions to be transmitted or not and whether the data corresponding to the first instructions are overlapped with the data corresponding to all the second instructions to be transmitted or not; wherein the data information includes a data address and data.
In some embodiments of the present application, if there are a plurality of second instructions that collide with the first instruction data, the dispatch unit 31 controls the first instruction to be issued after the second instruction is issued, including: if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions comprises all data corresponding to the first instruction, controlling the first instruction to be transmitted after the one second instruction is transmitted; and if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions does not comprise all the data corresponding to the first instruction, but at least part of the data corresponding to at least two second instructions closest to the first instruction can form all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the at least two second instructions are transmitted.
In some embodiments of the present application, the dispatch unit 31 controlling the first instruction to be issued after the second instruction is issued comprises: acquiring an instruction identifier of a second instruction; determining whether the second instruction is transmitted according to the instruction identification of the second instruction; if the second instruction has been issued, the first instruction is issued.
As another alternative implementation of the present disclosure, an embodiment of the present disclosure discloses a computer-readable storage medium having stored thereon instructions for executing the instruction transmitting method disclosed in any of the above embodiments.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
As another optional implementation of the disclosure, an embodiment of the present disclosure discloses an electronic device, which includes a processor as disclosed in any one of the embodiments above. As shown in fig. 7, the electronic device may include one or more processors 40 and one or more memories 41. It is to be understood that the electronic device may include other components as desired.
The electronic device may be loaded and thus include one or more applications. These applications are sets of instructions (e.g., computer program code) that, when read by the one or more processors 40, control the operation of the electronic device. To this end, the one or more memories 41 may include instructions/data executable by the one or more microprocessors 40, whereby the electronic device may perform a method in accordance with at least one embodiment of the present disclosure.
As an alternative implementation of the present disclosure, embodiments of the present disclosure disclose a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the method of transmitting instructions as disclosed in any of the embodiments above.
The computer program product may include program code for carrying out operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as python, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.
Claims (11)
1. A method of transmitting instructions, comprising:
before a first instruction is transmitted, acquiring data information corresponding to the first instruction;
predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on the data information corresponding to the first instructions and the data information corresponding to all second instructions to be transmitted;
if a second instruction which conflicts with the first instruction data exists, controlling the first instruction to be transmitted after the second instruction is transmitted so as to control the first instruction to be executed after the second instruction is executed;
if there are multiple second instructions that collide with the first instruction data, the controlling the first instruction to be transmitted after the second instruction is transmitted includes:
if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions comprises all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the one second instruction is transmitted;
and if the data corresponding to one second instruction closest to the first instruction in the plurality of second instructions does not comprise all the data corresponding to the first instruction, but at least partial data corresponding to at least two second instructions closest to the first instruction can form all the data corresponding to the first instruction, controlling the first instruction to be transmitted after the at least two second instructions are transmitted.
2. The method according to claim 1, wherein predicting whether the second instructions to be transmitted have second instructions that collide with the first instruction data based on the data information corresponding to the first instructions and the data information corresponding to the second instructions to be transmitted includes:
acquiring data information corresponding to all second instructions to be transmitted based on the data information record table;
and predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data or not based on the data information corresponding to the first instructions and the obtained data information corresponding to all second instructions to be transmitted.
3. The instruction transmitting method according to claim 2, characterized by further comprising:
and after any second instruction is decoded, acquiring the data information corresponding to the second instruction, and recording the data information corresponding to the second instruction in the data information recording table.
4. A method of transmitting instructions according to claim 2 or 3, further comprising:
and after any second instruction is transmitted, deleting the data information corresponding to the second instruction in the data information record table.
5. The method according to claim 1, wherein the data information includes a data address and an address register number, and the predicting whether the second instruction has a collision with the first instruction data in all the second instructions to be transmitted based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted includes:
and predicting whether all second instructions to be transmitted have second instructions which conflict with the data of the first instructions based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all second instructions to be transmitted and whether the address register numbers corresponding to the first instructions are the same as the address register numbers corresponding to all second instructions to be transmitted.
6. The method according to claim 1, wherein the data information includes a data address and data, and the predicting whether there is a second instruction that conflicts with the first instruction data in all the second instructions to be transmitted based on the data information corresponding to the first instruction and the data information corresponding to all the second instructions to be transmitted includes:
and predicting whether all second instructions to be transmitted have second instructions which conflict with the first instruction data based on whether the data addresses corresponding to the first instructions are overlapped with the data addresses corresponding to all second instructions to be transmitted or not and whether the data corresponding to the first instructions are overlapped with the data corresponding to all second instructions to be transmitted or not.
7. The instruction transmission method according to claim 1, wherein the controlling the first instruction to be transmitted after the second instruction is transmitted includes:
acquiring an instruction identifier of the second instruction;
determining whether the second instruction is transmitted according to the instruction identification of the second instruction;
and if the second instruction is transmitted, transmitting the first instruction.
8. The instruction issue method of claim 1, wherein said first instruction comprises a load instruction and said second instruction comprises a store instruction.
9. A processor configured to perform the method of instruction transmission of any one of claims 1 to 8.
10. An electronic device comprising the processor of claim 9.
11. A computer-readable storage medium having stored thereon instructions for executing the instruction transmitting method according to any one of claims 1 to 8.
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