CN112368676A

CN112368676A - Method and apparatus for processing data

Info

Publication number: CN112368676A
Application number: CN201980039501.1A
Authority: CN
Inventors: 仇晓颖; 韩彬; 吴迪
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2021-02-12
Also published as: WO2021056541A1

Abstract

A method and apparatus for processing data, the method comprising: receiving at least one request signal sent by a first device (S110), wherein the data processing tasks requested to be processed by any one request signal in the at least one request signal are at most M; storing address information of an mth data processing task requested by an nth request signal in the at least one request signal in an address register of an nth row and an mth column in an address register array of N rows and M columns, wherein N is greater than or equal to the number of the at least one request signal; and selecting a plurality of data processing tasks with non-conflicting address information in the at least one request signal for simultaneous processing according to the address information of each data processing task in the at least one request signal (S120). Therefore, the method and the device for processing data can reduce processing time delay under the condition that bank conflicts occur in read-write tasks in storage devices formed by multiple banks on a chip.

Description

Method and apparatus for processing data

Copyright declaration

The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.

Technical Field

The present application relates to the field of data processing, and in particular, to a method and apparatus for processing data.

Background

Nowadays, technologies such as Single Instruction Multiple Data (SIMD), Very Long Instruction Word (VLIW), Memory (Memory) interleaving structure, etc. are widely applied to various processors to improve the processing efficiency of the processors. An interleaved memory structure is formed by splicing a plurality of blocks (banks), and under the condition of fully utilizing a SIMD structure and a VLIW structure, the condition that a certain clock cycle (cycle) accesses the same memory bank often occurs, so that memory bank conflict (conflict) is caused.

Disclosure of Invention

The application provides a method and equipment for processing data, which can reduce processing time delay under the condition that bank conflicts occur in read-write tasks in storage equipment consisting of multiple banks on a chip.

In a first aspect, a method for processing data is provided, including: receiving at least one request signal sent by a first device, wherein the number of data processing tasks requested to be processed by any one request signal in the at least one request signal is at most M, and M is greater than or equal to 1; storing address information of data processing tasks requested by the at least one request signal in an address register array, wherein the address register array comprises N rows and M columns of address registers, and the address information of the mth data processing task requested by the nth request signal in the at least one request signal is stored in the address registers of the mth row and M columns in the address register array, wherein N is a positive integer which is greater than or equal to 1 and less than or equal to N, M is a positive integer which is greater than or equal to 1 and less than or equal to M, and N is greater than or equal to the number of the at least one request signal; selecting a plurality of data processing tasks with non-conflicting address information in the at least one request signal according to the address information of each data processing task in the at least one request signal; and simultaneously processing the plurality of data processing tasks.

In a second aspect, a method of processing data is provided, comprising: if the number of the uncompleted request signals in the second equipment is smaller than a preset value, sending at least one request signal to the second equipment, wherein the sum of the number of the at least one request signal and the number of the uncompleted request signals is smaller than or equal to the preset value, and each request signal is used for requesting the second equipment to process at least one data processing task; receiving a first completion signal sent by the second device, where the first completion signal is used to indicate that all data processing tasks included in a first request signal are completed, and the first request signal is any one of the at least one request signal and the incomplete request signal.

Based on the above scheme of the present application, a receiving end device may receive multiple request signals simultaneously, the receiving end device may be a storage device, the storage device selects data processing tasks with non-conflicting address information from the multiple request signals to perform simultaneous processing, and the processing tasks with conflicting addresses are processed according to a receiving sequence, so that bank conflicts occurring when reading and writing in a storage device formed by multiple banks on a chip can be processed, and compared with a conventional mechanism, delays (latency) caused by the bank conflicts are reduced, thereby improving parallel access processing efficiency.

In a third aspect, a second device for processing data is provided, configured to perform the method of the first aspect or any possible implementation manner of the first aspect. In particular, the second device comprises means for performing the method of the first aspect described above or any possible implementation manner of the first aspect.

In a fourth aspect, there is provided a first device for processing data for performing the method of the second aspect or any possible implementation manner of the second aspect. In particular, the first device comprises means for performing the method of the second aspect described above or any possible implementation of the second aspect.

In a fifth aspect, there is provided a second apparatus for processing data, comprising: a storage unit for storing instructions and a processor for executing the instructions stored by the memory, and when the processor executes the instructions stored by the memory, the execution causes the processor to perform the first aspect or the method of any possible implementation of the first aspect.

In a sixth aspect, there is provided a first device for processing data, comprising: a storage unit for storing instructions and a processor for executing the instructions stored by the memory, and when the processor executes the instructions stored by the memory, the execution causes the processor to perform the method of the second aspect or any possible implementation manner of the second aspect.

In a seventh aspect, a computer-readable medium is provided for storing a computer program comprising instructions for performing the first aspect or the method in any possible implementation manner of the first aspect.

In an eighth aspect, there is provided a computer readable medium for storing a computer program comprising instructions for performing the method of the second aspect or any possible implementation of the second aspect.

In a ninth aspect, there is provided a computer program product comprising instructions which, when executed by a computer, cause the computer to perform the method of processing data of the first aspect or any possible implementation form of the first aspect. In particular, the computer program product may be run on the second device of the above third aspect.

A tenth aspect provides a computer program product comprising instructions for a computer to perform the method of processing data of the first aspect described above or any possible implementation manner of the first aspect when the fingers of the computer program product are executed by the computer. In particular, the computer program product may be run on the first device of the fourth aspect described above.

In an eleventh aspect, a system for processing data is provided, which includes the second device of the third aspect and the first device of the fourth aspect.

Drawings

Fig. 1 is a schematic flow chart of a method of processing data of an embodiment of the present application.

Fig. 2 is a schematic block diagram of a first device for processing data according to an embodiment of the present application.

Fig. 3 is a schematic block diagram of a second apparatus for processing data according to an embodiment of the present application.

FIG. 4 is a diagram of a register array and processing modules in a second device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Fig. 1 shows a schematic flow diagram of a method 100 of processing data according to an embodiment of the application. As shown in fig. 1, the method 100 includes: s110, sending at least one request signal; i.e. the first device sends at least one request signal to the second device.

It should be understood that each request signal of the embodiments of the present application may be used to request to process one or more data processing tasks, and for convenience of description, the number of data processing tasks requested by each request signal is denoted as M, that is, the number of data processing tasks requested to be processed by each request signal is at most M, where M is a positive integer. For example, for any one request signal, the request signal may be a Read Request (RR) signal, and the data processing task in the request signal may include a read data task, that is, the data processing task may be used to request to read some data from the memory device; alternatively, the request signal may also be a Write Request (WR) signal, and the data processing task in the request signal may comprise a write data task, i.e. the data processing task may be used to request that certain data be written to the storage device.

Correspondingly, the first device in the embodiment of the present application may be any one of the sending-end devices, and the first device may be regarded as a master device (master) and configured to send a request signal to initiate a read or write command; the second device may be any sink device, and the second device may be regarded as a slave device (slave) configured to receive a request signal to passively accept reading or writing, for example, the second device may be a storage device, and the storage device may be a memory including multiple banks on a chip, but the embodiment of the present application is not limited thereto.

Alternatively, the first device and the second device may be two different devices; alternatively, the first device and the second device may also refer to the same device, for example, the first device and the second device correspond to two different functional modules in one device, respectively, and the embodiment of the present application is not limited thereto.

Fig. 2 shows a schematic block diagram of a first device 200 in an embodiment of the present application, and fig. 3 shows a schematic block diagram of a second device 200 in an embodiment of the present application. As shown in fig. 2 and 3, the first device may include a transmission Interface 210, and the second device may include a transmission Interface 310, for example, if the second device is a storage device, the transmission Interface 310 may be a Register Interface (RIF). Correspondingly, in S110, the first device may send at least one request signal to the second device through the transmission interface 210, and the second device receives the at least one request signal through the transmission interface 310.

It should be understood that prior to S110, the method 100 further includes: the first device records the number of outstanding request signals in the second device, for example, as shown in fig. 2, the first device may include a processing module 220, and the processing module 220 may be configured to record the number of outstanding request signals in the second device to decide whether to continue sending request signals or wait for a response from the second device. Specifically, for any request signal sent by the first device to the second device, after completing all data processing tasks requested by the request signal, the second device returns a completion signal to the first device, so that the first device can determine that the request signal is completed.

Therefore, the first device recording the number of outstanding request signals in the second device includes: if the first equipment sends l request signals to the second equipment, increasing the number of the recorded uncompleted request signals in the second equipment by l, wherein l is greater than or equal to 1; in addition, if the first device receives k completion signals corresponding to the k request signals, which are sent by the second device, the number of the recorded incomplete request signals in the second device is reduced by k, and k is greater than or equal to 1.

Correspondingly, the S110 may specifically include: if the number of the incomplete request signals in the second equipment is smaller than a preset value, the first equipment sends at least one request signal to the second equipment, and the sum of the number of the at least one request signal and the number of the incomplete request signals is smaller than or equal to the preset value. On the contrary, if the number of the uncompleted request signals in the second device is greater than or equal to the preset value, the first device determines not to send the request signals to the second device. That is, in order to reduce processing delay and improve throughput, the first device records the number of outstanding request signals in the second device, and when one or more request signals are sent to the second device, the number of outstanding request signals in the second device is guaranteed not to exceed a preset value.

For convenience of description, the preset value is denoted as N, that is, the number of the outstanding request signals in the second device is less than or equal to N, and the specific value of N may be combined with the algorithm investigation to select an appropriate value of N, thereby achieving a trade-off between resources and efficiency. The first device can continuously send N request signals to the second device at most, and if N outstanding request signals (including unanswered read requests (UnansweredRR) and unanswered write tasks (UnanseredWR)) exist in the current second device, the first device needs to wait for responses; the second device only needs to process the data processing task, and returns a completion signal to the first device when all data processing tasks of one request signal are completed.

As shown in fig. 1, the method 100 further includes: s120, processing the data processing task requested by the at least one request signal, that is, the second device processes the data processing task requested by the received at least one request signal. Specifically, as shown in fig. 3, the second device may include a register array 330, and the register array 330 may include a data register array including N rows and M columns of data registers. FIG. 4 shows a schematic diagram of a register array and processing modules of an embodiment of the application. As shown in FIG. 4, the register array 330 may include N rows and M columns of data registers (Reg). According to the fact that the second device receives N request signals at most, each request signal comprises M data processing tasks at most, and the data register array of the N rows and the M columns is arranged to be used for storing data of the data processing tasks included in the request signals corresponding to the request signals received by the second device.

It should be appreciated that, as shown in fig. 3, the second device may further include a control module 320, and the control module 320 may be configured to: and storing data information corresponding to the data processing task requested by the at least one request signal in a data register array, wherein the data information of the mth data processing task requested by the nth request signal in the at least one request signal is stored in the data register of the mth row and the mth column in the data register array, N can be any positive integer greater than or equal to 1 and less than or equal to N, and M can be any positive integer greater than or equal to 1 and less than or equal to M. For example, as shown in FIG. 4, N rows of registers correspond to at most N request signals, and M columns of registers in each row correspond to at most M data processing tasks in a request signal.

Specifically, if a first data processing task of the data processing tasks requested to be processed by the at least one request signal requests to write first data, data information of the first data processing task includes the first data, and a first data register is used for storing the first data to be written before the data processing tasks are processed, where the first data processing task is any one of read data tasks requested by any one of the at least one request signal, and the first data register is a data register in the data register array corresponding to the first data processing task.

Or, if a second data processing task of the data processing tasks requested to be processed by the at least one request signal requests to read second data, the data information of the second data processing task includes the second data, and the second data register is used for storing the read second data after the data processing task is processed, where the second data processing task is any one of the data writing tasks requested by any one of the at least one request signal, and the second data register is a data register in the data register array corresponding to the second data processing task. In addition, before the second data processing task is completed, the second data register may be empty, that is, there is no data information, and the embodiment of the present application is not limited thereto.

Optionally, as shown in fig. 3, the register array 330 in the embodiment of the present application may further include an address register array, where the address register array includes N rows and M columns of address registers, so as to store address information of at least one data processing task requested by a request signal. In particular, the control module 320 in the second device may be configured to: storing address information of the data processing task requested by the at least one request signal in an address register array, wherein the address information of the mth data processing task requested by the nth request signal in the at least one request signal is stored in an address register of the mth row and the mth column in the address register array.

For example, as shown in fig. 4, the register array 330 may include N rows and M columns of address registers (Reg), i.e., the register array in fig. 4 may represent an address register array. According to the fact that the second device receives N request signals at most, each request signal comprises M data processing tasks at most, and the address register array of the N rows and the M columns which are arranged corresponding to the request signals received by the second device can be used for storing address information of the data processing tasks included in the request signals.

It should be understood that the address register array and the data register array in the embodiment of the present application may be two register arrays, that is, the register array 330 includes two register arrays; alternatively, the address register array and the data register array in the embodiment of the present application may also be implemented by only one register array, that is, the register array 330 is one register array, for example, as shown in fig. 4, each register in the register array 330 may be used as both a data register for storing data information and an address register for storing address information, and the embodiment of the present application is not limited thereto.

In this embodiment of the application, the second device selects, according to the address information of each data processing task in the at least one request signal, a plurality of data processing tasks whose address information does not conflict in the at least one request signal; and, the second device may process the plurality of data processing tasks simultaneously. Specifically, as shown in fig. 3, the second device may include at least one processing module 340, and the processing module 340 may be configured to process a data processing task, for example, the processing module 340 may include a bank, that is, the second device may include at least one bank, and one bank may be referred to as one processing module, or multiple banks may also be referred to as one processing module.

For convenience of description, it is described below that the second device includes a plurality of banks, the number of the banks is greater than or equal to M, for example, if the number of the banks is greater than M, since each request signal includes at most M data processing tasks, the at most M data processing tasks requested by any one request signal correspond to at most M banks, that is, for the data processing tasks of any one request signal, there is a portion of the banks that will not be used by the data processing tasks of any one request signal; for another example, the number of banks may also be equal to M, i.e., as shown in fig. 4, it is assumed that there are M banks, which are respectively denoted as B0-B (M-1); and one bank corresponds to one address, different banks have different addresses, the plurality of banks can simultaneously process data processing tasks, and each bank can process read and/or write tasks. Therefore, in the embodiment of the present application, the control module 320 may select a plurality of data processing tasks whose address information does not conflict among the at least one request signal; and, the plurality of data processing tasks are processed simultaneously by the corresponding plurality of banks.

It will be appreciated that the second device may determine the corresponding bank based on the address information for each data processing task. Specifically, as shown in fig. 3, the control module 320 in the embodiment of the present application may be configured to rearrange address information of the data processing task in each request signal. For example, the control module 320 may include an address generating unit and/or an address processing unit to arrange address information corresponding to the data processing task in each request signal and a bank corresponding to the address information.

For convenience of description, it is assumed here that the second device does not include any request signal, that is, there is no data processing task, and if the second device continuously receives n request signals sent by the first device, the n request signals may be stored in n rows of registers in the register array 330, for example, address information of all data processing tasks included in the n request signals may be stored in n rows of the address register array; it is also possible to store data information of all data processing tasks comprised by the N request signals into N rows of the data register array, N being smaller than or equal to N.

Optionally, since the second device needs to process according to the receiving sequence of each data processing task in normal cases, the second device may store the address information and the data information of the data processing tasks of the n request signals according to the receiving sequence, so as to facilitate sequential processing. For example, the address information of all data processing tasks included in the n request signals is sequentially stored in the first n rows of the address register array according to the receiving sequence, and the data processing tasks in each row are also sequentially arranged backwards from the first column according to the receiving sequence; the data information of all the data processing tasks included in the n request signals can be sequentially stored in the first n rows of the data register array according to the receiving sequence, and the data processing tasks in each row are sequentially arranged backwards from the first column according to the receiving sequence. However, the second device may also store the data out of order, for example, indicating the receiving order of the data processing tasks in each request signal through a time identifier, and the embodiment of the present application is not limited thereto. For convenience of description, the embodiment of the present application is described by taking the example of arranging data processing tasks in order and processing in order.

Specifically, it is described first that the second device processes m data processing tasks included in the request signal received first in the first row. The second device has M banks, and the first case is that if there are M data processing tasks in the request signal of the first row, and there is no address conflict between the address information of the M data processing tasks, that is, the M data processing tasks are in one-to-one correspondence with the M banks, then the M data processing tasks can be processed simultaneously by the M banks.

In the second case, if the number of the request signals in the first row is less than M, it is assumed that the first request signal requests to process M data processing tasks, M is less than M, and there is no address conflict between the address information of the M data processing tasks, that is, the M data processing tasks are in one-to-one correspondence with M banks of the M banks, and then the M banks can simultaneously process the corresponding data processing tasks. In addition, there are M-M banks in M that have no data processing task, and at this time, the corresponding data processing task may be continuously searched in the request signal of the second row.

Taking the search for any one of the M-M banks as an example, if the data processing task corresponding to the bank is not found in the second row of request signals, continuing to search for the next row in sequence until the corresponding data processing task is found; if only one data processing task corresponding to the bank is found in the request signal of a certain row, the bank can be processed simultaneously with the m banks processing the data processing tasks of the first row; however, if a certain row of request signals is found to include multiple data processing tasks corresponding to the bank, the bank selects the data processing task received first from the multiple data processing tasks, and processes the data processing task and the m banks processing the data processing tasks in the first row at the same time, and the other data processing tasks corresponding to the bank can be processed in sequence according to the receiving sequence.

In a third case, the first request signal requests to process M data processing tasks, where M is less than or equal to M, and there is a case where multiple data processing tasks correspond to the same bank among the M data processing tasks, that is, an address conflict occurs, then the multiple data processing tasks with the address conflict may not be processed simultaneously, and other data processing tasks without the address conflict may be processed simultaneously. Specifically, for a plurality of data processing tasks with conflicting addresses, the bank corresponding to the data processing tasks together is sequentially processed according to the sequence of the receiving of the data processing tasks from early to late, that is, the common bank processes the first received data processing task first and can process the data processing task simultaneously with other banks, after the first received data processing task is completed, the common bank continues to process another data processing task in the first request signal corresponding to the common bank, and so on.

In addition, in the third case, since an address conflict occurs, at least one bank among the M banks does not have a data processing task corresponding to the request signal of the first row, and at this time, the data processing task may be allocated to the at least one bank with reference to the search manner of the M-M banks in the second case, so that data processing may be performed simultaneously with other banks, thereby saving time.

For example, assume that the second device includes 16 banks, respectively labeled bank0-bank15, and that each of the n request signals received by the second device includes 16 data processing tasks. If the 16 data processing tasks of the first request signal in the first row are respectively marked as 1-16 according to the receiving sequence, and the data processing task marked as 1 corresponds to the bank1, the data processing task marked as 2 corresponds to the bank2, and so on until the data processing task marked as 15 corresponds to the bank15 and the data processing task marked as 16 also corresponds to the bank15, then the data processing tasks 15 and 16 have address conflicts.

Due to the address collision, the second device determines that the bank15 processes the data processing tasks 15 first and then the data processing tasks 16 in the order received. In addition, since the bank0 also has no data processing task due to the address conflict, at least one data processing task corresponding to the bank0 may be looked up in the second request signal corresponding to the second row. Assuming that one or more data processing tasks corresponding to bank0 exist in the second request signal, wherein the data processing task 7 is the earliest received time, in the first round of data processing of the 16 banks, the 16 banks can simultaneously process the respective corresponding first data processing tasks, i.e., bank1-bank15 processes the data processing tasks 1-15 in the first request signal, and bank0 processes the corresponding data processing task 7 in the second request signal. According to this sequence, assuming that the processing time of all the data processing tasks are equal, after the first round of data processing tasks is completed, the bank1-14 continues to process the corresponding data processing task found in the second request signal, while the bank15 needs to process the data processing task 16 in the first request signal, the bank0 continues to process other data processing tasks corresponding to the bank0 in the second request signal except for the data processing task 7, or, in case that other data processing tasks corresponding to the bank0 do not exist in the second request, continues to find the third request signal, and so on.

It will be appreciated that processing each data processing task in each received request signal in turn in the order described above, even if the time required for the bank to process each data processing task is the same, there may still be a variety of possibilities for the order of processing of any two data processing tasks. Taking any two data processing tasks in the at least one request signal as an example, the data processing tasks are respectively referred to as a third data processing task and a fourth data processing task, wherein the third data processing task is received earlier than the fourth data processing task, and the third data processing task and the fourth data processing task may be two processing tasks in the same request signal or may also be two processing tasks in different request signals. Then, in case the time required for processing each data processing task in the at least one request signal by the bank is the same, there are several possibilities for the second device to process the order of the third data processing task and the fourth data processing task as follows.

Specifically, if the address information of the third data processing task is the same as the address information of the fourth data processing task, that is, the addresses of the third data processing task and the fourth data processing task are in conflict with each other, it is impossible to process the two data processing tasks at the same time, and according to the receiving sequence, the second device processes the fourth data processing task after processing the third data processing task, that is, the processing time of the fourth data processing task is later than the processing time of the third data processing task.

However, if the address information of the third data processing task is different from the address information of the fourth data processing task, the second device may further determine the processing order of the third data processing task and the fourth data processing task according to the number of data processing tasks having the same address information as the third data processing task and the number of data processing tasks having the same address information as the fourth data processing task. Specifically, assuming that the number of data processing tasks having the same address information as the third data processing task and having a processing order earlier than the third data processing task is a first value, and the number of data processing tasks having the same address information as the fourth data processing task and having a processing order earlier than the fourth data processing task is a second value, if the first value is equal to the second value, the second device processes the third data processing task and the fourth data processing task at the same time; if the first value is less than the second value, the second device processes the fourth data processing task after processing the third data processing task; if the first value is greater than the second value, the second device processes the fourth data processing task before processing the third data processing task.

For example, assuming that the second device does not currently have a data processing task, and receives a first request signal at this time, the first request signal includes the third data processing task and the fourth data processing task, and address information of the two data processing tasks is different, and address information of each of the two data processing tasks is also different from address information of other data processing tasks, that is, the first value and the second value defined above are both 0, the second device may process the third data processing task and the fourth data processing task at the same time.

Also for example, it is assumed that the second device, when receiving the first request signal, the first request signal comprising the third data processing task and the fourth data processing task, and the address information of the two data processing tasks being different, but before the reception time of the third data processing task, there is a fifth data processing task, the address information of which is the same as the address information of the third data processing task and the address information of the fourth data processing task is different from the address information of the other data processing tasks, then the first value defined above is equal to 1 and the second value is equal to 0, at which time the second device can process the fifth data processing task and the fourth data processing task simultaneously, and after the fifth data processing task is completed, the third data processing task is processed, i.e. the processing time of the third data processing task is later than the processing time of the fourth data processing task.

In summary, according to the address information and the receiving time sequence of each data processing task, one or more data processing tasks may be arranged for each bank, and each bank processes the corresponding data processing tasks in sequence according to the receiving sequence.

Optionally, as shown in fig. 1, the method 100 may further include: s130, a completion signal corresponding to the request signal is sent, that is, for any request signal in the second device, for example, it is referred to as a first request signal here, and if the second device completes all data processing tasks requested by the first request signal, the second device may send a first completion signal to the first device, where the first completion signal is used to indicate that all data processing tasks included in the first request signal are completed. Correspondingly, the first device receives the first completion signal sent by the second device, and determines that the second device has completed the data processing task included in the first request signal, and the first device may subtract 1 from the recorded number of the uncompleted signals in the second device.

It will be appreciated that the second device may determine whether each data processing task is complete based on the identity of that data processing task. Specifically, the second device may determine whether all data processing tasks included in the first request signal are completed according to the identifier of a row of data registers in the data register array corresponding to the first request signal; alternatively, the second device may also determine whether all data processing tasks included in the first request signal are completed according to the identifier of a row of address registers in the address register array corresponding to the first request signal. That is, for each register included in each line of data registers or address registers, an identifier may be set, which indicates that a data processing task of the register is not completed when the identifier shows one value, and indicates that the data processing task in the register is completed when the identifier shows another value.

For example, assume that the data processing task is completed by a flag "1", and that a flag "0" indicates incompletion. For a row of data registers corresponding to the first request signal, if the identifiers of the row of data registers are all displayed as "1", it indicates that the data processing tasks of the row are all completed, and the second device may determine that the first request signal is completed and send a first completion signal to the first device; however, if at least one of the identifiers of the line data register indicates "0", it indicates that the line data processing task is not completed completely, that is, the data processing task corresponding to the data register marked as "0" is not completed.

In this embodiment, if all the data processing tasks included in the first request signal are completed, the second device sends a first completion signal to the first device, where the first completion signal is used to indicate that all the data processing tasks included in the first request signal are completed. Optionally, the second device may process the data processing tasks according to the receiving order, and correspondingly, the second device may return the completion signal according to the receiving order. Specifically, if all data processing tasks included in the first request signal are completed, the second device may send the first completion signal after sending a second completion signal corresponding to a second request signal, where the second request signal is any one of the at least one request signal whose receiving time is earlier than that of the first request signal, and the second completion signal is used to indicate that all data processing tasks included in the second request signal are completed.

It should be appreciated that the first completion signal may be used to indicate that the first request signal is complete, and that other data may also be carried in the first completion signal. Specifically, taking the fifth data processing task in the first request signal as an example, the fifth data processing task is any one data processing task in the first request signal, and if the fifth data processing task requests to read fifth data, the first completion signal includes the fifth data. Alternatively, if the fifth data processing task of the first request signal requests to write fifth data, the fifth data may be included in the first request signal.

Therefore, according to the method and the device for processing data in the embodiment of the application, the storage device can simultaneously receive a plurality of request signals, the data processing tasks with non-conflicting address information in the plurality of request signals are selected for simultaneous processing, and the processing tasks with conflicting addresses are processed according to the receiving sequence, so that bank conflicts (reflicks) generated during reading and writing in the storage device formed by multiple banks on the chip can be processed. However, in the conventional mechanism, when a conflict occurs, the storage device may divide multiple cycles to complete processing of current data, and then receive a next task, that is, receive a next request after one request is completed, which may cause a delay (latency), and the bank with the most conflicts determines the latency size of the current operation. Compared with the traditional mechanism, the embodiment of the application reduces the delay (latency) caused by bank conflict, thereby improving the parallel memory access processing efficiency.

It should be understood that the apparatus of the embodiments of the present application may be implemented based on a memory and a processor, wherein each memory is used for storing instructions for executing the method of the embodiments of the present application, and the processor executes the instructions to make the apparatus execute the method of the embodiments of the present application.

It should be understood that the Processor mentioned in the embodiments of the present Application may be a Central Processing Unit (CPU), and may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory or storage devices referred to in the embodiments of the application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, the memory (memory module) is integrated in the processor.

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Embodiments of the present application further provide a computer-readable storage medium, on which instructions are stored, and when the instructions are executed on a computer, the instructions cause the computer to execute the method of each of the above method embodiments.

An embodiment of the present application further provides a computing device, which includes the computer-readable storage medium.

The embodiment of the application can be applied to the aircraft, especially the unmanned aerial vehicle field.

It should be understood that the division of circuits, sub-units of the various embodiments of the present application is illustrative only. Those of ordinary skill in the art will appreciate that the various illustrative circuits, sub-circuits, and sub-units described in connection with the embodiments disclosed herein can be split or combined.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., Digital Video Disk (DVD)), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It should be understood that the embodiments of the present application are described with respect to a total bit width of 16 bits (bit), and the embodiments of the present application may be applied to other bit widths.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of processing data, comprising:

receiving at least one request signal sent by a first device, wherein the number of data processing tasks requested to be processed by any one request signal in the at least one request signal is at most M, and M is greater than or equal to 1;

storing address information of data processing tasks requested by the at least one request signal in an address register array, wherein the address register array comprises N rows and M columns of address registers, and the address information of the mth data processing task requested by the nth request signal in the at least one request signal is stored in the address registers of the mth row and M columns in the address register array, wherein N is a positive integer which is greater than or equal to 1 and less than or equal to N, M is a positive integer which is greater than or equal to 1 and less than or equal to M, and N is greater than or equal to the number of the at least one request signal;

selecting a plurality of data processing tasks with non-conflicting address information in the at least one request signal according to the address information of each data processing task in the at least one request signal;

and simultaneously processing the plurality of data processing tasks.

2. The method of claim 1, further comprising:

and storing data information corresponding to the data processing task requested by the at least one request signal in a data register array, wherein the data register array comprises N rows and M columns of data registers, and the data information corresponding to the mth data processing task requested by the nth request signal in the at least one request signal is stored in the data register of the mth row and the mth column in the data register array.

3. The method of claim 2,

if a first data processing task of the data processing tasks requested to be processed by the at least one request signal requests to write first data, data information of the first data processing task includes the first data, a first data register is used for storing the first data to be written before the data processing tasks are processed, and the first data register is a data register corresponding to the first data processing task in the data register array;

if a second data processing task of the data processing tasks requested to be processed by the at least one request signal is a request to read second data, the data information of the second data processing task includes the second data, a second data register is used for storing the read second data after the data processing task is processed, and the second data register is a data register corresponding to the second data processing task in the data register array.

4. The method according to any of the claims 1 to 3, characterized in that a third data processing task and a fourth data processing task are any two data processing tasks of the at least one request signal, the third data processing task being received earlier in time than the fourth data processing task,

the method further comprises the following steps:

if the address information of the third data processing task is the same as the address information of the fourth data processing task, processing the fourth data processing task after processing the third data processing task; alternatively, the first and second electrodes may be,

if the address information of the third data processing task is different from the address information of the fourth data processing task, determining the processing sequence of the third data processing task and the fourth data processing task according to the number of the data processing tasks with the same address information as the third data processing task and the number of the data processing tasks with the same address information as the fourth data processing task.

5. The method according to claim 4, characterized in that the third data processing task and the fourth data processing task are any two data processing tasks in the same request signal.

6. The method according to claim 4 or 5, wherein the number of data processing tasks having the same address information as the third data processing task and having a processing order earlier than the third data processing task is a first value, the number of data processing tasks having the same address information as the fourth data processing task and having a processing order earlier than the fourth data processing task is a second value,

the determining a processing sequence of the third data processing task and the fourth data processing task according to the number of the data processing tasks having the same address information as the third data processing task and the number of the data processing tasks having the same address information as the fourth data processing task includes:

if the first value is equal to the second value, processing the third data processing task and the fourth data processing task simultaneously;

if the first value is less than the second value, processing the fourth data processing task after processing the third data processing task;

and if the first value is greater than the second value, processing the fourth data processing task before processing the third data processing task.

7. The method according to any one of claims 1 to 6, further comprising:

determining whether all data processing tasks included in a first request signal are completed according to the identification of a row of data registers corresponding to the first request signal in the data register array, wherein the first request signal is any one of the at least one request signal;

and if the data processing tasks included in the first request signal are all completed, sending a first completion signal to the first device, wherein the first completion signal is used for indicating that the data processing tasks included in the first request signal are all completed.

8. The method of claim 7, wherein sending a first completion signal to the first device if all data processing tasks included in the first request signal are completed comprises:

if all data processing tasks included in the first request signal are completed, after a second completion signal corresponding to a second request signal is sent to the first device, a first completion signal is sent to the first device, the second request signal is any one of the at least one request signal whose receiving time is earlier than that of the first request signal, and the second completion signal is used for indicating that all data processing tasks included in the second request signal are completed.

9. The method according to claim 7 or 8, wherein the first completion signal comprises a fifth data if a fifth data processing task of the first request signal is requesting to read the fifth data.

10. A method of processing data, comprising:

if the number of the uncompleted request signals in the second equipment is smaller than a preset value, sending at least one request signal to the second equipment, wherein the sum of the number of the at least one request signal and the number of the uncompleted request signals is smaller than or equal to the preset value, and each request signal is used for requesting the second equipment to process at least one data processing task;

receiving a first completion signal sent by the second device, where the first completion signal is used to indicate that all data processing tasks included in a first request signal are completed, and the first request signal is any one of the at least one request signal and the incomplete request signal.

11. The method of claim 10, further comprising:

and if the number of the uncompleted request signals in the second equipment is greater than or equal to a preset value, determining not to send the request signals to the second equipment.

12. The method according to claim 10 or 11,

if a first data processing task in the first request signal requests to write first data, the first request signal comprises the first data;

if the second data processing task in the first request signal is a request for reading second data, the first completion signal includes the second data.

13. The method according to any one of claims 10 to 12, further comprising:

recording the number of uncompleted request signals in the second device;

if l request signals are sent to the second equipment, increasing the number of the uncompleted request signals in the second equipment by l, wherein l is greater than or equal to 1;

and if k completion signals which are sent by the second equipment and correspond to the k request signals one by one are received, reducing the number of the uncompleted request signals in the second equipment by k, wherein k is greater than or equal to 1.

14. A second device for processing data, comprising: a transmission interface, an address register array, a control module and a plurality of processing modules, wherein a plurality of addresses corresponding to the processing modules are different,

the transmission interface is used for: receiving at least one request signal sent by a first device, wherein the number of data processing tasks requested to be processed by any one request signal in the at least one request signal is at most M, and M is greater than or equal to 1;

the control module is used for: storing address information of a data processing task requested by the at least one request signal in the address register array, wherein the address register array comprises N rows and M columns of address registers, and the address information of an mth data processing task requested by an nth request signal in the at least one request signal is stored in the address register of the mth row and M columns in the address register array, wherein N is a positive integer greater than or equal to 1 and less than or equal to N, M is a positive integer greater than or equal to 1 and less than or equal to M, and N is greater than or equal to the number of the at least one request signal;

the control module is further configured to: selecting a plurality of data processing tasks with non-conflicting address information in the at least one request signal according to the address information of each data processing task in the at least one request signal, wherein one data processing task in the plurality of data processing tasks corresponds to one processing module, and one processing module in the plurality of processing modules processes one data processing task at most at the same time;

the plurality of processing modules are to: and simultaneously processing the plurality of data processing tasks.

15. The second device of claim 14, further comprising: a data register array comprising N rows and M columns of data registers,

the control module is further configured to: and storing data information corresponding to the data processing task requested by the at least one request signal in the data register array, wherein the data information of the mth data processing task requested by the nth request signal in the at least one request signal is stored in the data register of the mth row and the mth column in the data register array.

16. The second apparatus of claim 15,

17. Second device according to one of the claims 14 to 16, characterized in that a third data processing task and a fourth data processing task are any two data processing tasks of the at least one request signal, the third data processing task being received earlier in time than the fourth data processing task,

the control module is further configured to:

if the address information of the third data processing task is the same as the address information of the fourth data processing task, controlling the plurality of processing modules to process the fourth data processing task after processing the third data processing task; alternatively, the first and second electrodes may be,

18. The second device according to claim 17, wherein the third data processing task and the fourth data processing task are any two data processing tasks in the same request signal.

19. Second device according to claim 17 or 18, characterized in that the number of data processing tasks having the same address information as the third data processing task and having a processing order earlier than the third data processing task is a first value, the number of data processing tasks having the same address information as the fourth data processing task and having a processing order earlier than the fourth data processing task is a second value,

the control module is used for:

if the first value is equal to the second value, controlling the plurality of processing modules to simultaneously process the third data processing task and the fourth data processing task;

if the first value is smaller than the second value, controlling the plurality of processing modules to process the fourth data processing task after processing the third data processing task;

and if the first value is larger than the second value, controlling the plurality of processing modules to process the fourth data processing task before processing the third data processing task.

20. The second device of any of claims 14 to 19, wherein the control module is further configured to:

and if the data processing tasks included in the first request signal are all completed, sending a first completion signal to the first device through the transmission interface, wherein the first completion signal is used for indicating that the data processing tasks included in the first request signal are all completed.

21. The second device of claim 20, wherein the control module is configured to:

if all data processing tasks included in the first request signal are completed, after a second completion signal corresponding to a second request signal is sent to the first device through the transmission interface, the first completion signal is sent to the first device through the transmission interface, the second request signal is any one request signal of which the receiving time is earlier than that of the first request signal in the at least one request signal, and the second completion signal is used for indicating that all data processing tasks included in the second request signal are completed.

22. The second apparatus according to claim 20 or 21, wherein the first completion signal comprises a fifth data if a fifth data processing task of the first request signal is a request to read the fifth data.

23. A first device for processing data, comprising: a transmission interface for the transmission of the data,

the transmission interface is used for: if the number of the uncompleted request signals in the second equipment is smaller than a preset value, sending at least one request signal to the second equipment, wherein the sum of the number of the at least one request signal and the number of the uncompleted request signals is smaller than or equal to the preset value, and each request signal is used for requesting the second equipment to process at least one data processing task;

the transmission interface is further configured to: receiving a first completion signal sent by the second device, where the first completion signal is used to indicate that all data processing tasks included in a first request signal are completed, and the first request signal is any one of the at least one request signal and the incomplete request signal.

24. The first device of claim 23, wherein the first device further comprises:

a processing module to: and if the number of the uncompleted request signals in the second equipment is greater than or equal to a preset value, determining not to send the request signals to the second equipment.

25. The first apparatus according to claim 23 or 24,

26. The first device according to any one of claims 23 to 25, characterized in that the first device further comprises: a processing module to:

recording the number of uncompleted request signals in the second device;

27. A system for processing data, comprising a second device according to any of claims 14-22, and a first device according to any of claims 23-26.

28. A computer-readable medium for storing a computer program comprising instructions for performing the method of any one of claims 1 to 9.

29. A computer-readable medium for storing a computer program comprising instructions for performing the method of any of claims 10 to 13.