CN116981264A

CN116981264A - Phase-change memory array, preparation method, phase-change memory and electronic equipment

Info

Publication number: CN116981264A
Application number: CN202210395719.4A
Authority: CN
Inventors: 周雪; 林军; 王校杰; 秦青; 焦慧芳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-04-14
Filing date: 2022-04-14
Publication date: 2023-10-31
Also published as: WO2023197771A1

Abstract

The embodiment of the application provides a phase-change memory array, a preparation method, a phase-change memory and electronic equipment. The phase-change memory array includes a substrate and a plurality of phase-change memory cells, each phase-change memory cell including: a bottom electrode disposed on a surface of the substrate; a phase change memory part disposed on the bottom electrode; a hard mask top electrode disposed on the phase change memory portion and including a top electrode and a first dielectric layer disposed around the top electrode, a projection of the hard mask top electrode in a direction toward the phase change memory portion coinciding with a cross-section of the phase change memory portion; and a second dielectric layer disposed around the phase change memory portion and the hard mask top electrode. The appearance and the property of the side wall of the phase change storage part can be obviously improved, so that the steepness of the phase change storage part is higher, and the integration level is improved. In addition, by optimizing the etching scheme, the thickness of the top electrode of the hard mask can be reduced, and the stress is reduced, so that the integration difficulty of materials is reduced.

Description

Phase-change memory array, preparation method, phase-change memory and electronic equipment

Technical Field

Embodiments of the present application generally relate to the field of semiconductor device fabrication. More particularly, embodiments of the application relate to a phase change memory, a method of manufacturing the same, and an electronic device.

Background

Non-Volatile Memory (NVM) technology has made some significant progress in many respects, bringing new opportunities for improving storage energy efficiency of computer systems, and researchers have suggested using new NVM technology to replace conventional storage technology, so as to adapt to the demands of computer technology development for high energy efficiency. Various novel NVM technologies represented by the phase change memory (Phase Change Memory) are widely paid attention to by researchers at home and abroad due to the characteristics of high integration level, low power consumption and the like. Phase change memory is a new type of nonvolatile memory technology that uses the conductivity differences exhibited by particular materials when they are transformed between crystalline and amorphous states to store data. The core technical point of the phase change memory is to implement the write '0/1' operation of information by applying different programming pulses to make the phase change memory material switch between crystalline and amorphous states.

The structure of the phase change memory cell is mainly divided into two types: mushroom heads and columnar structures. The technology based on phase change storage in the market at present mainly has two development paths, namely, embedded flash memory is replaced, and a mushroom head structure is adopted as a basic unit structure; and secondly, the basic unit structure of the storage type memory product is a columnar structure. Currently, phase change memory cells have various problems in the integration process. For example, phase change materials have high surface energy, poor adhesion, and are prone to spalling during film growth, and device collapse after small-size patterning. The complex element composition in the current commercial phase change material makes the etching process relatively difficult, easily causes insufficient sidewall sharpness after etching, and is unfavorable for high-density integration of the memory cell. In addition, the material properties of the phase change material change greatly after etching, such as a low density and formation of voids, etc., thereby adversely affecting the performance of the device.

Disclosure of Invention

In order to provide a phase change memory with stable performance and high density integration, embodiments of the application provide a phase change memory, a preparation method and related electronic equipment.

In a first aspect of the present application, a phase change memory array is provided. The phase change memory array includes a substrate and a plurality of phase change memory cells. Each phase change memory cell includes: a bottom electrode disposed on a surface of the substrate; a phase change memory part disposed on the bottom electrode; a hard mask top electrode disposed on the phase change memory portion and including a top electrode and a first dielectric layer disposed around the top electrode, a projection of the hard mask top electrode in a direction toward the phase change memory portion coinciding with a cross-section of the phase change memory portion; and a second dielectric layer disposed around the phase change memory section and the hard mask top electrode.

By forming the hard mask top electrode structure by disposing the first dielectric layer around the top electrode, the etching selectivity when the hard mask top electrode is used as a hard mask to etch the phase change memory portion can be increased. By selecting a proper first dielectric layer material and a corresponding etchant, the appearance and the property of the side wall of the phase-change storage part after etching can be obviously improved, so that the sharpness of the phase-change storage part is higher, and the integration level is improved. In addition, the improvement of the sidewall properties of the phase change memory portion (e.g., small composition and density variation, no voids) can further improve the performance and stability of the semiconductor device. In addition, the thickness of the top electrode of the hard mask can be reduced by increasing the etching selection ratio, so that the stress is reduced, and the integration difficulty of materials is reduced.

In one implementation, the phase change memory portion is made of a phase change memory material. In this way, a phase change memory with higher performance and reliability can be formed.

In one implementation, the top electrode is made of an amorphous material. In this way, the stress of the top electrode and phase change memory portion thin film stack can be further reduced, thereby reducing the likelihood of phase change material spalling during process integration.

In one implementation, the top electrode comprises a tantalum-based metal material or a tungsten-based metal material.

In one implementation, the top electrode comprises TaWSi, taW, or Ta.

In one implementation, the first dielectric layer is made of at least one of the following materials: aluminum oxide and aluminum nitride, and the phase change memory portion is formed by using a CFx-based etchant with the hard mask top electrode as a hard mask. In this way, the morphology and properties of the sidewalls of the phase change memory portion can be further improved, thereby improving the performance and reliability of the fabricated device.

In one implementation, the second dielectric layer is made of at least one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, and aluminum nitride. The second dielectric layer may be made of any suitable material to improve flexibility in manufacturing the semiconductor device.

According to a second aspect of an embodiment of the present application, a method of manufacturing a phase change memory cell is provided. The method comprises sequentially forming a bottom electrode layer, a phase change memory layer and a hard mask top electrode layer on the surface of a substrate; etching the hard mask top electrode layer to form a top electrode; disposing a first dielectric layer around sides of the top electrode to form a hard mask top electrode; etching the phase change memory portion layer using the top electrode and the first dielectric layer as a hard mask to form the phase change memory portion; and disposing a second dielectric layer around the hard mask top electrode and the phase change memory portion.

In one implementation, sequentially forming a bottom electrode layer, a phase change memory layer, and a hard mask top electrode layer on a surface of a substrate includes: forming a bottom electrode layer on the surface of the substrate; etching the bottom electrode layer to form the bottom electrode; depositing an interlayer dielectric material around the bottom electrode; and sequentially forming a phase change memory layer and the hard mask top electrode layer on the bottom electrode and the interlayer dielectric material.

In one implementation, the method further includes etching the bottom electrode layer with the hard mask top electrode, the phase change memory portion, and the second dielectric layer as a mask to form a bottom electrode.

In one implementation, disposing a first dielectric layer around the top electrode sides to form a hard mask top electrode includes: providing a first dielectric material layer outside the top electrode and the phase change memory section layer; the first dielectric material layer is etched to form the first dielectric layer around the top electrode.

In one implementation, disposing a second dielectric layer around the hard mask top electrode and the phase change memory portion includes: providing a second dielectric material layer outside the hard mask top electrode and the phase change memory portion; the second dielectric material layer is etched to form the second dielectric layer around the hard mask top electrode and the phase change memory portion.

In one implementation, the etchant used to etch the hard mask top electrode layer comprises a chlorine-based etchant; and/or the etchant used to etch the first dielectric material layer or the second dielectric material layer comprises a chlorine-based etchant.

In one implementation, the etchant used to etch the phase change memory layer comprises a CFx-based etchant, and wherein the first dielectric layer is made of at least one of the following materials: alumina and aluminum nitride.

According to a third aspect of embodiments of the present application, there is provided a phase change memory. The phase change memory comprises the phase change memory array and the control circuit according to the first aspect of the embodiment of the application. A control circuit is coupled to the phase change memory array and is adapted to control at least a state of the phase change memory portion.

According to a fourth aspect of embodiments of the present application, there is provided an electronic device. The electronic device comprises a circuit board and the phase change memory according to the third aspect of the embodiment of the application formed on the circuit board.

Drawings

The above and other features, advantages and aspects of embodiments of the present application will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a simplified schematic diagram of a conventional phase change memory cell;

FIG. 2 is a schematic diagram showing various stages in the fabrication of a phase change memory cell having a pillar structure in a conventional scheme;

FIG. 3 is a schematic diagram showing various stages in the fabrication of a mushroom head structured phase change memory cell in a conventional scheme;

FIG. 4 illustrates a schematic diagram of a phase change memory cell having a pillar structure in accordance with an embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a phase change memory cell having a mushroom head structure in accordance with an embodiment of the present disclosure;

FIG. 6 illustrates a flowchart of a method of fabricating a phase change memory cell according to an embodiment of the present disclosure;

FIG. 7 illustrates a schematic diagram of various stages in the fabrication of a phase change memory cell having a pillar structure in accordance with an embodiment of the present disclosure; and

fig. 8 illustrates a schematic diagram of various stages in the fabrication of a mushroom head structured phase change memory cell in accordance with an embodiment of the present disclosure.

Detailed Description

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.

In describing embodiments of the present application, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

It should be understood that in the present application, "disposing" may be understood as being formed in any suitable manner (such as deposition, coating and/or etching, etc.), which may include one or more intermediate steps.

The term "circuit" as used herein refers to one or more of the following: (a) Hardware-only circuit implementations (such as analog-only and/or digital-circuit implementations); and (b) a combination of hardware circuitry and software, such as (if applicable): (i) A combination of analog and/or digital hardware circuitry and software/firmware, and (ii) any portion of a hardware processor and software (including digital signal processors, software, and memory that work together to cause an apparatus, such as a communication device or other electronic device, to perform various functions); and (c) hardware circuitry and/or a processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but may not have software when software is not required for operation. Definition of circuitry applies to all scenarios in which this term is used in this application (including in the claims). As another example, the term "circuitry" as used herein also covers an implementation of only a hardware circuit or processor (or multiple processors), or a portion of a hardware circuit or processor, or accompanying software or firmware. For example, if applicable to particular claim elements, the term "circuitry" also covers a baseband integrated circuit or processor integrated circuit, a network device, a terminal device, or a similar integrated circuit in another device.

Phase change memory (Phase Change Memory, PCM) technology, as a new generation of memory technology, utilizes phase changes in which special materials are mutually converted between crystalline and amorphous states to store data. The writing speed of the phase change Memory adopting the phase change Memory technology is 100 times faster than that of the flash Memory, and the phase change Memory has the advantages of data erasing capability up to millions times, non-volatility and the like, and becomes a relay dynamic random access Memory (Dynamic Random Access Memory, DRAM), a Read-Only Memory (ROM) and a later-on flash Memory of the Memory industry.

Phase change memories are typically integrated from a phase change memory array of a plurality of phase change memory cells. In addition to the phase change memory array, the phase change memory also includes control circuitry for controlling the state of each phase change memory cell in the phase change memory array. The structures of the phase change memory cells are mainly of two types, mushroom head structures and columnar structures. Fig. 1 (a) shows a phase change memory having a mushroom head structure, and fig. 1 (B) shows a phase change memory cell having a pillar structure. As can be seen in fig. 1, a phase change memory cell generally includes a top electrode 5042, a phase change memory portion 503 made of a phase change material, and a bottom electrode 502. The structural difference between the mushroom head structure and the columnar structure is mainly in the bottom electrode 502 portion.

The technology based on phase change storage in the market at present mainly has two development paths, namely, embedded flash memory is replaced, and a mushroom head structure is usually selected as a basic unit structure; and secondly, the basic unit structure of the storage type memory product is usually a columnar structure.

The preparation processes of the phase change memory cells with mushroom head structures and columnar structures are slightly different due to the different structures. Fig. 2 shows a schematic diagram of the various stages of the fabrication process of a phase change memory with pillar structures. In fabricating a phase change memory cell having a pillar structure, a substrate 501 is provided. The substrate referred to herein comprises electronic devices, such as transistors, that are prepared in a preceding process for circuit functions and/or gate functions. Then, a bottom electrode layer 5021, a phase change memory section layer 5031, and a top electrode layer 5041 are sequentially formed on the substrate 501, as shown in (1) of fig. 2. The top electrode layer 5041 is then patterned by photoresist and etched to form a top electrode 5042, as shown in (2) of fig. 2. Subsequently, the phase-change memory portion layer 5031 is etched using the top electrode 5042 as a hard mask to form a phase-change memory portion 503, and a dielectric layer 5044 is deposited outside the top electrode 5042, the phase-change memory portion 503, and the bottom electrode layer 5021, as shown in (3) of fig. 2. Next, the dielectric layer 5044 is etched to leave a certain thickness of the cladding layer 505 on the side of the top electrode 5042 and the phase change memory section 503, as shown in (4) of fig. 2. Finally, as shown in (5) of fig. 2, the bottom electrode layer 5021 is etched with the top electrode 5042 and the phase change memory portion 503 covered with the cover layer 505 as a hard mask to form the bottom electrode 502, and thereby a phase change memory cell forming a pillar structure is finally manufactured.

Fig. 3 is a schematic diagram showing various stages in the fabrication of a phase change memory cell of mushroom head structure. Unlike the preparation of the phase change memory cell of the pillar structure, before the phase change memory portion layer 5031 and the top electrode layer 5041 are provided, the bottom electrode 502 having a predetermined shape is formed by photoresist patterning and etching, then the interlayer dielectric material 506 is provided between the bottom electrodes 502, and then the phase change memory portion layer 5031 and the top electrode layer 5041 are provided outside the bottom electrode 502 and the interlayer dielectric material 506, as shown in (1) of fig. 3. The subsequent process is similar to the earlier steps in the fabrication of the phase change memory cell of the pillar structure by patterning the photoresist and etching the top electrode layer 5041 to form the top electrode 5042, as shown in (2) of fig. 3. Subsequently, the phase-change memory portion layer 5031 is etched using the top electrode 5042 as a hard mask to form a phase-change memory portion 503, and an interlayer dielectric material is further provided outside the top electrode 5042, the phase-change memory portion 503, and the previously provided interlayer dielectric material 506, as shown in (3) of fig. 3, and finally a phase-change memory cell having a mushroom head structure is fabricated.

However, in the process of manufacturing the phase change memory cell, the surface energy of the phase change material is high, the adhesiveness is poor, so that the dielectric layer film is easy to peel off in the growth process (as shown in (3) of fig. 2), and the problem of device collapse is easy to occur after the dielectric layer is subjected to small-size patterning. In addition, the core materials that are widely used in phase change memory cells are typically alloys of germanium antimony tellurium mixed in proportions. In some cases, a fourth element, such as silicon, carbon, copper, etc., may also be doped. The complex elements in the phase change memory material make the etching process very difficult and cause the etched phase change memory to have various defects.

First, the etching process of the phase change material is described. Common etching gases for phase change materials are generally composed of two types: halogen etching gases such as SF6, cl2, and HBr, and hydrogen etching gases such as CH4 and H2. For the commonly used etching gases of these etching gases, the reaction by-products after etching have boiling point, gibbs free energy Δg _rxn The table is shown in Table (1).

Watch (1)

The bond energies of the phase change material and the bond generated by the etching gas are shown in table (2).

Watch (2)

Key with a key	Bond energy (kJ/mol)	Key with a key	Bond energy (kJ/mol)	Key with a key	Bond energy (kJ/mol)
						Ge-F	485±21	Sb-F	439±21	Te-F	N.A.
Ge-Cl	431	Sb-Cl	360±59	Te-Cl	N.A.
						Ge-Br	276	Sb-Br	314±59	Te-Br	N.A.
Ge-H	263.2	Sb-H	239	Te-H	270

From the boiling point relationship in Table (1), germanium (Ge) is typically removed first, followed by antimony (Sb) and then tellurium (Te) during etching due to the lowest boiling point of reaction with the etching gas. As the etching process advances, the sidewalls of the finally formed etched device (i.e., the aforementioned phase change memory portion) will be depleted of Ge, while enriched in Sb and Te. The differences in material composition can cause the resulting devices to perform erratically and even fail. In addition to the difference in material composition, the material properties of the sidewalls of the phase change memory portion change significantly, e.g., the material density becomes low and even voids are formed, which can adversely affect the performance of the device. In addition, as can be seen from table (2) for different halogen etching gases, the bond energy between fluorine-based gases and Ge, sb is higher than that between chlorine-based and bromine-based gases, so that the degree of halogenation of the device after etching is fluorine > chlorine > bromine, which also affects the performance of the device.

For hydrogen-based etchants, the etch by-products (hydrides) are high volatile, and for volatility, ge > Sb > Te, which can cause environmental contamination as well as the aforementioned device composition and property variations. In addition, because the radius of the hydrogen atoms is small, compared with the halogenation degree of halogen gas, the hydrogen etchant is adopted to cause the hydrogenation degree of the phase change material to have larger influence on the device, thereby further deteriorating the performance of the device. Therefore, a halogen gas is used as an etchant in a large amount, and a hydrogen-based gas etchant is used in a small amount.

Furthermore, in an ideal case, the etched top electrode and the phase change memory section have substantially vertical sidewalls, that is, substantially have columnar structures having the same upper and lower dimensions. However, due to various factors such as reaction between the phase change material and the etching gas, the sharpness of the phase change memory part after etching is insufficient. This means that the phase change memory portion has a generally frustoconical shape with a small top and a large bottom. This lack of sharpness in the phase change memory section presents a subsequent set of problems that affect the performance and stability of the final fabricated device. For example, the bottom of the frustum-shaped phase change memory portion has a larger size, which is disadvantageous in forming a high-density array of semiconductor devices and ultimately affects high-density integration of memory cells.

In the case of mushroom head phase change memory cells, during the integration process of the mushroom head phase change memory cells (e.g., as shown in (3) of fig. 3), since the phase change memory portion made of the phase change material is in direct contact with the interlayer dielectric material, the phase change material is easily peeled off from the interlayer dielectric material due to the excessive influence of the accumulated stress, thereby causing the problem of failure of the finally formed device.

To address or at least partially address the above-mentioned or other potential problems with semiconductor devices such as phase change memories, embodiments in accordance with the present disclosure provide a method of fabricating a phase change memory cell and a phase change memory array including a plurality of phase change memory cells and a phase change memory. The phase change memory includes a phase change memory array and a control circuit coupled to the phase change memory array. The phase change memory array includes a plurality of phase change memory cells arranged together through an integration step. Fig. 4 and 5 illustrate schematic diagrams of a phase change memory cell of a pillar structure and a mushroom head structure, respectively, prepared by a method according to an embodiment of the present disclosure. As shown in fig. 4 and 5, in general, a phase change memory array according to an embodiment of the present disclosure includes a substrate 101 and a plurality of phase change memory cells disposed on the substrate 101. Each phase change memory cell includes a bottom electrode 102, a phase change memory section 103, and a hard mask top electrode 104. A bottom electrode 102 is disposed on the surface of the substrate 101, a phase change memory part 103 is disposed on the bottom electrode 102, and a hard mask top electrode 104 is disposed on the phase change memory part 103. In some embodiments, the phase change memory portion 103 may be made of a phase change memory material. As mentioned previously, a phase change memory material is a material that is capable of switching between crystalline and amorphous states in response to an electrical pulse applied thereto. The control circuit can control at least the state of the phase change memory section to realize the storage of data. The phase change memory material is typically an alloy of germanium, antimony and tellurium. In some embodiments, the phase change memory material may also include elements such as silicon, carbon, or copper. Embodiments according to the present disclosure will be described hereinafter mainly with an example in which a core element (i.e., the phase-change memory portion 103) is made of a phase-change memory material, and it should be understood that any suitable semiconductor device in which the above-described situation may exist will also be applicable, and will not be described separately hereinafter.

Unlike a conventional phase change memory cell, the hard mask top electrode 104 according to an embodiment of the present disclosure includes a dielectric layer (hereinafter, will be referred to as a first dielectric layer 1043) disposed around the top electrode 1042, in addition to the top electrode 1042 itself. As is well known, the conductive properties of the dielectric layer are far less than those of the top electrode 1042 made of a metallic material, and the hard mask top electrode 104 herein is merely a term indicating where it is located in the semiconductor device, whether the portion of the hard mask top electrode 104 actually functions as an electrode or as a top electrode 1042. The first dielectric layer 1043 is different from the cladding layer 505 mentioned above. The first dielectric layer 1043 is etched as a hard mask together with the top electrode 1042 in the process of etching the phase change memory part 103. That is, during the fabrication of the phase change memory, the hard mask top electrode 104, including the first dielectric layer 1043 and the top electrode 1042, is used as a whole hard mask to etch the phase change memory portion layer 1031 to fabricate the phase change memory portion 103, which will be further described below. In this way, the projection of the hard mask top electrode 104 of the phase change memory cell in the prepared phase change memory in the direction toward the phase change memory portion 103 coincides with the cross section of the phase change memory portion 103. It is, of course, understood that the difference in the degree of coincidence between the two can be regarded as coincidence mentioned herein by floating in the range of + -5% to + -10% of the dimension of the two due to the influence of the manufacturing accuracy and the like.

By providing the first dielectric layer 1043 at the side portion, when the hard mask top electrode 104 is used as a hard mask to etch the phase change memory section layer 1031, the dielectric material of the first dielectric layer 1043 is not the top electrode but the side portion is in direct contact with the etching gas. By selecting an appropriate dielectric material as the first dielectric layer 1043, an etching selection ratio of etching the phase-change memory portion 103 made of the phase-change material can be significantly improved. For example, in some embodiments, the first dielectric layer 1043 may be made of at least one of the following materials: aluminum oxide and aluminum nitride, and CFx-based etchant may be selected when forming the phase change memory portion 103 by etching with the hard mask top electrode 104 as a hard mask. The CFx-based etchant has a higher etching selectivity to the first dielectric layer 1043 made of aluminum oxide and/or aluminum nitride and the phase-change memory section 103 made of a phase-change material. The improvement of the etching selectivity ratio brings about the reduction of the influence on the side wall of the phase change memory part 103, so that the improvement of the etching morphology of the side wall of the phase change memory part 103, namely, the sharpness can be remarkably improved, and the ideal situation can be basically achieved.

The increase in the sharpness of the phase change memory section 103 means that the upper and lower ends of the phase change memory section 103 have substantially uniform dimensions. This can facilitate the formation of a high density array of phase change memory cells and ultimately allow for higher integration of the phase change memory array, and thus the entire semiconductor device. The improvement of the etching selection ratio of the etching gas to the hard mask top electrode 104 and the phase change memory section 103 can also bring about a smaller change in the property of the side wall of the phase change memory section 103, i.e., a smaller difference in density throughout the phase change memory section 103, and also reduce the probability of void generation, etc. In addition, an increase in etch selectivity can also be beneficial in reducing the thickness of the hard mask top electrode 104 in contact therewith. The reduced thickness of the hard mask top electrode 104 further reduces the stress on the top electrode 1042, which makes the bond between them more secure, thereby further contributing to the improved stability of the device.

It should be appreciated that the embodiments described above in which the first dielectric layer 1043 is alumina and/or aluminum nitride and the etchant is CFx based are exemplary only and are not intended to limit the scope of the present disclosure. By selecting a proper material of the first dielectric layer 1043 and selecting an etchant corresponding to the material, the etching morphology and properties of the side wall of the etched phase change memory 103 can be significantly improved, thereby being beneficial to improving the performance of the prepared semiconductor device.

In some embodiments, to further reduce stress between the phase change memory portion 103 and the adjacent top electrode 1042, the top electrode 1042 may be made of an amorphous material. The Amorphous (amorphlus) material referred to herein is an Amorphous metal alloy, and refers to a metal material having a disordered structure on an atomic scale, which can be prepared by physical vapor deposition or the like. For example, in some embodiments, the top electrode 1042 may be made of a tantalum-based metal material or a tungsten-based metal material such as TaWSi, taW, or Ta, so that the stress between the phase change memory part 103 and the top electrode 1042 can be further reduced, thereby reducing the difficulty of integration of the semiconductor device material.

The phase change memory cell according to the present disclosure further includes a second dielectric layer 105 formed at the sides of both the phase change memory part 103 and the hard mask top electrode 104, as shown in fig. 4 and 5.

In some embodiments, the second dielectric layer 105 may be made of the same material as the first dielectric layer 1043, such as aluminum oxide and/or aluminum nitride, so that the dielectric layers formed at the sides of the top electrode 1042 and the sides of the phase change memory part 103 are only different in thickness. In some alternative embodiments, the second dielectric layer 105 may also be made of a different material than the first dielectric layer 1043. For example, the second dielectric layer 105 may be made of at least one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and the like, thereby improving the degree of freedom in material selection and reducing the manufacturing cost of the semiconductor device.

There is also provided, in accordance with an embodiment of the present disclosure, a method of fabricating a phase change memory cell as described herein before. Fig. 6 shows a flowchart of a method of fabricating the phase change memory cell, fig. 7 shows a schematic diagram of stages of fabricating a phase change memory cell of a pillar structure, and fig. 8 shows a schematic diagram of stages of fabricating a phase change memory cell of a mushroom head structure. The substrate 101 is provided prior to the fabrication of the phase change memory cell. As mentioned previously, the substrate 101 mentioned herein includes electronic devices such as transistors, etc. for the functions of the circuit functions and/or the gating functions prepared in the previous process, which may include or constitute the control circuit mentioned previously. After the substrate 101 is provided, a bottom electrode layer 1021, a phase change memory section layer 1031, and a hard mask top electrode layer 1041 are sequentially formed on the surface of the substrate 101 at block 410. For the semiconductor device of the columnar structure, as shown in (1) in fig. 7, the above layers may be formed separately by depositing the corresponding materials layer by layer.

For a mushroom head structured phase change memory cell, in some embodiments, the bottom electrode layer 1021 may be formed first as follows. First, a bottom electrode layer 1021 may be formed on the surface of the substrate 101, as shown in (1.1) of fig. 8. The bottom electrode 102 having a predetermined shape is then formed by photoresist patterning, etching, as shown in (1.2) of fig. 8. A new bottom electrode layer 1021 is then formed by depositing and then chemical mechanical planarization (Chemical Mechanical Planarization, CMP) of the interlayer dielectric material around the bottom electrode 102. Phase change memory layer 1031 and hard mask top electrode layer 1041 are then disposed outside of bottom electrode 102 and the interlayer dielectric material, as shown in fig. 8 (1).

After forming the bottom electrode layer 1021, the phase change memory section layer 1031, and the hard mask top electrode layer 1041, respectively, next, at block 420, the hard mask top electrode layer 1041 is etched to form a top electrode 1042 after patterning the hard mask top electrode layer 1041 with photoresist, as shown in (2) of fig. 7 and 8. In some embodiments, the etchant used for etching the hard mask top electrode 104 may comprise a chlorine-based etchant. Next, at 430, a first dielectric layer 1043 is disposed around the top electrode 1042 to form the hard mask top electrode 104 mentioned previously, as shown in (3) in fig. 7 and 8. The placement of the first dielectric layer 1043 around the top electrode 1042 may be achieved by any suitable means. For example, in some embodiments, as shown in (2.1) of fig. 7 and 8, a first dielectric material layer 1044 is provided outside the top electrode 1042 and the phase change memory layer 1031 by deposition or the like. However, the first dielectric material layer 1044 is etched to form a first dielectric layer 1043 having a certain thickness around the top electrode 1042, thereby forming the hard mask top electrode 104. In some embodiments, the etchant used for etching the first dielectric material layer 1044 may include a chlorine-based etchant.

After forming the hard mask top electrode 104 having the first dielectric layer 1043, the phase-change memory portion layer 1031 is etched using the hard mask top electrode 104 as a hard mask to form the phase-change memory portion 103, as shown in (4) of fig. 7 and 8, at 440. In this way, the etching selectivity of the etchant to the hard mask top electrode 104 and the phase change memory section layer 1031 can be increased. As mentioned above, by selecting an appropriate etchant to etch the phase-change memory portion 1031 according to the material of the first dielectric layer 1043, the etching morphology and properties of the phase-change memory portion 103, and in particular, the sidewalls of the phase-change memory portion 103, can be further improved, thereby facilitating improvement of the performance and reliability of the semiconductor device while improving the integration of the semiconductor device. In addition, the increase in etch selectivity is also beneficial in reducing the thickness of the hard mask top electrode layer 1041, thereby reducing stress and thus reducing the difficulty of integration between materials of the semiconductor device. In addition, as mentioned previously, the top electrode 1042 in the hard mask top electrode 104 may be made of an amorphous material such as tantalum-based metal material or tungsten-based metal material, thereby facilitating further stress reduction.

After forming the hard mask top electrode 104, at block 450, a second dielectric layer 105 is formed around the hard mask top electrode 104 and the functional layer, as shown in (5) in fig. 7 and 8. Forming the second dielectric layer 105 on the sides of the hard mask top electrode 104 and the functional layer may be accomplished by any suitable means. For example, in some embodiments, the second dielectric material layer 1051 is disposed outside the top electrode 1042 and the phase change memory section layer 1031 by deposition or the like, as shown in (4.1) of fig. 7. Subsequently, for a mushroom head structured phase change memory cell, the second dielectric layer material on top of the hard mask top electrode 104 may be removed by etching, as shown in fig. 8 (5). For a phase change memory cell of columnar structure, the form shown in fig. 7 (5) may be formed by etching the second dielectric material layer 1051, thereby removing the second dielectric layer on top of the hard mask top electrode 104 and outside the bottom electrode layer 1021. For a phase change memory cell of a pillar structure, bottom electrode layer 1021 is then etched with hard mask top electrode 104, phase change memory portion 103 and second dielectric layer 105 as a mask to form bottom electrode 102, as shown in (5.1) of fig. 7.

It should be understood, of course, that the process of forming one phase change memory cell in a phase change memory array is described above by reference to the accompanying drawings. It should be appreciated that a phase change memory array formed of a plurality of phase change memory cells may be formed on the substrate 101. After the basic structure of each phase change memory cell is formed, an interlayer dielectric material may be disposed around the phase change memory cells to integrate them to ultimately form the desired phase change memory array.

There is also provided, in accordance with an embodiment of the present disclosure, a phase change memory. The phase change memory comprises the phase change memory array and the control circuit mentioned in the foregoing. As mentioned previously, the control circuit is coupled to the phase change memory array and can control at least the state of the phase change memory portion, thereby enabling the storage of data.

There is also provided an electronic apparatus according to an embodiment of the present disclosure, including a circuit board and a semiconductor device according to the foregoing, the semiconductor device being formed on the circuit board. By the improvement of the performance and stability of the semiconductor device described in the foregoing, the performance and reliability of the electronic apparatus using the same can be improved.

Although the application has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely examples of implementing the claims.

Claims

1. A phase change memory array, comprising:

a substrate; and

a plurality of phase change memory cells, each of the phase change memory cells comprising:

a bottom electrode disposed on a surface of the substrate;

a phase change memory part disposed on the bottom electrode;

a hard mask top electrode disposed on the phase change memory portion and including a top electrode and a first dielectric layer disposed around the top electrode, a projection of the hard mask top electrode in a direction toward the phase change memory portion coinciding with a cross-section of the phase change memory portion; and

a second dielectric layer disposed around the phase change memory portion and the hard mask top electrode.

2. The phase-change memory array of claim 1, wherein the phase-change memory portion is made of a phase-change memory material.

3. The phase change memory array of claim 1 or 2, wherein the top electrode is made of an amorphous material.

4. The phase-change memory array of any one of claims 1-3, wherein the top electrode comprises a tantalum-based metal material or a tungsten-based metal material.

5. The phase-change memory array of claim 4, wherein the top electrode comprises TaWSi, taW, or Ta.

6. The phase-change memory array of any one of claims 1-5, wherein the first dielectric layer is made of at least one of the following materials: alumina and aluminum nitride, and

the phase change memory portion is formed by using a CFx-based etchant with the hard mask top electrode as a hard mask.

7. The phase-change memory array of any one of claims 1-6, wherein the second dielectric layer is made of at least one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.

8. A method for fabricating a phase change memory cell, comprising:

sequentially forming a bottom electrode layer, a phase change memory part layer and a hard mask top electrode layer on the surface of the substrate;

etching the hard mask top electrode layer to form a top electrode;

disposing a first dielectric layer around the top electrode to form a hard mask top electrode;

etching the phase change memory portion layer using the top electrode and the first dielectric layer as a hard mask to form the phase change memory portion; and

a second dielectric layer is disposed around the hard mask top electrode and the phase change memory portion.

9. The method of claim 8, wherein sequentially forming a bottom electrode layer, a phase change memory layer, and a hard mask top electrode layer on a surface of a substrate comprises:

forming a bottom electrode layer on the surface of the substrate;

etching the bottom electrode layer to form the bottom electrode;

depositing an interlayer dielectric material around the bottom electrode; and

a phase change memory layer and the hard mask top electrode layer are sequentially formed on the bottom electrode and the interlayer dielectric material.

10. The method of claim 8, further comprising:

and etching the bottom electrode layer by taking the hard mask top electrode, the phase change memory part and the second dielectric layer as masks to form a bottom electrode.

11. The method of any of claims 8-10, wherein disposing a first dielectric layer around the top electrode to form a hard mask top electrode comprises:

providing a first dielectric material layer outside the top electrode and the phase change memory section layer;

the first dielectric material layer is etched to form the first dielectric layer around the top electrode.

12. The method of any of claims 8-10, wherein disposing a second dielectric layer around the hard mask top electrode and the phase change memory portion comprises:

providing a second dielectric material layer outside the hard mask top electrode and the phase change memory portion;

the second dielectric material layer is etched to form the second dielectric layer around the hard mask top electrode and the phase change memory portion.

13. The method of claim 11, wherein the etchant used to etch the hard mask top electrode layer comprises a chlorine-based etchant; and/or

The etchant used to etch the first dielectric material layer or the second dielectric material layer includes a chlorine-based etchant.

14. The method of any of claims 8-10 and 13, wherein the etchant used to etch the phase change memory layer comprises a CFx-based etchant, and

wherein the first dielectric layer is made of at least one of the following materials: alumina and aluminum nitride.

15. A phase change memory, comprising:

the phase change memory array of any one of claims 1-7; and

a control circuit is coupled to the phase change memory array and adapted to control at least a state of the phase change memory portion.

16. An electronic device, comprising:

a circuit board; and

the phase change memory of claim 15, disposed on the circuit board.