CN116978863A

CN116978863A - Display panel, array substrate and manufacturing method thereof

Info

Publication number: CN116978863A
Application number: CN202310802606.6A
Authority: CN
Inventors: 王睿轩; 谢俊烽
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-10-31

Abstract

The application discloses a display panel, an array substrate and a manufacturing method thereof, wherein the method comprises the following steps: s10: providing a substrate, forming a first metal layer on the substrate, patterning the first metal layer by using a first photomask to form a grid, and sequentially forming a grid insulating layer, a semiconductor layer and a second metal layer on the grid and the substrate, wherein the grid insulating layer is made of silicon oxide or silicon nitride; the second metal layer comprises a first region and a second region; s20: patterning the second metal layer and the semiconductor layer of the first region by using a second photomask to form a source electrode, a drain electrode and an amorphous silicon island; in the orthographic projection direction of the array substrate, the edge of the amorphous silicon island is larger than the edges of the source electrode and the drain electrode; s25: and patterning the second metal layer of the second region by using a third photomask to form a wiring region. The application combines the 4Mask process and the 5Mask process, thereby improving the yield and reinforcing the film structure.

Description

Display panel, array substrate and manufacturing method thereof

Technical Field

The application relates to the technical field of display, in particular to a display panel, an array substrate and a manufacturing method thereof.

Background

With the increasing maturity of the technology of liquid crystal display panels, masks (Photo masks), also called photomasks, photolithographic masks, etc., are pattern masters used in the photolithographic process of microelectronics manufacturing, display manufacturing, forming mask patterns on transparent substrates by opaque light-shielding films and transferring the patterns to product substrates by exposure. The yield of the existing 5Mask process is stable, the film structure is more excellent, but the input labor and time cost is too high, and the productivity is not high. The 4Mask process has higher productivity, better laminating and covering effects, higher process requirements, lower yield and poorer film structure compared with the 5Mask process.

Disclosure of Invention

In view of this, the present application provides a display panel, an array substrate and a manufacturing method thereof, so as to solve the problems of high cost, low productivity in the 5Mask process, and high process requirement and low yield in the 4Mask process in the prior art.

In order to solve the technical problems, the first technical scheme provided by the application is as follows: the manufacturing method of the array substrate comprises the following steps:

s10: providing a substrate, forming a first metal layer on the substrate, patterning the first metal layer by adopting a first photomask process to form a grid, and sequentially forming a grid insulating layer, a semiconductor layer and a second metal layer on the grid and the substrate, wherein the grid insulating layer is made of silicon oxide or silicon nitride; wherein the second metal layer comprises a first region and a second region;

s20: patterning the second metal layer and the semiconductor layer in the first region by adopting a second photomask process to form a source electrode, a drain electrode and an amorphous silicon island; the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode;

s25: patterning the second metal layer of the second region by using a third photomask to form a wiring region;

s30: forming passivation layers on the gate insulating layer, the source electrode and the drain electrode, and performing patterning treatment on the passivation layers by adopting a fourth photomask process to form a via hole; and

s40: and patterning the passivation layer by adopting a fifth photomask process to form a pixel electrode, wherein the pixel electrode is connected with the drain electrode through the via hole.

Optionally, step S20 includes the steps of:

s201: coating a photoresist material on the second metal layer of the first region;

s202: exposing and developing the photoresist material by adopting the second photomask to form a first photoresist layer;

s203: etching to remove the second metal layer of the first area uncovered by the first photoresist layer;

s204: ashing the first photoresist layer to form a second photoresist layer, wherein the second photoresist layer corresponds to the source electrode and the drain electrode;

s205: etching the second metal layer of the first region to form the source electrode and the drain electrode;

s206: stripping the second photoresist layer; and

s207: and etching to remove the semiconductor layer uncovered by the source electrode and the drain electrode.

Wherein the semiconductor layer includes an amorphous silicon layer and an n+ amorphous silicon layer, and step S207 further includes etching to remove the n+ amorphous silicon layer of the channel region to expose the amorphous silicon layer.

Wherein the second metal layer of the first region corresponds to an element region of the transistor region; the second metal layer of the second region corresponds to the routing region of the transistor region.

Optionally, step S25 includes the steps of:

s251: coating a photoresist material on the second metal layer of the second region;

s252: exposing and developing the photoresist material by adopting the third photomask to form a first photoresist layer;

s253: etching to remove the second metal layer of the second area uncovered by the first photoresist layer;

s254: ashing the first photoresist layer to form a second photoresist layer, wherein the second photoresist layer corresponds to the wiring area;

s255: and etching the second metal layer of the second region to form the wiring region.

The wiring area is arranged on the side surfaces of the amorphous silicon island, the source electrode and the drain electrode and used for connecting a circuit between film layers.

In the orthographic projection direction of the array substrate, the edge length of the source electrode is equal to that of the drain electrode; the second photomask is a half-tone mask.

In order to solve the technical problems, a second technical scheme provided by the application is as follows: an array substrate is provided, which comprises a substrate, a grid electrode insulating layer, an amorphous silicon island, a source electrode, a drain electrode, a passivation layer and a pixel electrode; the grid electrode is positioned on the substrate base plate; a gate insulating layer covering the gate electrode and the substrate; the amorphous silicon island is arranged on the grid insulating layer; the source electrode and the drain electrode are arranged on the amorphous silicon island, and a channel region is formed between the source electrode and the drain electrode; the passivation layer is arranged on the gate insulating layer, the source electrode and the drain electrode, and a via hole is formed in the passivation layer; the pixel electrode is arranged on the passivation layer and is connected with the drain electrode through the via hole; the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode.

Wherein the amorphous silicon island includes an amorphous silicon layer and an n+ amorphous silicon layer, the n+ amorphous silicon layer corresponding to the source and the drain, the amorphous silicon layer corresponding to the source, the drain, and a channel region.

Wherein the amorphous silicon island, the source electrode and the drain electrode are formed in a first region of the second metal layer.

The array substrate further comprises a wiring area formed in a second area of the second metal layer; the wiring area is arranged on the side surfaces of the amorphous silicon island, the source electrode and the drain electrode, and the amorphous silicon island and the drain electrode are conducted through the wiring area.

In order to solve the technical problems, a third technical scheme provided by the application is as follows: the display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate is any one of the array substrates; the color film substrate and the array substrate are oppositely arranged; the liquid crystal layer is arranged between the array substrate and the color film substrate.

The application has the beneficial effects that: compared with the prior art, the array substrate and the manufacturing method thereof adopt a second photomask process to carry out patterning treatment on the second metal layer and the semiconductor layer of the first area so as to form a source electrode, a drain electrode and an amorphous silicon island; the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode; and patterning the second metal layer of the second region by using a third photomask to form a wiring region. According to the application, a 4Mask process and a 5Mask process are combined, the second metal layer is divided into a first area and a second area for separate preparation, and the second metal layer and the semiconductor layer of the first area are patterned through a second photomask, so that a source electrode, a drain electrode and an amorphous silicon island with more excellent film structure are obtained; the second area of the second metal layer is patterned through a third photomask to form a wiring area with more excellent Overlay and better alignment effect between film layers, and the amorphous silicon substrate has higher yield, more excellent film layer structure and better Overlay effect through the design of a semiconductor layer (ACT), a source drain metal layer (SD) and an S-HTM (Half-Tone Mask). Thereby overcoming the defects of the 4Mask process and the 5Mask process and achieving the purposes of improving the yield and reinforcing the film structure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart diagram of a method for manufacturing an array substrate provided by the application;

FIG. 2 is a block flow diagram of a sub-step of step S20 provided in FIG. 1;

fig. 3A is a schematic process diagram of sequentially forming a gate insulating layer, a semiconductor layer and a second metal layer on a gate electrode and a substrate according to the present application;

FIG. 3B is a schematic diagram of a process for forming a second metal layer by a halftone mask according to the present application;

FIG. 3C is a schematic view of a process for forming a device region according to the present application;

FIG. 3D is a schematic illustration of a wet etching process for etching a first region of a second metal layer according to the present application;

fig. 3E is a schematic process diagram of patterning the first region by a dry etching process to form a source electrode and a drain electrode according to the present application;

fig. 3F is a schematic process diagram of patterning a semiconductor layer by a dry etching process according to the present application;

FIG. 3G is a schematic diagram of a patterning process of a semiconductor layer by a wet etching process to form amorphous silicon islands, an amorphous silicon layer and an N+ amorphous silicon layer according to the present application;

FIG. 3H is a schematic diagram of a passivation layer forming process according to the present application;

FIG. 3I is a schematic diagram of a process for patterning a passivation layer to form a via hole according to the present application;

FIG. 3J is a schematic diagram of a process for forming a pixel electrode and via connection according to the present application;

FIG. 4 is a schematic top view and an enlarged partial structure of a device region and a trace region of a second metal layer formed by a halftone mask according to the present application;

FIG. 5A is a schematic diagram of a third mask and dry etching process for patterning a semiconductor layer according to the present application;

FIG. 5B is a schematic diagram of a process for depositing a second metal layer according to the present application;

FIG. 5C is a schematic diagram of a patterning process for forming a trace region on a second region of a second metal layer according to the present application;

fig. 5D is a schematic process diagram of forming a passivation layer on a side of the trace area away from the semiconductor layer according to the present application;

FIG. 5E is a schematic diagram of a process for patterning a passivation layer of a trace region to form a via hole according to the present application;

FIG. 5F is a schematic diagram of a process for forming pixel electrode and via connections in a routing area according to the present application;

FIG. 6 is a schematic diagram of an array substrate according to the present application;

fig. 7 is a schematic structural diagram of a display panel provided by the present application.

Reference numerals illustrate:

10-substrate base plate, 20-first metal layer, 201-grid electrode, 21-second mask plate, 30-grid electrode insulating layer, 40-semiconductor layer, 401-amorphous silicon layer, 402-N+ amorphous silicon layer, 50-amorphous silicon island, 60-second metal layer, 61-element region, 62-wiring region, 63-semiconductor layer extension, 601-source electrode, 602-drain electrode, 603-channel region, 70-passivation layer, 701-via hole, 80-pixel electrode, 100-first photoresist layer, 200-second photoresist layer, 300-array base plate, 301-liquid crystal layer, 3011-liquid crystal subunit, 302-color film base plate and 400-display panel.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and "first," herein, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first", "second", or "first" may include at least one such feature, either explicitly or implicitly. All directional indications (such as up, down, left, right, front, back … …) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The mask is a graph 'negative film' in the display manufacturing process and is used for transferring high-precision circuit design and bearing intellectual property information such as graph design and process technology. The mask plate is used for mass production of the amorphous silicon substrate of the display, is a key part of the connection of the downstream production flow, and is one of determining factors of the precision and the quality of the substrate.

The existing basic 5Mask process for manufacturing the amorphous silicon substrate needs five photolithography processes, including: the first photoetching process comprises the following steps: forming a gate electrode pattern; the second photoetching process: forming a semiconductor pattern; and a third photoetching process: forming a source drain metal layer; fourth photoetching process: forming a contact hole; fifth photoetching process: forming ITO electrodes. Each lithography process comprises five steps of film formation, exposure, development, etching and stripping. Although the yield of the 5Mask process is stable, the film structure is more excellent, the time cost is too high and the productivity is not high due to the input of manpower, so that the 4Mask process is generated.

Just as 4Mask is 5Mask, only 4Mask is a half tone Mask structure, and one Mask is used for the semiconductor layer and the source drain metal layer. Namely, the 4Mask process is used for manufacturing the semiconductor layer and the source drain metal layer by adopting the same Mask, so that the productivity is higher, the Overlay effect is better, but the requirements on the process are higher, the yield is lower, and the film layer structure is worse than that of the 5 Mask.

In order to solve the problems, the application provides a novel display panel, an array substrate and a manufacturing method thereof by combining a 4Mask process and a 5Mask process.

Referring to fig. 1, 3A to 3F, fig. 1 is a flow chart of a method for manufacturing an array substrate according to the present application; fig. 3A is a schematic process diagram of sequentially forming a gate insulating layer, a semiconductor layer and a second metal layer on a gate electrode and a substrate according to the present application; FIG. 3B is a schematic diagram of a process for forming a second metal layer by a halftone mask according to the present application; FIG. 3C is a schematic view of a process for forming a device region according to the present application; FIG. 3D is a schematic illustration of a wet etching process for etching a first region of a second metal layer according to the present application; fig. 3E is a schematic process diagram of patterning the first region by a dry etching process to form a source electrode and a drain electrode according to the present application; fig. 3F is a schematic process diagram of patterning a semiconductor layer by a dry etching process according to the present application.

The method for manufacturing the array substrate 300 provided by the application can comprise the following steps:

s10: providing a substrate 10, forming a first metal layer 20 on the substrate 10, patterning the first metal layer 20 by a first photomask process to form a gate 201, and sequentially forming a gate insulating layer 30, a semiconductor layer 40 and a second metal layer 60 on the gate 201 and the substrate 10.

Specifically, as shown in fig. 3A, a physical vapor deposition process may be used to deposit the first metal layer 20, and the material of the first metal layer 20 may be copper, aluminum or molybdenum; the first metal layer 20 is exposed, developed, and etched through a first photomask process to form the gate electrode 201 on the substrate 10. It should be noted that, in the present embodiment, the forming process of the gate 201 is omitted in fig. 3A to 3J, that is, the manufacturing process of the first mask is omitted, and the specific process is started from the second mask, that is, the improvement point of the present application.

As shown in fig. 3A, a gate insulating layer 30 is deposited on the gate electrode 201 and the substrate base plate 10, a semiconductor layer 40 is deposited on the gate insulating layer 30, and a second metal layer 60 is deposited on the semiconductor layer 40; the material of the gate insulating layer 30 may be silicon oxide or silicon nitride. As shown in fig. 3D, the semiconductor layer 40 includes an amorphous silicon layer 401 and an n+ amorphous silicon layer 402 which are stacked, the amorphous silicon layer 401 is formed on the gate insulating layer 30, and the n+ amorphous silicon layer 402 is formed on the amorphous silicon layer 401.

S20: the second metal layer 60 and the semiconductor layer 40 in the first region are patterned by a second photomask process to form a source electrode 601, a drain electrode 602 and an amorphous silicon island 50, wherein the length of the edge of the source electrode 601 is equal to the length of the edge of the drain electrode 602 in the orthographic projection direction of the array substrate 300, and the edge of the amorphous silicon island 50 is larger than the edge of the source electrode 601 and the edge of the drain electrode 602. That is, the edges of the source electrode 601 and the drain electrode 602 have the same length on both sides with respect to the amorphous silicon layer 401 and the n+ amorphous silicon layer 402. In the front projection direction of the array substrate 300, the edges of the amorphous silicon islands 50 are larger than the edges of the source electrodes 601 and the edges of the drain electrodes 602, so that the lengths of the amorphous silicon islands 50 are longer than the lengths of the source electrodes 601 and the drain electrodes 602 on both sides in the side view direction as shown in fig. 3D and the like.

Specifically, as shown in fig. 3C to 3F, the second metal layer 60 of the first region corresponds to the element region 61 of the transistor region, and the element region 61 includes the source electrode 601, the drain electrode 602, and the amorphous silicon island 50 described above to form a TFT device. The device region 61 is formed by a separate second mask (e.g., the second mask 21 shown in fig. 3B), and the first region is etched by the first photoresist layer 100, so that the formation of the source electrode 601, the drain electrode 602, and the amorphous silicon island 50 with misalignment of edges is avoided, so that the product performance is better, the formation of the misalignment of edges is avoided, and the formation of the interlayer Overlay (stack coverage) of the structures of the source electrode 601, the drain electrode 602, and the amorphous silicon island 50 is better, the alignment effect is better, and the conductivity and the light transmittance are better. In this embodiment, the second mask may specifically be a halftone mask.

It should be noted that, the patterning of the semiconductor layer 40 to form the amorphous silicon island 50 includes patterning both the amorphous silicon layer 401 and the n+ amorphous silicon layer 402 to remove the amorphous silicon layer tail fiber and the n+ amorphous silicon layer tail fiber.

Further, as shown in fig. 2, the step S20 may specifically include the following steps:

referring specifically to fig. 2, 3G to 3J, fig. 2 is a block flow diagram of a sub-step of step S20 provided in fig. 1; FIG. 3G is a schematic diagram of a patterning process of a semiconductor layer by a wet etching process to form amorphous silicon islands, an amorphous silicon layer and an N+ amorphous silicon layer according to the present application;

FIG. 3H is a schematic diagram of a passivation layer forming process according to the present application; FIG. 3I is a schematic diagram of a process for patterning a passivation layer to form a via hole according to the present application; fig. 3J is a schematic diagram of a process for forming a connection between a pixel electrode and a via hole according to the present application.

S201: a photoresist material is coated on the second metal layer 60 of the first region.

S202: the photoresist material is exposed to light and developed using a second photomask to form the first photoresist layer 100.

As shown in fig. 3B, a first photoresist layer 100 is formed on a side of the second metal layer 60 away from the semiconductor layer 40 by the second mask 21, and the first photoresist layer 100 may be a photoresist layer. As shown in fig. 3B, the photoresist is exposed and developed by using a halftone mask plate to remove part of the photoresist located at both side edges and corresponding to the channel region 603, and the remaining photoresist forms the first photoresist layer 100, and the thickness of the first photoresist layer 100 corresponding to the channel region 603 is smaller than that of the first photoresist layer 100 corresponding to other regions.

S203: the second metal layer 60 is etched away from the first region not covered by the first photoresist layer 100.

Specifically, as shown in fig. 3C, the second metal layer 60 is partially covered by the first photoresist layer 100, and then the region not covered by the first photoresist layer 100 is removed by dry etching or wet etching, thereby obtaining the element region 61. For example, wet etching may be used, and since wet etching is isotropic, the orthographic projection of the second metal layer 60 (the element region 61) of the first region after wet etching treatment on the substrate 10 is located within the orthographic projection of the first photoresist layer 100 on the substrate 10, that is, at least the second metal layer 60 of the first region uncovered by the first photoresist layer 100 is removed, resulting in the element region 61 shown in fig. 3C.

As shown in fig. 3D, after the element region 61 is obtained through the wet etching process, the amorphous silicon island 50 may be further etched through the wet etching process to form an amorphous silicon layer 401 and an n+ amorphous silicon layer 402. Since the conductive lines formed by the semiconductor layer adjacent to other second metal layers in the prior art have a leakage risk, the overall length of the etched edges of the amorphous silicon layer 401 and the n+ amorphous silicon layer 402 in the orthographic projection direction of the array substrate 300 is longer than that of the edges of the element region 61 in the present application, so that the problem of leakage can be avoided. As shown in fig. 3D and 3E, in the present application, since four masks are applied to the device region 61, the semiconductor layer 40, the source electrode 601 and the drain electrode 602 are formed by one mask, so that the alignment accuracy of the film structure of the device region 61 is high, the device size is more accurate, and the device performance is better.

S204: ashing is performed on the first photoresist layer 100 to form a second photoresist layer 200, the second photoresist layer 200 corresponding to the source electrode 601 and the drain electrode 602.

Specifically, as shown in fig. 3E, the photoresist material corresponding to the channel region 603 is removed, and the remaining photoresist material forms a second photoresist layer 200, where the second photoresist layer 200 corresponds to the source electrode 601 and the drain electrode 602 to be subsequently fabricated.

S205: the second metal layer 60 of the first region is subjected to an etching process to form a source electrode 601 and a drain electrode 602.

Likewise, as shown in fig. 3F and 3G, a wet etching may be used to remove the element region 61 corresponding to the channel region 603, and the second metal layer 60 of the remaining first region forms the source electrode 601 and the drain electrode 602. Specifically, the portion in the center of the element region 61 may be removed by a mask process, that is, a portion that is not required to be remained is removed, and the remaining regions are located at two sides of the removed region, so as to form the source electrode 601 and the drain electrode 602, respectively. As shown in fig. 3G, a further etching is performed in the region between the source electrode 601 and the drain electrode 602, forming a channel region 603 between the source electrode 601 and the drain electrode 602.

S206: the second photoresist layer 200 is stripped.

Specifically, as shown in fig. 3G, the second photoresist layer 200 is stripped from the source electrode 601 and the drain electrode 602, so that the source electrode 601, the drain electrode 602 and the channel region 603 are exposed. In actual operation, the step of forming the channel region 603 and the step of stripping the second photoresist layer 200 may be formed in two steps or may be performed simultaneously, which is not limited in the present application.

S207: the semiconductor layer 40 uncovered by the source electrode 601 and the drain electrode 602 is etched away.

Specifically, the semiconductor layer 40 includes an amorphous silicon layer 401 and an n+ amorphous silicon layer 402, and the step S207 may further include removing the n+ amorphous silicon layer 402 located in the channel region 603 by a dry etching process to expose the amorphous silicon layer 401.

Similarly, the n+ amorphous silicon layer 402 in the channel region 603 is removed by a dry etching process to expose the amorphous silicon layer 401, so that the n+ amorphous silicon tail fiber in the channel region 603 is completely removed, i.e. as shown in fig. 3H, the n+ amorphous silicon tail fiber in the channel region 603 exposes the amorphous silicon layer 401, thereby forming a TFT device. The metal areas of the source electrode 601 and the drain electrode 602 can be reduced due to the structure without the N+ amorphous silicon tail fiber, so that the size of a TFT device is reduced, and the layout space is saved. In the present embodiment, the thickness of the n+ amorphous silicon layer of the channel region is removedSo that the TFT device is reduced on the basis of ensuring the functional integrity of the TFT device.

Referring to fig. 4 to 5F, fig. 4 is a schematic top view and an enlarged partial structure of a device region and a trace region of a second metal layer formed by a halftone mask according to the present application; fig. 5A to 5F are process flow diagrams of the present application for preparing a trace region of a second metal layer by a 5Mask process. Specifically, fig. 5A is a schematic process diagram of patterning a semiconductor layer through a third photomask and a dry etching process according to the present application; FIG. 5B is a schematic diagram of a process for depositing a second metal layer according to the present application; FIG. 5C is a schematic diagram of a patterning process for forming a trace region on a second region of a second metal layer according to the present application; fig. 5D is a schematic process diagram of forming a passivation layer on a side of the trace area away from the semiconductor layer according to the present application; FIG. 5E is a schematic diagram of a process for patterning a passivation layer of a trace region to form a via hole according to the present application; fig. 5F is a schematic view of a process for forming a pixel electrode and a via connection in a trace region according to the present application.

S25: the second metal layer 60 in the second region is patterned by using a third mask to form a trace region 62.

Specifically, as shown in fig. 5B and 5C, the second metal layer 60 of the second region corresponds to a wiring region 62 of the transistor region, and the wiring region 62 is disposed on the sides of the amorphous silicon island 50, the source electrode 601, and the drain electrode 602 for connecting the circuits between the film layers. The formation of the trace region 62 in fig. 5C from the second metal layer 60 in fig. 5B may also be performed by a wet etching process, which is not described herein. Because the number of the lines of the line area 62 is large and the distance is short, the line area 62 is formed by using a single third photomask, so that the distance between the lines is kept clear and definite, short circuit is not easy to occur, and the line area 62 and the element area 61 are manufactured separately, so that the effect of each layer of line is better. The step of patterning the trace region 62 using the third mask is shown in fig. 5A to 5F. It should be noted that, in fig. 5A to 5F, the formation process of the gate 201 is omitted, that is, the preparation process of the first mask is omitted, and the specific process starts from the second mask, that is, the improvement point of the present application.

The first region of the second metal layer 60 and the pattern of the semiconductor layer 40 are designed separately, and the exposure requires two exposures (i.e., a 5Mask process), leaving the patterns of the source electrode 601, the drain electrode 602, and the semiconductor layer 40, respectively.

Specifically, in the steps S20 and S25, exposure is performed once through the halftone mask, as shown in fig. 4, a pattern of the element region 61 with better Overlay is left on the substrate 10, such as a portion A2 and a portion B2 in fig. 4, which each have a semiconductor extension 63, and the semiconductor extension 63 is specifically the semiconductor layer 40 extending to the outside of the second metal layer 60 and not completely covered by the second metal layer 60.

The other portions are exposed twice, as shown in a portion A1 and a portion B1 in fig. 5C and 4, so that patterns of the trace region 62 with more excellent film structure are left, thereby ensuring the lamination effect of the element region 61, saving the process, and preventing short circuits caused by too short circuit of the line distance of the trace region 62. As can be seen from the portions A1 and B1 in fig. 4, the wiring region 62 is formed by two exposures in the figure without the semiconductor extension 63.

The manufacturing method provided in this embodiment is actually that in the process of 5Mask, the TFT element region 61 is formed by using the 4Mask process for the element region 61. The specific exposure step is a normal exposure process and can comprise film forming, coating, developing, exposure, etching, stripping and the like.

S30: a passivation layer 70 is formed on the gate insulating layer 30, the source electrode 601 and the drain electrode 602, and the passivation layer 70 is patterned by a fourth photomask process to form a via 701.

Specifically, as shown in fig. 3H and 5D, the passivation layer 70 may be deposited by physical vapor deposition, and the material of the passivation layer 70 may be oxide, nitride or oxynitride. As shown in fig. 5E, the passivation layer 70 is exposed, developed and etched by a fourth photomask process to form a via 701, as shown in fig. 3I.

S40: a fifth masking process is used to pattern the passivation layer to form the pixel electrode 80, and the pixel electrode 80 is connected to the drain electrode 602 through the via 701.

Specifically, after the via 701 is formed in the first region of the second metal layer 60 as shown in fig. 3I and 3J, a transparent conductive layer (not shown) may be deposited by sputtering or thermal evaporation, and then the transparent conductive layer is exposed, developed and etched by a fourth photomask process to form the pixel electrode 80, and the pixel electrode 80 is connected to the drain electrode 602 through the via 701 in the first region.

After the via 701 is formed in the second region of the second metal layer 60 as shown in fig. 5E and 5F, a transparent conductive layer (not shown) may be deposited by sputtering or thermal evaporation, and then the transparent conductive layer is exposed, developed and etched by a fifth photomask process to form the pixel electrode 80, where the pixel electrode 80 is connected to the drain electrode 602 through the via 701 in the first region and connected to the routing region 62 through the via 701 in the second region.

It can be understood that, compared with the conventional 4Mask process and 5Mask, the length of the amorphous silicon tail fiber exposed outside the source electrode 601 and the drain electrode 602 of the array substrate 300 formed by the manufacturing method provided by the application is only the distance between the source electrode 601 and the drain electrode 602 after the wet etching treatment in the step S205 and after the source electrode 601 and the drain electrode 602 are retracted to the second photoresist layer 200, and the wet etching method adopted in the step etches only the source electrode 601 and the drain electrode 602, the retraction distance is smaller, so that the area of the amorphous silicon island 50 formed can be effectively reduced, the size of the TFT device is further reduced, and the display quality of the large-size high-resolution liquid crystal panel under high backlight intensity is effectively improved.

Referring to fig. 7, fig. 7 is a schematic structural diagram of an array substrate provided by the present application.

The application also provides an array substrate 300, wherein the array substrate 300 comprises a substrate 10, a grid electrode 201, a grid electrode insulating layer 30, an amorphous silicon island 50, a source electrode 601, a drain electrode 602, a passivation layer 70 and a pixel electrode 80. Wherein the gate 201 is located on the substrate 10, the gate insulating layer 30 covers the gate 201 and the substrate 10, and the amorphous silicon island 50 is disposed on the gate insulating layer 30. The source electrode 601 and the drain electrode 602 are disposed on the amorphous silicon island 50, a channel region 603 is formed between the source electrode 601 and the drain electrode 602, the passivation layer 70 is disposed on the gate insulating layer 30, the source electrode 601 and the drain electrode 602, the passivation layer 70 is provided with a via 701, the pixel electrode 80 is disposed on the passivation layer 70, and the pixel electrode 80 is connected to the drain electrode 602 through the via 701.

In the orthographic projection direction of the array substrate 300, the edge of the source electrode 601 and the edge of the drain electrode 602 have the same length, and the edge of the amorphous silicon island 50 is larger than the edge of the source electrode 601 and the edge of the drain electrode 602.

The amorphous silicon island 50, the source electrode 601 and the drain electrode 602 are formed in the first region of the second metal layer 60, and the amorphous silicon island 50, the source electrode 601 and the drain electrode 602 are located in the device region 61, and the above description and fig. 3A to 5F will be omitted herein.

The trace region 62 is formed in the second region of the second metal layer 60, and the trace region 62 is disposed on the sides of the amorphous silicon island 50, the source electrode 601 and the drain electrode 602, and conducts the amorphous silicon island 50 and the drain electrode 602 through the trace region 62.

The amorphous silicon island 50 includes an amorphous silicon layer 401 and an n+ amorphous silicon layer 402, the n+ amorphous silicon layer 402 corresponding to the source 601 and the drain 602, the amorphous silicon layer 401 corresponding to the source 601, the drain 602, and the channel region 603; the amorphous silicon layer 401 is disposed on the substrate 10, and the n+ amorphous silicon layer 402 is disposed on the amorphous silicon layer 401, and reference may be made to the foregoing descriptions and fig. 3A to 5F, which are not repeated here. Since the gate insulating layer 30 corresponding to the outer side of the source electrode 601 and the outer side of the drain electrode 602 has no amorphous silicon tail fiber and no n+ amorphous silicon tail fiber, and the amorphous silicon layer 401 corresponding to the channel region 603 has no n+ amorphous silicon tail fiber, the situation that when the refracted or reflected light irradiates the part of the semiconductor layer 40 exposed outside the TFT device, the leakage current of the TFT device is increased can be avoided, the light stability of the TFT device is further improved, and meanwhile, the area of the amorphous silicon island 50 can be reduced, the size of the TFT device is further reduced, and the layout is saved.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a display panel according to the present application.

The present application further provides a display panel 400, which includes an array substrate 300, a color film substrate 302, and a liquid crystal layer 301, where the array substrate 300 is any one of the array substrates 300 described above, and details are not repeated here.

The color film substrate 302 is arranged opposite to the array substrate 300; the color film substrate 302 includes a substrate (not shown), a filter layer (not shown) on a side of the substrate near the array substrate 300, a black matrix (not shown) and a transparent conductive layer (not shown), and a polarizer (not shown) on a side of the substrate far from the array substrate 300. The filter layer comprises filter films of three colors of red, blue and green. The color film substrate 302 may further include other functional layers, which are not limited herein.

The liquid crystal layer 301 is disposed between the array substrate 300 and the color film substrate 302, and the liquid crystal layer 301 includes a plurality of liquid crystal sub-units 3011 disposed at intervals for transmitting light incident on the display panel 400.

The array substrate and the manufacturing method thereof adopt a second photomask process to carry out patterning treatment on the second metal layer and the semiconductor layer of the first area so as to form a source electrode, a drain electrode and an amorphous silicon island; the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode; and patterning the second metal layer of the second region by using a third photomask to form a wiring region. According to the application, a 4Mask process and a 5Mask process are combined, the second metal layer is divided into a first area and a second area for separate preparation, and the second metal layer and the semiconductor layer of the first area are patterned through a second photomask, so that a source electrode, a drain electrode and an amorphous silicon island with more excellent film structure are obtained; and patterning the second region of the second metal layer through a third photomask to form a wiring region with more excellent Overlay (lamination coverage) and more excellent alignment effect between film layers, thereby overcoming the defects of a 4Mask process and a 5Mask process and achieving the purposes of improving the yield and reinforcing the film layer structure.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:

s20: patterning the second metal layer and the semiconductor layer in the first region by adopting a second photomask process to form a source electrode, a drain electrode and an amorphous silicon island; in the orthographic projection direction of the array substrate, the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode;

2. The method of manufacturing an array substrate according to claim 1, wherein the step S20 includes the steps of:

s206: stripping the second photoresist layer; and

3. The method according to claim 2, wherein the semiconductor layer includes an amorphous silicon layer and an n+ amorphous silicon layer, and step S207 further includes etching to remove the n+ amorphous silicon layer of the channel region to expose the amorphous silicon layer.

4. The method according to claim 1, wherein the second metal layer of the first region corresponds to an element region of a transistor region; the second metal layer of the second region corresponds to the routing region of the transistor region.

5. The method of manufacturing an array substrate according to claim 1, wherein step S25 includes the steps of:

6. The method of claim 5, wherein the routing area is disposed on sides of the amorphous silicon island, the source electrode, and the drain electrode, and is used for connecting a circuit between film layers.

7. The method for manufacturing an array substrate according to claim 1, wherein the edge of the source electrode is equal to the edge of the drain electrode in length in the orthographic projection direction of the array substrate; the second photomask is a half-tone mask.

8. An array substrate, characterized in that the array substrate is prepared by the method for manufacturing an array substrate according to any one of claims 1 to 7; the array substrate includes:

a substrate base;

the grid electrode is positioned on the substrate base plate;

a gate insulating layer covering the gate electrode and the substrate;

the amorphous silicon island is arranged on the grid insulating layer;

the source electrode and the drain electrode are arranged on the amorphous silicon island, and a channel region is formed between the source electrode and the drain electrode;

the passivation layer is arranged on the gate insulating layer, the source electrode and the drain electrode, and a via hole is formed in the passivation layer; and

the pixel electrode is arranged on the passivation layer and is connected with the drain electrode through the via hole;

in the orthographic projection direction of the array substrate, the edge of the amorphous silicon island is larger than the edge of the source electrode and the edge of the drain electrode; the amorphous silicon island comprises an amorphous silicon layer and an n+ amorphous silicon layer, the n+ amorphous silicon layer corresponds to the source electrode and the drain electrode, and the amorphous silicon layer corresponds to the source electrode, the drain electrode and a channel region; the amorphous silicon island, the source electrode and the drain electrode are formed in a first region of the second metal layer.

9. The array substrate of claim 8, further comprising:

the wiring area is formed in the second area of the second metal layer; the wiring area is arranged on the side surfaces of the amorphous silicon island, the source electrode and the drain electrode, and the amorphous silicon island and the drain electrode are conducted through the wiring area.

10. A display panel, comprising:

an array substrate according to any one of claims 8 to 9;

the color film substrate is arranged opposite to the array substrate;

the liquid crystal layer is arranged between the array substrate and the color film substrate.