CN116978332A - Voltage conversion circuit and driving device - Google Patents

Voltage conversion circuit and driving device Download PDF

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Publication number
CN116978332A
CN116978332A CN202311030063.7A CN202311030063A CN116978332A CN 116978332 A CN116978332 A CN 116978332A CN 202311030063 A CN202311030063 A CN 202311030063A CN 116978332 A CN116978332 A CN 116978332A
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CN
China
Prior art keywords
voltage
voltage level
level shifter
switching device
terminal
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CN202311030063.7A
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Chinese (zh)
Inventor
陈廷仰
廖志洋
谢玉轩
梁耀升
林佳欣
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Yuchuang Semiconductor Shenzhen Co ltd
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Yuchuang Semiconductor Shenzhen Co ltd
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Priority to CN202311030063.7A priority Critical patent/CN116978332A/en
Publication of CN116978332A publication Critical patent/CN116978332A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a voltage conversion circuit and a driving device, which relate to the field of circuits, low-voltage signals output by a time sequence controller are converted into higher-voltage signals step by step through a plurality of voltage level shifters, the output voltage range of each voltage level shifter is controlled within a preset threshold, under the condition that a power rail with higher voltage is required for a source driver of an LCD (liquid crystal display), the preset threshold can be set to be a withstand voltage value of a medium-voltage MOS (metal oxide semiconductor) tube so that the voltage of each voltage level shifter does not exceed the rated voltage of the medium-voltage MOS tube when the time sequence controller works, the low-voltage signals output by the time sequence controller can be converted through the voltage level shifters formed by the medium-voltage MOS tube, the response speed is high, the switching characteristic is good, the area of the whole integrated circuit can be greatly reduced compared with the high-voltage MOS tube, the peak current and the signal delay degree in the whole circuit can be better controlled in design, and the control and the signal transmission of the source driver by the time sequence controller are effectively realized.

Description

Voltage conversion circuit and driving device
Technical Field
The present invention relates to the field of circuits, and in particular, to a voltage conversion circuit and a driving device.
Background
With the development of LCD (Liquid Crystal Display ), the source driving signal of the medium-sized LCD can reach 9 to 12V, and the gate driving signal thereof can reach 30 to 40V, so that a high-voltage process is required for a single integrated driving chip of the LCD, and TCON (Timer Control Register, timing controller) is integrated in the chip. Currently, complementary metal oxide semiconductor (cmos) processes of the generation around 0.1 μm are used for such chip products, and the rated voltages of the main MOSFETs (Metal Oxide Semiconductor Field Effect Trans istor, metal-oxide semiconductor field effect transistors) used in such processes can be divided into three types: the high-voltage MOS tube (rated voltage is about 30V), the medium-voltage MOS tube (rated voltage is about 6V) and the low-voltage MOS tube (rated voltage is about 1.2V), if the MOS tube exceeds the rated voltage in the operation process, the MOS tube can be damaged due to the condition of the excessive voltage; when the source driving signal of the LCD needs to reach 12V, the output voltage range of the source driving signal in different display periods of the LCD is 0-6V or 6-12V, and only one of the voltage ranges is followed in one display period, so that the two drivers, namely the power rail 0-6V voltage and the power rail 6-12V voltage, need to be formed by using the medium voltage MOS transistor to form the source driver. The timing controller is a digital circuit formed by low-voltage MOS tubes and provides data signals for a source driver so as to realize the work of an LCD (liquid crystal display) through the source driver, but the data signals output by the timing controller are low-voltage signals, the low-voltage signals (0-1.2V) can be converted into medium-voltage signals (0-6V) through a voltage level shifter, for a driver of a power rail 0-6V, the traditional voltage level shifter formed by the medium-voltage MOS tubes can be used for converting the digital signals, but when the low-voltage signals are converted into the signals of the power rail 6-12V and are transmitted to the driver of the power rail 6-12V, the traditional voltage level shifter formed by the medium-voltage MOS tubes can not be used due to exceeding the withstand voltage of a device.
In the prior art, a scheme of converting a low-voltage signal into a power rail 6-12V signal is realized by forming a voltage level shifter through a high-voltage MOS tube, but although the voltage level shifter formed by the high-voltage MOS tube can convert the low-voltage signal into the power rail 6-12V signal and the limitation exceeding withstand voltage does not exist, the area of the high-voltage MOS tube is far larger than that of the medium-voltage MOS tube, the operation speed is slower, the working efficiency is low when the high-voltage MOS tube is adopted, the response speed is slow, and the area cost of the whole chip can be greatly increased when the high-voltage MOS tube is adopted, so that the method for realizing the power rail 6-12V signal by forming the voltage level shifter through the high-voltage MOS tube is difficult to implement.
Disclosure of Invention
The invention aims to provide a voltage conversion circuit and a driving device, wherein a preset threshold value is set as a withstand voltage value of a medium-voltage MOS tube so that the voltage of each voltage level shifter does not exceed the rated voltage of the medium-voltage MOS tube when the voltage level shifter works, thus the low-voltage signal output by a time sequence controller can be converted through the voltage level shifter formed by the medium-voltage MOS tube, the response speed is high, the switching characteristic is good, the area of the whole integrated circuit can be greatly reduced compared with a high-voltage MOS tube, the peak current and the signal delay degree in the whole circuit can be better controlled in design, and the control and the signal transmission of the time sequence controller to a source driver are effectively realized.
In order to solve the above technical problems, the present invention provides a voltage conversion circuit, including:
the input end of the first inverter is connected with the output end of the time schedule controller and is used for outputting a voltage signal opposite to the output signal of the time schedule controller;
the first input end of the circuit after being connected in series is connected with the output end of the time sequence controller, the second input end of the circuit after being connected with the output end of the first inverter, the first power ends of the N voltage level shifters are respectively connected with first reference voltages with different values, the second power ends of the N voltage level shifters are respectively connected with second reference voltages with different values, for any voltage level shifter, the first reference voltage connected with the voltage level shifter is smaller than the maximum value of a voltage signal received by the voltage level shifter, the second reference voltage connected with the voltage level shifter is larger than the maximum value of the voltage signal received by the voltage level shifter, the voltage difference between the second reference voltage and the first reference voltage is not larger than a preset threshold value, and N is a positive integer larger than 1;
the voltage level shifter is used for outputting a first target voltage corresponding to a first reference voltage accessed by the voltage level shifter and a second target voltage corresponding to a second reference voltage accessed by the voltage level shifter based on control of a voltage signal received by the voltage level shifter.
Optionally, the first voltage level shifter sequentially connected in series includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, where a gate of the first NMOS tube is connected to the output end of the timing controller, a source is connected to a first reference voltage and to a source of the second NMOS tube, a gate of the second NMOS tube is connected to the output end of the first inverter, a source of the first PMOS tube and a source of the second PMOS tube are connected to a second reference voltage, a drain of the first PMOS tube is connected to a source of the third PMOS tube, a drain of the second PMOS tube is connected to a source of the fourth PMOS tube, a gate of the second PMOS tube is connected to a gate of the third PMOS tube and a drain of the first NMOS tube, a gate of the first PMOS tube is connected to a gate of the fourth PMOS tube and a drain of the second NMOS tube, and a drain of the first NMOS tube is used as the first output end of the first voltage level shifter.
Optionally, the second voltage level shifter sequentially connected in series until any one of the N-th voltage level shifters includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh NMOS tube and an eighth PMOS tube, wherein a gate of the third NMOS tube is connected to a first output terminal of the last voltage level shifter connected in series with itself, a gate of the fourth NMOS tube is connected to a second output terminal of the last voltage level shifter connected in series with itself, a source of the third NMOS tube and a source of the fourth NMOS tube are connected to a first reference voltage, a gate of the fifth NMOS tube and a gate of the sixth NMOS tube are connected to a preset voltage corresponding to a maximum value of a voltage signal received by itself, a source of the fifth NMOS tube is connected to a drain of the third NMOS tube, a source of the sixth NMOS tube is connected to a drain of the fourth NMOS tube, a source of the fifth NMOS tube and a source of the sixth NMOS tube are connected to a drain of the PMOS tube, a source of the fifth NMOS tube and a drain of the PMOS tube are connected to a drain of the fifth NMOS tube, a drain of the fifth NMOS tube is connected to a drain of the fifth NMOS tube, and a drain of the fifth NMOS tube is connected to the seventh PMOS is connected to the drain of the fifth NMOS tube, respectively.
Optionally, the first inverter includes a first switching device and a second switching device, a first end of the first switching device is connected to a first power supply, a second end of the first switching device is connected to a first end of the second switching device, a second end of the second switching device is grounded, a control end of the first switching device is connected to a control end of the second switching device, and the control end of the first switching device is used as an input end of the first inverter, and a second end of the first switching device is used as an output end of the first inverter.
Optionally, the voltage level shifter further comprises a second inverter and a third inverter, wherein the input end of the second inverter is connected with the first output end of the nth voltage level shifter, the first power end is connected with a first reference voltage corresponding to the nth voltage level shifter, the second power end is connected with a second reference voltage corresponding to the nth voltage level shifter, the output end of the second inverter is connected with the input end of the third inverter, the first power end of the third inverter is connected with a first reference voltage corresponding to the nth voltage level shifter, and the second power end is connected with a second reference voltage corresponding to the nth voltage level shifter.
Optionally, the second inverter includes a third switching device and a fourth switching device, where a first end of the third switching device is connected to a first reference voltage corresponding to the nth voltage level shifter, a control end of the third switching device is connected to a first output end of the nth voltage level shifter, a second end of the third switching device is connected to a first end of the fourth switching device, a control end of the fourth switching device is connected to a first output end of the nth voltage level shifter, a second end of the fourth switching device is connected to a second reference voltage corresponding to the nth voltage level shifter, and the first end of the fourth switching device is used as an output end of the second inverter.
Optionally, the third inverter includes a fifth switching device and a sixth switching device, where a first end of the fifth switching device is connected to a first reference voltage corresponding to the nth voltage level shifter, a second end of the fifth switching device is connected to a first end of the sixth switching device, a control end of the fifth switching device is connected to a control end of the sixth switching device, a first end of the fourth switching device is connected to a second end of the third switching device, a second end of the sixth switching device is connected to a second reference voltage corresponding to the nth voltage level shifter, and the first end of the sixth switching device is used as an output end of the third inverter.
Optionally, the device further comprises a reference voltage generating module, wherein the reference voltage generating module is respectively connected with the first power supply terminals of the N voltage level shifters and the second power supply terminals of the N voltage level shifters and is used for outputting reference voltages.
Optionally, the reference voltage generating module includes an operational amplifier, a first resistor and a second resistor, a power end of the operational amplifier is connected with a second power supply, an inverting input end is respectively connected with a first end of the first resistor and a first end of the second resistor, a second end of the first resistor is grounded, a second end of the second resistor is connected with an output end of the operational amplifier, and the output end of the operational amplifier is used as an output end of the reference voltage generating module.
In order to solve the technical problem, the invention also provides a driving device which comprises a time sequence controller, a source electrode driver and the voltage conversion circuit, wherein the input end of the voltage conversion circuit is connected with the output end of the time sequence controller, and the output end of the voltage conversion circuit is connected with the input end of the source electrode driver.
The invention provides a voltage conversion circuit, which comprises a first inverter and N voltage level shifters, wherein low-voltage signals output by a time sequence controller are converted into higher voltage signals step by step through the voltage level shifters, and the output voltage range of each voltage level shifter is controlled within a preset threshold value, so that under the condition that a power rail with higher voltage is required for a source driver of an LCD (liquid crystal display), the preset threshold value can be set to be a withstand voltage value of a medium-voltage MOS (metal oxide semiconductor) tube so that the voltage of each voltage level shifter does not exceed the rated voltage of the medium-voltage MOS tube during working, and thus, the low-voltage signals output by the time sequence controller can be converted through the voltage level shifters formed by the medium-voltage MOS tube.
The invention also provides a driving device which has the same beneficial effects as the voltage conversion circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a voltage conversion circuit according to the present invention;
fig. 2 is a schematic diagram of another voltage conversion circuit according to the present invention;
FIG. 3 is a schematic diagram of a specific circuit structure of a voltage converting circuit provided by the present invention when the number of voltage level shifters is three;
FIG. 4 is a schematic diagram of a structure of a reference voltage generating module outputting a first preset voltage according to the present invention;
FIG. 5 is a schematic diagram of a structure of a reference voltage generating module outputting a second preset voltage according to the present invention;
FIG. 6 is a schematic diagram of a structure of a reference voltage generating module outputting a third predetermined voltage according to the present invention;
Fig. 7 is a schematic structural diagram of a driving device provided by the present invention.
Detailed Description
The invention has the core of providing a voltage conversion circuit and a driving device, wherein a preset threshold value is set as the withstand voltage value of a medium-voltage MOS tube so that the voltage of each voltage level shifter does not exceed the rated voltage of the medium-voltage MOS tube when in operation, thereby being capable of converting a low-voltage signal output by a time sequence controller through the voltage level shifter formed by the medium-voltage MOS tube, having high response speed and good switching characteristic, greatly reducing the area of the whole integrated circuit compared with a high-voltage MOS tube, being capable of better controlling the peak current and the signal delay degree in the whole circuit in design and effectively realizing the control and signal transmission of the time sequence controller to a source driver.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a voltage converting circuit according to the present invention; to solve the above technical problem, the present invention provides a voltage conversion circuit 21, comprising:
a first inverter 2 having an input connected to an output of the timing controller 1 for outputting a voltage signal opposite to the output signal of the timing controller 1;
the N voltage level shifters 3 are sequentially connected in series, a first input end of a circuit after being connected in series is connected with an output end of the time sequence controller 1, a second input end of the circuit after being connected with an output end of the first inverter 2, first power supply ends of the N voltage level shifters 3 are respectively connected with first reference voltages with different values, second power supply ends of the N voltage level shifters 3 are respectively connected with second reference voltages with different values, for any voltage level shifter 3, the first reference voltage connected with the voltage level shifter 3 is smaller than the maximum value of a voltage signal received by the voltage level shifter 3, the second reference voltage connected with the voltage level shifter 3 is larger than the maximum value of the voltage signal received by the voltage level shifter 3, the voltage difference between the second reference voltage and the first reference voltage is not larger than a preset threshold value, and N is a positive integer larger than 1;
the voltage level shifter 3 is configured to output a first target voltage corresponding to a first reference voltage to which itself is connected and a second target voltage corresponding to a second reference voltage to which itself is connected, based on control of a voltage signal received by itself.
Specifically, the first inverter 2 receives a data signal output by the timing controller 1, the data signal is a relatively low-voltage level signal, when the first inverter 2 receives a low-level signal of the data signal, the low-level signal is inverted, so as to obtain a high-level signal of the data signal, when the first inverter 2 receives a high-level signal of the data signal, the high-level signal is inverted, so as to obtain a low-level signal of the data signal, two input ends of a series-connected first voltage level shifter 3 are also connected in series, two input ends of the first voltage level shifter 3 are respectively connected with two level signals output by the timing controller 1, and two power supply ends are respectively connected with different reference voltages, as shown in fig. 1, the first reference voltages which are respectively connected with the voltage level shifters 3 are respectively Vc1, vf2 are respectively up to Vcn, so that the first voltage level shifter 3 can also output substantially equal to the first voltage level shifter 3, namely, the first voltage level shifter 3 is substantially equal to the first voltage level shifter, and the second voltage level shifter 3 is also connected with the first voltage level shifter, the second voltage level shifter is substantially equal to the first voltage level shifter 3, the first voltage level shifter is connected with the second voltage level shifter 3, the first voltage level shifter is substantially equal to the first voltage level shifter 3, the first voltage and the second voltage are connected with two input ends of the second voltage level shifter 3, and the second voltage level shifter 3 outputs a first target voltage corresponding to a first reference voltage connected to the second voltage and a second target voltage corresponding to a second reference voltage connected to the second voltage based on control of the first voltage and the second voltage, so that level signals are shifted again until the Nth voltage level shifter 3 outputs final target voltage level signals required by users.
It will be understood that the operating principle of the voltage level shifter 3 is based on the control of the level signals received by the two input terminals, the voltage signals with the same magnitude as the two reference voltages are output by using the reference voltages connected to the two power supply terminals of the voltage level shifter 3, so as to generate a new level signal, and the level signal which is generally output is larger than the level signal received by the input terminals, so that a boosting process is realized, and the first reference voltage connected to the voltage level shifter 3 is taken as a smaller value of the two reference voltages, and needs to be smaller than the larger value of the two reference voltages of the previous voltage level shifter 3, that is, the first reference voltage connected to the voltage level shifter 3 is smaller than the maximum value of the voltage signals received by the voltage level shifter 3, so that the process of outputting the target voltage through the control of the received level signal can be realized. The voltage level shifter 3 performs the conversion and shift of the level signals by the low level signal and the high level signal simultaneously, so that the input end needs to be connected with the low level signal and the high level signal of the original level signal, and therefore, the first inverter 2 is arranged between the first voltage level shifter 3 and the time schedule controller 1 to realize that the low level signal and the high level signal output by the time schedule controller 1 are simultaneously input into the first voltage level shifter 3, and since the two output ends of the voltage level shifter 3 are the low level signal and the high level signal which respectively output the shifted level signal when outputting, the subsequent circuit only needs to connect the output ends and the input ends of the N voltage level shifters 3 in series.
It should be noted that, the specific number of the voltage level shifters 3, that is, the value of N depends on factors such as the final target voltage and the withstand voltage of the adopted device, and the larger the value of N, the higher the voltage conversion process can be realized by the whole voltage conversion circuit 21, but the withstand voltage of the adopted device needs to be considered in the conversion process, the rated voltage of the adopted device is taken as a preset threshold value, the condition that the voltage level shifter 3 exceeds the withstand voltage of the device in the working process is avoided, and the specific implementation mode of the value of N is not particularly limited herein.
It will be understood that the specific circuit structures and implementation manners of the first inverter 2 and the voltage level shifters 3 are not particularly limited, and the application is generally implemented by a circuit formed by a switching device such as a MOS transistor, and the application is not particularly limited, and the application can be selected according to the requirements of different voltage level signals in the practical application process; the specific value of the preset threshold value and the like are not particularly limited herein, and mainly depend on the voltage withstand condition and specific circuit structure of the adopted device.
Taking the source rail of 6-12V required by the source driver 22 of the LCD as the final target voltage as an example, considering various problems caused by using a high-voltage MOS transistor in the prior art, the present invention needs to use a medium-voltage MOS transistor to convert a low-voltage signal to a voltage threshold of 6-12V, so as to achieve the purpose of transmitting a large amount of data signals to the source driver 22 of 6-12V of the source rail, and the device required to be used at this time is a medium-voltage MOS transistor of about 6V rated voltage commonly used by the LCD, so that the preset threshold is set to 6V, and in order to further save cost and reduce volume, the present embodiment uses three voltage level shifters 3 to implement this voltage level shifting scheme.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of another voltage conversion circuit according to the present invention; considering that the low voltage digital signal output by the timing controller 1 is usually 0-1.2V, the first voltage level shifter 3 is set to convert the low voltage level signal output by the timing controller 1 into a voltage level signal of 0-6V, then the second voltage level shifter 3 converts the voltage level signal of 0-6V output by the first voltage level shifter 3 into a voltage level signal of 3-9V, and finally the third voltage level shifter 3 converts the voltage level signal of 3-9V output by the second voltage level shifter 3 into a voltage level signal of 6-12V; at this time, the first reference voltage GND accessed by the first voltage level shifter 3 is 0V, and is between 0 and 1.2V of the voltage level signal output by the timing controller, the difference between the accessed second reference voltage MAVDD and 0V of the first reference voltage GND is 6V, and is not greater than the preset threshold, and the second reference voltage MAVDD is greater than the high level signal of 1.2V output by the timing controller 1, so that the voltage level signal output by the timing controller 1 is boosted to a certain extent; the first reference voltage VQL connected to the second voltage level shifter 3 is 3V, and is between 0 and 6V of the voltage level signal output by the first voltage level shifter 3, the second reference voltage VQH connected to the first voltage level shifter 3 is 9V, the difference between the first reference voltage VQL and the first reference voltage is 6V, the difference is not greater than a preset threshold value, the second reference voltage VQH is greater than the high level signal of 6V output by the first voltage level shifter 3, and the voltage level signal output by the first voltage level shifter 3 is boosted to a certain degree; the first reference voltage MAVDD connected to the third voltage level shifter 3 is 6V, and is between the voltage level signals 3-9V output by the second voltage level shifter 3, the second reference voltage AVDD connected to the first voltage level shifter 3 is 12V, the difference between the first reference voltage AVDD and the 6V of the first reference voltage MAVDD is 6V, which is not greater than the preset threshold value, and the second reference voltage AVDD is greater than the 9V high level signal output by the second voltage level shifter 3, so that the voltage level signal output by the second voltage level shifter 3 is boosted to a certain extent, the voltage of 6-12V finally output is the target voltage required by the source driver 22, the output end of the first voltage level shifter 3 can also directly provide the required voltage of the power supply rail GND-MAVDD, and the output end of the second voltage level shifter 3 can also directly provide the required voltage of the power supply rail VQL-VQH.
In the embodiment, the step-by-step boosting and shifting of the three voltage level shifters 3 are adopted to ensure that the voltage withstand of the medium-voltage MOS tube is not exceeded in the whole voltage conversion process when the circuit is operated, and the requirement of the source driver 22 on a 6-12V power supply is met by utilizing the medium-voltage MOS tube. The low voltage digital signal is converted into a digital signal with a power supply rail of GND-MAVDD through the first voltage level shifter 3, then is converted into a digital signal with a power supply rail of VQL-VQH through the second voltage level shifter 3, and then is converted into a digital signal with a power supply rail of MAVDD-AVDD through the third voltage level shifter 3, so that the digital signal of the low voltage digital signal power supply rail MAVDD-AVDD is completed.
It will be appreciated that for different target demand voltages, the process of implementing the high voltage level signal by the low voltage level signal shift may be implemented by selecting different values of N or different reference voltages, for example, when the target demand voltage is 12-18V, it may be implemented by setting the five voltage level shifters 3 to 0-6V,3-9V,6-12V,10-16V,12V-18V, respectively, that is, by setting the two reference voltages of the first voltage level shifter 3 to 0V and 6V, setting the two reference voltages of the second voltage level shifter 3 to 3V and 9V, setting the two reference voltages of the third voltage level shifter 3 to 6V and 12V, setting the two reference voltages of the fourth voltage level shifter 3 to 10V and 16V, setting the two reference voltages of the fifth voltage level shifter 3 to 12V and 18V, respectively, and especially when the target demand voltage is multiple target demand voltage is 21-18V, it may be implemented by implementing the two demand voltage conversion circuits of the two demand voltage level shifters 21-18 simultaneously.
The voltage conversion circuit 21 provided by the invention can convert the low-voltage signal into the digital signal with the rated voltage and 2 times of the rated voltage by the medium-voltage MOS tube with good switching characteristics, namely, the 0-6V and 6-12V power rails required by the source driver 22 of the LCD can be realized by the medium-voltage MOS tube, and the rated voltage of the device can not be exceeded when all the medium-voltage MOS tubes are operated by the cooperation of a plurality of voltage level shifters 3. The voltage level shifter 3 formed by the medium voltage MOS tube is used for converting digital level signals, compared with the high voltage MOS tube, the area of an integrated circuit can be greatly reduced, the peak current and the signal delay degree can be better controlled in design through converting the digital signals by a plurality of voltage level shifters 3, the peak current in a preset threshold control circuit is improved by adopting a medium voltage device, the signal delay is avoided, and the method is particularly suitable for being applied to chip designs which need to convert a large number of digital signals at the same time, and the method does not cause excessive volume and excessive cost.
The invention provides a voltage conversion circuit 21, which comprises a first inverter 2 and N voltage level shifters 3, wherein low-voltage signals output by a time sequence controller 1 are converted into higher voltage signals step by step through the voltage level shifters 3, and the output voltage range of each voltage level shifter 3 is controlled within a preset threshold value, so that when a power rail with higher voltage is required for a source driver 22 facing an LCD, the preset threshold value can be set to be the withstand voltage value of a medium-voltage MOS tube, the voltage of each voltage level shifter 3 does not exceed the rated voltage of the medium-voltage MOS tube during operation, and thus the low-voltage signals output by the time sequence controller 1 can be converted through the voltage level shifters 3 formed by the medium-voltage MOS tube, the response speed is high, the switching characteristic is good, the area of the whole integrated circuit can be greatly reduced compared with that of the high-voltage MOS tube, and the peak current and the signal delay degree in the whole circuit can be better controlled in design, and the control and signal transmission of the time sequence controller 1 to the source driver 22 are effectively realized.
Referring to fig. 3, fig. 3 is a schematic diagram of a specific circuit structure of a voltage converting circuit provided in the present invention when the number of voltage level shifters is three; based on the above embodiments:
as an alternative embodiment, the first voltage level shifter 3 sequentially connected in series includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, where the gate of the first NMOS tube is connected to the output end of the timing controller 1, the source is connected to the first reference voltage and to the source of the second NMOS tube, the gate of the second NMOS tube is connected to the output end of the first inverter 2, the source of the first PMOS tube and the source of the second PMOS tube are connected to the second reference voltage, the drain of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the second PMOS tube is connected to the source of the fourth PMOS tube, the gate of the second PMOS tube is connected to the gate of the third PMOS tube and the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the gate of the fourth PMOS tube and the drain of the second NMOS tube, and the drain of the first NMOS tube is used as the first output end of the first voltage level shifter 3, and the drain of the second NMOS tube is used as the second output end of the first voltage level shifter 3.
It is to be understood that the voltage level shifter 3 may be implemented by a circuit formed by MOS transistors, where the two level signals output by the timing controller 1 are implemented by controlling the on and off states of the first NMOS transistor and the second NMOS transistor, when the timing controller 1 outputs the low level signal, the control terminal of the first NMOS transistor receives the low level, the control terminal of the second NMOS transistor receives the high level after the inversion of the first inverter 2, at this time, the first NMOS transistor is turned off, the second NMOS transistor is turned on, the first output terminal of the first voltage level shifter 3 is pulled up to the second reference voltage by the first PMOS transistor and the third PMOS transistor, and the second output terminal is pulled down to the first reference voltage by the turned-on second NMOS transistor; when the time sequence controller 1 outputs a high-level signal, the first NMOS tube is turned on, the second NMOS tube is turned off, the first output end of the first voltage level shifter 3 is pulled down to a first reference voltage by the first NMOS tube which is turned on, and the second output end is pulled up to a second reference voltage by the second PMOS tube and the fourth PMOS tube; so that the first voltage level shifter 3 outputs a first target voltage corresponding to the first reference voltage and a second target voltage corresponding to the second reference voltage. The specific types and implementation of the NMOS and PMOS transistors used in the voltage level shifter 3 are not particularly limited herein.
Specifically, through the cooperation of MOS pipe and two reference voltages, realize the output of level signal through two output terminals of pull-up or pull-down voltage level shifter 3, and the level signal of output and two reference voltages of self access direct correlation, thereby through setting up the process that different reference voltages realized different voltage conversion and shifted, whole circuit structure is simple, easily realizes, the flexibility is high, the device cost who adopts is low, small, be convenient for integrate, be favorable to the nimble application of whole voltage conversion circuit 21.
As an alternative embodiment, any one of the voltage level shifters 3 from the second voltage level shifter 3 to the nth voltage level shifter 3 connected in series in turn comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, the gate of the third NMOS tube is connected with the first output end of the last voltage level shifter 3 connected in series with itself, the gate of the fourth NMOS tube is connected with the second output end of the last voltage level shifter 3 connected in series with itself, the source of the third NMOS tube and the source of the fourth NMOS tube are connected with a first reference voltage, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are connected with a preset voltage corresponding to the maximum value of the voltage signal received by itself, the source electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the second reference voltage, the drain electrode of the fifth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the eighth PMOS tube, the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the seventh PMOS tube and the drain electrode of the fifth NMOS tube, the grid electrode of the fifth PMOS tube is respectively connected with the grid electrode of the eighth PMOS tube and the drain electrode of the sixth NMOS tube, the drain electrode of the fifth NMOS tube is used as the first output end of the voltage level shifter 3, and the drain electrode of the sixth NMOS tube is used as the second output end of the voltage level shifter 3.
It is to be understood that each voltage level shifter 3 connected in series can be realized through a circuit formed by MOS tubes, two level signals output by the last voltage level shifter 3 connected in sequence are output by the current voltage level shifter 3 through controlling the on and off of a third NMOS tube and a fourth NMOS tube of the current voltage level shifter 3, when a first output end of the last voltage level shifter 3 outputs a low level signal, a control end of the third NMOS tube receives a low level, a control end of the fourth NMOS tube receives a high level output by a second output end of the last voltage level shifter 3, at this time, the third NMOS tube is turned off, the fourth NMOS tube is turned on, a first output end of the current voltage level shifter 3 is pulled up to a second reference voltage by a fifth PMOS tube and a seventh PMOS tube, and a fourth NMOS tube, of which the second output end is turned on, is pulled down to the first reference voltage; when the first output end of the last voltage level shifter 3 outputs a high-level signal, the third NMOS tube is turned on, the fourth NMOS tube is turned off, the first output end of the current voltage level shifter 3 is pulled down to a first reference voltage by the third NMOS tube which is turned on, and the second output end is pulled up to a second reference voltage by the sixth PMOS tube and the eighth PMOS tube; so that the present voltage level shifter 3 outputs a first target voltage corresponding to the first reference voltage to which itself is connected and a second target voltage corresponding to the second reference voltage to which itself is connected. Meanwhile, considering that the voltage between the grid electrode and the drain electrode of the third NMOS tube and the fourth NMOS tube may exceed the withstand voltage due to the fact that the value of the reference voltage is too large, in order to further ensure the safety of the third NMOS tube and the fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube are respectively overlapped on the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube, the voltage between the grid electrode and the drain electrode of the third NMOS tube and the voltage between the grid electrode and the drain electrode of the fourth NMOS tube cannot exceed the withstand voltage, the preset voltage of the control ends of the fifth NMOS tube and the sixth NMOS tube is between the first reference voltage and the second reference voltage, in order to reduce different numbers of the reference voltages, the maximum value of the voltage signals received by the third NMOS tube and the fourth NMOS tube can be directly multiplexed to serve as the preset voltage, and the second reference voltage of the last voltage level shifter 3 connected with the third NMOS tube is about to serve as the preset voltage. The specific types and implementation of the NMOS and PMOS transistors used in the voltage level shifter 3 are not particularly limited herein.
Specifically, through the cooperation of MOS pipe and two reference voltages, realize the output of level signal through two output terminals of pull-up or pull-down voltage level shifter 3, and the level signal of output and two reference voltages direct correlation that self inserts, thereby realize different voltage conversion and the process of shifting through setting up different reference voltages, whole circuit structure is simple, easily realize, the flexibility is high, the device that adopts is with low costs, small, be convenient for integrate, be favorable to the nimble application of whole voltage conversion circuit 21, further avoid exceeding the condition of withstand voltage in the circuit through increasing two NMOS pipes that set up, the security and the reliability of whole voltage conversion circuit 21 are improved.
As an alternative embodiment, the first inverter 2 includes a first switching device Q1 and a second switching device Q2, a first terminal of the first switching device Q1 is connected to the first power supply, a second terminal of the first switching device Q2 is connected to the first terminal of the second switching device Q2, a second terminal of the second switching device Q2 is grounded, a control terminal of the first switching device Q1 is connected to a control terminal of the second switching device Q2, and the control terminal of the first switching device Q1 serves as an input terminal of the first inverter 2, and a second terminal of the first switching device Q1 serves as an output terminal of the first inverter 2.
It should be understood that the first inverter 2 may be implemented by matching between the switching device and the first power supply, where the value of the first power supply of the first inverter 2 needs to be approximately equal to the voltage value corresponding to the high level signal output by the timing controller 1, and preferably, the voltage value is kept completely consistent, and the implementation manner of the first power supply is not particularly limited herein; when the control terminal of the first switching device Q1 and the control terminal of the second switching device Q2 receive the low level signal output by the timing controller 1, the first switching device Q1 is turned on, the second switching device Q2 is turned off, and the output signal of the first inverter 2 is pulled up to the first power supply by the turned-on first switching device Q1, thereby outputting a level signal consistent with a high level signal among the output level signals of the timing controller 1; when the control terminal of the first switching device Q1 and the control terminal of the second switching device Q2 receive the high level signal output from the timing controller 1, the first switching device Q1 is turned off, the second switching device Q2 is turned on, and the output signal of the first inverter 2 is pulled down to ground by the turned-on second switching device Q2, thereby outputting a level signal consistent with a low level signal among the output level signals of the timing controller 1. The specific types and implementations of the first switching device Q1 and the second switching device Q2 are not particularly limited herein.
Specifically, the function of the first inverter 2 is realized by controlling the on and off of the first switching device Q1 and the second switching device Q2 through the level signal output by the timing controller 1, so that the first inverter 2 outputs a level signal opposite to the current output of the timing controller 1, and the level signal is obtained based on the level signal which can be output by the timing controller 1.
As an alternative embodiment, the device further comprises a second inverter 11 and a third inverter 12, wherein the input end of the second inverter 11 is connected with the first output end of the nth voltage level shifter 3, the first power end is connected with the first reference voltage corresponding to the nth voltage level shifter 3, the second power end is connected with the second reference voltage corresponding to the nth voltage level shifter 3, the output end is connected with the input end of the third inverter 12, the first power end of the third inverter 12 is connected with the first reference voltage corresponding to the nth voltage level shifter 3, and the second power end is connected with the second reference voltage corresponding to the nth voltage level shifter 3.
It will be understood that the first target voltage and the second target voltage finally output by the nth voltage level shifter 3 are formed based on the pull-up or pull-down of the MOS transistor, but in this process, due to the influence of factors such as the internal resistance of the MOS transistor, there may be a certain difference between the first target voltage and the second target voltage finally output by the nth voltage level shifter 3 and the first reference voltage and the second reference voltage of the nth voltage level shifter 3, that is, the final output voltage may be only substantially close to the required target voltage, rather than completely equal, so that in order to further ensure that the final output voltage may be consistent with the required target voltage, the second inverter 11 and the third inverter 12 are added at the output end of the nth voltage level shifter 3 to further improve the accuracy of the final output voltage, the second inverter 11 outputs a level signal opposite to the third voltage level shifter 3, and the third inverter 12 outputs a level signal identical to the nth voltage level shifter 3. When one voltage conversion circuit 21 satisfies a plurality of required voltages, a structure in which two inverters are similarly provided may be added to the converter of the voltage level shifter 3 corresponding to different required voltages to further improve the accuracy and reliability of the respective output voltages. The specific type and implementation of the second inverter 11 and the third inverter 12 are not particularly limited herein, and compared with the voltage level shifter 3, the circuit structure of the second inverter 11 and the third inverter 12 is simpler, and excessive loss in the circuit can be avoided, so that the error between the final output voltage and the target required voltage is reduced.
Specifically, by adding the second inverter 11 and the third inverter 12 provided to further process the voltage level signal output from the nth voltage level shifter 3, the accuracy of the target required voltage finally output is improved, and the accuracy and reliability of the entire voltage conversion circuit 21 are ensured.
As an alternative embodiment, the second inverter 11 includes a third switching device Q3 and a fourth switching device Q4, where a first end of the third switching device Q3 is connected to a first reference voltage corresponding to the nth voltage level shifter 3, a control end is connected to a first output end of the nth voltage level shifter 3, a second end is connected to a first end of the fourth switching device Q4, a control end of the fourth switching device Q4 is connected to a first output end of the nth voltage level shifter 3, a second end is connected to a second reference voltage corresponding to the nth voltage level shifter 3, and a first end of the fourth switching device Q4 serves as an output end of the second inverter 11.
It should be understood that, when the first output end of the nth voltage level shifter 3 outputs a low level signal corresponding to the first reference voltage connected to the nth voltage level shifter 3, the third switching device Q3 is turned off, the fourth switching device Q4 is turned on, the output end of the second inverter 11 is pulled up to the second reference voltage connected to the nth voltage level shifter 3 by the fourth switching device Q4, and at this time, the second inverter 11 outputs a high level signal corresponding to the second reference voltage, that is, outputs a high level signal of the target demand voltage; when the first output end of the nth voltage level shifter 3 outputs a high level signal corresponding to the second reference voltage connected to the nth voltage level shifter 3, the third switching device Q3 is turned on, the fourth switching device Q4 is turned off, the output end of the second inverter 11 is pulled down to the first reference voltage connected to the nth voltage level shifter 3 by the third switching device Q3, and at this time, the second inverter 11 outputs a low level signal corresponding to the first reference voltage, that is, outputs a low level signal of a target demand voltage; in this embodiment, the second inverter 11 is connected to the first output terminal of the nth voltage level shifter 3, and the second inverter 11 may be connected to the second output terminal of the nth voltage level shifter 3. The specific types and implementations of the third switching device Q3 and the fourth switching device Q4 are not particularly limited herein.
Specifically, the second inverter 11 outputs a level signal closer to the final target demand voltage, so that the accuracy of the final output target demand voltage is improved, the accuracy and reliability of the whole voltage conversion circuit 21 are ensured, and the whole circuit is simple in structure, easy to implement and beneficial to the simple implementation of the whole voltage conversion circuit 21.
As an alternative embodiment, the third inverter 12 includes a fifth switching device Q5 and a sixth switching device Q6, where a first end of the fifth switching device Q5 is connected to a first reference voltage corresponding to the nth voltage level shifter 3, a second end of the fifth switching device Q5 is connected to a first end of the sixth switching device Q6, control ends of the fifth switching device Q6, a first end of the fourth switching device Q4, and a second end of the third switching device Q3 are respectively connected to a control end of the sixth switching device Q6, a second end of the sixth switching device Q6 is connected to a second reference voltage corresponding to the nth voltage level shifter 3, and the first end of the sixth switching device Q6 serves as an output end of the third inverter 12.
It should be understood that, when the second inverter 11 outputs the low level signal corresponding to the first reference voltage connected to the nth voltage level shifter 3, the fifth switching device Q5 is turned off, the sixth switching device Q6 is turned on, the output end of the third inverter 12 is pulled up to the second reference voltage connected to the nth voltage level shifter 3 by the sixth switching device Q6, and at this time, the third inverter 12 outputs the high level signal corresponding to the second reference voltage, that is, outputs the high level signal of the target demand voltage; when the second inverter 11 outputs a high level signal corresponding to the second reference voltage connected to the nth voltage level shifter 3, the fifth switching device Q5 is turned on, the sixth switching device Q6 is turned off, the output end of the third inverter 12 is pulled down to the first reference voltage connected to the nth voltage level shifter 3 by the fifth switching device Q5, and at this time, the third inverter 12 outputs a low level signal corresponding to the first reference voltage, that is, outputs a low level signal of the target demand voltage; the specific types and implementations of the fifth and sixth switching devices Q5 and Q6 are not particularly limited herein.
Specifically, the third inverter 12 outputs a level signal opposite to the second inverter 11, so that the voltage finally output is consistent with the output level condition of the nth voltage level shifter 3, and the level signal of the final output voltage is more close to the target required voltage through cooperation with the second inverter 11, so that the accuracy of the final output target required voltage is improved, the accuracy and reliability of the whole voltage conversion circuit 21 are ensured, the whole circuit is simple in structure and easy to realize, and the simple and convenient realization of the whole voltage conversion circuit 21 is facilitated.
As an alternative embodiment, the device further comprises a reference voltage generating module, which is respectively connected to the first power terminals of the N voltage level shifters 3 and the second power terminals of the N voltage level shifters 3, and is used for outputting a reference voltage.
It should be understood that the voltage level shifter 3 needs to use multiple reference voltages in the process of voltage conversion and shift, so that the reference voltage generating module can be added, the reference voltages with different values can be generated through the power supply, so that the number of the required power supply is reduced, the cost is reduced, the specific types and implementation modes of the reference voltage generating module are not particularly limited, the reference voltage generating modules of the first reference voltage and the second reference voltage can be separately arranged, one reference voltage generating module can be directly arranged, and the reference voltage generating module can be realized through a simple resistor voltage dividing circuit or an operational amplifier voltage dividing circuit.
Specifically, the reference voltage generating module is added to output each reference voltage required by the voltage level shifter 3, so that errors of the reference voltages caused by damage of the power supply and the like due to the fact that each reference voltage is realized through different power supplies are avoided, the cost is further reduced, the size of the whole voltage converting circuit 21 is reduced, and the accuracy of each reference voltage is improved.
As an alternative embodiment, the reference voltage generating module includes an operational amplifier, a first resistor and a second resistor, the power end of the operational amplifier is connected to the second power supply, the inverting input end is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is grounded, the second end of the second resistor is connected to the output end of the operational amplifier, and the output end of the operational amplifier is used as the output end of the reference voltage generating module.
It should be understood that the reference voltage generating module may be implemented by a circuit formed by an operational amplifier, a first resistor and a second resistor, the reference voltage may be generated by a voltage dividing circuit formed by the first resistor and the second resistor and a second power supply connected to the operational amplifier, different reference voltage outputs may be implemented by adjusting a ratio of the first resistor to the second resistor, or different reference voltage outputs may be implemented by setting a plurality of different groups of such circuits, and the specific types and implementation modes of the operational amplifier, the first resistor and the second resistor are not particularly limited herein, and the first resistor and the second resistor may be implemented by fixed resistors or variable resistors.
As a specific embodiment, taking fig. 3 as an example, reference voltages required in fig. 3 include MAVDD (6V), VQL (3V), VQH (9V) and AVDD (12V), and referring to fig. 4, fig. 5 and fig. 6, fig. 4 is a schematic structural diagram of a reference voltage generating module according to the present invention for outputting a first preset voltage; FIG. 5 is a schematic diagram of a structure of a reference voltage generating module outputting a second preset voltage according to the present invention; FIG. 6 is a schematic diagram of a structure of a reference voltage generating module outputting a third predetermined voltage according to the present invention; directly taking a 12V POWER supply as a reference, as shown in FIG. 4, firstly, a system POWER AVDD (12V) is used for establishing an LDO (low dropout regulator, low dropout linear regulator), and the circuit comprises an operational amplifier U1, a resistor R1 and a resistor R2, and outputs a voltage which is half of the AVDD and is defined as MAVDD (6V); as shown in fig. 5, a LDO is built again by using the system POWER AVDD (12V) and MAVDD (6V), and the circuit includes an operational amplifier U2, a resistor R3 and a resistor R4, and outputs a voltage half of the voltage between AVDD and MAVDD, defined as VQH (9V); as shown in fig. 6, an LDO is built by using the MAVDD, and the circuit includes an operational amplifier U3, a resistor R5 and a resistor R6, and outputs half of the voltage of the MAVDD, which is defined as VQL (3V), that is, four reference voltages of the MAVDD (6V), VQL (3V), VQH (9V) and AVDD (12V) are generated by one 12V voltage.
Specifically, the reference voltage generating module is realized through the operational amplifier, the operational amplifier voltage dividing circuit formed by the first resistor and the second resistor, different reference voltages can be output through adjusting the resistance values of the first resistor and the second resistor, and the like, the circuit structure is simple, the implementation is easy, the adopted device is low in cost, small in size and easy to integrate, and the simple implementation of the whole voltage conversion circuit 21 is facilitated.
As a specific embodiment, taking fig. 3 as an example, the MOS transistors N1, N2, P1, P2, P3 and P4 IN fig. 3 constitute a first voltage level shifter 3, the MOS transistors N3, N4, N5, N6, P5, P6, P7 and P8 constitute a second voltage level shifter 3, the MOS transistors N7, N8, N9, N10, P9, P10, P11 and P12 constitute a second voltage level shifter 3, the low voltage digital signal IN generates an IN ' inverted signal via an inverter, the two signals are respectively connected to the gate terminals of the NMOS transistors N1, N2 as input signals of the first voltage level shifter 3, VOUT1 and VOUT1' are output signals of the first voltage level shifter 3, and the gate terminals of the NMOS transistors N4, N3 connected to the second voltage level shifter 3 are connected as input signals thereof, the gate terminals of the NMOS transistors N5, N6 are connected, and the NMOS transistors vdd 1 or manode 2 are pulled up to a voltage made before being applied to manode, the NMOS transistors N5, N6 are turned off, so that the voltage of the node1 or the node2 is lower than MAVDD when IN operation, the drain-gate voltages of the NMOS transistors N3, N4 are avoided, namely, the voltage between the nodes 1-VOUT1', the voltage between the nodes 2-VOUT1 exceeds the rated voltage of the medium voltage device, the second voltage level shifter 3 generates output signals VOUT2 and VOUT2' and is connected to the gate ends of the NMOS transistors N7, N8 of the third voltage level shifter 3 as input signals, the gate ends of the NMOS transistors N9, N10 are connected VQH, the voltage of the node3 or the node4 is lower than VQH when IN operation, the drain-gate voltages of the NMOS transistors N7, N8 are avoided, namely, the voltage between the nodes 3-VOUT 2', the voltage between the nodes 4-VOUT2' exceeds the rated voltage of the medium voltage device, the third voltage level shifter 3 generates output signals VOUT3 and VOUT3', VOUT3 can be respectively connected to the gate ends of the PMOS transistors and the NMOS transistors of the second inverter 11, the output terminal OUT' of the second inverter 11 is connected to the input terminal of the third inverter 12, and the third inverter 12 generates the output signal OUT, completing the process of converting the low voltage digital signal IN into the digital signal OUT of the power supply rail MAVDD-AVDD.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a driving device according to the present application. In order to solve the above technical problems, the present application further provides a driving device, which includes a timing controller 1, a source driver 22, and a voltage conversion circuit 21 as described above, wherein an input end of the voltage conversion circuit 21 is connected to an output end of the timing controller 1, and an output end is connected to an input end of the source driver 22.
It should be understood that, when the plurality of output terminals of one timing controller 1 output different low voltage data signals or the plurality of power ports of one source driver 22 require different target voltages, the plurality of voltage conversion circuits 21 may be disposed to be connected to different output terminals of the timing controller 1 or different power ports of the source driver 22, respectively, so as to implement a chip design process that requires a plurality of digital signals to be converted at the same time, and the present application is not limited in particular herein with respect to the specific types and implementation of the timing controller 1 and the source driver 22, the number of the voltage conversion circuits 21 to be disposed, and the like.
For an introduction of a driving device provided by the present application, please refer to the embodiment of the voltage conversion circuit 21, and the description of the present application is omitted herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A voltage conversion circuit, comprising:
the input end of the first inverter is connected with the output end of the time schedule controller and is used for outputting a voltage signal opposite to the output signal of the time schedule controller;
the first input end of the circuit after being connected in series is connected with the output end of the time sequence controller, the second input end of the circuit after being connected with the output end of the first inverter, the first power ends of the N voltage level shifters are respectively connected with first reference voltages with different values, the second power ends of the N voltage level shifters are respectively connected with second reference voltages with different values, for any voltage level shifter, the first reference voltage connected with the voltage level shifter is smaller than the maximum value of a voltage signal received by the voltage level shifter, the second reference voltage connected with the voltage level shifter is larger than the maximum value of the voltage signal received by the voltage level shifter, the voltage difference between the second reference voltage and the first reference voltage is not larger than a preset threshold value, and N is a positive integer larger than 1;
The voltage level shifter is used for outputting a first target voltage corresponding to a first reference voltage accessed by the voltage level shifter and a second target voltage corresponding to a second reference voltage accessed by the voltage level shifter based on control of a voltage signal received by the voltage level shifter.
2. The voltage conversion circuit of claim 1, wherein a first voltage level shifter sequentially connected in series comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein a gate of the first NMOS tube is connected with an output end of the timing controller, a source is connected with a first reference voltage and is connected with a source of the second NMOS tube, a gate of the second NMOS tube is connected with an output end of the first inverter, a source of the first PMOS tube and a source of the second PMOS tube are connected with a second reference voltage, a drain of the first PMOS tube is connected with a source of the third PMOS tube, a drain of the second PMOS tube is connected with a source of the fourth PMOS tube, a gate of the second PMOS tube is respectively connected with a gate of the third PMOS tube and a drain of the first NMOS tube, a gate of the first PMOS tube is respectively connected with a gate of the fourth PMOS tube and a drain of the second PMOS tube, and the first voltage level shifter is used as the first output end of the second voltage level shifter.
3. The voltage conversion circuit according to claim 1, wherein any one of the second voltage level shifters connected in series in sequence up to the nth voltage level shifter includes a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor, a gate of the third NMOS transistor is connected to a first output terminal of the last voltage level shifter connected in series with itself, a gate of the fourth NMOS transistor is connected to a second output terminal of the last voltage level shifter connected in series with itself, a source of the third NMOS transistor and a source of the fourth NMOS transistor are connected to a first reference voltage, a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected to a preset voltage corresponding to a maximum value of a voltage signal received by itself, a source of the fifth NMOS transistor is connected to a drain of the third NMOS transistor, a source of the sixth NMOS transistor is connected to a drain of the fourth NMOS transistor, a PMOS transistor is connected to a drain of the fifth PMOS transistor, a source of the fifth NMOS transistor is connected to a drain of the fifth NMOS transistor, a drain of the PMOS transistor is connected to a drain of the fifth NMOS transistor, a source of the fifth NMOS transistor is connected to a drain of the fifth NMOS transistor is connected to a maximum voltage.
4. The voltage conversion circuit of claim 1, wherein the first inverter comprises a first switching device and a second switching device, a first terminal of the first switching device is connected to a first power supply, a second terminal of the first switching device is connected to a first terminal of the second switching device, a second terminal of the second switching device is grounded, a control terminal of the first switching device is connected to a control terminal of the second switching device, and the control terminal of the first switching device is used as an input terminal of the first inverter, and a second terminal of the first switching device is used as an output terminal of the first inverter.
5. The voltage conversion circuit of claim 1, further comprising a second inverter and a third inverter, wherein an input terminal of the second inverter is connected to a first output terminal of the nth voltage level shifter, a first power terminal is connected to a first reference voltage corresponding to the nth voltage level shifter, a second power terminal is connected to a second reference voltage corresponding to the nth voltage level shifter, an output terminal is connected to an input terminal of the third inverter, a first power terminal of the third inverter is connected to a first reference voltage corresponding to the nth voltage level shifter, and a second power terminal is connected to a second reference voltage corresponding to the nth voltage level shifter.
6. The voltage conversion circuit of claim 5, wherein the second inverter comprises a third switching device and a fourth switching device, a first end of the third switching device is connected to a first reference voltage corresponding to an nth voltage level shifter, a control end of the third switching device is connected to a first output end of the nth voltage level shifter, a second end of the third switching device is connected to a first end of the fourth switching device, a control end of the fourth switching device is connected to a first output end of the nth voltage level shifter, a second end of the fourth switching device is connected to a second reference voltage corresponding to the nth voltage level shifter, and a first end of the fourth switching device serves as an output end of the second inverter.
7. The voltage conversion circuit according to claim 6, wherein the third inverter includes a fifth switching device and a sixth switching device, a first terminal of the fifth switching device is connected to a first reference voltage corresponding to an nth voltage level shifter, a second terminal of the fifth switching device is connected to the first terminal of the sixth switching device, a control terminal of the fifth switching device is connected to a control terminal of the sixth switching device, the first terminal of the fourth switching device and the second terminal of the third switching device, respectively, a second terminal of the sixth switching device is connected to a second reference voltage corresponding to the nth voltage level shifter, and the first terminal of the sixth switching device is used as an output terminal of the third inverter.
8. The voltage conversion circuit according to any one of claims 1 to 7, further comprising a reference voltage generation module connected to the first power supply terminals of the N voltage level shifters and the second power supply terminals of the N voltage level shifters, respectively, for outputting a reference voltage.
9. The voltage conversion circuit of claim 8, wherein the reference voltage generation module comprises an operational amplifier, a first resistor and a second resistor, a power supply terminal of the operational amplifier is connected to a second power supply, an inverting input terminal is connected to a first terminal of the first resistor and a first terminal of the second resistor, respectively, a second terminal of the first resistor is grounded, a second terminal of the second resistor is connected to an output terminal of the operational amplifier, and an output terminal of the operational amplifier is used as an output terminal of the reference voltage generation module.
10. A driving device comprising a timing controller, a source driver and a voltage conversion circuit according to any one of claims 1 to 9, wherein an input terminal of the voltage conversion circuit is connected to an output terminal of the timing controller, and an output terminal is connected to an input terminal of the source driver.
CN202311030063.7A 2023-08-15 2023-08-15 Voltage conversion circuit and driving device Pending CN116978332A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315610A1 (en) * 2008-06-24 2009-12-24 Hee-Seok Han Integrated Circuit Devices Having Level Shifting Circuits Therein
CN102820880A (en) * 2011-06-09 2012-12-12 美格纳半导体有限公司 Level shifter and method of using the same
CN109347473A (en) * 2018-09-04 2019-02-15 上海东软载波微电子有限公司 Level shift circuit
CN112436834A (en) * 2020-11-27 2021-03-02 广州鸿博微电子技术有限公司 Signal level conversion circuit and implementation method thereof
CN114694607A (en) * 2020-12-25 2022-07-01 蓝碧石科技株式会社 Signal level conversion circuit, drive circuit, display driver, and display device
CN115588415A (en) * 2022-12-08 2023-01-10 禹创半导体(深圳)有限公司 Driving chip for LCD panel power supply system and LCD panel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315610A1 (en) * 2008-06-24 2009-12-24 Hee-Seok Han Integrated Circuit Devices Having Level Shifting Circuits Therein
CN102820880A (en) * 2011-06-09 2012-12-12 美格纳半导体有限公司 Level shifter and method of using the same
CN109347473A (en) * 2018-09-04 2019-02-15 上海东软载波微电子有限公司 Level shift circuit
CN112436834A (en) * 2020-11-27 2021-03-02 广州鸿博微电子技术有限公司 Signal level conversion circuit and implementation method thereof
CN114694607A (en) * 2020-12-25 2022-07-01 蓝碧石科技株式会社 Signal level conversion circuit, drive circuit, display driver, and display device
CN115588415A (en) * 2022-12-08 2023-01-10 禹创半导体(深圳)有限公司 Driving chip for LCD panel power supply system and LCD panel

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