CN116959974A

CN116959974A - Method for manufacturing semiconductor structure and semiconductor structure

Info

Publication number: CN116959974A
Application number: CN202210385869.7A
Authority: CN
Inventors: 吴玉雷
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-13
Filing date: 2022-04-13
Publication date: 2023-10-27
Also published as: WO2023197432A1

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors, wherein the method for manufacturing the semiconductor structure comprises providing a target layer; forming a plurality of first mask patterns on the top surface of the target layer; forming a plurality of second mask patterns over the target layer, each second mask pattern covering at least a portion of a top surface of each first mask pattern in an extension direction thereof and a portion of a top surface of the target layer; performing first etching on the target layer based on the second mask pattern; removing the second mask pattern; and performing second etching on the target layer based on the first mask pattern. In the method, the target layer is etched twice through the second mask pattern and the first mask pattern respectively, so that a repeated structure which is finer and more complex and higher in density is formed by etching, the difficulty of forming the repeated structure is reduced, and the method is beneficial to forming an integrated circuit with high integration level.

Description

Method for manufacturing semiconductor structure and semiconductor structure

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.

Background

With the development of integrated circuits (Integrated Circuit, ICs), the feature sizes of electronic components in the integrated circuits are continuously reduced and the integration density is continuously increased, so that the integrated circuits have higher integration levels. However, the feature sizes of electronic devices have been reduced to the physical limit of the size that can be achieved by the mainstream photolithography technology, and the resolution of the photolithography technology is difficult to meet the manufacturing requirements of the integrated circuit, and the manufacturing process of the integrated circuit faces a great challenge.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure.

A first aspect of the present disclosure provides a method for fabricating a semiconductor structure, the method comprising:

providing a target layer;

forming a plurality of first mask patterns on the top surface of the target layer, wherein two arbitrarily adjacent first mask patterns in the first direction are arranged at intervals;

forming a plurality of second mask patterns above the target layer, each second mask pattern extending in the first direction and being disposed apart from each other, each second mask pattern covering at least a portion of a top surface of each first mask pattern in the extending direction thereof and a portion of a top surface of the target layer;

performing first etching on the target layer based on the second mask pattern;

and performing second etching on the target layer based on the first mask pattern.

According to some embodiments of the present disclosure, forming a plurality of first mask patterns on a top surface of the target layer includes:

forming a crossover structure on the target layer, the crossover structure including an overlap region;

removing part of the cross structure, reserving part of the overlapped area, and forming a plurality of initial mask patterns in the reserved overlapped area;

and removing part of the structure of each initial mask pattern, wherein the part of the structure of each initial mask pattern which is reserved is formed into the first mask pattern.

According to some embodiments of the present disclosure, forming a crossover structure on the target layer includes:

forming a plurality of first line structures, each first line structure extending along a second direction, the plurality of first line structures being disposed in a spaced apart relationship in a direction perpendicular to the second direction, the first direction obliquely intersecting the second direction;

forming a plurality of second line structures, wherein the second line structures are positioned above the first line structures, extend along a third direction, are arranged at intervals in a direction perpendicular to the third direction, and are obliquely intersected with the third direction;

the plurality of first line structures and the plurality of second line structures together form the intersection structure, and overlapping portions of the plurality of first line structures and the plurality of second line structures form the overlapping region.

According to some embodiments of the present disclosure, forming a plurality of second mask patterns over the target layer includes:

forming a second mask material layer, wherein the second mask material layer covers the initial mask pattern and the exposed top surface of the target layer;

and removing part of the second mask material layer to form a plurality of second mask patterns extending along the first direction, wherein any two adjacent second mask patterns are separated by a first groove in the direction perpendicular to the first direction.

According to some embodiments of the present disclosure, a projection of each of the second mask patterns formed on the target layer is divided into a plurality of sub-patterns which are independently disposed by a projection of the first mask pattern located in an extending direction thereof formed on the target layer.

According to some embodiments of the present disclosure, performing a first etching on the target layer based on the second mask pattern includes:

and removing part of the target layer exposed by the second mask pattern, etching the reserved part of the target layer to form a plurality of active strips extending along the first direction, and separating two adjacent active strips by a first shallow trench in the direction perpendicular to the first direction.

According to some embodiments of the disclosure, the method further comprises:

a first isolation material is deposited to form a first isolation layer, and the first isolation layer fills the first shallow trench and covers the first mask pattern and the top surface of the active strip exposed by the first mask pattern.

According to some embodiments of the disclosure, the method further comprises:

and flattening the top surfaces of the first isolation layers to expose the top surfaces of the plurality of first mask patterns.

According to some embodiments of the present disclosure, performing a second etching on the target layer based on the first mask pattern includes:

and removing the first mask pattern and part of the active strip covered by the first mask pattern, wherein the reserved part of the active strip forms a plurality of independently arranged active areas, the active areas extend along the first direction, and two adjacent active areas are separated by a second shallow trench in the first direction.

According to some embodiments of the disclosure, the method further comprises:

and filling a second isolation material in the second shallow trench to form a second isolation layer.

According to some embodiments of the disclosure, the method further comprises:

and removing the first isolation layer and the second isolation layer above the top surface of the target layer, wherein the reserved first isolation layer and the reserved second isolation layer form a shallow trench isolation structure together.

According to some embodiments of the disclosure, the first and second insulating materials comprise the same or different materials.

According to some embodiments of the disclosure, the method further comprises:

and forming a plurality of word lines, wherein each word line extends along the fourth direction and penetrates through the plurality of active areas in the extending direction, and the plurality of word lines are arranged at intervals.

According to some embodiments of the present disclosure, the second direction and the third direction intersect at a first angle, the first direction and the fourth direction intersect at a second angle, and the relationship between the first angle and the second angle is as follows:

wherein, the first contained angle is alpha 1, and the second contained angle is alpha 2.

A second aspect of the present disclosure provides a semiconductor structure fabricated according to the method for fabricating a semiconductor structure described above.

In the manufacturing method of the semiconductor structure and the semiconductor structure provided by the embodiment of the disclosure, the second mask pattern and the first mask pattern are used as masks to etch the target layer twice, so that the target layer is etched to form a more fine and complex repeated structure with higher density, the difficulty of forming the repeated structure is reduced, and the formation of the integrated circuit with high integration level is facilitated.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 2 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 3 is a schematic diagram illustrating formation of a first line structure on a target layer according to an example embodiment.

Fig. 4 is a schematic diagram illustrating formation of a first layer structure according to an example embodiment.

Fig. 5 is a schematic diagram illustrating the formation of a second dielectric layer according to an example embodiment.

Fig. 6 is a schematic diagram illustrating formation of a second line structure according to an example embodiment.

Fig. 7 is a schematic diagram illustrating a formed crossover structure according to an example embodiment.

Fig. 8 is a top view of a formed crossover structure, according to an example embodiment.

Fig. 9 is a top view illustrating etching of a first layer structure according to a second line structure, according to an example embodiment.

Fig. 10 is a schematic diagram illustrating the formation of an initial mask pattern according to an exemplary embodiment.

Fig. 11 is a schematic diagram illustrating the formation of a second mask material layer according to an exemplary embodiment.

Fig. 12 is a top view of a third reticle and an initial mask pattern shown according to an example embodiment.

Fig. 13 is a schematic diagram illustrating formation of a second mask pattern according to an exemplary embodiment.

Fig. 14 is a top view of the second mask pattern and the first mask pattern shown according to an exemplary embodiment.

Fig. 15 is a schematic diagram illustrating a first etching of a target layer according to an exemplary embodiment.

Fig. 16 is a schematic diagram illustrating formation of a first isolation layer according to an exemplary embodiment.

Fig. 17 is a schematic diagram illustrating a second etching of a target layer according to an exemplary embodiment.

Fig. 18 is a schematic diagram illustrating the formation of a second isolation layer according to an example embodiment.

Fig. 19 is a schematic diagram illustrating the formation of isolation structures according to an example embodiment.

Fig. 20 is a top view of an active region shown in accordance with an exemplary embodiment.

FIG. 21 is a top view illustrating the formation of word lines and bit lines according to an example embodiment.

FIG. 22 is a schematic diagram of a constructed coordinate system shown according to an example embodiment.

Reference numerals:

100. a target layer; 110. an active stripe; 111. an active region; 120. a first shallow trench; 130. a second shallow trench; 200. a crossing structure; 201. a first mask pattern; 210. a first wire structure; 211. an initial mask pattern; 220. A second line structure; 221. a second dielectric layer; 230. an auxiliary layer; 240. a first layer structure; 250. an overlap region; 260. a third mask; 300. a second mask material layer; 310. a second mask pattern; 311. a sub-graph; 320. A first trench; 400. shallow trench isolation structures; 410. a first isolation layer; 420. a second isolation layer; 500. a word line; 600. a bit line;

d1, a first direction; d2, a second direction; d3, a third direction; d4, in the fourth direction; α1, a first included angle; α2, a second angle; α3, a third angle; α4, fourth included angle.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some, but not all, embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that may be made by those skilled in the art without the inventive effort are within the scope of the present disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, where a second mask pattern and a first mask pattern are used as masks to perform two etching processes on a target layer, so that a repetitive structure with a finer and more complex shape and higher density can be formed in the target layer.

As shown in fig. 1, fig. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, in which the method for fabricating a semiconductor structure includes the following steps.

Step S110: a target layer is provided.

Referring to fig. 13, the target layer 100 refers to a material layer to be etched that needs to be patterned, and the target layer 100 may be any configuration for forming a semiconductor element.

The target layer 100 may be a semiconductor substrate, and a material of the semiconductor substrate may include silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); silicon On Insulator (SOI) or Germanium On Insulator (GOI); or may include other materials such as III-V compounds such as gallium arsenide. Part of impurity ions can be doped in the semiconductor substrate according to the requirement, and the impurity ions can be N-type impurity ions or P-type impurity ions.

The target layer 100 may also be a material layer, such as a dielectric layer or a metal layer, used to form a semiconductor element. The material layer may be, for example, an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, or the like, without being limited thereto.

Step S120: a plurality of first mask patterns are formed on the top surface of the target layer, and two arbitrarily adjacent first mask patterns in the first direction are arranged at a distance from each other.

Referring to fig. 13 and 14, in the present embodiment, a plurality of first mask patterns 201 are independently provided on the top surface of the target layer 100, and in the first direction D1, the plurality of first mask patterns 201 are arranged in a plurality of rows, and any two adjacent first mask patterns 201 in the first direction D1 are arranged at a distance.

Step S130: a plurality of second mask patterns are formed over the target layer, each second mask pattern extending in the first direction and being disposed apart from each other, each second mask pattern covering at least a portion of a top surface of each first mask pattern in the extending direction thereof and a portion of a top surface of the target layer.

Referring to fig. 13 and 14, each of the second mask patterns 310 formed in the present embodiment is correspondingly disposed on one row of the first mask patterns 201, and each of the second mask patterns 310 correspondingly fills a partial region between two adjacent first mask patterns 201 in the same row.

In the present embodiment, the projection of each second mask pattern 310 formed on the target layer 100 is divided into a plurality of sub-patterns 311 which are independently arranged by the projection of the first mask pattern 201 located in the extending direction thereof formed on the target layer 100. In other embodiments, the shapes and arrangement densities of the first and second mask patterns 201 and 310 are set according to the semiconductor structure to be formed.

Step S140: and performing first etching on the target layer based on the second mask pattern.

Referring to fig. 13, 14 and 15, in the present embodiment, the second mask pattern 310 is used as a mask to etch the target layer 100, a portion of the target layer 100 exposed by the second mask pattern 310 is removed, the pattern of the second mask pattern 310 is extended into the target layer 100, and the target layer 100 is left to form a plurality of structures that are independently arranged. The etching process of the first etching can be dry etching or wet etching.

Step S150: and performing second etching on the target layer based on the first mask pattern.

First, the second mask pattern 310 is removed by dry or wet etching, exposing the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310.

Then, referring to fig. 17 and 20, the first mask pattern 201 and a portion of the target layer 100 covered by the first mask pattern 201 are etched away to extend the pattern of the first mask pattern 201 into the target layer 100, dividing the target layer 100, which is left by the etching, into a plurality of independently arranged sub-structures.

According to the manufacturing method of the semiconductor structure, the first mask pattern and the second mask pattern are formed on the target layer, the target layer is etched for two times according to the second mask pattern and the first mask pattern, and the high-density repeated structure is formed in the target layer.

Fig. 2 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, and fig. 3 to 22 are schematic views illustrating various stages of the method for fabricating a semiconductor structure according to the present embodiment, and the method for fabricating a semiconductor structure according to the present embodiment is described below with reference to fig. 3 to 22.

In the exemplary embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, the semiconductor structure is not limited to this embodiment, and the semiconductor structure is described below as a dynamic random access memory (Dynamic Random Access Memory, DRAM) for example, to form an active region in the semiconductor structure to describe this embodiment, but the present embodiment is not limited to this, and the semiconductor structure in this embodiment may also be other structures.

In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, as shown in fig. 2, including the following steps:

step S210: a target layer is provided.

As shown in fig. 3, in the present embodiment, the target layer 100 is a semiconductor substrate, and the material of the semiconductor substrate is the same as that of the semiconductor substrate in the above embodiment.

Step S220: a plurality of initial mask patterns are formed on the top surface of the target layer, and two adjacent initial mask patterns are arranged at intervals in the first direction.

A plurality of initial mask patterns 211 are formed on the top surface of the target layer 100, and the following method may be employed:

step S221: a crossover structure is formed on the target layer, the crossover structure including an overlap region.

First, as shown in fig. 3, a plurality of first line structures 210 are formed on the top surface of the target layer 100, each of the first line structures 210 extends along the second direction D2, the plurality of first line structures 210 are disposed apart in a direction perpendicular to the second direction D2, and the first direction D1 obliquely intersects the second direction D2.

A dielectric material may be deposited by a chemical vapor deposition process or a physical vapor deposition process, and a first dielectric layer (not shown) may be formed on the top surface of the target layer 100, wherein the material of the first dielectric layer may include silicon nitride and/or silicon oxide.

Referring to fig. 8, a first mask (not shown) is formed on a top surface of the first dielectric layer, a portion of the first dielectric layer is removed according to the first mask etching, and the remaining first dielectric layer forms a plurality of first line structures 210 that are independently disposed, each of the first line structures 210 extending in the second direction D2, and two adjacent first line structures 210 are disposed apart in a direction perpendicular to the second direction D2.

Then, as shown in fig. 4, an auxiliary material may be deposited by an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (Chemical Vapor Deposition, CVD), the auxiliary material forming an auxiliary layer 230, the auxiliary layer 230 covering the first line structures 210 and filling the trenches between adjacent first line structures 210, the auxiliary layer 230 and the first line structures 210 together forming a first layer structure 240. The polishing process then polishes the top surface of the first layer structure 240 to a plane so that the second line structure 220 is subsequently formed on the top surface of the first layer structure 240. The material of the auxiliary layer 230 may include, but is not limited to, silicon nitride, silicon oxynitride, and the like. The auxiliary layer 230 may also be formed by other processes in some embodiments, for example, the auxiliary layer 230 may be formed by Spin-coating an auxiliary material by a Spin-coating process, and the material of the auxiliary layer 230 may be Spin-on Carbon (SOC).

Next, as shown in fig. 5, a dielectric material may be deposited by a chemical vapor deposition process or a physical vapor deposition process, and a second dielectric layer 221 is formed on the top surface of the target layer 100, wherein the material of the second dielectric layer 221 may include silicon nitride and/or silicon oxide.

As shown in fig. 6, 7 and 8, a second mask (not shown) is formed on the top surface of the second dielectric layer 221, a portion of the second dielectric layer 221 is etched away according to the second mask, the remaining second dielectric layer 221 forms a plurality of second line structures 220, the plurality of second line structures 220 are located above the first line structures 210, the plurality of second line structures 220 are independently disposed, each of the second line structures 220 extends along a third direction D3, the plurality of second line structures 220 are disposed at intervals in a direction perpendicular to the third direction D3, and the first direction D1 obliquely intersects the third direction D3.

As shown in fig. 7 and 8, the first line structure 210 and the second line structure 220 form a cross structure 200 in the space above the target layer 100, and the first line structure 210 and the second line structure 220 have an overlapping portion in the space above the target layer 100, and the overlapping portion is an overlapping region 250 of the cross structure 200.

Step S222: and removing part of the cross structure, reserving part of the overlapped area, and forming a plurality of initial mask patterns in the reserved overlapped area.

The removal of portions of the intersection structure 200 may be performed by the following method:

referring to fig. 6, referring to fig. 9, the first layer structure 240 is etched according to the second line structure 220, the auxiliary layer 230 and the first line structure 210 exposed by the second line structure 220 are removed, the pattern of the second line structure 220 is transferred into the first layer structure 240, and the reserved first layer structure 240 includes a portion of the first line structure 210 and a portion of the auxiliary layer 230, wherein the reserved portion of the first line structure 210 corresponds to the overlap region 250 of the crossing structure 200.

Then, as shown in fig. 10, referring to fig. 6 and 9, the remaining first layer structure 240 is exposed by dry etching or wet etching all of the second line structure 220. The auxiliary layer 230 in the reserved first layer structure 240 may be removed by dry or wet etching, and the reserved first line structure 210 may be formed with a plurality of initial mask patterns 211 independent of each other, and the plurality of initial mask patterns 211 formed in this embodiment may be arranged in a plurality of rows along the first direction D1.

In this embodiment, the first line structure 210 and the second line structure 220 are formed on the target layer 100 in a stacked manner, and only the overlapping area of the first line structure 210 and the second line structure 220 is remained by etching the second line structure 220 and a part of the first line structure 210, so that the feature size of the initial mask pattern 211 is small, and the first mask pattern 201 (refer to fig. 14) formed by the initial mask pattern 211 according to this embodiment is smaller, and in the subsequent second etching process, the target layer 100 can be etched according to the first mask pattern 201 to form a repeated structure with a larger repetition density and a smaller size.

Step S230: a second masking material layer is formed that covers the initial masking pattern and the exposed top surface of the target layer.

As shown in fig. 11, referring to fig. 10, a second mask material layer 300 may be deposited by a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or a physical vapor deposition process (Physical Vapor Deposition, PVD), and the second mask material layer 300 covers the initial mask pattern 211 and the exposed top surface of the target layer 100.

Step S240: and removing part of the second mask material layer to form a plurality of second mask patterns extending along the first direction, and simultaneously removing part of the structure of each initial mask pattern, wherein the part of the structure of each initial mask pattern which is reserved forms a first mask pattern.

Referring to fig. 11, as shown in fig. 12, a third mask 260 is formed on the top surface of the second mask material layer 300, and the second mask material layer 300 and the initial mask pattern 211 are etched according to the third mask 260. As shown in fig. 13 and 14, the remaining second mask material layer 300 forms a plurality of second mask patterns 310 extending in the first direction D1, and the remaining portion of each of the initial mask patterns 211 forms the first mask pattern 201, and any adjacent two of the second mask patterns 310 are separated by a first trench 320 in a direction perpendicular to the first direction D1, and the first trench 320 exposes a portion of the top surface of the target layer 100.

As shown in fig. 14, the projection of each second mask pattern 310 formed on the target layer 100 is divided into a plurality of sub-patterns 311 which are independently arranged by the projection of the first mask pattern 201 located in the extending direction thereof formed on the target layer 100. So that the target layer 100 is subsequently etched according to the first mask pattern 201 and the second mask pattern 310 to form a plurality of independently disposed active regions 111.

In the present embodiment, a plurality of first mask patterns 201 and a plurality of second mask patterns 310 are simultaneously formed, the projection of each second mask pattern 310 formed on the target layer 100 is divided into a plurality of sub patterns 311 which are independently provided by the projection of the first mask pattern 201 on the target layer 100 in the extending direction thereof, and the projection of the first mask pattern 201 on the target layer 100 is located in the projection of the second mask pattern 310 formed on the target layer 100. The arrangement positions and distribution of the first mask pattern 201 and the second mask pattern 310 formed in this embodiment can ensure that the target layer 100 is etched into the plurality of active regions 111 according to the first mask pattern 201 and the second mask pattern 310.

Step S250: and performing first etching on the target layer based on the second mask pattern.

Referring to fig. 15 and fig. 13, in the present embodiment, the target layer 100 is etched using the second mask pattern 310 as a mask, a portion of the target layer 100 exposed by the second mask pattern 310 is removed, and the remaining portion of the target layer 100 is etched to form a plurality of active stripes 110 extending along the first direction D1, and two adjacent active stripes 110 are separated by the first shallow trench 120 in a direction perpendicular to the first direction D1. The etching process of the first etching can be dry etching or wet etching.

Step S260: a first isolation layer is formed, and fills the first shallow trench.

Referring to fig. 15, the second mask pattern 310 is removed by dry or wet etching, exposing the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310.

As shown in fig. 16, in this embodiment, the first isolation layer 410 may be formed by depositing the first isolation material through any one of an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, and the first isolation layer 410 fills the first shallow trench 120 and covers the first mask pattern 201 and the top surface of the active stripe 110 exposed by the first mask pattern 201. The first isolation material may include one of silicon oxide, silicon nitride, or silicon oxynitride. Then, the top surfaces of the first isolation layers 410 are planarized by a chemical mechanical polishing (Chemical Mechanical Polish, CMP) process, exposing the top surfaces of the plurality of first mask patterns 201, so that the active stripes 110 are subsequently subjected to a second etching according to the first mask patterns 201.

Step S270: and performing second etching on the target layer based on the first mask pattern.

As shown in fig. 17, referring to fig. 16, the target layer 100 is subjected to the second etching based on the first mask pattern 201, and the following method may be adopted: the first mask pattern 201 and the portion of the active stripe 110 covered by the first mask pattern 201 are removed, the remaining portion of the active stripe 110 forms a plurality of independently disposed active regions 111, the active regions 111 extend along a first direction D1, and adjacent two active regions 111 are separated by a second shallow trench 130 in the first direction D1, the second shallow trench 130 extending the pattern of the first mask pattern 201 into the active stripe 110.

Step S280: and filling a second isolation material in the second shallow trench to form a second isolation layer.

As shown in fig. 18, referring to fig. 17, a second isolation layer 420 is formed by depositing a second isolation material through any one of an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, and the second isolation layer 420 fills the second shallow trench 130 and covers the first isolation layer 410. The second isolation material may comprise one of silicon oxide, silicon nitride or silicon oxynitride, the first isolation material and the second isolation material comprising the same or different materials.

Then, referring to fig. 18, as shown in fig. 19, the first isolation layer 410 and the second isolation layer 420 located above the top surface of the target layer 100 are etched away, and the first isolation layer 410 and the second isolation layer 420 that are left together form a shallow trench isolation structure 400, and the top surface of the shallow trench isolation structure 400 is flush with the top surface of the active region 111.

In this embodiment, the target layer is etched into a plurality of independently arranged active regions, so that the difficulty in forming the active regions is reduced, the active regions with smaller size can be formed, the resolution precision requirement on the photolithography process is lower, the process difficulty and the process cost are reduced, and the method is suitable for forming integrated circuits with high integration level.

In this embodiment, the shallow trench isolation structure is formed by two different deposition processes, and the two deposition processes can select different materials to be filled according to the depth-to-width ratio of the first shallow trench and the second shallow trench, so that the first shallow trench and the second shallow trench are ensured to be filled with isolation materials, the formed shallow trench isolation structure is ensured to have high density and stable structure, good electrical isolation effect is achieved, short circuit of an active region can be better avoided, good electrical performance of a semiconductor structure is ensured, filling difficulty caused by complex shape of the trench between the active regions is avoided, partial region filling of the trench is not full, and isolation effect of the shallow trench isolation structure is reduced.

According to an exemplary embodiment, as shown in fig. 2, the following steps are added to the above embodiment:

step S290: a plurality of word lines are formed, each extending in the fourth direction and penetrating the plurality of active regions in the extending direction thereof, and the plurality of word lines are disposed apart from each other.

The second direction D2 and the third direction D3 intersect at a first angle α1, the first direction D1 and the fourth direction D4 intersect at a second angle α2, and the relationship between the first angle α1 and the second angle α2 is as follows:

wherein the first included angle is alpha 1, and the second included angle is alpha 2.

As shown in fig. 21, referring to fig. 20, in forming the word line 500, a word line mask is first formed, the word line mask covering a portion of the active region 111 and a portion of the top surface of the shallow trench isolation structure 400, the word line mask extending in the fourth direction D4. The active regions 111 and the shallow trench isolation structures 400 are etched according to a word line mask to form word line trenches that extend through the active regions 111 in a fourth direction D4, each active region 111 being penetrated by two word line trenches. Then, the word line 500 is formed in the word line trench.

Step S300: and forming a bit line, wherein the bit line covers the top surface of part of the active region and the top surface of part of the isolation structure, and extends along the fifth direction, and the fifth direction is vertical to the fourth direction.

As shown in fig. 21, referring to fig. 20, a plurality of bit lines 600 are formed on the top surfaces of the active region 111 and the shallow trench isolation structure 400, each bit line 600 extends along the fifth direction D5, and the plurality of bit lines 600 are disposed at equal intervals in the fourth direction D4.

The length and arrangement mode of the active region formed in the embodiment can meet the process requirements of other electronic elements, and the word lines and bit lines formed in the patterned target layer in the embodiment are arranged in accordance with the process requirements of the DRAM.

According to an exemplary embodiment, this embodiment is an illustration of the implementation of the step S220, and in the implementation process, a plurality of initial mask patterns are formed on the top surface of the target layer, and further includes the following steps:

the arrangement direction of the first and second line structures 210 and 220 to be formed is defined according to the target layer 100. This step is performed before the formation of the intersection 200 on the target layer 100.

Since the present exemplary embodiment is described with respect to the process of forming the active region 111, in the semiconductor field, the process of forming the DRAM memory generally includes the process of forming the word line 500 penetrating through the active region 111 after forming the active region 111.

In the present embodiment, referring to fig. 21, a subsequently formed word line 500 extends in the fourth direction D4. In a plane parallel to the top surface of the target layer 100, the first direction D1 and the fourth direction D4 intersect at a second included angle α2. In this embodiment, the second included angle α2 is an acute angle. The second included angle α2 may be, for example, 50 ° to 85 °. For example, the second included angle α2 may be 50 °, 53 °, 56 °, 59 °, 63 °, 66 °, 69 °, 74 °, 75 °, 77 °, 79 °, 81 °, 83 °, or 85 °.

In this step, the fourth direction D4 of the word line 500 in the subsequent process is taken as the X axis, and the first direction D1 in which the active region 111 extends is taken as the Y axis, so as to establish the coordinate system XOY. The coordinate system XOY established in this embodiment is an oblique coordinate system. Then, the extending direction of the first line structure 210 and the extending direction of the second line structure 220 to be formed are determined according to the coordinate system XOY.

In the present embodiment, the extending direction of the first line structure 210 to be formed is defined as the second direction D2, and the extending direction of the second line structure 220 to be formed is defined as the third direction D3. The second direction D2 intersects the third direction D3 at a first included angle α1. In this embodiment, the first included angle α1 is 70 ° to 95 °. For example, the first included angle may be 70 °, 72 °, 75 °, 77 °, 79 °, 82 °, 85 °, 88 °, 90 °, 92 °, or 95 °. As shown in fig. 22, the second direction D2 and the first direction D1 obliquely intersect, and the second direction D2 obliquely intersects with the fourth direction D4. The included angle between the second direction D2 and the fourth direction D4 is a third included angle alpha 3, and the third included angle alpha 3 is 30-50 degrees. Illustratively, the third included angle α3 may be 30 °, 32 °, 34 °, 36 °, 37 °, 39 °, 41 °, 45 °, or 50 °. As shown in fig. 22, the third direction D3 and the first direction D1 obliquely intersect, and the third direction D3 obliquely intersects with the fourth direction D4. The included angle between the third direction D3 and the fourth direction D4 is a fourth included angle alpha 4, and the fourth included angle alpha 4 is 30-50 degrees. Illustratively, the fourth included angle α4 may be 30 °, 32 °, 34 °, 36 °, 37 °, 39 °, 41 °, 45 °, or 50 °.

The first angle α1 is equal to the sum of the third angle α3 and the fourth angle α4. For example, the first angle α1 is 80 degrees, the third angle α3 is 30 °, and the fourth angle α4 is 50 °. In this embodiment, the angles of the third included angle α3 and the fourth included angle α4 are equal. For example, the first angle α1 is 82 degrees, the third angle α3 is 41 °, and the fourth angle α4 is 41 °. Meanwhile, the relationship between the first included angle α1 and the second included angle α2 is as follows:

in this embodiment, according to the extending direction of the active region to be formed and the extending direction of the word line in the subsequent word line process, the extending direction of the first line structure to be formed and the setting direction and the included angle of the second line structure are defined, so that a plurality of initial mask patterns are formed to be arranged in a plurality of rows along the first direction, it is ensured that the projection formed by the second mask pattern formed subsequently on the target layer can be divided into a plurality of sub-patterns which are independently set by the projection formed by the first mask pattern located in the extending direction on the target layer, and the arrangement of the active region formed by the first mask pattern and the second mask pattern meets the process requirement of the DRAM memory.

According to an exemplary embodiment, a semiconductor structure is provided, which is formed according to the method for manufacturing the semiconductor structure in the above embodiment. The semiconductor structure of the present embodiment may be a memory chip, which may be used in a dynamic random access memory (Dynamic Random Access Memory, DRAM). However, it is also applicable to Static Random-Access Memory (SRAM), flash EPROM (flash EPROM), ferroelectric Memory (Ferroelectric Random-Access Memory, FRAM), magnetic Random-Access Memory (MRAM), phase change Random-Access Memory (PRAM), and the like.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements to be referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced equivalently; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, the method comprising:

providing a target layer;

forming a plurality of second mask patterns above the target layer, each second mask pattern extending in the first direction and being spaced apart from each other, each second mask pattern covering at least a portion of a top surface of each first mask pattern in the direction of extension thereof and a portion of a top surface of the target layer;

performing first etching on the target layer based on the second mask pattern;

2. The method of claim 1, wherein forming a plurality of first mask patterns on a top surface of the target layer comprises:

and removing part of the structure of each initial mask pattern, and forming the first mask pattern by the reserved part of the structure of each initial mask pattern.

3. The method of fabricating a semiconductor structure of claim 2, wherein forming a cross-over structure on the target layer comprises:

forming a plurality of first line structures, each first line structure extending along a second direction, the plurality of first line structures being disposed apart in a direction perpendicular to the second direction, the first direction obliquely intersecting the second direction;

forming a plurality of second line structures, wherein the plurality of second line structures are positioned above the first line structures, the second line structures extend along a third direction, the plurality of second line structures are arranged at intervals in a direction perpendicular to the third direction, and the first direction obliquely intersects with the third direction;

4. The method of fabricating a semiconductor structure according to claim 2, wherein forming a plurality of second mask patterns over the target layer comprises:

5. A method of fabricating a semiconductor structure according to claim 3, wherein the projection of each of the second mask patterns formed on the target layer is divided into a plurality of sub-patterns which are independently arranged by the projection of the first mask pattern located in the extending direction thereof formed on the target layer.

6. The method of fabricating a semiconductor structure according to claim 5, wherein performing a first etch of the target layer based on the second mask pattern comprises:

7. The method of fabricating a semiconductor structure of claim 6, further comprising:

8. The method of fabricating a semiconductor structure of claim 7, further comprising:

9. The method of fabricating a semiconductor structure of claim 8, wherein performing a second etch on the target layer based on the first mask pattern comprises:

10. The method of fabricating a semiconductor structure of claim 9, further comprising:

11. The method of fabricating a semiconductor structure of claim 10, further comprising:

12. The method of claim 10, wherein the first isolation material and the second isolation material comprise the same or different materials.

13. The method of fabricating a semiconductor structure of claim 9, further comprising:

14. The method of claim 13, wherein the second direction and the third direction intersect at a first included angle, the first direction and the fourth direction intersect at a second included angle, and the relationship between the first included angle and the second included angle is as follows:

15. A semiconductor structure, characterized in that it is manufactured according to the method of manufacturing a semiconductor structure according to any of the preceding claims 1-14.