CN117832164A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN117832164A CN117832164A CN202211186516.0A CN202211186516A CN117832164A CN 117832164 A CN117832164 A CN 117832164A CN 202211186516 A CN202211186516 A CN 202211186516A CN 117832164 A CN117832164 A CN 117832164A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 238000003860 storage Methods 0.000 claims abstract description 138
- 239000000463 material Substances 0.000 claims abstract description 125
- 230000002093 peripheral effect Effects 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000011810 insulating material Substances 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims description 152
- 230000004888 barrier function Effects 0.000 claims description 151
- 239000007769 metal material Substances 0.000 claims description 66
- 229910052751 metal Inorganic materials 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 44
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 abstract description 12
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 373
- 238000002955 isolation Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 239000006227 byproduct Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same, the method of fabricating the semiconductor structure including the following steps. Providing a substrate, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area; forming a storage node contact structure and a first contact structure; forming an insulating material layer; patterning the insulating material layer to remove the insulating material layer in the array region, and forming a second contact hole exposing the first contact structure in the insulating material layer in the peripheral region to obtain an insulating layer; forming a conductive contact layer and a second contact structure; the conductive contact layer and the storage node contact structure are patterned to form landing pads. The preparation method can avoid etching the material of the second contact structure, thereby ensuring the electrical characteristics of the second contact structure and the first contact structure and avoiding being polluted by etching, further being beneficial to ensuring the electrical characteristics of the contact structure and improving the reliability of the semiconductor structure.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technology, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses. DRAM is comprised of a plurality of repeating memory cells. Each memory cell typically includes a capacitance structure and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitance structure.
At present, with the development of semiconductor technology, particularly after the semiconductor process enters into deep submicron and nanometer stages, the size of each component element and the distance between adjacent elements in DRAM are also smaller and smaller, and the preparation of partial elements is widely performed by using high aspect ratio ion etching technology. However, contact structures located in the peripheral region are prone to by-products that are difficult to remove during etching. In addition, with the miniaturization of the DRAM size, the sizes of all the component elements and the spacing between the adjacent elements in the DRAM are also continuously miniaturized, and the existence of byproducts is easy to cause electric leakage and even short circuit, thereby seriously affecting the production yield of the DRAM.
Therefore, how to effectively avoid the by-products generated in the etching process of the contact structure located in the peripheral area is also a problem to be solved in the related art.
Disclosure of Invention
Based on this, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can effectively avoid the problem that a contact structure located in a peripheral region generates byproducts in an etching process, thereby being beneficial to ensuring the electrical characteristics of the contact structure and improving the reliability of the semiconductor structure.
In one aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with an array region and a peripheral region positioned on at least one side of the array region, and comprises a bit line structure and a storage node contact hole which are positioned in the array region, a dielectric layer positioned in the peripheral region and a first contact hole penetrating through the dielectric layer; forming a storage node contact structure and a first contact structure, wherein the storage node contact structure fills the storage node contact hole, and the first contact structure fills the first contact hole; forming an insulating material layer, wherein the insulating material layer covers the bit line structure, the storage node contact structure, the dielectric layer and the first contact structure; patterning the insulating material layer to remove the insulating material layer in the array region, and forming a second contact hole exposing the first contact structure in the insulating material layer in the peripheral region to obtain an insulating layer; forming a conductive contact layer and a second contact structure, wherein the conductive contact layer covers the bit line structure and the storage node contact structure, and the second contact structure fills the second contact hole and is coupled with the first contact structure; the conductive contact layer and the storage node contact structure are patterned to form landing pads.
In some embodiments of the present disclosure, forming the storage node contact structure and the first contact structure includes: forming a first diffusion barrier material layer, wherein the first diffusion barrier material layer covers the bit line structure, the storage node contact hole, the dielectric layer and the first contact hole in a conformal manner; forming a first metal material layer, wherein the first metal material layer covers the first diffusion barrier material layer and fills the storage node contact hole and the first contact hole; and removing the first metal material layer and the first diffusion barrier material layer which are positioned outside the storage node contact hole and the first contact hole, wherein the first diffusion barrier material layer and the first metal material layer which are reserved in the storage node contact hole are used as storage node contact structures, and the first diffusion barrier material layer and the first metal material layer which are reserved in the first contact hole are used as first contact structures.
In some embodiments of the present disclosure, forming the conductive contact layer and the second contact structure includes: forming a second diffusion barrier material layer, wherein the second diffusion barrier material layer covers the bit line structure, the storage node contact structure, the insulating layer and the second contact hole in a conformal manner; forming a second metal material layer, wherein the second metal material layer covers the second diffusion barrier material layer and fills the second contact hole; and removing the second metal material layer and the second diffusion barrier material layer which are positioned outside the second contact hole in the peripheral region, wherein the second diffusion barrier material layer and the second metal material layer which are reserved in the array region are used as conductive contact layers, and the second diffusion barrier material layer and the second metal material layer which are reserved in the second contact hole are used as second contact structures.
In some embodiments of the present disclosure, the second diffusion barrier material layer and the first diffusion barrier material layer are the same material.
In some embodiments of the present disclosure, the second metal material layer and the first metal material layer are the same material.
In some embodiments of the present disclosure, prior to patterning the conductive contact layer and the storage node contact structure to form the landing pad, the method of making further comprises: forming a mask material layer; the mask material layer covers the conductive contact layer, the second contact structure and the insulating layer; patterning the mask material layer to form a mask pattern in the mask material layer of the array region to obtain a mask layer; wherein patterning the conductive contact layer and the storage node contact structure to form a landing pad further comprises: the conductive contact layer and the storage node contact structure are etched based on the mask pattern to form a landing pad.
In some embodiments of the present disclosure, the landing pad includes a first portion located in the storage node contact hole and a second portion located on the bit line structure and the first portion.
In some embodiments of the present disclosure, after patterning the conductive contact layer and the storage node contact structure to form the landing pad, the method of preparing further comprises: the mask layer is removed.
In some embodiments of the present disclosure, the substrate further includes an active region exposed by the storage node contact hole and a storage node connection located in the storage node contact hole, the landing pad being coupled with the active region through the storage node contact.
In another aspect, some embodiments of the present disclosure provide a semiconductor structure, the semiconductor structure comprising: a substrate having an array region and a peripheral region located on at least one side of the array region; the substrate comprises a bit line structure and a storage node contact hole which are positioned in the array region, a dielectric layer positioned in the peripheral region and a first contact hole penetrating through the dielectric layer; a landing pad including a first portion located in the storage node contact hole and a second portion located on the bit line structure and the first portion; the first contact structure is arranged in the first contact hole; the insulating layer is positioned in the peripheral area, covers the dielectric layer and is provided with a second contact hole exposing the first contact structure; and the second contact structure is arranged in the second contact hole and is coupled with the first contact structure.
In some embodiments of the present disclosure, the first contact structure includes: a first diffusion barrier layer covering the sidewall and the bottom surface of the first contact hole; and a first metal layer covering the first diffusion barrier layer and filling the first contact hole; the first portion of the landing pad includes: a third diffusion barrier layer; and a third metal layer covering the third diffusion barrier layer.
In some embodiments of the present disclosure, the first diffusion barrier layer and the third diffusion barrier layer are the same material, and the first metal layer and the third metal layer are the same material.
In some embodiments of the present disclosure, the first diffusion barrier layer and the third diffusion barrier layer are the same thickness.
In some embodiments of the present disclosure, the second contact structure includes: a second diffusion barrier layer covering the sidewall and the bottom surface of the second contact hole; and a second metal layer covering the second diffusion barrier layer and filling the second contact hole; the second portion of the landing pad includes: a fourth diffusion barrier layer; and a fourth metal layer covering the fourth diffusion barrier layer.
In some embodiments of the present disclosure, the second diffusion barrier layer and the fourth diffusion barrier layer are the same material, and the second metal layer and the fourth metal layer are the same material.
In some embodiments of the present disclosure, the second diffusion barrier layer and the fourth diffusion barrier layer are the same thickness.
In some embodiments of the present disclosure, the substrate further includes an active region exposed by the storage node contact hole and a storage node connection located in the storage node contact hole, the landing pad being coupled with the active region through the storage node contact.
The semiconductor structure and the preparation method thereof are provided in the embodiment of the disclosure. In the embodiment of the disclosure, the contact structure of the peripheral region is split into a first contact structure and a second contact structure, and the first contact structure and the second contact structure are prepared respectively. Thus, after forming the storage node contact structure and the first contact structure, a conductive contact layer may be formed in the array region and a second contact structure connected to the first contact structure may be formed in the peripheral region after forming an insulating material layer covering the bit line structure, the storage node contact structure, the dielectric layer and the first contact structure and patterning the insulating material layer to expose the array region and the peripheral region first contact structure. Thus, the second contact structure in the peripheral area can be prepared independently of the structure of the array area, and can be directly formed by adopting a filling process, so that the material of the second contact structure is prevented from being etched, the electrical characteristics of the second contact structure and the first contact structure are ensured, the etched pollution is avoided, and the electrical characteristics of the contact structure are further ensured, so that the reliability of the semiconductor structure is improved.
In addition, in the embodiment of the disclosure, the first contact structure is formed by adopting the first diffusion barrier layer and the first metal layer, the second contact structure is formed by adopting the second diffusion barrier layer and the second metal layer, and molecular diffusion between the first metal layer and the second metal layer can be blocked by utilizing the second diffusion barrier layer, so that the electrical characteristics of the first contact structure and the second contact structure are effectively ensured and improved.
In addition, the first contact structure of the peripheral region may be formed using the same process as the storage node contact structure of the array region. In this way, the formation of the storage node contact structure in the array region and the first contact structure in the periphery region can be achieved simultaneously, so as to avoid the redundant process steps.
The second contact structure of the peripheral region may be formed by the same process as the conductive contact layer of the array region. In this way, the second contact structure connected with the first contact structure can be formed in the peripheral area without affecting the preparation process of the array area, so that etching of the material of the second contact structure is avoided, and the electrical characteristics of the second contact structure are ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a schematic top view of a semiconductor structure according to one embodiment;
FIG. 3 is a schematic cross-sectional view of the structure obtained in step S100 in the array region and the peripheral region along the aa' direction in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 4 is a schematic cross-sectional view of the structure obtained in step S200 in the array region and the peripheral region along the aa' direction in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a flow chart illustrating a method for forming a storage node contact structure and a first contact structure in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S300 in the array region and the peripheral region along the aa' direction in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 7 is a schematic cross-sectional view of the structure obtained in step S400 in the array region and the peripheral region along the aa' direction in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S500 in the array region and the peripheral region along the aa' direction in a method for fabricating a semiconductor structure according to one embodiment;
Fig. 9 is a flowchart illustrating a method for forming a conductive contact layer and a second contact structure in a method for manufacturing a semiconductor structure according to an embodiment;
FIG. 10 is a flow chart illustrating a method for forming landing pads in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 11 is a schematic cross-sectional view of the structure obtained in step S550 in the array region and the peripheral region along the aa' direction in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 12 is a schematic cross-sectional view of the structure obtained in step S551 in the array region and the peripheral region along the aa' direction in the method for fabricating a semiconductor structure according to one embodiment;
fig. 13 is a schematic cross-sectional view of the structure obtained in step S600 in the array region and the peripheral region along the aa' direction in the method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate:
1-a substrate; 11-a storage node contact hole; 12-a dielectric layer; 13-a first contact hole; 14-shallow trench isolation structures; 15-storage node connection; 16-storage node contact structure; 161-a first diffusion barrier material layer in the storage node contact hole; 162-a first metal material layer in the storage node contact hole; 17-a first contact structure; 171-a first diffusion barrier material layer/first diffusion barrier layer in the first contact hole; 172-a first metal material layer/first metal layer in the first contact hole;
200-a layer of insulating material; 20-an insulating layer; 21-a second contact hole; 22-a conductive contact layer; 221-a second diffusion barrier material layer in the array region; 222-a layer of a second metal material in the array region; 23-a second contact structure; 231-a second diffusion barrier material layer/second diffusion barrier layer in the second contact hole; 232-a second metal material layer/second metal layer in the second contact hole;
300-a layer of mask material; 30-a mask layer;
40-landing pads; 41-a third diffusion barrier; 42-a third metal layer; 43-a fourth diffusion barrier; 44-fourth metal layer.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can effectively avoid the problem that a contact structure positioned in a peripheral area generates byproducts in an etching process, thereby being beneficial to ensuring the electrical characteristics of the contact structure and improving the reliability of the semiconductor structure.
Referring to fig. 1, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including the following steps:
s100: the method comprises the steps of providing a substrate, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area, and the substrate comprises a bit line structure and a storage node contact hole which are positioned in the array area, a dielectric layer positioned in the peripheral area and a first contact hole penetrating through the dielectric layer.
S200: and forming a storage node contact structure and a first contact structure, wherein the storage node contact structure fills the storage node contact hole, and the first contact structure fills the first contact hole.
S300: an insulating material layer is formed, wherein the insulating material layer covers the bit line structure, the storage node contact structure, the dielectric layer and the first contact structure.
S400: patterning the insulating material layer to remove the insulating material layer in the array region, and forming a second contact hole exposing the first contact structure in the insulating material layer in the peripheral region to obtain an insulating layer.
S500: and forming a conductive contact layer and a second contact structure, wherein the conductive contact layer covers the bit line structure and the storage node contact structure, and the second contact structure fills the second contact hole and is coupled with the first contact structure.
S600: the conductive contact layer and the storage node contact structure are patterned to form landing pads.
In the embodiment of the disclosure, the contact structure of the peripheral region is split into a first contact structure and a second contact structure, and the first contact structure and the second contact structure are prepared respectively. Thus, after forming the storage node contact structure and the first contact structure, a conductive contact layer may be formed in the array region and a second contact structure connected to the first contact structure may be formed in the peripheral region after forming an insulating material layer covering the bit line structure, the storage node contact structure, the dielectric layer and the first contact structure and patterning the insulating material layer to expose the array region and the peripheral region first contact structure. Thus, the second contact structure in the peripheral area can be prepared independently of the structure of the array area, and can be directly formed by adopting a filling process, so that the material of the second contact structure is prevented from being etched, the electrical characteristics of the second contact structure and the first contact structure are ensured, the etched pollution is avoided, and the electrical characteristics of the contact structure are further ensured, so that the reliability of the semiconductor structure is improved.
In some embodiments of the present disclosure, forming the storage node contact structure and the first contact structure in step S200 includes: forming a first diffusion barrier material layer, wherein the first diffusion barrier material layer covers the bit line structure, the storage node contact hole, the dielectric layer and the first contact structure in a conformal manner; forming a first metal material layer, wherein the first metal material layer covers the first diffusion barrier material layer and fills the storage node contact hole and the first contact hole; and removing the first metal material layer and the first diffusion barrier material layer which are positioned outside the storage node contact hole and the first contact hole, wherein the first diffusion barrier material layer and the first metal material layer which are reserved in the storage node contact hole are used as storage node contact structures, and the first diffusion barrier material layer and the first metal material layer which are reserved in the first contact hole are used as first contact structures.
It should be noted that, in the embodiment of the present disclosure, the first contact structure of the peripheral area may be formed by the same process as the storage node contact structure of the array area. In this way, the formation of the storage node contact structure in the array region and the first contact structure in the periphery region can be achieved simultaneously, so as to avoid the redundant process steps.
In addition, in the embodiment of the disclosure, the first contact structure is formed by adopting the first diffusion barrier layer and the first metal layer, the second contact structure is formed by adopting the second diffusion barrier layer and the second metal layer, and metal atoms in the first metal layer and the second metal layer can be blocked from diffusing outwards by utilizing the first diffusion barrier layer and the second diffusion barrier layer, so that the electrical characteristics of the first contact structure and the second contact structure are effectively ensured and improved.
In some embodiments of the present disclosure, forming the conductive contact layer and the second contact structure in step S500 includes: forming a second diffusion barrier material layer, wherein the second diffusion barrier material layer covers the bit line structure, the storage node contact structure, the insulating layer and the second contact hole in a conformal manner; forming a second metal material layer, wherein the second metal material layer covers the second diffusion barrier material layer and fills the second contact hole; and removing the second metal material layer and the second diffusion barrier material layer which are positioned outside the second contact hole in the peripheral region, wherein the second diffusion barrier material layer and the second metal material layer which are reserved in the array region are used as conductive contact layers, and the second diffusion barrier material layer and the second metal material layer which are reserved in the second contact hole are used as second contact structures.
It should be noted that the second contact structure of the peripheral region may be formed by the same process as the conductive contact layer of the array region. In this way, the second contact structure connected with the first contact structure can be formed in the peripheral area without affecting the preparation process of the array area, so that etching of the material of the second contact structure is avoided, and the electrical characteristics of the second contact structure are ensured.
In some embodiments of the present disclosure, the substrate further includes an active region exposed by the storage node contact hole and a storage node connection located in the storage node contact hole, the landing pad being coupled with the active region through the storage node contact.
In order to more clearly illustrate the preparation method of the semiconductor structure in some of the above embodiments, please understand with reference to fig. 2 to 13. FIG. 2 shows a schematic top view of a semiconductor structure in which a plurality of bit line structures BL are arranged in parallel and spaced apart, and a plurality of word line structures WL are arranged in parallel and spaced apart; wherein the bit line structure BL extends in a first direction (e.g., Y-direction) and the word line structure WL extends in a second direction (e.g., X-direction), the first and second directions intersecting, e.g., perpendicular. The semiconductor structure has an array region A and a peripheral region B located at least on one side of the array region A, and the array region A is further provided with a plurality of active regions 10. The following embodiments are described in detail with reference to a schematic cross-sectional view of the semiconductor structure along aa', which is a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
In step S100, referring to fig. 3, a substrate 1 is provided, wherein the substrate 1 has an array area a and a peripheral area B located at least on one side of the array area a. The substrate 1 includes a bit line structure BL and a storage node contact hole 11 in an array region a, a dielectric layer 12 in a peripheral region B, and a first contact hole 13 penetrating the dielectric layer 12.
In the embodiment of the present disclosure, the bit line structure BL includes a conductive layer (not shown) and a sidewall (not shown). The specific arrangement of the conductive layer and the side wall is known to those skilled in the art, and will not be described here.
Alternatively, the conductive layer may be a metal layer having good conductivity such as titanium nitride (TiN) or tungsten (W).
Alternatively, the side wall may have a single-layer structure or a multi-layer structure. For example, the sidewall may be formed of a stacked structure of silicon oxide, silicon nitride, and silicon oxide.
In the embodiment of the present disclosure, the substrate 1 may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate 1 may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator.
In one example, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Alternatively, the substrate 1 is a sapphire substrate, a silicon germanium substrate, or a silicon carbide substrate.
With continued reference to fig. 3, in some embodiments, the semiconductor structure further includes a shallow trench isolation structure 14 in the array region a. The shallow trench isolation structures 14 separate the active regions 10.
By way of example, the shallow trench isolation structure 14 may be an oxide isolation structure, such as a silicon oxide isolation structure.
The active region 10 may be a columnar structure, for example. The orthographic projection of the active region 10 on the surface of the substrate 1 may be elliptical or parallelogram.
In one example, as shown in fig. 2, the plurality of active regions 10 isolated by the shallow trench isolation structure 14 are arranged in an array, specifically in a row along a first direction (for example, X direction) and in a column along a second direction (for example, Y direction); wherein the first direction and the second direction intersect, e.g. perpendicular.
Alternatively, the active regions 10 of adjacent rows are arranged offset in the first direction.
Alternatively, the active regions 10 of adjacent columns are arranged offset in the second direction.
Alternatively, referring to fig. 3, in the peripheral region B, the dielectric layer 12 may have a single-layer structure or a multi-layer structure. For example, the dielectric layer 12 may be a nitride layer, an oxide layer, or an oxynitride layer.
In one example, dielectric layer 12 includes a silicon nitride layer 121 and a silicon oxide layer 122.
In step S200, referring to fig. 4, a storage node contact structure 16 and a first contact structure 17 are formed, wherein the storage node contact structure 16 fills the storage node contact hole 11, and the first contact structure 17 fills the first contact hole 13.
For example, in the array region a, the storage node contact structure 16 fills the storage node contact hole 11, and in the peripheral region B, the first contact structure 17 fills the first contact hole 13.
In some embodiments of the present disclosure, referring to fig. 5, forming the storage node contact structure 16 and the first contact structure 17 includes:
s201: and forming a first diffusion barrier material layer, wherein the first diffusion barrier material layer covers the bit line structure, the storage node contact hole, the dielectric layer and the first contact hole in a conformal manner.
S202: and forming a first metal material layer, wherein the first metal material layer covers the first diffusion barrier material layer and fills the storage node contact hole and the first contact hole.
S203: and removing the first metal material layer and the first diffusion barrier material layer which are positioned outside the storage node contact hole and the first contact hole, wherein the first diffusion barrier material layer and the first metal material layer which are reserved in the storage node contact hole are used as storage node contact structures, and the first diffusion barrier material layer and the first metal material layer which are reserved in the first contact hole are used as first contact structures.
In step S201, referring to fig. 4, a first diffusion barrier material layer (not shown) is formed, wherein in the array region a, the first diffusion barrier material layer conformally covers the bit line structure BL and the storage node contact hole 11; in the peripheral region B, the first diffusion barrier material layer conformally covers the dielectric layer 12 and the first contact hole 13.
In step S202, referring to fig. 4, a first metal material layer (not shown) is formed, wherein in the array region a, the first metal material layer covers the first diffusion barrier material layer and fills the storage node contact hole 11; in the peripheral region B, the first metal material layer covers the first diffusion barrier material layer and fills the first contact hole 13.
In step S203, referring to fig. 4, in the array area a, the first metal material layer and the first diffusion barrier material layer outside the storage node contact hole 11 are removed, and the first diffusion barrier material layer 161 and the first metal material layer 162 remaining in the storage node contact hole 11 are used as the storage node contact structure 16; in the peripheral region B, the first metal material layer and the first diffusion barrier material layer outside the first contact hole 13 are removed, and the first diffusion barrier material layer 171 and the first metal material layer 172 remaining in the first contact hole 13 serve as the first contact structure 17.
Alternatively, the first diffusion barrier material layer may be a titanium nitride layer.
Alternatively, the first metal material layer may be a metal layer having good conductivity such as titanium (Ti) or tungsten (W).
In some embodiments of the present disclosure, in the array region a, the substrate 1 further includes an active region 10 exposed by the storage node contact hole 11 and a storage node connection 15 located in the storage node contact hole 11.
In some examples, at array region a, prior to forming the first diffusion barrier material layer, further comprising: a storage node connection 15 is formed in the storage node contact hole 11 in contact with the active region 10.
Alternatively, the storage node contact layer 15 may be a polysilicon layer.
In the above method for manufacturing the semiconductor structure, the first contact structure 17 of the peripheral area B may be formed by the same process as the storage node contact structure 16 of the array area a. In this way, simultaneous formation of the storage node contact structures 16 in the array region a and the first contact structures 17 in the peripheral region B can be achieved to avoid redundant process steps.
In step S300, referring to fig. 6, an insulating material layer 200 is formed, wherein the insulating material layer 200 covers the bit line structure BL, the storage node contact structure 16, the dielectric layer 12 and the first contact structure 17.
For example, in array region A, insulating material layer 200 covers bit line structures BL and storage node contact structures 16; in the peripheral region B, the insulating-material layer 200 covers the dielectric layer 12 and the first contact structure 17.
Alternatively, the insulating material layer 200 may be an oxide layer, such as a silicon oxide layer.
In step S400, referring to fig. 7, the insulating material layer 200 is patterned to remove the insulating material layer in the array region a, and the second contact hole 21 exposing the first contact structure 17 is formed in the insulating material layer in the peripheral region B to obtain the insulating layer 20.
In step S500, referring to fig. 8, a conductive contact layer 22 and a second contact structure 23 are formed, wherein the conductive contact layer 22 covers the bit line structure BL and the storage node contact structure 16, and the second contact structure 23 fills the second contact hole 21 and is coupled with the first contact structure 17.
For example, in array region A, conductive contact layer 22 overlies bit line structure BL and storage node contact structure 16; in the peripheral region B, the second contact structure 23 fills the second contact hole 21 and is coupled with the first contact structure 17.
In some embodiments of the present disclosure, referring to fig. 9, forming the conductive contact layer 22 and the second contact structure 23 includes:
s501: and forming a second diffusion barrier material layer, wherein the second diffusion barrier material layer covers the bit line structure, the storage node contact structure, the insulating layer and the second contact hole in a conformal manner.
S502: and forming a second metal material layer, wherein the second metal material layer covers the second diffusion barrier material layer and fills the second contact hole.
S503: and removing the second metal material layer and the second diffusion barrier material layer which are positioned outside the second contact hole in the peripheral region, wherein the second diffusion barrier material layer and the second metal material layer which are reserved in the array region are used as conductive contact layers, and the second diffusion barrier material layer and the second metal material layer which are reserved in the second contact hole 21 are used as second contact structures.
In step S501, referring to fig. 8, a second diffusion barrier material layer (not shown) is formed, wherein in the array region a, the second diffusion barrier material layer conformally covers the bit line structure BL and the storage node contact hole 11; in the peripheral region B, the second diffusion barrier material layer conformally covers the insulating layer 20 and the second contact hole 21.
In step S502, referring to fig. 8, a second metal material layer (not shown) is formed, wherein in the array region a, the second metal material layer covers the first diffusion barrier material layer; in the peripheral region B, the second metal material layer covers the first diffusion barrier material layer and fills the second contact hole 21.
In step S503, referring to fig. 8, in the array region a, the second diffusion barrier material layer 221 and the second metal material layer 222 are reserved as the conductive contact layer 22; in the peripheral region B, the second metal material layer and the second diffusion barrier material layer outside the second contact hole 21 in the peripheral region B are removed, and the second diffusion barrier material layer 231 and the second metal material layer 232 remaining in the second contact hole 21 serve as the second contact structure 23.
In some embodiments of the present disclosure, the second diffusion barrier material layer and the first diffusion barrier material layer are the same material; of course, may also be different.
Alternatively, the second diffusion barrier material layer and the first diffusion barrier material layer may each be a titanium nitride layer.
In some embodiments of the present disclosure, the second metal material layer and the first metal material layer are the same material; of course, may also be different.
Alternatively, the second metal material layer and the first metal material layer may be metal layers having good conductivity such as titanium (Ti) or tungsten (W).
In the above method for manufacturing a semiconductor structure, the second contact structure 23 of the peripheral area B may be formed by the same process as the conductive contact layer 22 of the array area a. In this way, the second contact structure 23 connected to the first contact structure 17 may be formed in the peripheral region B without affecting the manufacturing process of the array region a, so as to avoid etching the material of the second contact structure 23, thereby ensuring the electrical characteristics of the second contact structure 23.
In some embodiments of the present disclosure, the surface of the second contact structure 23 remote from the substrate 1 is in the same plane as the surface of the insulating layer 20 remote from the substrate 1.
In step S600, referring to fig. 10-13, the conductive contact layer 22 and the storage node contact structure 16 are patterned to form the landing pad 40.
In some embodiments of the present disclosure, referring to fig. 10, prior to patterning the conductive contact layer 22 and the storage node contact structure 16 to form the landing pad 40 at step S600, the method of fabrication further comprises:
s550: forming a mask material layer; the mask material layer covers the conductive contact layer, the second contact structure and the insulating layer.
S551: patterning the mask material layer to form a mask pattern in the mask material layer of the array region, thereby obtaining a mask layer.
In step S550, referring to fig. 11, in the array region a, the mask material layer 300 covers the conductive contact layer 22; in the peripheral region B, the mask material layer 300 covers the second contact structure 23 and the insulating layer 20.
In step S551, referring to fig. 12, the mask material layer 300 is patterned, a mask pattern is formed in the mask material layer 300 of the array region a, and the mask material layer 300 of the peripheral region B is remained to obtain the mask layer 30.
Mask layer 12 is illustratively a hard mask layer, which may be, for example, a silicon nitride layer.
In step S600, referring to fig. 13, the conductive contact layer 22 and the storage node contact structure 16 are patterned to form the landing pad 40.
For example, in array region a, conductive contact layer 22 is patterned to form fourth diffusion barrier layer 43 and fourth metal layer 44, and storage node contact structure 16 is further patterned to form third diffusion barrier layer 41 and third metal layer 42; the fourth diffusion barrier layer 43, the fourth metal layer 44, the third diffusion barrier layer 41 and the third metal layer 42 together constitute the landing pad 40. In the peripheral region B, the insulating layer 20 and the second contact structure 23 are protected from etching under the coverage of the mask material layer 300.
Illustratively, patterning the conductive contact layer 22 and the storage node contact structure 16 to form the landing pad 40, further includes: the conductive contact layer 22 and the storage node contact structure 16 are etched based on the mask pattern to form a landing pad 40.
In some embodiments of the present disclosure, in array region a, landing pad 40 is coupled to active region 10 through storage node contact 15.
In some embodiments of the present disclosure, after patterning the conductive contact layer 22 and the storage node contact structure 16 to form the landing pad 40 in the array region a in step S600, the fabrication method further includes: the mask layer 30 is removed.
In some embodiments of the present disclosure, the landing pad 40 includes a first portion located in the storage node contact hole 11 and a second portion located on the bit line structure BL and the first portion.
Based on the same inventive concept, some embodiments of the present disclosure further provide a semiconductor structure, referring to fig. 13, the semiconductor structure includes: a substrate 1 having an array region A and a peripheral region B located on at least one side of the array region A; the substrate 1 comprises a bit line structure BL and a storage node contact hole 11 which are positioned in an array area A, a dielectric layer 12 positioned in a peripheral area B and a first contact hole 13 penetrating through the dielectric layer 12; a landing pad 40 including a first portion located in the storage node contact hole 11 and a second portion located on the bit line structure BL and the first portion; a first contact structure 17 disposed in the first contact hole 13; an insulating layer 20 located at the peripheral region B, covering the dielectric layer 12, and having a second contact hole 21 exposing the first contact structure 17; and a second contact structure 23 disposed in the second contact hole 21 and coupled with the first contact structure 17.
The semiconductor structure separates the contact structure of the peripheral region B into the first contact structure 17 and the second contact structure 23. The insulating layer 20 on the substrate 1 has a second contact hole 21 exposing the first contact structure 17 in the array area a and the peripheral area B, so that the second contact structure 23 is disposed in the second contact hole 21 and connected to the first contact structure 17, so as to avoid etching the material of the second contact structure 23, thereby ensuring the electrical characteristics of the second contact structure 23 and avoiding being polluted by etching, and further being beneficial to ensuring the electrical characteristics of the contact structure, so as to improve the reliability of the semiconductor structure.
In the embodiment of the present disclosure, the bit line structure BL includes a conductive layer (not shown) and a sidewall (not shown). The specific arrangement of the conductive layer and the side wall is known to those skilled in the art, and will not be described here.
Alternatively, the conductive layer may be a metal layer having good conductivity such as titanium nitride (TiN) or tungsten (W).
Alternatively, the side wall may have a single-layer structure or a multi-layer structure. For example, the sidewall may be formed of a stacked structure of silicon oxide, silicon nitride, and silicon oxide.
In some embodiments of the present disclosure, the substrate 1 further includes an active region 10 exposed by the storage node contact hole 11 and a storage node connector 15 located in the storage node contact hole 11, and the landing pad 40 is coupled with the active region 10 through the storage node connector 15.
In some embodiments, referring to fig. 13, the array region of the semiconductor structure further includes a shallow trench isolation structure 14. The shallow trench isolation structures 14 separate the active regions 10.
By way of example, the shallow trench isolation structure 14 may be an oxide isolation structure, such as a silicon oxide isolation structure.
The active region 10 may be a columnar structure, for example. The orthographic projection of the active region 10 on the surface of the substrate 1 may be elliptical or parallelogram.
In some embodiments of the present disclosure, referring to fig. 13, in the peripheral region B, the first contact structure 17 includes: a first diffusion barrier 171 covering the sidewalls and bottom surface of the first contact hole 13; and a first metal layer 172 covering the first diffusion barrier layer 171 and filling the first contact hole 11; the first portion of the landing pad 40 includes: a third diffusion barrier 41; and a third metal layer 42 covering the third diffusion barrier 41.
In some embodiments of the present disclosure, the first diffusion barrier layer 171 and the third diffusion barrier layer 41 are the same material, and the first metal layer 172 and the third metal layer 42 are the same material.
Alternatively, the first diffusion barrier layer 171 and the third diffusion barrier layer 41 may be titanium nitride layers.
Alternatively, the first and third metal layers 172 and 42 may be metal layers having good conductivity such as titanium (Ti) or tungsten (W).
In some embodiments of the present disclosure, the thickness of the first diffusion barrier 171 and the third diffusion barrier 41 are the same.
In some embodiments of the present disclosure, referring to fig. 13, in the peripheral region B, the second contact structure 23 includes: a second diffusion barrier 231 covering sidewalls and bottom surfaces of the second contact hole 21; and a second metal layer 232 covering the second diffusion barrier layer 231 and filling the second contact hole 21; the second portion of the landing pad 40 includes: a fourth diffusion barrier layer 43; and a fourth metal layer 44 covering the fourth diffusion barrier layer 43.
In some embodiments of the present disclosure, the second diffusion barrier 231 and the fourth diffusion barrier 43 are the same material, and the second metal layer 232 and the fourth metal layer 44 are the same material.
In some embodiments of the present disclosure, the second diffusion barrier 231 and the fourth diffusion barrier 43 are the same thickness.
Alternatively, the second diffusion barrier layer 231 and the fourth diffusion barrier layer 43 may be titanium nitride layers.
Alternatively, the second and fourth metal layers 232 and 44 may be metal layers having good conductivity such as titanium (Ti) or tungsten (W).
In some embodiments of the present disclosure, the top surface of the second metal layer 232 and the top surface of the second diffusion barrier layer 231 are both in the same plane as the surface of the insulating layer 20 away from the substrate 1.
In some embodiments of the present disclosure, the insulating layer 20 includes: an oxide layer, a nitride layer, or a stack of oxide and nitride layers.
In the embodiment of the disclosure, the first contact structure is formed by a first diffusion barrier layer and a first metal layer, the second contact structure is formed by a second diffusion barrier layer and a second metal layer, and metal atoms in the first metal layer and the second metal layer can be blocked from diffusing outwards by the first diffusion barrier layer and the second diffusion barrier layer, so that the electrical characteristics of the first contact structure and the second contact structure are effectively ensured and improved.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (17)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with an array region and a peripheral region positioned at least one side of the array region, and the substrate comprises a bit line structure and a storage node contact hole which are positioned in the array region, a dielectric layer positioned in the peripheral region and a first contact hole penetrating through the dielectric layer;
forming a storage node contact structure and a first contact structure, wherein the storage node contact structure fills the storage node contact hole, and the first contact structure fills the first contact hole;
forming an insulating material layer, wherein the insulating material layer covers the bit line structure, the storage node contact structure, the dielectric layer and the first contact structure;
patterning the insulating material layer to remove the insulating material layer in the array region, and forming a second contact hole exposing the first contact structure in the insulating material layer in the peripheral region to obtain an insulating layer;
forming a conductive contact layer and a second contact structure, wherein the conductive contact layer covers the bit line structure and the storage node contact structure, and the second contact structure fills the second contact hole and is coupled with the first contact structure;
The conductive contact layer and the storage node contact structure are patterned to form a landing pad.
2. The method of manufacturing a semiconductor structure of claim 1, wherein forming the storage node contact structure and the first contact structure comprises:
forming a first diffusion barrier material layer, wherein the first diffusion barrier material layer covers the bit line structure, the storage node contact hole, the dielectric layer and the first contact hole in a conformal manner;
forming a first metal material layer, wherein the first metal material layer covers the first diffusion barrier material layer and fills the storage node contact hole and the first contact hole;
and removing the first metal material layer and the first diffusion barrier material layer outside the storage node contact hole and the first contact hole, wherein the first diffusion barrier material layer and the first metal material layer remained in the storage node contact hole are used as the storage node contact structure, and the first diffusion barrier material layer and the first metal material layer remained in the first contact hole are used as the first contact structure.
3. The method of manufacturing a semiconductor structure of claim 2, wherein forming the conductive contact layer and the second contact structure comprises:
Forming a second diffusion barrier material layer, wherein the second diffusion barrier material layer covers the bit line structure, the storage node contact structure, the insulating layer and the second contact hole in a conformal manner;
forming a second metal material layer, wherein the second metal material layer covers the second diffusion barrier material layer and fills the second contact hole;
and removing the second metal material layer and the second diffusion barrier material layer which are positioned outside the second contact hole in the peripheral region, wherein the second diffusion barrier material layer and the second metal material layer which are reserved in the array region are used as the conductive contact layer, and the second diffusion barrier material layer and the second metal material layer which are reserved in the second contact hole are used as the second contact structure.
4. The method of claim 3, wherein the second diffusion barrier material layer and the first diffusion barrier material layer are the same material.
5. The method of claim 4, wherein the second metal material layer and the first metal material layer are the same material.
6. The method of manufacturing a semiconductor structure of claim 1, wherein prior to said patterning the conductive contact layer and the storage node contact structure to form a landing pad, the method of manufacturing further comprises:
forming a mask material layer; the mask material layer covers the conductive contact layer, the second contact structure and the insulating layer;
patterning the mask material layer to form a mask pattern in the mask material layer of the array region to obtain a mask layer;
wherein the patterning the conductive contact layer and the storage node contact structure to form a landing pad further comprises: the conductive contact layer and the storage node contact structure are etched based on the mask pattern to form the landing pad.
7. The method of claim 6, wherein the landing pad comprises a first portion located in the storage node contact hole and a second portion located on the bit line structure and the first portion.
8. The method of manufacturing a semiconductor structure of claim 6, wherein after said patterning the conductive contact layer and the storage node contact structure to form a landing pad, the method further comprises: and removing the mask layer.
9. The method of manufacturing a semiconductor structure of claim 1, wherein the substrate further comprises an active region exposed by the storage node contact hole and a storage node connection located in the storage node contact hole, the landing pad being coupled with the active region through the storage node contact.
10. A semiconductor structure, comprising:
a substrate having an array region and a peripheral region located on at least one side of the array region; the substrate comprises a bit line structure and a storage node contact hole which are positioned in the array area, a dielectric layer positioned in the peripheral area and a first contact hole penetrating through the dielectric layer;
a landing pad including a first portion located in the storage node contact hole and a second portion located on the bit line structure and the first portion;
the first contact structure is arranged in the first contact hole;
the insulating layer is positioned in the peripheral area, covers the dielectric layer and is provided with a second contact hole exposing the first contact structure; and
and the second contact structure is arranged in the second contact hole and is coupled with the first contact structure.
11. The semiconductor structure of claim 10, wherein,
The first contact structure includes:
a first diffusion barrier layer covering the side wall and the bottom surface of the first contact hole; and
a first metal layer covering the first diffusion barrier layer and filling the first contact hole;
the first portion of the landing pad includes:
a third diffusion barrier layer; and
and a third metal layer covering the third diffusion barrier layer.
12. The semiconductor structure of claim 11, wherein the first diffusion barrier layer and the third diffusion barrier layer are the same material, and the first metal layer and the third metal layer are the same material.
13. The semiconductor structure of claim 11, wherein the first diffusion barrier layer and the third diffusion barrier layer are the same thickness.
14. The semiconductor structure of any of claims 11-13, wherein,
the second contact structure includes:
a second diffusion barrier layer covering the side wall and the bottom surface of the second contact hole; and
a second metal layer covering the second diffusion barrier layer and filling the second contact hole;
the second portion of the landing pad includes:
a fourth diffusion barrier layer; and
And a fourth metal layer covering the fourth diffusion barrier layer.
15. The semiconductor structure of claim 14, wherein the second diffusion barrier layer and the fourth diffusion barrier layer are the same material, and the second metal layer and the fourth metal layer are the same material.
16. The semiconductor structure of claim 15, wherein the second diffusion barrier layer and the fourth diffusion barrier layer are the same thickness.
17. The semiconductor structure of claim 10, wherein the substrate further comprises an active region exposed by the storage node contact hole and a storage node connection located in the storage node contact hole, the landing pad being coupled with the active region through the storage node contact.
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| CN202211186516.0A CN117832164A (en) | 2022-09-27 | 2022-09-27 | Semiconductor structure and preparation method thereof |
| PCT/CN2023/082153 WO2024066235A1 (en) | 2022-09-27 | 2023-03-17 | Semiconductor structure and manufacturing method therefor |
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| CN111640747A (en) * | 2019-09-27 | 2020-09-08 | 福建省晋华集成电路有限公司 | Semiconductor device, electric contact structure and manufacturing method thereof |
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