CN116959359A - Display panel and display device - Google Patents
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Abstract
The embodiment of the invention provides a display panel and a display device. The display panel comprises a shift register, the shift register comprises a first output pipe and a second output pipe, the control end of the first output pipe is electrically connected with a first node, the first end of the first output pipe receives a first level signal, the control end of the second output pipe is electrically connected with a second node, the first end of the second output pipe receives a second level signal, the second end of the first output pipe and the second end of the second output pipe are both electrically connected with the output end of the shift register, and the voltage value of the first level signal is larger than that of the second level signal; the shift register further comprises an anti-static module, wherein the anti-static module is coupled with the second node and is used for stabilizing the potential of the second node after the potential of the second node is affected by static electricity. The invention can prevent static electricity from influencing the potential of the second node, ensure the working state of the second output pipe to be stable, further ensure the normal output of the signal at the output end of the shift register and avoid abnormal display.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
In the display field, a shift register is required to realize a progressive scanning display mode. The output end of the shift register is connected with the row strobe line, and one pixel row is driven by one row strobe line. The stability of the output signal of the shift register is a key for ensuring the normal operation of the pixel rows, and if the output signal of the shift register is abnormal, abnormal opening of the pixel rows may be caused, resulting in abnormal display.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the technical problem of abnormal display caused by abnormal signal output by a shift register.
In a first aspect, an embodiment of the present invention provides a display panel, including a shift register, where the shift register includes a first output pipe and a second output pipe, a control end of the first output pipe is electrically connected to a first node, a first end of the first output pipe receives a first level signal, a control end of the second output pipe is electrically connected to a second node, a first end of the second output pipe receives a second level signal, a second end of the first output pipe and a second end of the second output pipe are both electrically connected to an output end of the shift register, and a voltage value of the first level signal is greater than a voltage value of the second level signal;
the shift register further comprises an anti-static module, wherein the anti-static module is coupled with the second node and is used for stabilizing the potential of the second node after the potential of the second node is affected by static electricity.
In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, including a display panel provided by any embodiment of the present invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the anti-static module is coupled with the second node, and can be used for stabilizing the potential of the second node after the potential of the second node is affected by static electricity, so that the potential abnormality of the second node caused by static electricity is prevented, and abnormal signals are prevented from being instantaneously output at the output end of the shift register to cause abnormal display of the pixel rows.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a shift register structure;
FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a shift register according to the prior art;
FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 8 is a timing diagram of another shift register according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another shift register according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a display device according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Fig. 1 is a schematic diagram of a shift register, as shown IN fig. 1, the shift register includes an input module 01 and an output module 02, an input end IN of the input module 01 receives a start signal, the output module 02 includes a first output tube T1 and a second output tube T2, a control end of the first output tube T1 is electrically connected to a first node N1, a control end of the second output tube T2 is connected to a second node N2, a first end of the first output tube T1 receives a high level signal VGH, a second end of the first output tube T1 is connected to an output end OUT of the shift register, a first end of the second output tube T2 receives a low level signal VGL, and a second end of the second output tube T2 is connected to the output end OUT of the shift register. When the first node N1 is at a low level, the first output pipe T1 is controlled to be started, and the output end OUT outputs a high-level signal VGH; when the second node N2 is at the low level, the second output tube T2 is controlled to be turned on, and the output terminal OUT outputs the low level signal VGL. Take the low level signal VGL output from the output terminal OUT as an active enable signal for driving the operation of the pixel row as an example. If the potential of the second node N2 is pulled up by static electricity during the period in which the second node N2 should be at the low level, the output terminal OUT may not normally output the valid enable signal, and the pixel row may not be displayed.
In order to solve the problems in the prior art, the embodiment of the invention provides a display panel, wherein an anti-static module is additionally arranged in a shift register of the display panel, and the anti-static module is used for preventing the shift register from outputting abnormal signals after static electricity affects the potential of a second node. Further, in some embodiments, an anti-tailing module is further disposed in the shift register, and the anti-tailing module is used to prevent the output end of the shift register from generating a tailing phenomenon when the output high level jumps to the low level. Further, in some embodiments, a voltage stabilizing module is further disposed in the shift register, and the voltage stabilizing module is used to pull the potential of the second node high during the period when the second output pipe needs to be turned off so as to stabilize the potential of the second node, thereby improving performance stability of the shift register.
The embodiment of the invention provides a display panel, which comprises a driving circuit, wherein the driving circuit comprises a plurality of shift registers in cascade connection. The driving circuit is used for outputting signals to the display panel row by row, such as outputting scanning signals to each scanning line of the display panel row by row, or outputting light-emitting control signals to each light-emitting control line of the display panel row by row.
Fig. 2 is a schematic diagram of a shift register according to an embodiment of the present invention. Each transistor is illustrated as p-type in fig. 2. As shown in FIG. 2, the shift register includes a first output tube T1 and a second output tube T2, the first output tube T1The control end is electrically connected with the first node N1, the first end of the first output tube T1 receives the first level signal V1, and the first voltage stabilizing capacitor C0 1 One of the plates is connected to the first node N1 and the other plate receives the first level signal V1. The control end of the second output tube T2 is electrically connected with the second node N2, the first end of the second output tube T2 receives a second level signal V2, the second end of the first output tube T1 and the second end of the second output tube T2 are both electrically connected with the output end OUT of the shift register, and the voltage value of the first level signal V1 is larger than that of the second level signal V2; the first level signal V1 is a high level signal, and the second level signal V2 is a low level signal. The second output pipe T2 is turned on under the control of the potential of the second node N2, and a second level signal V2 of a low level is supplied to the output terminal OUT, which outputs the low level signal as an active enable signal in the scan signal (or the light emission control signal).
The shift register further includes an anti-static module 10, the anti-static module 10 is coupled to the second node N2, and the anti-static module 10 is configured to stabilize the potential of the second node N2 after the potential of the second node N2 is affected by static electricity. The stabilizing the potential of the second node N2 in the present invention means stabilizing the potential of the second node N2 within a desired voltage range, and preventing the second node N2 from having a larger range of potential fluctuation.
As shown in fig. 2, the shift register further includes an input transistor T3 and a protection transistor T4, and the input transistor T3 and the protection transistor T4 constitute a second potential control module 20. The control end of the input transistor T3 receives the clock signal CK, the first end of the input transistor T3 receives the start signal STV, and the second end of the input transistor T3 is connected with the third node N3; the control end of the protection transistor T4 receives the second level signal V2, the first end of the protection transistor T4 is connected with the third node N3, the second end of the protection transistor T4 is connected with the second node N2, and the protection transistor T4 is in a normally-on state. In the driving circuit, the start signal STV of the 1 st stage shift register is provided separately, and the start signal STV of the 2 nd stage shift register and the following shift registers are signals output by the output terminal OUT of the last stage shift register. The shift register further comprises a first potential control module 30, the first potential control module 30 being connected to the first node N1, the control terminals of some of the transistors in the first potential control module 30 being connected to the third node N3, the first potential control module 30 being illustrated in fig. 2 only in a block diagram, the structure of which will be exemplified in the following embodiments. In fig. 2, only the electrostatic protection module 10 is electrically connected between the protection transistor T4 and the second output tube T2.
In the conventional technology, in a period in which the start signal STV is at a low level, when the input transistor T3 is in an off state, the second node N2 cannot be charged, so that the second node N2 is in a floating state after being coupled for a long time, the second node N2 is easily affected by static electricity to cause potential abnormality, after the second node N2 is pulled up by the static electricity to cause potential abnormality, the output of the second node N2 may be abnormal in a period in which the output terminal OUT outputs a low level, and the output of the row scan signal (or the row light emission control signal) is abnormal to cause abnormal display of the pixel row.
In the shift register provided by the embodiment of the invention, the second node N2 controls the working state of the second output tube T2 outputting the effective enabling signal, the anti-static module 10 is arranged and coupled with the second node N2, and the anti-static module 10 can be used for stabilizing the potential of the second node N2 after the potential of the second node N2 is affected by static electricity, so that the potential abnormality of the second node N2 caused by static electricity is prevented, and the abnormal signal is prevented from being instantaneously output at the output end OUT of the shift register, so that the display of a pixel row is abnormal.
In some embodiments, fig. 3 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 3, a control end of the anti-static module 10 is electrically connected to the second node N2, a first end of the anti-static module 10 receives the first clock signal CK1, and a second end of the anti-static module 10 is electrically connected to the second node N2. The clock signal received by the control terminal of the input transistor T3 is a second clock signal CK2, and the second clock signal CK2 and the first clock signal CK1 are a pair of clock signals with the same duty ratio. The anti-static module 10 is configured to pull the potential of the second node N2 low to stabilize the potential of the second node N2 after the potential of the second node N2 is affected by static electricity during a period when the input transistor T3 is turned off and the second output terminal T2 needs to be turned on.
Fig. 4 is a timing chart of a shift register according to an embodiment of the present invention. The ordinate of the timing diagram represents voltage and the abscissa represents time. As shown in fig. 4, in a period in which the start signal STV is at a low level, for example, in a period T1, the output terminal OUT of the shift register outputs a low level signal, in which the second clock signal CK2 is at a high level and the input transistor T3 is turned off, and the anti-static module 10 is capable of acting to pull the potential of the second node N2 low at this stage. The position indicated by the broken line in fig. 4 shows that the potential of the second node N2 is pulled down by the antistatic module 10. In the embodiment of the present invention, the antistatic module 10 is provided, when the second node N2 is affected by static electricity and has abnormal potential, the second node N2 can be instantly reset by the start signal STV when the second clock signal CK2 controls the input transistor T3 to be turned on, it can be understood that in the display panel, the output end OUT of the cascaded shift register sequentially outputs the valid enable signal, the start signal STV of the shift register is a signal output by the output end OUT of the previous shift register, and the output end OUT of the shift register is connected to a whole row of pixel circuits through the scan line (or the light emitting control line), that is, the output end OUT is coupled with a relatively larger parasitic capacitance in the display area, and the start signal STV received by the first end of the input transistor T3 has a certain charging capability. The second node N2 can be reset by a low level of the start signal STV instantaneously when the input transistor T3 is turned on. After the second node N2 is instantly reset by the start signal STV, the anti-static module 10 uses the low potential of the first clock signal CK1 to pull the potential coupling of the second node N2 low. The first clock signal CK1 and the second clock signal CK2 continuously provide low-level signals, so that the second node N2 is charged, reset and combined with the action of the antistatic module 10 to couple and pull the potential of the second node N2 low, thereby preventing the potential of the second node N2 from being abnormal caused by static electricity, and avoiding abnormal display of the pixel row caused by instantaneous output of an abnormal signal at the output end OUT of the shift register.
As shown in fig. 3, the antistatic module 10 includes a first switching tube M1 and a first capacitor C1, wherein a control end of the first switching tube M1 is electrically connected to the second node N2, a first end of the first switching tube M1 receives the first clock signal CK1, a second end of the first switching tube M1 is electrically connected to a first electrode plate of the first capacitor C1, and a second electrode plate of the first capacitor C1 is electrically connected to the second node N2. The second node N2 controls the operation state of the first switching tube M1 in the antistatic module 10. When the second node N2 is abnormal due to electrostatic charge, the second clock signal CK2 controls the input transistor T3 to turn on during the period T2, and the start signal STV is used to instantaneously reset the second node N2. Then, in the period t1, the second node N2 is charged and reset, and then the first switching tube M1 is controlled to be turned on, and after the first switching tube M1 is turned on, the low potential of the first clock signal CK1 is written into the first polar plate of the first capacitor C1, and due to the bootstrap effect of the first capacitor C1, the potential coupling of the second node N2 is pulled down. The first clock signal CK1 and the second clock signal CK2 continuously provide low-level signals, so that the second node N2 is charged, reset and combined with the action of the antistatic module 10 to couple and pull the potential of the second node N2 low, thereby preventing the potential of the second node N2 from being abnormal caused by static electricity, and avoiding abnormal display of the pixel row caused by instantaneous output of an abnormal signal at the output end OUT of the shift register.
In the prior art, the output end of the shift register may have a tailing phenomenon when the output signal jumps from a high level to a low level. FIG. 5 is a timing diagram of a shift register according to the prior art. The tailing phenomenon occurs when the signal of the output terminal OUT of the position shift register jumps from the high level to the low level as circled by the dotted line in fig. 5. As can be seen from fig. 1, for the second output tube T2, vgs=vth is the threshold state of the transistor, vgs is the voltage difference between the gate and the source of the transistor, and Vth is the threshold voltage of the transistor. After the second output tube T2 is turned on, the signal at the output terminal OUT jumps from high level to low level, and if the voltage at the second node N2 is the low level voltage VGL, it is turned off when VGL-vout=vth, where Vout is the voltage at the output terminal OUT, and vout=vgl-Vth. That is, the output of the output terminal OUT does not reach the target voltage (i.e., VGL) due to the threshold loss of the transistor. The prior art OUT output goes through two stages until the target voltage is reached so tailing occurs. Taking the example that the output end OUT of the shift register is connected with a light-emitting control signal line, when the output end OUT outputs a low-level enabling signal, the pixel circuit can work in a light-emitting stage, and the voltage value at the trailing position of the output end OUT signal cannot determine whether the pixel circuit can be controlled to work in the light-emitting stage. Even if the voltage at this position can control the pixel circuit to operate in the light emission phase, there is a difference between the light emission condition in this state and the light emission condition when the output terminal OUT signal is at the target low level, thereby causing display abnormality. It is also particularly critical to address the tailing problem.
In order to solve the tailing problem, the shift register provided by the embodiment of the invention is provided with an tailing prevention module. In some embodiments, fig. 6 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 6, where the shift register further includes a tailing prevention module 40, and the tailing prevention module 40 is configured to prevent a signal at an output terminal OUT of the shift register from generating a tailing when the signal transitions from a high level to a low level. The control terminal of the anti-tailing module 40 receives the second clock signal CK2, the first terminal of the anti-tailing module 40 is electrically connected to the output terminal OUT of the shift register, and the second terminal of the anti-tailing module 40 is electrically connected to the second node N2.
As shown in fig. 6, the first potential control module 30 includes a fifth switching tube T5, a sixth switching tube T6, a seventh switching tube T7, an eighth switching tube T8, a ninth switching tube T9, and a second stabilizing capacitor C0 2 。
The operation of the shift register is understood in conjunction with the timing diagram illustrated in fig. 4. As shown in fig. 4, in the period T3, the first node N1 maintains a low level, the second node N2 maintains a high level, the first output pipe T1 is turned on, the second output pipe T2 is turned off, and the output terminal OUT outputs a high level signal. In the period T4, the low level signal of the second clock signal CK2 controls the input transistor T3 to be turned on, the low level signal of the start signal STV is written into the circuit, the potential of the second node N2 is charged and pulled down, the second output tube T2 is turned on under the control of the low potential, the second output tube T2 generates leakage current, and the voltage of the output signal of the output terminal OUT gradually decreases. Meanwhile, in the t4 period, the anti-tailing module 40 further pulls down the potential of the second node N2 by the signal output from the output terminal OUT under the control of the second clock signal CK 2. Then when V N2 V when vout=vth and the leakage flow of the second output pipe T2 is cut off N2 At the potential of the second node N2, V N2 Is further coupled to be pulled low so that the second output tube T2 continuesAnd starting to generate leakage current, and continuously reducing the signal output by the output end OUT until the signal is equal to the voltage value of the second level signal V2, so as to finish the jump from the high level signal to the low level signal.
The shift register provided by the embodiment of the invention is provided with the tailing preventing module 40, when the signal of the output end OUT of the shift register jumps from high level to low level, the tailing preventing module 40 utilizes the signal of the output end OUT to further couple and pull down the potential of the second node N2, so that the second output pipe T2 is continuously in an on state until the signal of the output end OUT continuously drops to be equal to the voltage value of the second level signal V2, and the jump from the high level signal to the low level signal is completed, thereby improving the tailing phenomenon.
As shown in fig. 6, the anti-tailing module 40 includes a second switching tube M2 and a second capacitor C2, wherein a control end of the second switching tube M2 receives the second clock signal CK2, a first end of the second switching tube M2 is electrically connected with the output end OUT of the shift register, a second end of the second switching tube M2 is electrically connected with a first polar plate of the second capacitor C2, and a second polar plate of the second capacitor C2 is electrically connected with the second node N2. In the period T4, the low level signal of the second clock signal CK2 controls the input transistor T3 to be turned on, the low level signal of the start signal STV is written into the circuit, the potential of the second node N2 is charged and pulled down, the second output tube T2 is turned on under the control of the low potential, the second output tube T2 generates leakage current, and the voltage of the output signal of the output terminal OUT gradually decreases. Meanwhile, in the period t4, the second clock signal CK2 controls the second switching tube M2 to be turned on, a signal output by the output end OUT is written into the first polar plate of the second capacitor C2, and the bootstrap action of the second capacitor C2 further couples and pulls down the potential of the second node N2. Then when V N2 V when vout=vth and the leakage flow of the second output pipe T2 is cut off N2 The potential of the output terminal OUT is further coupled and pulled down, so that the second output pipe T2 is continuously turned on to generate leakage current, and the signal output by the output terminal OUT is continuously reduced until the signal is equal to the voltage value of the second level signal V2, and the jump from the high level signal to the low level signal is completed, thereby improving the tailing phenomenon.
In this embodiment, the control end of the second switching tube M2 in the anti-tailing module 40 is coupled to the second clock signal CK2, the first end of the first switching tube M1 in the anti-static module 10 is coupled to the first clock signal CK1, and the first switching tube M1 and the second switching tube M2 are turned on respectively, so that the signal of the output end OUT can be prevented from being coupled by the first clock signal CK 1. When the output end OUT jumps from high level to low level, the second clock signal CK2 controls the second switching tube M2 to be turned on, the potential of the second node N1 is further coupled and pulled down by utilizing the signal of the output end OUT, so that the second output tube T2 is continuously turned on, the jump from high level signal to low level signal is completed, and the tailing phenomenon is improved. When the second node N2 is abnormal due to electrostatic charge, the second clock signal CK2 controls the input transistor T3 to turn on during the period T2, and the start signal STV is used to instantaneously reset the second node N2. Then, in the period t1, after the second node N2 is charged and reset, the first switching tube M1 is controlled to be turned on, and the potential coupling of the second node N2 is pulled down by utilizing the first clock signal CK1, so that the potential abnormality of the second node N2 caused by static electricity can be prevented, and the abnormal signal is prevented from being instantaneously output by the output end OUT of the shift register, so that the abnormal display of the pixel row is avoided.
In other embodiments, fig. 7 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 7, a control end of the anti-static module 10 is electrically connected to the second node N2, a first end of the anti-static module 10 receives the third clock signal CK3, and a second end of the anti-static module 10 is electrically connected to the third node N3; the control end of the protection transistor T4 receives the second level signal V2, the first end of the protection transistor T4 is connected with the third node N3, the second end of the protection transistor T4 is connected with the second node N2, and the protection transistor T4 is in a normally-on state. This couples the anti-static module 10 with the second node N2. The anti-static module 10 is configured to pull the potential of the second node N2 low after the potential of the second node N2 is affected by static electricity during a period when the second output tube T2 needs to be turned on.
Fig. 8 is a timing diagram of another shift register according to an embodiment of the present invention. As shown in fig. 8, the third clock signal CK3 provides a low level signal during a period when the second node N2 is at a low level, such as a period t7, during which the anti-static module 10 is capable of using the third clock signal CK3 to pull the potential coupling of the third node N3 low due to the second node N2 and the third node N3When the protection transistor T4 is connected in series, the potential of the third node N3 is pulled down, and the potential of the second node N2 is correspondingly pulled down. When the second node N2 is affected by static electricity and has abnormal potential, the anti-static module 10 can utilize the low level of the third clock signal CK3 to pull the potential coupling of the second node N2 low, so as to prevent the potential abnormality of the second node N2 caused by static electricity, and thereby avoid abnormal display of the pixel row caused by instantaneous output of an abnormal signal at the output end OUT of the shift register. In addition, in the embodiment of FIG. 7, when V is the period in which the signal output at the output terminal OUT jumps from high level to low level N2 When vout=vth and the leakage current of the second output tube T2 is cut off, the potential of the second node N2 may be further coupled and pulled down by using the parasitic capacitance of the second output tube T2, so that the second output tube T2 is continuously turned on to generate the leakage current, and the signal output by the output terminal OUT is continuously reduced until the signal is equal to the voltage value of the second level signal V2, so as to complete the jump from the high level signal to the low level signal, thereby improving the tailing phenomenon.
In this embodiment, the antistatic module 10 is connected to the third node N3 instead of the second node N2. Assuming that the anti-static module 10 is connected to the second node N2, the third clock signal CK3 may pull the potential coupling of the second node N2 high in the period t9 in fig. 8, so that the occurrence of tailing cannot be suppressed.
As shown in fig. 7, the antistatic module 10 includes a third switching tube M3 and a third capacitor C3, wherein a control end of the third switching tube M3 is electrically connected to the second node N2, a first end of the third switching tube M3 receives the third clock signal CK3, a second end of the third switching tube M3 is electrically connected to a first electrode plate of the third capacitor C3, and a second electrode plate of the third capacitor C3 is electrically connected to the third node N3. As shown in fig. 8, when the second node N2 is abnormal due to the electrostatic charge, the third node N3 can be reset by the start signal STV instantaneously when the fourth clock signal CK4 controls the input transistor T3 to be turned on, and the second node N2 is also reset by the charge. It can be understood that in the display panel, the output terminals OUT of the cascaded shift registers sequentially output the valid enable signal, the start signal STV of the shift register is a signal output by the output terminal OUT of the previous stage shift register, and the output terminal OUT of the shift register is connected to a whole row of pixel circuits through the scan line (or the light emitting control line), that is, the output terminal OUT is coupled to a relatively large parasitic capacitance in the display area, and the start signal STV received by the first terminal of the input transistor T3 has a certain charging capability. The second node N2 can be reset by a low level of the start signal STV instantaneously when the input transistor T3 is turned on. After the second node N2 is instantly reset by the start signal STV, the anti-static module 10 uses the low potential of the third clock signal CK3 to pull the potential of the third node N3 low, and the potential of the second node N2 is also pulled low. The fourth clock signal CK4 and the third clock signal CK3 continuously provide low-level signals, so that the second node N2 is reset by charging and the potential of the second node N2 is coupled and pulled down by cooperating with the anti-static module 10, thereby preventing the potential abnormality of the second node N2 caused by static electricity, and avoiding abnormal display of the pixel row caused by instantaneous output of an abnormal signal at the output end OUT of the shift register.
In other embodiments, fig. 9 is a schematic diagram of another shift register according to an embodiment of the present invention, as shown in fig. 9, the shift register further includes a voltage stabilizing module 50, a control end of the voltage stabilizing module 50 is electrically connected to the first node N1, a first end of the voltage stabilizing module 50 receives the fourth clock signal CK4, and a second end of the voltage stabilizing module 50 is electrically connected to the second node N2. The fourth clock signal CK4 and the third clock signal CK3 are a pair of clock signals, and the duty ratios of both are equal. As shown in fig. 9, the first potential control module 30 includes a fifth switching tube T5, a sixth switching tube T6, a seventh switching tube T7, an eighth switching tube T8, a ninth switching tube T9, and a second stabilizing capacitor C0 2 。
The voltage stabilizing module 50 is configured to pull the potential of the second node N2 high to stabilize the potential of the second node N2 during a period when the second output pipe T2 needs to be turned off. In addition, the control terminal of the input transistor T3 receives the third clock signal CK3, the first terminal of the input transistor T3 receives the start signal STV, and the second terminal is connected to the third node N3.
As shown in the timing chart of fig. 8, in the period T5, the second node N2 is at a high potential, and at this time, the second output tube T2 is in an off state, the protection transistor T4 is connected in series between the second node N2 and the third node N3, and due to the parasitic capacitance of the input transistor T3, the potential of the third node N3 is easily pulled down by the coupling of the fourth clock signal CK4 received by the control terminal of the input transistor T3, so that the potential of the second node N2 is pulled down, and when the second node N2 is at a high potential, the output terminal OUT may be abnormal due to the pulled potential. In the embodiment of the present invention, the voltage stabilizing module 50 is configured to pull up the potential coupling of the second node N2 by using the high level time (such as the period T6 in fig. 8) of the fourth clock signal CK4 under the control of the potential of the first node N1, so as to reduce the potential fluctuation range of the second node N2 in the high level, so that the second node N2 is continuously at a higher potential to ensure that the second output pipe T2 is in a closed state, thereby avoiding abnormal output of the output terminal OUT. As shown in fig. 9, the voltage stabilizing module 50 includes a fourth switching tube M4 and a fourth capacitor C4, wherein a control end of the fourth switching tube M4 is electrically connected to the first node N1, a first end of the fourth switching tube M4 receives the fourth clock signal CK4, a second end of the fourth switching tube M4 is electrically connected to a first electrode plate of the fourth capacitor C4, and a second electrode plate of the fourth capacitor C4 is electrically connected to the second node N2. In the time period T6 in the timing chart of fig. 8, the fourth clock signal CK4 is at a high level, the fourth switching tube M4 is turned on and then writes the high level into the first plate of the fourth capacitor C4, and the bootstrap effect of the fourth capacitor C4 pulls the potential coupling of the second node N2 high, so that the potential fluctuation of the second node N2 at the high potential can be reduced, so that the second node N2 is continuously at a higher potential to ensure that the second output tube T2 is in a closed state, thereby avoiding abnormal output of the output terminal OUT.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 10 is a schematic diagram of the display device provided by the embodiment of the present invention, as shown in fig. 10, the display device includes a display panel 100, and the display panel 100 includes a shift register provided by any embodiment of the present invention. The structure of the shift register is already described in the above embodiments, and will not be described in detail here. The display device provided by the embodiment of the invention can be electronic equipment such as a mobile phone, a computer, a tablet, a television, intelligent wearable equipment and the like.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. The display panel is characterized by comprising a shift register, wherein the shift register comprises a first output pipe and a second output pipe, the control end of the first output pipe is electrically connected with a first node, the first end of the first output pipe receives a first level signal, the control end of the second output pipe is electrically connected with a second node, the first end of the second output pipe receives a second level signal, the second end of the first output pipe and the second end of the second output pipe are both electrically connected with the output end of the shift register, and the voltage value of the first level signal is larger than that of the second level signal;
the shift register further comprises an anti-static module, wherein the anti-static module is coupled with the second node and is used for stabilizing the potential of the second node after the potential of the second node is affected by static electricity.
2. The display panel of claim 1, wherein the display panel comprises,
the control end of the anti-static module is electrically connected with the second node, the first end of the anti-static module receives a first clock signal, and the second end of the anti-static module is electrically connected with the second node;
the anti-static module is used for pulling down the potential of the second node after the second output pipe needs to be started and the potential of the second node is affected by static electricity.
3. The display panel of claim 2, wherein the display panel comprises,
the anti-static module comprises a first switch tube and a first capacitor, wherein the control end of the first switch tube is electrically connected with the second node, the first end of the first switch tube receives the first clock signal, the second end of the first switch tube is electrically connected with a first polar plate of the first capacitor, and a second polar plate of the first capacitor is electrically connected with the second node.
4. The display panel of claim 2, wherein the display panel comprises,
the shift register further includes an anti-tailing module,
the control end of the anti-tailing module receives a second clock signal, the first end of the anti-tailing module is electrically connected with the output end of the shift register, and the second end of the anti-tailing module is electrically connected with the second node.
5. The display panel of claim 4, wherein the display panel comprises,
the tailing prevention module comprises a second switching tube and a second capacitor, wherein a control end of the second switching tube receives the second clock signal, a first end of the second switching tube is electrically connected with an output end of the shift register, a second end of the second switching tube is electrically connected with a first polar plate of the second capacitor, and a second polar plate of the second capacitor is electrically connected with the second node.
6. The display panel of claim 1, wherein the display panel comprises,
the shift register further includes a protection transistor; the protection transistor is connected in series between the second node and a third node;
the control end of the anti-static module is electrically connected with the second node, the first end of the anti-static module receives a third clock signal, and the second end of the anti-static module is electrically connected with the third node;
the anti-static module is used for pulling down the potential of the second node after the second output pipe needs to be started and the potential of the second node is affected by static electricity.
7. The display panel of claim 6, wherein the display panel comprises,
the anti-static module comprises a third switch tube and a third capacitor, wherein the control end of the third switch tube is electrically connected with the second node, the first end of the third switch tube receives the third clock signal, the second end of the third switch tube is electrically connected with the first polar plate of the third capacitor, and the second polar plate of the third capacitor is electrically connected with the second node.
8. The display panel of claim 6, wherein the display panel comprises,
the shift register also comprises a voltage stabilizing module;
the control end of the voltage stabilizing module is electrically connected with the first node, the first end of the voltage stabilizing module receives a fourth clock signal, and the second end of the voltage stabilizing module is electrically connected with the second node.
The voltage stabilizing module is used for pulling the potential of the second node high in a period when the second output pipe needs to be closed so as to stabilize the potential of the second node.
9. The display panel of claim 8, wherein the display panel comprises,
the voltage stabilizing module comprises a fourth switching tube and a fourth capacitor, wherein the control end of the fourth switching tube is electrically connected with the first node, the first end of the fourth switching tube receives the fourth clock signal, the second end of the fourth switching tube is electrically connected with the first polar plate of the fourth capacitor, and the second polar plate of the fourth capacitor is electrically connected with the second node.
10. A display device comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310988181.2A CN116959359A (en) | 2023-08-07 | 2023-08-07 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310988181.2A CN116959359A (en) | 2023-08-07 | 2023-08-07 | Display panel and display device |
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| CN116959359A true CN116959359A (en) | 2023-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310988181.2A Pending CN116959359A (en) | 2023-08-07 | 2023-08-07 | Display panel and display device |
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- 2023-08-07 CN CN202310988181.2A patent/CN116959359A/en active Pending
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