CN116955899A - Signal processing method and device - Google Patents

Abstract

A signal processing method and device, do not introduce the twiddle factor additionally, have introduced the dimension of the space, replace and multiply twiddle factor by the space switch, split the larger point into the transformation of a plurality of small points, use Fourier transform of the smaller point to combine the space transform to realize all N point transforms, can reduce the twiddle factor number of N point Fourier transform. Due to the orthogonality of space, the transformation mode does not influence the orthogonality of transformation, reduces the multiplication complexity of transformation, and reduces rounding errors caused by rotation factors by fewer rotation factors.

Description

Signal processing method and device

Technical Field

The present application relates to the field of information processing technologies, and in particular, to a signal processing method and apparatus.

Background

In the field of information processing, particularly data processing of communication systems and image processing systems, it is necessary to forward-convert data to transform the data into a transform domain, then to perform corresponding processing in the transform domain, and then to inverse-transform the processed data to complete the data processing process.

Currently, a fast fourier transform (fast fourier transform, FFT) is generally used to transform data from the time domain to the frequency domain where it is processed. For the transformation of the time domain signal, in order to reduce the number of times of using twiddle factors, in order to reduce the number of multiplications, various ways of simplifying FFT are proposed, such as a radix-2 (radix-2), a radix-4 (radix-4) or a split radix (split radix) algorithm. However, the current FFT method is difficult to further reduce the number of twiddle factors, and is difficult to further reduce the signal processing delay.

Disclosure of Invention

The embodiment of the application provides a signal processing method and device, which are used for reducing the number of twiddle factors and reducing signal processing time delay.

In a first aspect, an embodiment of the present application provides a signal processing method, including: receiving N time domain signals to be processed and performing grouping processing, wherein N=2 ⁿ N is an integer greater than 1, and the N time domain signals after grouping are stored in a first storage space; performing N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals; wherein, before executing the i+1st stage butterfly operation, the back butterfly operation in the i stage is output according to the base 2 type butterfly operationSwitching the last half of the signals from the first memory space to the second memory space; when the i+1th level butterfly operation is executed, the method aims at the front ++1 in the i level output according to the radix-2 butterfly operation>Performing radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly>The signals are in accordance with +.>Performing butterfly operation by point Fourier transform; i is a positive integer less than n and greater than or equal to 0.

In the embodiment of the application, the twiddle factors are not additionally introduced, the dimension of the space is introduced, the twiddle factors are multiplied by the space switching instead of multiplying, the larger points are split into a plurality of small point transformations, the Fourier transformation of the smaller points is combined with the space transformation to realize all N point transformations, and the number of twiddle factors of the N point FFT transformation can be reduced. Due to the orthogonality of space, the transformation mode does not influence the orthogonality of transformation, reduces the multiplication complexity of transformation, and reduces rounding errors caused by rotation factors by fewer rotation factors.

In one possible design, the first memory space belongs to a real part register and the second memory space belongs to an imaginary part register.

In one possible design, thePoint Fourier transform is +.>Point fast Fourier transform->Or->Point number theory transformation->Or->Point Fermat transformation->

Compared with the traditional FFT, the embodiment of the application introduces the space dimension, and the space switching is used for multiplying the twiddle factors, so that the number of twiddle factors of the N-point FFT can be reduced. Due to the orthogonality of space, the transformation mode does not influence the orthogonality of transformation, reduces the multiplication complexity of transformation, and reduces rounding errors caused by rotation factors by fewer rotation factors.

In the above schemeWhen NTT or FNT is used for the point fourier transform, after introducing the spatial dimension,all N-point transformations can be implemented by a smaller number of NTT transformations in combination with the scheme provided by the embodiments of the present application, so that the dynamic range can be increased compared to directly performing NTT transformations in a finite field of the same size. Further, when using a smaller number of NTT transforms, a smaller finite field may be used, and the bit-width resources of the transform may be reduced.

In one possible design, the method further comprises: processing the N transform domain signals to obtain N processed transform domain signals, and grouping the N processed transform domain signals. The inverse transform (or inverse transform) is performed on the N processed transform domain signals after grouping. Specifically, performing N-level butterfly operation on the N processed transform domain signals after grouping, and dividing the signal output by the N-th level by N to obtain N processed time domain signals;

wherein, before the output of the n-k stageThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-k+1 level butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>A signal;

when executing n-k+1 level butterfly operation, for the front partA signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals;

k is a positive integer less than n and greater than 0.

The processing may include filtering or convolution, or the like. For example, during filtering, the forward conversion mode provided by the embodiment of the application can be adopted for the filtering coefficient and the input signal, the time domain is converted into the conversion domain, and then the filtering is realized in the conversion domain by adopting a mode of dot product by dot product for the conversion domain signal and the conversion domain filtering coefficient.

In the design, after the signal is processed in the transformation domain, the inverse transformation is executed, and the transformation of the larger number of points into a plurality of small numbers is carried out by adopting a mode of switching back to the original space in the inverse transformation, so that the number of twiddle factors of the N-point FFT transformation can be reduced. Due to the orthogonality of space, the transformation mode does not influence the orthogonality of transformation, reduces the multiplication complexity of transformation, and reduces rounding errors caused by rotation factors by fewer rotation factors.

In one possible design, the post output in the ith stage is output according to the radix-2 butterflyThe last 1/2 signal of the signals is switched from the first memory space to the second memory space, comprising: output the back +_f of the butterfly according to the radix 2 type in the ith stage>Performing S multiplication operation on half of signals at the tail of the signals; for the back->Post->Switching signals from the second memory space to the first memory space, comprising: for the back->Post->S is carried out by the signals ^-1 A multiplication operation; wherein S is ² ＝-1。

In the above design, the switching space in the forward transform uses S-multiplication operation, and the switching space in the inverse transform uses S ^-1 Multiplication operation, ensure S ² = -1, so that the signal after the forward transformation can be restored to the original signal after the reverse transformation is performed.

In one possible design, s= -j, or s=j. In the design, the S multiplication operation adopts the j multiplication operation, so that the implementation is simple, and the complexity can be reduced.

In one possible design, theInverse point Fourier transform to +.>Dot fast Fourier transform +.>Or->Inverse transformation of point number theory->Or->Inverse transformation of the dot-fermat number->

In a second aspect, an embodiment of the present application provides a signal processing apparatus, including:

an input control unit for receiving N time domain signals to be processed and performing packet processing, wherein N=2 ⁿ N is an integer greater than 1, and the N time domain signals after grouping are stored in a first storage space;

the first signal conversion unit is used for performing N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals;

wherein, before executing the i+1st stage butterfly operation, the back butterfly operation in the i stage is output according to the base 2 type butterfly operationSwitching the last half of the signals from the first memory space to the second memory space;

when the (i+1) -th butterfly operation is executed, the method aims at the front output according to the radix-2 butterfly operation in the (i) -th stagePerforming radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly >The signals are in accordance with +.>Performing butterfly operation by point Fourier transform;

i is a positive integer less than n and greater than or equal to 0.

In one possible design, the first memory space belongs to a real part register and the second memory space belongs to an imaginary part register.

In one possible design, thePoint Fourier transform is +.>Point fast Fourier transform->Or->Point number theory transformation->Or->Point Fermat transformation->

In one possible design, the method further comprises:

a processing unit, configured to process the N transform domain signals to obtain N processed transform domain signals, and group the N processed transform domain signals;

a second signal conversion unit for performing N-stage butterfly operation on the N processed transform domain signals after grouping, and dividing a signal output from the N-th stage by N to obtain N processed time domain signals;

wherein, before the output of the n-k stageThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-k+1 level butterfly operation, for the postPost- >The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>A signal;

when executing n-k+1 level butterfly operation, for the front partA signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals;

k is a positive integer less than n and greater than 0.

In one possible design, the second signal conversion unit is specifically configured to:

output the subsequent stage according to the radix-2 butterfly operation in the ith stagePerforming S multiplication operation on half of signals at the tail of the signals;

for the rear partPost->Switching signals from the second memory space to the first memory space, comprising:

for the rear partPost->S is carried out by the signals ^-1 A multiplication operation;

wherein S is ² ＝-1。

In one possible design, s= -j, or s=j.

In one possible design, theInverse point Fourier transform to +.>Dot fast Fourier transform +.>Or->Inverse transformation of point number theory->Or->Inverse transformation of the dot-fermat number->

In a third aspect, embodiments of the present application provide a computer readable storage medium storing a computer program which, when run on an apparatus, performs the method of the first aspect or any of the designs of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer program product comprising a computer program for performing the method of the first aspect or any of the designs of the first aspect when the computer program is run on a device.

In a fifth aspect, embodiments of the present application provide a chip comprising at least one processor and a communication interface; the communication interface is used for providing program instructions or data for the at least one processor; the at least one processor is configured to execute the program line instructions to implement the method of the first aspect or any of the designs of the first aspect.

In a sixth aspect, an embodiment of the present application provides a chip including at least one processor and a memory; the memory is configured to store program code that is invoked by the at least one processor to implement the method of the first aspect or any of the designs of the first aspect.

Further combinations of the present application may be made to provide further implementations based on the implementations provided in the above aspects.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below.

FIG. 1 is a schematic diagram of an 8-point FFT butterfly network;

FIG. 2 is a schematic diagram of a calculation mode of a radix-2 butterfly network;

FIG. 3 is a schematic diagram of an 8-point split radix FFT flow;

fig. 4 is a schematic flow chart of a forward conversion signal processing method according to an embodiment of the present application;

fig. 5 is a schematic diagram of a signal processing flow of N-point forward conversion according to an embodiment of the present application;

fig. 6 is a schematic diagram of a signal processing flow of the inverse transformation provided in an embodiment of the present application;

fig. 7 is a schematic diagram of a signal processing flow of an N-point inverse transform according to an embodiment of the present application;

fig. 8 is a schematic diagram of a signal processing flow of 8-point forward conversion according to an embodiment of the present application;

fig. 9 is a schematic diagram of a signal processing flow of an 8-point inverse transformation according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another 8-point forward conversion signal processing flow according to an embodiment of the present application;

fig. 11 is a schematic diagram of a signal processing flow of another 8-point inverse transformation according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a communication scenario application transformation provided by an embodiment of the present application;

FIG. 13 is a schematic flow chart of filtering in the transform domain according to an embodiment of the present application;

fig. 14 is a schematic diagram of a signal processing device according to an embodiment of the present application;

Fig. 15 is a schematic diagram of another signal processing apparatus according to an embodiment of the present application.

Detailed Description

The scheme provided by the embodiment of the application is applied to a scene that the signal needs to be converted from a time domain to other domains for processing. Such as may be applied in a digital signal processing scenario. For example, in an optical digital signal processing (optical digital signal processing, oDSP) scenario in communications. As another example, the method can be applied to a convolutional neural network processing scene. The scheme provided by the embodiment of the application can be applied to audio/video or image codecs. The audio-video or image codec can be applied to various electronic devices such as a mobile terminal, a wireless device, a handheld or portable computer, a camera, an audio-video player, a video camera, a video recorder, a monitoring device, and the like. The audio video or image codec may be implemented by a digital circuit or chip, such as a digital signal processor (optical digital signal processor), or by a software code driving processor executing a flow in software code.

The terms "first," "second," and the like, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

Before describing embodiments of the present application, concepts and technologies related to the present application will be described.

(1) The fast fourier transform (fast Fourier transform, FFT) is a fast algorithm for calculating a discrete fourier transform (discrete Fourier transform, DFT) or its inverse, and is very widely used in engineering, science and mathematics fields, such as signal decomposition, digital filtering, image processing, etc. By fourier analysis, the source data will be transformed from the original domain (typically time or space) to a representation of the transform domain (such as the frequency domain) or vice versa. To accommodate the numerical calculations performed on a computer, the fourier transform needs to be discretized, called DFT, with the mathematical expression of the following formula (1):

wherein X is _f (k) Is the input signal in the transform domain.Is the twiddle factor of the transformation. Twiddle factors may also be referred to as butterfly factors. The twiddle factor has cyclic symmetry: />N represents the number of points used for fourier transform. Similarly, the inverse transform is formally identical to the forward transform, except that it is rotatedThe conversion factors are different, and when the result after filtering is outputted, the result is divided by the number of points N point by point.

The rotation factor of FFT is complexThe transformation formula of the FFT can be expressed as formula (2).

(2) Number theory transformation (number theory transform, NTT). The twiddle factor of NTT is integer real number, adoptingThe transformation formula of NTT may be expressed as formula (3).

Wherein mod _F The dividend representing the remainder is F. Alpha represents the basis of the twiddle factor and takes on a real number.

The number theory transformation includes the fermat number theory transformation (fermat number transform, FNT), and may also be simply referred to as the fermat number transformation. In the case of the FNT,f is the Fermat number. Alpha is the substrate of the twiddle factor, the most common value being 2, i.e. 2 ^nk . The twiddle factor can be realized by shifting without multiplication. Therefore, the conversion process of FNT does not need multiplication, and the positive inverse conversion can be realized quickly and simply in theory.

(3) Butterfly operations. Taking the 8-point fourier transform FFT-8 with radix-2 (radix-2) as an example, the data sequence length n=8. Referring to fig. 1, the butterfly network abstraction of FFT-8 is three layers: stage-section butterfly unit (butterfly). For example, as can be seen from fig. 1, the 1 st stage comprises one segment, each segment comprising 4 butterfly units, the second stage comprises 2 segments, each segment comprising 2 butterfly units, and the third stage comprises 4 segments, each segment comprising 1 butterfly unit. Furthermore, the concept of segments can be simplified, and only the hierarchical and butterfly units can be logically distinguished. The basic operation rules of the butterfly unit are shown in fig. 2.

It will be understood by those skilled in the art that the butterfly network is a schematic diagram for performing FFT, and the output of each stage of the butterfly network is the input of the next stage, and the value of the base is the number of types of butterflies that correspond to the base and can process data at a time. For example, for the butterfly network shown in fig. 1, the butterfly network is used for processing a data sequence with a length of 8, and the basis of each stage is 2, so that each butterfly in each stage represents that 2 input data are operated on, and 2 output data are output; the 8 outputs of each stage are the 8 inputs of the next stage.

Currently, for the transformation of time domain signals, in order to reduce the number of times of using twiddle factors, in order to reduce the number of multiplications, various simplified fourier transformation approaches are proposed, such as the radix-2 (radix-2), radix-4 (radix-4) or split radix (split radix) algorithms.

Take the radix-4 (radix-4) type N-point FFT as an example. The transformation formula (2) of the N-point FFT can be converted to be represented by the following formula (4).

Wherein x (n),are combined together in the form of the output of a 4-point FFT transform. And these four sequences can be further nested with 4-point FFT step-wise disassembled in the manner described above. From the above, it can be seen that the 4-point FFT transformation requires no multiplication and a total of 8 addition implementations. And when the 4-point FFT is combined into N points, the corresponding twiddle factors are required to be multiplied, and the (3N/8) lb (N) times are required to be multiplied. lb is expressed as log ₂ 。

The Split radio FFT algorithm can be realized by combining the radio-2 and radio-4 FFT together. Referring to fig. 3, a schematic diagram of an 8-point Split radius FFT butterfly network is shown. In the case of the view of figure 3,in the Split Radix FFT algorithm, the characteristic that twiddle factors among multiple layers of transformation can be combined by successive multiplication is utilized, so that the number of twiddle factors is reduced. The number of twiddle factors used by the Radix-4 FFT is smaller than that of Radix-2 FFT alone, so that the complexity of FFT transformation can be reduced.

The FNT included in the NTT is used as a common transformation, multiplication is not needed, and the complexity of the transformation is reduced. However, FNT requires taking a margin (also called a modulus) during the transformation, which brings about the limitation of NTT in mathematical principle. According to equation (3), a remainder is required after shifting the input data, which results in the calculated bit width locking to the bit width of the dividend. Since the NTT transform is a finite field transform, taking FNT as an example, the fermat number f=2 ^b +1, b is bit-wide, then x (mod _F ) Expressed as a remainder for x, the dividend is a fermat number, the data range of the remainder is [0,F), and is an integer.

In combination with the above formula (3), when the input signal in_x= -1, the remainder operation in the NTT transform causes: mod (in_x) =2 ^b -1, and when the input signal in_x=2 ^b -1, the remainder operation of the NTT transform causes: mod (in_x) =2 ^b -1, i.e. the two input signals are modulo identical, the magnitudes of the two input signals cannot be distinguished. To avoid this, it is necessary to limit the size of the input data. When considering signs, the input data needs to lie within the range [ -F/2,F/2). For example, when the output data is negative,x∈[-F/2，0)，x(mod _F ) =f+x. Namely: x (mod) _F ) E [ F/2,F), the bit width of which is b-1 to b+1. That is, the bit-wide range depends on the size of the input data. In combination with a series of operations such as shift accumulation remainder in formula (3), the bit width of the input signal is locked to (b+1) bits. Even if the absolute value of the input data is small, so that the bit width of the time domain is small, the input data needs to be represented by (b+1) bits in the transform domain, and excessive bit resources are consumed. The dynamic range is also limited due to the need to limit the size of the input data, resulting in performance penalty.

Therefore, in the present FFT scheme, it is difficult to further reduce the number of twiddle factors without performance penalty, and it is difficult to further reduce the signal processing delay.

Based on the above, the present application provides a signal processing method and apparatus, which are used to simplify the transformation operation from the time domain to the transform domain, reduce the number of rotation factors used, and reduce the complexity.

Referring to fig. 4, a flow chart of a signal processing method provided in an embodiment of the application is shown. The method flow may be performed by an electronic device, or by an audio-video or image codec in an electronic device, or by one or more chips in an audio-video or image codec.

401, receiving N time domain signals to be processed and performing packet processing, where n=2 ⁿ N is an integer greater than 1.

The N time domain signals after grouping are stored in the first storage space. In one example, after receiving N time domain signals to be processed, the N time domain signals may be stored in the first storage space. The N time domain signals are then grouped. In another example, after receiving N time domain signals to be processed, the N time domain signals are grouped, and then the N time domain signals after being grouped are stored in the first storage space.

It should be appreciated that grouping time domain signals for butterfly operations, grouping signals for performing butterfly operations.

In some embodiments, the acquired time domain signal is a discrete digital signal, and the N discrete digital signals form a data sequence having a length N. If the received signal is a continuous digital signal, the received signal is discretized into a data sequence, the length of the data sequence is N, and the discretized digital sequence comprises N time domain signals.

And 402, performing N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals.

Referring to fig. 5, the input time domain signal includes N numbers and is stored in the first storage space. After the N time domain signals are subjected to the 1 st stage of butterfly operation of the base-2, the N signals obtained are divided into front N/2 signals and rear N/2 signals. The last half (1/2) of the last N/2 signals, i.e. the last N/4 of the last N/2 signals, are switched from the first memory space to the second memory space. The latter N/2 signals (including the last N/4 signals of the second memory space) perform butterfly operations from stage 2 to stage N according to an N/2 point fourier transform. For example, the latter N/2 signals (including the N/4 signals of the last second memory space) perform radix 2 or radix 4 or split radix butterfly operations from level 2 to level N according to an N/2 point FFT or NTT.

The first N/2 signals continue to execute the butterfly operation of the base-2 in the 2 nd stage to obtain N/2 signals output by the 2 nd stage. The last 1/2 signal (N/4 signal) of the last N/2 signals output by the level 1 radix-2 butterfly operation has been switched from the first memory space to the second memory space before the level 2 butterfly operation is performed. The N/2 signals output by the 2 nd-stage base 2-type butterfly operation are divided into a front N/4 signal and a rear N/4 signal. The last half (1/2) of the last N/4 signals, i.e. the last N/8 of the last N/4 signals, are switched from the first memory space to the second memory space. The latter N/4 signals (including the last N/8 signals of the second memory space) perform butterfly operations from stage 3 to stage N according to an N/4 point fourier transform. For example, the latter N/4 signals (including the N/8 signals of the last second memory space) perform radix 2 or radix 4 or split radix butterfly operations from level 3 to level N according to an N/4 point FFT or NTT.

The first N/4 signals output by the butterfly operation of the base-2 executed by the 2 nd stage are continuously executed by the butterfly operation of the base-2 executed by the 3 rd stage to obtain N/4 signals output by the 3 rd stage. The last 1/2 signal (N/8 signal) of the last N/4 signals output by the level 2 radix-2 butterfly has been switched from the first memory space to the second memory space before the level 3 butterfly is performed. The N/4 signals output by the 3 rd-stage base 2 type butterfly operation are divided into a front N/8 signal and a rear N/8 signal. If N is greater than 3, the last half (1/2) of the last N/8 signals, i.e., the last N/16 of the last N/8 signals, are switched from the first memory space to the second memory space. The latter N/8 signals (including the last N/16 signals of the second memory space) perform butterfly operations from stage 4 to stage N according to an N/8-point fourier transform. For example, the latter N/8 signals (including the N/16 signals of the last second memory space) perform radix 2 or radix 4 or split radix butterfly operations from level 4 to level N according to an N/8 point FFT or NTT. And by analogy, completing the butterfly operation of n stages.

Further, before executing the (i+1) th butterfly operation, outputting the subsequent butterfly operation according to the radix-2 butterfly operation in the (i) th stageThe last 1/2 signal of the signals (i.e.. End +. >Signals) from the first memory space to a second memory space. i is a positive integer less than n and greater than or equal to 0. When the i+1th level butterfly operation is executed, the method aims at the front ++1 in the i level output according to the radix-2 butterfly operation>Performing radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly>The signals are in accordance with +.>The point fourier transform performs a butterfly operation.

The term "rear" as used hereinThe last 1/2 signal of the signals, which means, post->The signal is equally divided into two parts, the latter part is the last 1/2 signal. It can also be understood that>End>A signal.

Illustratively, the followingPoint Fourier transform is +.>Point fast Fourier transform->Or->Point number theory transformation NTT->Or->Point Fermat transformation->

Compared with the traditional FFT, the embodiment of the application introduces the space dimension, and the space switching is used for multiplying the twiddle factors, so that the number of twiddle factors of the N-point FFT can be reduced. Due to the orthogonality of space, the transformation mode does not influence the orthogonality of transformation, reduces the multiplication complexity of transformation, and reduces rounding errors caused by rotation factors by fewer rotation factors.

In the above schemeWhen the point fourier transform adopts NTT, after introducing the spatial dimension, the NTT transform with smaller points can be combined with the scheme provided by the embodiment of the present application to realize all N-point transforms, so that the dynamic range can be increased compared with directly executing the NTT transform in a finite field with the same size. Further, when using a smaller number of NTT transforms, a smaller finite field may be used, and the bit-width resources of the transform may be reduced.

In some embodiments, the signal is switched from the first memory space to the second memory space, which may be the signal multiplied by the sign S of the switching space. S may be j or-j. The first memory space may be a real part register and the second memory space may be an imaginary part register.

The description above with respect to fig. 4 and 5 is made with respect to the forward transform from the time domain to the transform domain, and the manner of the inverse transform from the transform domain to the time domain is described below. The step of performing the memory switching in the inverse transformation is understood to be that the signal of the memory 2 is combined into the memory 1 and then the butterfly operation of the base-2 is performed. The manner of combining may be, for example, addition.

Referring to fig. 6, another signal processing method according to an embodiment of the present application is shown. The method flow may be performed by an electronic device, or by an audio-video or image codec in an electronic device, or by one or more chips in an audio-video or image codec.

601, N transform domain signals are acquired and grouped.

At 602, N-level butterfly operations are performed on the N transform domain signals after grouping, and the N-th level output signal is divided by N to obtain N time domain signals.

Referring to FIG. 7, the N signals output at the N-1 stage include a front generated using a radix-2 butterfly operationIndividual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the nth stage butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>Signals (comprising switching from the second memory space to the first memory space +.>A signal). When executing the nth butterfly operation, for the front +.>A signal and the post-memory-space switchingAnd performing radix-2 butterfly operation on each signal.

Also, before the n-2 th stage outputThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-1 level butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch >Signals (comprising switching from the second memory space to the first memory space +.>A signal). When executing n-1 level butterfly operation, for the former +.>A signal and said memory switched back +.>The individual signals are subjected to radix-2 butterfly operations, and so on.

Specifically, the output of the n-k stage is preceded byThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal; before the n-k+1 th butterfly, said post +.>Post->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>A signal; when executing n-k+1 level butterfly operation, for the front->A signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals; k is a positive integer less than n and greater than 0.

In some embodiments, switching a signal from a first memory space to a second memory space may be understood as performing an S-multiplication operation on the signal. The switching of a signal from the second memory space back to the first memory space can be understood as S ^-1 And (5) a multiplication operation. Wherein S is ² = -1. For example, S= -j, then S ^-1 For example, s=j, then S ^-1 ＝-j。

The forward and reverse transforms provided by embodiments of the present application are described below in connection with specific examples.

Taking n=8 as an example, 8-point transformation is performed. Referring to fig. 8, the input time domain signal is X (0)..x (7), and the output transform domain signal is X _f (0)...X _f (7). Wherein the basic unit is a butterfly unit.

In the butterfly network structure shown in fig. 8, symbol S represents a switching symbol for switching from the first memory space to the second memory space.

The input time domain signal x (0)..x (7) outputs T (0)..t (3), L (0)..l (3) after the level 1 is subjected to the butterfly operation of the base 2. The last N/4 signals output by the butterfly operation of the 1 st stage by adopting the base 2 are switched from the first storage space to the second storage space, namely L (2), and L (3) is switched from the first storage space to the second storage space. It can be understood that L (2), L (3) are multiplied by the switching space symbol S, i.e., L (2), L (3) are multiplied by S to obtain s×l (2), s×l (3).

The subsequent transforms are completed using a 4-point fourier transform for L (0), L (1), s×l (2), s×l (3).

For T (0)..t (3), continuing to execute the butterfly output T of radix 2 at stage 2 ₁ (0)…T ₁ (3). Switching the last N/8 signal in the N/4 output by the butterfly operation of the 2 nd stage execution base 2 from the first storage space to the second storage space, namely T ₁ (3) Switch from the first storage space to the second storage space. It can be understood that T ₁ (3) Multiplying the switching space symbols S, i.e. T, respectively ₁ (3) Multiplying S to obtain S ₁ (3). For T ₁ (2)、S*T ₁ (3) The subsequent transformation is completed using the 2-point fourier transform. T (T) ₁ (0)、T ₁ (1) The butterfly of base 2 is performed at stage 3. Fig. 8 illustrates fourier transform as FFT.

Taking s=j as an example, the butterfly output may be:

X _f (0)＝T ₁ (0)+T ₁ (1)；T ₁ (0)＝T(0)+T(2)；T ₁ (2)＝T(0)-T(2)；

X _f (1)＝L(0)+L(1)+jL(2)+jL(3)；

X _f (2)＝T ₁ (2)+jT ₁ (3)；T ₁ (2)＝T(0)-T(2)；T ₁ (3)＝T(1)-T(3)；

X _f (4)＝T ₁ (0)-T ₁ (1)；T ₁ (1)＝T(1)+T(3)；

X _f (5)＝L(0)-L(1)+jL(2)-jL(3)；

X _f (6)＝T ₁ (2)-jT ₁ (3)；

the method comprises the following steps of:

X _f (0)＝X(0)+X(1)+X(2)+X(3)+X(4)+X(5)+X(6)+X(7)；

X _f (4)＝X(0)-X(1)+X(2)-X(3)+X(4)-X(5)+X(6)-X(7)；

X _f (2)＝X(0)+jX(1)-X(2)-jX(3)+X(4)+jX(5)-X(6)-jX(7)；

X _f (6)＝X(0)-jX(1)-X(2)+jX(3)+X(4)-jX(5)-X(6)+jX(7)；

X _f (1)＝X(0)+X(1)+jX(2)+jX(3)-X(4)-X(5)-jX(6)-jX(7)；

X _f (5)＝X(0)-X(1)+jX(2)-jX(3)-X(4)+X(5)-jX(6)+jX(7)；

X _f (3)＝X(0)-jX(1)-jX(2)-X(3)-X(4)+jX(5)+jX(6)-X(7)；

X _f (7)＝X(0)+jX(1)-jX(2)+X(3)-X(4)-jX(5)+jX(6)+X(7)。

from the above, it can be seen that the 8-point transform does not require multiplication operations, does not require twiddle factors, and can reduce complexity.

The input time domain signal may be a real signal or a complex signal. In some scenarios, if the input is a complex signal, in one possible processing approach, the complex signal may be split into two parts, a real part and a complex part, and the time domain signal is transformed into the transform domain using the forward transform approach provided by the present application for the real part and the complex part.

The first storage space and the second storage space may belong to different memories respectively, or may belong to two different storage spaces of the same memory. The memory may be a volatile memory (RAM), such as a random-access memory (RAM). The memory may also be a nonvolatile memory such as a Hard Disk Drive (HDD) or a Solid State Drive (SSD), or the like.

The inverse transformation will be described below with reference to fig. 9, taking n=8 as an example. Referring to fig. 9, the input transform domain signal is X _f (0)…X _f (7) The output time domain signal x (0)..x (7). In the butterfly network structure shown in fig. 9, symbol S ^-1 A switching symbol representing a switch from the second memory space to the first memory space. The butterfly network structure of the inverse transform in fig. 9 is symmetrical to the butterfly network structure of the forward transform shown in fig. 8. The transform domain signal output in fig. 8 is used as an input in the inverse transform. The butterfly network structure in fig. 9 includes 3 stages.

X for input _f (0)...X _f (7) The last half of the signal is subjected to 4-point inverse fast fourier transform at stages 1 and 2. I.e. for X _f (1)、X _f (5)、X _f (3)、X _f (7) An inverse fast fourier transform of 4 points is performed. Then the last 2 signals of the 4 signals output by the 4-point inverse fast Fourier transform are switched from the second storage space back to the first storage space, using S ^-1 Representing L of switching back to the original storage space to obtain output _inv (0)...L _inv (3). X for input _f (0)...X _f (7) The first half of the signal, the 2-point inverse fourier transform is performed at stage 1. The last N/8 point (i.e. last signal) of the output is switched back to the original memory space, and then the butterfly operation of the 2 nd level base 2 is carried out to obtain the output T _inv (0)...T _inv (3)。

And performing the butterfly operation of the base 2 on the 8 signals input into the 3 rd stage at the 3 rd stage, and dividing the output signal by 8 to recover the time domain signal, namely obtaining x (0)..x (7).

Optionally, on the premise of not changing the operation mode, the index of the signal input and output by the positive and negative transformation can be changed so as to flexibly match different circuit designs.

In combination with the output of fig. 8, the output may be subjected to the level 1 butterfly operation as follows:

X ₁ (0)＝2X(0)+2X(2)+2X(4)+2X(6)；

X ₁ (4)＝2X(1)+2X(3)+2X(5)+2X(7)；

X ₁ (2)＝2X(0)-2X(2)+2X(4)-2X(6)；

X ₁ (6)＝2jX(1)-2jX(3)+2jX(5)-2jX(7)；

X ₁ (1)＝2X(0)+2jX(2)-2X(4)-2jX(6)；

X ₁ (5)＝2X(1)+2jX(3)-2X(5)-2jX(7)；

X ₁ (3)＝2X(0)-2jX(2)-2X(4)+2jX(6)；

X ₁ (7)＝-2jX(1)-2X(3)+2jX(5)+2X(7)。

S ^-1 ＝-j，the output can be:

T _inv (0)＝4X(0)+4X(4)；

T _inv (1)＝4X(1)+4X(5)；

T _inv (2)＝4X(2)+4X(6)；

T _inv (3)＝4X(3)+4X(7)；

L _inv (0)＝4X(0)-4X(4)；

L _inv (1)＝4X(1)-4X(5)；

L _inv (2)＝-j*(4jX(2)-4jX(6))＝4X(2)-4X(6)；

L _inv (3)＝-j*(4jX(3)-4jX(7))＝4X(3)-4X(7)。

the third butterfly operation output is multiplied by 1/8 and then output x (0) … x (7).

Referring to fig. 10 and 11, NTT-4 is used as an example of a 4-point fourier transform.

Referring to fig. 10, the input time domain signal x (0.) x (7) outputs T (0.) T (3), L (0.) L (3) after the level 1 is subjected to the butterfly operation of the base 2. The last N/4 signals output by the butterfly operation of the 1 st stage by adopting the base 2 are switched from the first storage space to the second storage space, namely L (2), and L (3) is switched from the first storage space to the second storage space. It can be understood that L (2), L (3) are multiplied by the switching space symbol S, i.e., L (2), L (3) are multiplied by S to obtain s×l (2), s×l (3).

Subsequent transformations were performed using NTT-4 for L (0), L (1), s×l (2), s×l (3).

For T (0)..t (3), continuing to execute the butterfly output T of radix 2 at stage 2 ₁ (0)...T ₁ (3). Switching the last N/8 signal in the N/4 output by the butterfly operation of the 2 nd stage execution base 2 from the first storage space to the second storage space, namely T ₁ (3) Switch from the first storage space to the second storage space. It can be understood that T ₁ (3) Multiplying the switching space symbols S, i.e. T, respectively ₁ (3) Multiplying S to obtain S ₁ (3). For T ₁ (2)、S*T ₁ (3) Subsequent transformations continue to be completed using FTT-2. T (T) ₁ (0)、T ₁ (1) The butterfly of base 2 is performed at stage 3.

From the above, it can be seen that the 8-point transform does not require multiplication operations, does not require twiddle factors, and can reduce complexity.

The inverse transformation will be described below with reference to fig. 10, taking n=8 as an example. Referring to FIG. 11, the input transform domain signal is X _f (0)...X _f (7) The output time domain signal x (0)..x (7). In the butterfly network structure shown in fig. 11, symbol S ^-1 A switching symbol representing a switch from the second memory space to the first memory space. The butterfly network structure of the inverse transform in fig. 11 is symmetrical to the butterfly network structure of the forward transform shown in fig. 10. The transform domain signal output in fig. 10 is used as an input in the inverse transform. The butterfly network structure in fig. 11 includes 3 stages.

X for input _f (0)...X _f (7) The last half of the signals are INTT at the 1 st and 2 nd stages-4. I.e. for X _f (1)、X _f (5)、X _f (3)、X _f (7) INTT-4 was performed. Then the last 2 signals of the 4 signals output by the 4-point inverse fast Fourier transform are switched from the second storage space back to the first storage space, using S ^-1 Representing L of switching back to the original storage space to obtain output _inv (0)...L _inv (3). X for input _f (0)...X _f (7) The first half of the signal, the 2-point inverse fourier transform is performed at stage 1. The last N/8 point (i.e. last signal) of the output is switched back to the original memory space, and then the butterfly operation of the 2 nd level base 2 is carried out to obtain the output T _inv (0)...T _inv (3). And performing the butterfly operation of the base 2 on the 8 signals input into the 3 rd stage at the 3 rd stage, and dividing the output signal by 8 to recover the time domain signal, namely obtaining x (0)..x (7).

In some possible scenarios, the forward and inverse transforms provided by the present application may be applied in signal filtering. Referring to fig. 12, the application to an oDSP scenario is exemplified as digital signal filtering in the digital signal codec process. In one example, the communication transmitter performs digital signal processing, including filtering, upon encoding the modulated signal to obtain the encoded modulated signal for transmission to the communication receiver. In another example, after the communication receives the signal to be decoded, digital signal processing, such as filtering, may be performed.

In the filtering process, a signal processing manner that achieves high performance and low complexity in the transform domain, such as a dot product-by-dot product manner in the transform domain, may be employed instead of a calculation manner in which the signal and the filter coefficient are convolved in the time domain. The specific flow can be seen in fig. 13. A time domain signal is acquired and filter coefficients are acquired. Then, forward conversion is executed by adopting the forward conversion mode provided by the embodiment of the application aiming at the time domain signal and the filter coefficient, then the signal in the conversion domain after forward conversion and the filter coefficient after forward conversion are processed by the item-by-item dot product, and then the signal after the item-by-item dot product is subjected to inverse conversion by adopting the inverse conversion mode provided by the application to obtain output, so that the filtering processing of the input time domain signal is realized.

The mathematical expression for the dot product by dot product is shown in equation (5):

X _f (k).*H _f (k) (5)

H _f (k) Filter coefficients in the transform domain are expressed. In the above process, the forward and reverse transformation is a main complexity source, and by adopting the forward and reverse transformation modes provided by the embodiment of the application, the complexity can be reduced, so that the power consumption can be reduced.

Based on the same inventive concept as the method embodiment, the embodiment of the application further provides a signal processing device, which may specifically be a processor in an electronic device, or a chip system, or a module in an electronic device. Schematically, referring to fig. 14, the apparatus may include an input control unit 1401 and a first signal conversion unit 1402. The input control unit 1401 and the first signal conversion unit 1402 are used to perform the method steps shown in the corresponding embodiment of fig. 4.

An input control unit 1401 for receiving N time domain signals to be processed and performing packet processing, wherein n=2 ⁿ N is an integer greater than 1, and the N time domain signals after grouping are stored in a first storage space;

a first signal conversion unit 1402, configured to perform N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals;

wherein, before executing the i+1st stage butterfly operation, the back butterfly operation in the i stage is output according to the base 2 type butterfly operationThe last 1/2 signal of the signals is switched from the first storage space to the second storage space;

when the (i+1) -th butterfly operation is executed, the method aims at the front output according to the radix-2 butterfly operation in the (i) -th stagePerforming radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly>The signals are in accordance with +.>Performing butterfly operation by point Fourier transform;

i is a positive integer less than n and greater than or equal to 0.

In one possible implementation, the first memory space belongs to a real part register and the second memory space belongs to an imaginary part register.

In one possible implementation, thePoint Fourier transform is +.>Point fast Fourier transform- >Or->Point number theory transformation->Or->Point Fermat transformation->

In one possible implementation, the method further includes:

a processing unit 1403 is configured to process the N transform domain signals to obtain N processed transform domain signals, and group the N processed transform domain signals.

Processing may include filtering, convolution, and the like.

A second signal conversion unit 1404 configured to perform N-stage butterfly operation on the N processed transform domain signals after grouping, and divide the signal output by the N-th stage by N to obtain N processed time domain signals;

wherein, before the output of the n-k stageThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-k+1 level butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>A signal;

when executing n-k+1 level butterfly operation, for the front partA signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals;

k is a positive integer less than n and greater than 0.

In one possible implementation manner, the first signal conversion unit 1402 is specifically configured to: output the subsequent stage according to the radix-2 butterfly operation in the ith stagePerforming S multiplication operation on the last 1/2 signal in the signals;

the second signal conversion unit 1404 is specifically configured to: for the rear partPost->S is carried out by the signals ^-1 A multiplication operation;

wherein S is ² ＝-1。

In one possible implementation, s= -j, or s=j.

In one possible implementation, theInverse point Fourier transform to +.>Dot fast fourier inverse transformOr->Inverse transformation of point number theory->Or->Inverse transformation of the dot-fermat number->

Embodiments of the present application also provide another structure of the apparatus, as shown in fig. 15, where a communication interface 1510 and a processor 1520 may be included in the apparatus 1500. Optionally, a memory 1530 may also be included in the apparatus 1500. The memory 1530 may include an internal memory, or the memory 1530 may include an external memory, or the memory 1530 may include an internal memory and an external memory. The internal memory is located inside the device and the external memory is located outside the device. In an example, the input control unit 1401 and the first signal conversion unit 1402, the processing unit 1403, and the second signal conversion unit 1404 shown in fig. 14 described above may be implemented by the processor 1520. Processor 1520 receives the time domain signals over communication interface 1510 and is used to implement the methods described in fig. 4 and 6. In implementation, the steps of the process flow may be performed by integrated logic circuitry in hardware in the processor 1520 or instructions in software to perform the methods described in fig. 4 and 6.

Also included in memory 1503 are memory spaces for storing signals or butterfly intermediate results, such as a first memory space and a second memory space. For example, the first storage space and the second storage space belong to an internal memory, and may belong to the same internal memory or may belong to different internal memories.

The communication interface 1510 in embodiments of the present application may be a circuit, bus, transceiver, or any other device that may be used to interact with information. The other device may be, for example, an apparatus coupled to device 1500.

The processor 1520 in the embodiments of the present application may be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software elements in the processor for execution. Program code executed by the processor 1520 to implement the methods described above may be stored in the memory 1530. Memory 1530 is coupled to processor 1520.

The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be in electrical, mechanical, or other forms for information interaction between the devices, units, or modules.

Processor 1520 may operate in conjunction with memory 1530. The memory 1530 may be a nonvolatile memory such as a Hard Disk Drive (HDD) or a Solid State Drive (SSD), or may be a volatile memory (RAM). Memory 1530 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such.

The specific connection medium between the communication interface 1510, the processor 1520, and the memory 1530 is not limited to the specific connection medium described above in the embodiments of the present application. The connection between the memory 1530, the processor 1520, and the communication interface 1510 in fig. 15 is shown by a bus, which is shown by a thick line in fig. 15, and the connection between other components is merely illustrative and not limiting. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 15, but not only one bus or one type of bus.

Based on the above embodiments, the present application also provides a computer storage medium in which a software program is stored, which when read and executed by one or more processors can implement the method provided by any one or more of the above embodiments. The computer storage medium may include: various media capable of storing program codes, such as a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

Based on the above embodiments, the present application further provides a chip, where the chip includes a processor, and the chip is configured to implement the functions related to any one or more of the above embodiments, for example, obtain or process information or messages related to the above method. Optionally, the chip further comprises a memory for the necessary program instructions and data to be executed by the processor. The chip may be formed by a chip, or may include a chip and other discrete devices.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described communication system may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.

An embodiment of the application provides a computer readable medium for storing a computer program comprising instructions for performing the method steps in the corresponding method embodiment of fig. 4.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described communication system may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (17)

1. A signal processing method, comprising:

receiving N time domain signals to be processed and performing grouping processing, wherein N=2 ⁿ N is an integer greater than 1, and the N time domain signals after grouping are stored in a first storage space;

performing N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals;

wherein, before executing the i+1st stage butterfly operation, the back butterfly operation in the i stage is output according to the base 2 type butterfly operationSwitching the last half of the signals from the first memory space to the second memory space;

when the (i+1) -th butterfly operation is executed, the method aims at the front output according to the radix-2 butterfly operation in the (i) -th stagePerforming radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly>The signals are in accordance with +.>Performing butterfly operation by point Fourier transform;

i is a positive integer less than n and greater than or equal to 0.

2. The method of claim 1, wherein the first memory space belongs to a real part register and the second memory space belongs to an imaginary part register.

3. The method of claim 1 or 2, wherein thePoint Fourier transform is +.>Point fast Fourier transform->Or->Point number theory transformation->Or->Point Fermat transformation->

4. A method according to any one of claims 1-3, wherein the method further comprises:

processing the N transform domain signals to obtain N processed transform domain signals, and grouping the N processed transform domain signals;

performing N-level butterfly operation on the N processed transform domain signals after grouping, and dividing the signal output by the N-th level by N to obtain N processed time domain signals;

wherein, before the output of the n-k stageThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-k+1 level butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch >A signal;

when executing n-k+1 level butterfly operation, for the front partA signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals;

k is a positive integer less than n and greater than 0.

5. The method of claim 4, wherein the post-stage in the ith stage output according to the radix-2 butterfly is outputThe last 1/2 signal of the signals is switched from the first memory space to the second memory space, comprising:

output the subsequent stage according to the radix-2 butterfly operation in the ith stagePerforming S multiplication operation on half of signals at the tail of the signals;

for the rear partPost->Switching signals from the second memory space to the first memory space, comprising:

for the rear partStart/stop in individual signals>S is carried out by the signals ^-1 A multiplication operation;

wherein S is ² ＝-1。

6. The method of claim 5, wherein s= -j, or S = j.

7. The method of any one of claims 4-6, wherein theInverse point Fourier transform to +.>Dot fast Fourier transform +.>Or->Inverse transformation of point number theory->Or->Inverse transformation of the dot-fermat number->

8. A signal processing apparatus, comprising:

an input control unit for receiving N time domain signals to be processed and performing packet processing, wherein N=2 ⁿ N is an integer greater than 1, and the N time domain signals after grouping are stored in a first storage space;

the first signal conversion unit is used for performing N-level butterfly operation on the N time domain signals after grouping to obtain N transform domain signals;

wherein, before executing the i+1st stage butterfly operation, the back butterfly operation in the i stage is output according to the base 2 type butterfly operationSwitching the last half of the signals from the first memory space to the second memory space;

when the (i+1) -th butterfly operation is executed, the method aims at the front output according to the radix-2 butterfly operation in the (i) -th stagePerforming radix-2 butterfly operation on the signals; for the back +_f output in the ith stage according to the radix 2 butterfly>The signals are in accordance with +.>Performing butterfly operation by point Fourier transform;

i is a positive integer less than n and greater than or equal to 0.

9. The apparatus of claim 8, wherein the first memory space is a real part register and the second memory space is an imaginary part register.

10. The apparatus of claim 8 or 9, wherein thePoint Fourier transform is +.>Point fast Fourier transform->Or->Point number theory transformation->Or->Point Fermat transformation- >

11. The apparatus of any one of claims 8-10, further comprising:

a processing unit, configured to process the N transform domain signals to obtain N processed transform domain signals, and group the N processed transform domain signals;

a second signal conversion unit for performing N-stage butterfly operation on the N processed transform domain signals after grouping, and dividing a signal output from the N-th stage by N to obtain N processed time domain signals;

wherein, before the output of the n-k stageThe signal includes the front +.2 butterfly>Individual signals and according to->Post-f generated by performing butterfly operation in point Fourier inverse transform mode>A signal;

before the n-k+1 level butterfly operation, for the postPost->The signal is switched from the second memory space to the first memory space to obtain a post-memory space switch>A signal;

when executing n-k+1 level butterfly operation, for the front partA signal and said memory switched back +.>Performing radix-2 butterfly operation on the signals;

k is a positive integer less than n and greater than 0.

12. The apparatus of claim 11, wherein the first signal conversion unit is specifically configured to: will be The i-th stage outputs the back part according to the radix-2 butterfly operationPerforming S multiplication operation on half of signals at the tail of the signals;

the first signal conversion unit is specifically configured to: for the rear partPost->S is carried out by the signals ^-1 A multiplication operation;

wherein S is ² ＝-1。

13. The apparatus of claim 12, wherein s= -j, or S = j.

14. The apparatus of any one of claims 11-13, wherein theInverse point Fourier transform to +.>Dot fast Fourier transform +.>Or->Inverse transformation of point number theory->Or->Inverse transformation of the dot-fermat number->

15. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when run on a device, performs the method according to any one of claims 1-7.

16. A computer program product, characterized in that the computer program product comprises a computer program which, when run on a device, performs the method according to any one of claims 1-7.

17. A chip comprising at least one processor and a communication interface;

the communication interface is used for providing program instructions or data for the at least one processor;

The at least one processor is configured to execute the program line instructions to implement the method of any one of claims 1-7.