CN116945774A

CN116945774A - Thermal print head

Info

Publication number: CN116945774A
Application number: CN202310453862.9A
Authority: CN
Inventors: 渡边俊夫
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2022-04-26
Filing date: 2023-04-25
Publication date: 2023-10-27
Also published as: JP2023161853A

Abstract

A thermal head (A1) is provided with a head substrate (11) (substrate 1) having a substrate main surface (11 a) facing one of the thickness directions z, an IC chip (5) mounted on the substrate main surface (11 a), a conductive member (wiring layer (3) and cables (61, 62)) which is in electrical communication with the IC chip (5), and A1 st resin member (71) which covers the IC chip (5), wherein the conductive member (wiring layer (3) and cables (61, 62)) contains silver, the 1 st resin member (71) includes A1 st resin layer (711) and a 2 nd resin layer (712), the 1 st resin layer (711) is in contact with the conductive member (wiring layer (3) and cables (61, 62)), the 2 nd resin layer (712) covers the 1 st resin layer (711), and the hygroscopicity of the 1 st resin layer (711) is lower than that of the 2 nd resin layer (712).

Description

Thermal print head

Technical Field

The present invention relates to thermal printheads.

Background

The thermal head includes, for example, a plurality of heat generating portions, a substrate, a driving IC, a conductive member, and a sealing resin (patent document 1). Each of the plurality of heat generating portions is formed on the substrate. The drive IC selectively heats the plurality of heat generating portions by energizing the plurality of heat generating portions. The conduction member is used for conducting the drive IC and the plurality of heating parts. In the thermal head described in patent document 1, the conductive member includes, for example, a wiring layer and a cable. The cable connects the drive IC and the wiring layer. The sealing resin covers the driving ICs. The sealing resin also covers a cable connected to the drive IC and a wiring layer connected to the cable.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2019-34482

Disclosure of Invention

Problems to be solved by the invention

Conventionally, gold has been used as a material for the wiring layer and the cable. Jin Anggui from the viewpoint of reducing the cost of the product, a thermal print head using silver which is relatively inexpensive and has good conductivity has been proposed. However, if the material is simply changed from gold to silver, there is a possibility that ion migration occurs. For example, ion migration may occur in a conductive member (wiring layer or cable) of a portion covered with the sealing resin. This ion migration is a cause of short-circuit failure, and there is a problem that sufficient performance cannot be obtained in practical use.

It is an object of the present invention to provide a thermal print head that is improved over prior art implementations. In particular, in view of the above, an object of the present invention is to provide a thermal head capable of suppressing the generation of ion migration.

Means for solving the problems

A thermal print head (thermal print head) provided by a first aspect of the invention comprises: a substrate having one substrate main surface facing the thickness direction; an IC chip mounted on the main surface of the substrate; a conduction member that is electrically connected to the IC chip; and a 1 st resin member covering the IC chip, wherein the conductive member contains silver, the 1 st resin member includes a 1 st resin layer and a 2 nd resin layer, the 1 st resin layer is in contact with the conductive member, the 2 nd resin layer covers the 1 st resin layer, and the 1 st resin layer has a lower hygroscopicity than the 2 nd resin layer.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the above configuration, the occurrence of ion migration can be suppressed in the thermal head.

Drawings

Fig. 1 is a plan view showing a thermal head according to embodiment 1.

Fig. 2 is a schematic cross-sectional view taken along line II-II of fig. 1.

Fig. 3 is an enlarged view of a portion of fig. 1.

Fig. 4 is an enlarged view of a portion of fig. 2.

Fig. 5 is an enlarged view of a main portion of fig. 4.

Fig. 6 is an enlarged cross-sectional view showing a main part of the thermal head according to embodiment 2.

Fig. 7 is an enlarged cross-sectional view of a main part of a thermal head according to modification 1 of embodiment 2.

Fig. 8 is an enlarged cross-sectional view of a main part of a thermal head according to modification 2 of embodiment 2.

Fig. 9 is an enlarged cross-sectional view showing a main part of the thermal head according to embodiment 3.

Fig. 10 is an enlarged cross-sectional view showing a main part of a thermal head according to embodiment 4.

Fig. 11 is an enlarged cross-sectional view of a main part of a thermal head according to a modification of embodiment 4.

Fig. 12 is a cross-sectional view showing a thermal head according to embodiment 5.

Fig. 13 is an enlarged view of a main portion of fig. 12.

Fig. 14 is a cross-sectional view of a thermal head according to a modification of embodiment 5.

Fig. 15 is an enlarged view of a main portion of fig. 14.

Fig. 16 is an enlarged plan view of a main part of a thermal head according to a modification.

Fig. 17 is an enlarged plan view of a main part of a thermal head according to a modification.

Detailed Description

Preferred embodiments of the thermal head of the present invention are described below with reference to the accompanying drawings. In the following description, the same or similar constituent elements are denoted by the same reference numerals, and repetitive description thereof will be omitted. The terms "1 st", "2 nd", "3 rd" and the like in the present invention are used simply as labels, and are not necessarily ordered with respect to their objects.

In the present invention, "something a is formed in something B" and "something a is formed on (something) B" include "something a is formed directly in something B" and "something a is formed in something B with something in between" something a and something B "as long as it is not particularly prohibited. Similarly, "something a is disposed on something B" and "something a is disposed on (on) something B" include "something a is disposed directly on something B" and "something a is disposed on something B with something in between" something a and something B "as long as it is not particularly prohibited. Similarly, "something a is located (above) something B" includes "something a is in contact with something B, something a is located (above) something B" and "something a is located (above) something B with something in between" something a and something B, as long as it is not particularly prohibited. Further, "see something a overlaps something B in a certain direction" includes "all overlap of something a and something B" and "a part of something a overlaps something B" as long as it is not particularly prohibited.

Fig. 1 to 5 show a thermal head A1 according to embodiment 1. The thermal head A1 includes a substrate 1, a protective layer 2, a wiring layer 3, a resistor layer 4, a plurality of IC chips 5, a connector 59, a plurality of cables 61, 62, and a protective resin 7.

For convenience of explanation, the thickness direction of the substrate 1 will be referred to as "thickness direction z". In the following description, one direction in the thickness direction z is sometimes referred to as an upper direction, and the other direction is sometimes referred to as a lower direction. The terms "upper", "lower", "upper surface" and "lower surface" and the like are used to describe relative positional relationships between the respective components, portions and the like in the thickness direction z, and do not necessarily define relationships with the gravitational direction. Further, the main scanning direction of the thermal head A1 is referred to as "main scanning direction x", and the sub-scanning direction of the thermal head A1 is referred to as "sub-scanning direction y".

The thermal head A1 is incorporated in a thermal printer Pr (see fig. 2) that prints on the print medium P1. The thermal printer Pr includes a thermal print head A1 and a platen roller 91. The platen roller 91 faces the thermal head A1. The printing medium P1 is sandwiched between the thermal head A1 and the platen roller 91, and is transported in the sub-scanning direction y by the platen roller 91. In the following description, a direction in which the printing medium P1 is discharged in the sub-scanning direction y is referred to as "downstream". Examples of the printing medium P1 include thermal paper for producing a receipt sheet and a receipt. In the thermal head A1, a plurality of heat generating portions 41 are formed in the resistor layer 4 by a structure described in detail later. The thermal head A1 selectively drives the plurality of heat generating portions 41 to generate heat, thereby printing on the printing medium P1. Instead of the platen roller 91, a platen made of flat rubber may be used. The platen comprises a portion of cylindrical rubber having a large radius of curvature that is arcuate in cross-section. In the present invention, the term "platen" includes both the platen roller 91 and a flat platen. The thermal printer Pr is not limited to a printer that prints directly on thermal paper, and may be a thermal transfer printer that selectively heats a ribbon to print on a print medium.

The substrate 1 supports other elements of the thermal head A1. The substrate 1 includes a head substrate 11. The head substrate 11 is, for example, a ceramic substrate. The head substrate 11 may be a semiconductor substrate (for example, a silicon substrate) instead of a ceramic substrate. In the thermal head A1, the head substrate 11 is a ceramic substrate, and includes a base material 111 and an enamel layer 112 as shown in fig. 4. The base material 111 is made of, for example, alN (aluminum nitride) or Al ₂ O ₃ (alumina), zirconia, and the like. The thickness of the base material 111 is, for example, 0.6mm to 1.0 mm. The enamel layer 112 covers at least a part of the upper surface (the surface facing upward in the thickness direction z) of the base material 111. The enamel layer 112 may be an entire surface enamel covering the entire surface of the base material 111, a partial enamel covering a part of the base material 111, or a combination of a partial enamel and an entire surface enamel. The enamel layer 112 is made of a glass material such as amorphous glass. The head substrate 11 supports the protective layer 2, the wiring layer 3, the resistor layer 4, and the plurality of IC chips 5. The head substrate 11 (substrate 1) is rectangular in the longitudinal direction in the main scanning direction x in the thickness direction z view.

As shown in fig. 2 and 4, the head substrate 11 has a substrate main surface 11a and a substrate rear surface 11b. The substrate main surface 11a and the substrate rear surface 11b are spaced apart in the thickness direction z. The substrate main surface 11a is the upper surface of the head substrate 11, and faces upward in the thickness direction z. In the present embodiment, the substrate main surface 11a is the upper surface of the enamel layer 112. The substrate back surface 11b is a lower surface of the head substrate 11, and faces downward in the thickness direction z.

The wiring layer 3 constitutes a conduction path for conduction with the resistor layer 4. The wiring layer 3 is formed of a conductive material. In this embodiment, the material of the wiring layer 3 contains silver. The wiring layer 3 may be a single layer or a plurality of layers may be stacked. In the case where the wiring layer 3 is composed of a plurality of layers, the uppermost layer (surface layer) contains silver. As shown in fig. 3 and 4, the wiring layer 3 is formed on the substrate main surface 11 a. The thickness (the dimension in the thickness direction z) of the wiring layer 3 is, for example, 5 μm, but is not limited thereto. The wiring layer 3 includes a common wiring 31, a plurality of individual wirings 32, and a signal wiring 33. The shape and arrangement of each portion (common wiring 31, plurality of individual wirings 32, and signal wiring 33) of the wiring layer 3 are not limited to the configuration shown in fig. 1, 3, and 4, and various configurations are possible.

As shown in fig. 3 and 4, the common wiring 31 includes a plurality of belt-shaped portions 311 and connection portions 312. The plurality of belt portions 311 are each in a belt shape extending in the sub-scanning direction y in the thickness direction z view. The plurality of belt-like portions 311 are arranged at equal intervals in the main scanning direction x. The plurality of belt portions 311 are arranged parallel to each other. The connection portion 312 is disposed downstream of the resistor layer 4 in the sub-scanning direction y, and extends in the main scanning direction x. The connecting portion 312 is connected to each of the plurality of belt portions 311, and connects the plurality of belt portions 311.

The plurality of individual wires 32 are wires for energizing the resistor layer 4, and are opposite in polarity to the common wire 31. As shown in fig. 3, the plurality of individual wires 32 are arranged at intervals in the main scanning direction x. As shown in fig. 3, the plurality of individual wirings 32 include a band portion 321 and a pad portion (pad portion) 322, respectively. The plurality of belt-shaped portions 321 are each in a belt shape extending in the sub-scanning direction y in the thickness direction z view. The plurality of belt-shaped portions 321 are arranged at equal intervals in the main scanning direction x. The plurality of belt-shaped portions 321 are arranged parallel to each other. The plurality of belt-shaped portions 321 are located between 2 belt-shaped portions 311 adjacent to each other in the main scanning direction x, respectively. Thereby, the plurality of belt portions 311 and the plurality of belt portions 321 are alternately arranged in the main scanning direction x. Each of the plurality of pad portions 322 is engaged with a corresponding 1 of the plurality of cables 61. As shown in fig. 4 and 5, the plurality of pad portions 322 are exposed from the protective layer 2, respectively.

The signal wiring 33 constitutes a wiring pattern connected to each IC chip 5 and the connector 59. As shown in fig. 1, the signal wiring 33 is arranged between the plurality of IC chips 5 and the connector 59. The signal wiring 33 includes a plurality of pad portions (pad portions) 331. As can be understood from fig. 4, corresponding 1 of the plurality of cables 62 is engaged at each of the plurality of pad portions 331. As shown in fig. 4 and 5, the plurality of pad portions 331 are exposed from the protective layer 2, respectively.

The resistivity of the resistor layer 4 is higher than the resistivity of the material constituting the wiring layer 3. The resistor layer 4 is made of ruthenium oxide, for example. The resistor layer 4 is formed in a strip shape extending in the main scanning direction x in a thickness direction z view. As shown in fig. 3, the resistor layer 4 crosses the plurality of band portions 311 of the common wiring line 31 and the plurality of band portions 321 of the individual wiring lines 32. As shown in fig. 4, the resistor layer 4 is formed on the substrate main surface 11 a. In the present embodiment, the resistor layer 4 is laminated on the opposite side of the substrate 1 from the plurality of band portions 311 of the common wiring 31 and the plurality of band portions 321 of the individual wiring 32.

As shown in fig. 1 to 4, the resistor layer 4 includes a plurality of heat generating portions 41. Each heat generating portion 41 is a portion of the resistor layer 4 sandwiched between each band 311 and each band 321. Each heat generating portion 41 generates heat by being partially energized by the wiring layer 3. The print dots are formed by the heat generated by each heat generating portion 41. The plurality of heat generating portions 41 are arranged along the main scanning direction x. The greater the number of heat generating portions 41 arranged in the main scanning direction x in a unit length (for example, 1 mm) of the head substrate 11 in the main scanning direction x, the greater the dot density of the thermal head A1.

The protective layer 2 protects the wiring layer 3 and the resistor layer 4. The protective layer 2 covers the wiring layer 3 and the resistor layer 4. In fig. 3, the protective layer 2 is omitted. When the thermal printer Pr is used, the protective layer 2 is pressed against the print medium by the platen roller 91. The protective layer 2 contains amorphous glass, for example. The protective layer 2 may be formed of an amorphous glass single body or may be formed by stacking a lower layer formed of amorphous glass and an upper layer formed of SiAlON or SiC (silicon carbide). SiAlON is in silicon nitride (Si ₃ N ₄ ) Middle synthetic alumina (Al) ₂ O ₃ ) And silicon dioxide (SiO) ₂ ) And the obtained silicon nitride engineering ceramic. The upper layer is formed, for example, by sputtering. The thickness (dimension in the thickness direction z) of the protective layer 2 is not limited at all, and is, for example, 7.5 μm.

The protective layer 2 comprises a plurality of openings 29. Each opening 29 penetrates the protective layer 2 in the thickness direction z. For example, 1 plurality of openings 29 is provided for each of the plurality of IC chips 5. The plurality of openings 29 partially expose the wiring layer 3, respectively. In the example shown in fig. 4 and 5, the pad portions 322 of the individual wirings 32 and the pad portions 331 of the signal wirings 33 are exposed from the plurality of openings 29. The individual wires 32 and the signal wires 33 are not covered by the protective layer 2 except for the areas exposed from the openings 29. As shown in fig. 4 and 5, the substrate main surface 11a is exposed at each opening 29. The plurality of IC chips 5 are bonded to the substrate main surface 11a exposed at the corresponding 1 of the plurality of openings 29.

The plurality of IC chips 5 selectively energize the plurality of individual wires 32 to partially heat the resistor layer 4. The plurality of IC chips 5 are driver ICs, respectively. The plurality of IC chips 5 are arranged upstream of the resistor layer 4 (the plurality of heat generating portions 41) in the sub-scanning direction y.

As shown in fig. 4 and 5, the plurality of IC chips 5 have a chip main surface 5a and a chip back surface 5b, respectively. The chip main surface 5a and the chip back surface 5b are spaced apart in the thickness direction z. The chip main surface 5a is an upper surface of the IC chip 5 and faces upward in the thickness direction z. Thus, the chip main surface 5a faces in the same direction as the substrate main surface 11 a. The chip back surface 5b is a lower surface of the IC chip 5, and faces downward in the thickness direction z. The dimensions of each IC chip 5 along the thickness direction z of the chip main surface 5a and the chip back surface 5b, that is, the thickness of each IC chip 5 is not limited at all, and is, for example, 250 μm to 300 μm.

As shown in fig. 4 and 5, each IC chip 5 has a plurality of upper surface electrodes 51, 52. A plurality of upper surface electrodes 51, 52 are formed on the chip main surface 5 a. As shown in fig. 4 and 5, the corresponding 1 of the plurality of cables 61 is joined to each of the upper surface electrodes 51. Each of the upper surface electrodes 52 is connected to a corresponding 1 of the plurality of wires 62. The upper surface electrodes 51 and 52 may be flush with the chip main surface 5a or may protrude upward in the thickness direction z.

The connector 59 is used to connect the thermal head A1 with the thermal printer Pr. As shown in fig. 1 and 2, the connector 59 is mounted on the head substrate 11 and is electrically connected to the upper surface electrodes 52 of the IC chips 5 via the signal wiring 33 of the wiring layer 3 and the cables 62.

The plurality of cables 61, 62 are each a bonding cable. The material of each cable 61, 62 contains any one of gold, copper, aluminum, silver, and the like. In the present embodiment, the material of each of the cables 61 and 62 contains silver. The wire diameters of the respective cables 61 and 62 are not limited at all, and are, for example, 20 μm.

The plurality of cables 61 connect the upper surface electrodes 51 of the plurality of IC chips 5 to the plurality of individual wirings 32, respectively. As shown in fig. 5, the plurality of cables 61 include an electrode bonding portion 611 and a wire bonding portion 612, respectively. The electrode bonding portion 611 is a portion to be bonded to the upper surface electrode 51 in each cable 61. The wire bonding portion 612 is a portion where the pad portions 322 of the individual wires 32 are bonded to each cable 61.

The plurality of cables 62 connect the upper surface electrodes 52 of the plurality of IC chips 5 to the signal wiring 33, respectively. As shown in fig. 5, the plurality of cables 62 include an electrode bonding portion 621 and a wire bonding portion 622, respectively. The electrode joint 621 is a portion joined to the upper surface electrode 52 in each cable 62. The wire bonding portion 622 is a portion bonded to the pad portion 331 of the signal wire 33 in each cable 62.

As shown in fig. 1, 2, 4, and 5, the protective resin 7 covers the plurality of IC chips 5 and the plurality of cables 61, 62. In the illustrated example, a plurality of IC chips 5 are covered with 1 protective resin 7, or the like, but unlike this example, 1 protective resin 7 may be provided for each of the plurality of IC chips 5. In fig. 3, the protective resin 7 is shown by a phantom line. The protective resin 7 has a 1 st resin member 71 and a 2 nd resin member 72.

The 1 st resin member 71 is connected to each of the plurality of IC chips 5 and the plurality of cables 61 and 62, and directly covers them. The 1 st resin member 71 covers a part of the wiring layer 3 exposed at each opening 29 and a part of the substrate main surface 11 a. The wiring layers 3 shown in the description of the protective resin 7 (the 1 st resin member 71 and the 2 nd resin member 72) are exposed at the portions of the openings 29, for example, the pad portions 322 and the pad portions 331, unless otherwise specified. As shown in fig. 5, the 1 st resin member 71 includes a 1 st resin layer 711, a 2 nd resin layer 712, and a 3 rd resin layer 713.

In the illustrated example, the 1 st resin layer 711, the 3 rd resin layer 713, and the 2 nd resin layer 712 are laminated in this order from the side closer to the substrate main surface 11a in the thickness direction z. The 1 st resin layer 711 is provided between the 2 nd resin layer 712 and the wiring layer 3, and the 1 st resin layer 711 is in contact with the wiring layer 3. The 1 st resin layer 711 is in contact with the pad portion 322 of each individual wire 32 and the pad portion 331 of each signal wire 33, which are portions of the wiring layer 3 exposed from the opening 29 of the protective layer 2. The 2 nd resin layer 712 is a surface layer in the 1 st resin member 71. The 2 nd resin layer 712 covers the 1 st resin layer 711 and the 3 rd resin layer 713. In the example shown in fig. 5, the upper end in the thickness direction z of the 2 nd resin layer 712 protrudes from the upper end in the thickness direction z of the 2 nd resin member 72. The surface of the 2 nd resin layer 712 is smoother than the surface of the 1 st resin layer 711 and the surface of the 2 nd resin layer 712. The 3 rd resin layer 713 is provided between the 1 st resin layer 711 and the 2 nd resin layer 712. The 3 rd resin layer 713 is in contact with the electrode joint 611 of each cable 61 and the electrode joint 621 of each cable 62. The 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 are respectively connected to the 2 nd resin member 72.

In the example shown in fig. 5, the interface 701 between the 1 st resin layer 711 and the 3 rd resin layer 713 is located between the chip main surface 5a and the chip back surface 5b in the thickness direction z. Further, the 2 nd resin layer 712 is located above the chip main surface 5a in the thickness direction z compared to the interface 702 of the 3 rd resin layer 713. A portion of each cable 61 is located above the thickness direction z than a portion of each cable 62 with respect to the interface 702.

The 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 contain a resin material and a glass filler (glass filler), respectively. The resin material is electrically insulating, for example, epoxy resin. In the thermal head A1, the content of the glass filler in the 1 st resin layer 711 is greater than the content of the glass filler in the 2 nd resin layer 712. Thus, the hygroscopicity of the 1 st resin layer 711 is lower than that of the 2 nd resin layer 712. In the thermal head A1, the content of the glass filler in the 3 rd resin layer 713 is smaller than that in the 1 st resin layer 711 and larger than that in the 2 nd resin layer 712. Thus, the hygroscopicity of the 3 rd resin layer 713 is higher than the hygroscopicity of the 1 st resin layer 711 and lower than the hygroscopicity of the 2 nd resin layer 712. As a result, in the thermal head A1, the 1 st resin member 71 is formed by stacking a plurality of resin layers so that the hygroscopicity thereof becomes lower from the upper layer (2 nd resin layer 712) as the surface layer to the lower layer (1 st resin layer 711) close to the substrate main surface 11 a. The hygroscopicity of each of the 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 may be adjusted by the content of a substance other than the glass filler.

The 2 nd resin member 72 is frame-shaped in a plan view. As shown in fig. 1, the 2 nd resin member 72 surrounds the plurality of IC chips 5 in a plan view. The 1 st resin member 71 is filled to the 2 nd resin member 72. The 1 st resin member 71 is located on the inner side of the outer periphery of the 2 nd resin member 72 in the thickness direction z. In this structure, the outer periphery of the 1 st resin member 71 overlaps with the 2 nd resin member 72 in a plan view. The material of the 2 nd resin member 72 is, for example, epoxy resin. The viscosity of the 2 nd resin member 72 is higher than that of the 1 st resin member 71. The thickness (dimension in the thickness direction z) of the 2 nd resin member 72 is, for example, 1.0mm to 1.5mm, but is not limited thereto. In the illustrated example, the thickness of the 2 nd resin member 72 is larger than the thickness of the IC chip 5. In the illustrated example, the 1 st resin member 71 has a thickness larger than that of the 2 nd resin member 72, and the 1 st resin member 71 protrudes upward in the thickness direction z from the 2 nd resin member 72. Unlike this structure, the upper end of the 1 st resin member 71 and the upper end of the 2 nd resin member 72 may be at the same height in the thickness direction z, or the 1 st resin member 71 may be recessed with respect to the 2 nd resin member 72.

The protective resin 7 is formed as follows, for example. First, the 2 nd resin member 72 is coated in a frame shape by a dispenser. Then, the 1 st resin layer 711 is coated in the frame of the 2 nd resin member 72 by a dispenser. Next, the 1 st resin layer 711 and the 2 nd resin member 72 are vacuum defoamed, and then heat-cured. Then, the 3 rd resin layer 713 is coated on the 1 st resin layer 711 using a dispenser. Thereafter, the 3 rd resin layer 713 is vacuum defoamed and then heat-cured. Next, a 2 nd resin layer 712 is coated on the 3 rd resin layer 713 using a dispenser. Then, the 2 nd resin layer 712 was subjected to vacuum defoamation and then heat-cured. Through the above steps, the protective resin 7 including the 1 st resin member 71 and the 2 nd resin member 72 is formed. The vacuum degassing and heating (curing) of the 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 may be performed simultaneously.

The thermal head A1 functions and effects as follows.

The thermal head A1 includes a conductive member that is conductive with the IC chip 5 and A1 st resin member 71 that covers the IC chip 5. In the thermal head A1, the conductive member includes a wiring layer 3. The wiring layer 3 contains silver, and the 1 st resin member 71 includes a1 st resin layer 711 and a 2 nd resin layer 712. The 1 st resin layer 711 is in contact with the wiring layer 3, and the 2 nd resin layer 712 covers the 1 st resin layer 711. Further, the hygroscopicity of the 1 st resin layer 711 is lower than that of the 2 nd resin layer 712. In a configuration different from the thermal head A1, when the 1 st resin member 71 is constituted only by the 2 nd resin layer 712, the wiring layer 3 is in contact with the 2 nd resin layer 712. In this case, ion migration may occur from the wiring layer 3 containing silver in the material. The ion migration is related to the hygroscopicity of the resin (the 2 nd resin layer 712) in contact with the wiring layer 3, and the lower the hygroscopicity of the resin is, the more the occurrence of the resin can be suppressed. Therefore, in the thermal head A1, as described above, the 1 st resin layer 711 having lower hygroscopicity than the 2 nd resin layer 712 is added, and the 1 st resin layer 711 is connected to the wiring layer 3. As a result, the thermal head A1 can suppress ion migration from the wiring layer 3 as a conductive member, compared with the case where the 1 st resin member 71 is constituted only by the 2 nd resin layer 712.

In the thermal head A1, the content of the glass filler in the 1 st resin layer 711 is greater than the content of the glass filler in the 2 nd resin layer 712. With this structure, the hygroscopicity of the 1 st resin layer 711 can be made lower than the hygroscopicity of the 2 nd resin layer 712.

The thermal head A1 further includes cables 61 and 62 as the conductive members. Each of the cables 61, 62 contains silver, and the 1 st resin member 71 further includes a 3 rd resin layer 713. The 3 rd resin layer 713 is in contact with at least a part of each of the cables 61 and 62, and the 2 nd resin layer 712 covers the 3 rd resin layer 713. Further, the hygroscopicity of the 3 rd resin layer 713 is lower than that of the 2 nd resin layer 712. According to this structure, the 3 rd resin layer 713 having lower hygroscopicity than the 2 nd resin layer 712 is in contact with at least a part of each of the cables 61 and 62. As a result, compared with the case where the 1 st resin member 71 is constituted by only the 2 nd resin layer 712, the thermal head A1 can suppress occurrence of ion migration from the respective cables 61, 62 as the conductive members. In particular, in the thermal head A1, the 3 rd resin layer 713 is in contact with the electrode joint 611 of the cable 61 and the electrode joint 621 of the cable 62. The main body of the IC chip 5 is at the ground potential, and the electrode bonding portions 611, 621 are closer to the main body of the IC chip 5 than the other portions of the cables 61, 62. In such a case, ion migration that may occur in the cables 61, 62 is likely to occur in the electrode bonding portions 611, 621. Therefore, in the thermal head A1, by making the 3 rd resin layer 713 cover at least the electrode bonding portions 611, 621 of the respective cables 61, 62, the occurrence of ion migration from the respective cables 61, 62 can be suppressed.

In the thermal head A1, the content of the glass filler in the 3 rd resin layer 713 is greater than the content of the glass filler in the 2 nd resin layer 712. According to this structure, the hygroscopicity of the 3 rd resin layer 713 can be made lower than the hygroscopicity of the 2 nd resin layer 712.

In the thermal head A1, the protective resin 7 has A1 st resin member 71 and a 2 nd resin member 72. The 2 nd resin member 72 is formed in a frame shape in a plan view, and the 1 st resin member 71 is filled inside the 2 nd resin member 72. The 2 nd resin layer 712 of the 1 st resin member 71 is in contact with the 2 nd resin member 72. The 2 nd resin layer 712 has a higher probability of occurrence of ion migration than the 1 st resin layer 711, and has a higher adhesion to the 2 nd resin member 72 than the 1 st resin layer 711. Therefore, the thermal head A1 can suppress the peeling of the 1 st resin member 71 from the substrate 1 (head substrate 11) and the 2 nd resin member 72 by providing the 2 nd resin layer 712 in the region not in contact with the wiring layer 3 and the electrode bonding portions 611, 621. Further, since the 3 rd resin layer 713 has higher adhesion to the 2 nd resin member 72 than the 1 st resin layer 711, peeling of the 1 st resin member 71 from the substrate 1 and the 2 nd resin member 72 can be suppressed.

In the thermal head A1, the viscosity of the 1 st resin member 71 is lower than that of the 2 nd resin member 72. According to this structure, when the 1 st resin member 71 is formed, bubbles are easily detached by vacuum degassing of the 1 st resin member 71. That is, the incorporation of bubbles into the 1 st resin member 71 can be suppressed.

In the thermal head A1, the 2 nd resin layer 712 is a surface layer of the 1 st resin member 71. The surface of the 2 nd resin layer 712 is smoother than the surface of the 1 st resin layer 711. According to this configuration, even if the printing medium P1 touches the surface of the 1 st resin member 71, scratch of the printing medium P1 or the like can be suppressed.

Hereinafter, other embodiments and modifications of the thermal head according to the present invention will be described. The configurations of the respective portions in the respective embodiments and the respective modifications can be combined with each other within a range where no technical contradiction occurs.

Fig. 6 shows a thermal head A2 according to embodiment 2. The thermal head A2 is different from the thermal head A1 in the following points. That is, as shown in fig. 6, the 1 st resin member 71 of the thermal head A2 does not include the 3 rd resin layer 713, and includes the 1 st resin layer 711 and the 2 nd resin layer 712.

In the example shown in fig. 6, the 1 st resin layer 711 is in contact with the pad portion 322 of the independent wiring 32 and the pad portion 331 of the signal wiring 33. Further, the 1 st resin layer 711 is in contact with the electrode joint 611 of the cable 61 and the electrode joint 621 of the cable 62. The 2 nd resin layer 712 is laminated on the 1 st resin layer 711, and is in contact with the 1 st resin layer 711. The 1 st resin layer 711 is located above the chip main surface 5a in the thickness direction z with respect to the interface 703 of the 2 nd resin layer 712. A portion of the cable 61 is located above the thickness direction z than a portion of the cable 62 is at the interface 703.

Fig. 7 shows a thermal head a21 according to modification 1 of embodiment 2. The thermal head a21 is different from the thermal head A2 in the following respects. That is, as shown in fig. 7, the interface 703 between the 1 st resin layer 711 and the 2 nd resin layer 712 is located above the upper ends of the cables 61 and 62 in the thickness direction z.

In the example shown in fig. 7, the entire cables 61 and 62 are in contact with the 1 st resin layer 711. That is, the 1 st resin layer 711 is located above the interface 703 of the 2 nd resin layer 712 in the thickness direction z with respect to the cables 61 and 62.

Fig. 8 shows a thermal head a22 according to modification 2 of embodiment 2. The thermal head a22 is different from each of the thermal heads A2, a21 in comparison as follows. That is, as shown in fig. 8, the 1 st resin layer 711 of the thermal head a22 covers only the vicinity of the wiring layer 3 (the pad portion 322 and the pad portion 331).

In the illustrated example, the 1 st resin layer 711 is in contact with and covers the pad portion 322 of the individual wire 32 and the wire bonding portion 612 bonded to the pad portion 322. The 1 st resin layer 711 is in contact with and covers the pad portion 331 of the signal wiring 33 and the wiring bonding portion 622 bonded to the pad portion 331. Thus, in the present modification, the 1 st resin layer 711 is not in contact with the IC chip 5.

For example, when the voltage of each cable 61, 62 is low and each cable 61, 62 does not contain silver but contains gold, there is a low possibility that ion migration occurs from each electrode bonding portion 611, 621. In such a case, as shown in fig. 8, the 1 st resin layer 711 may be formed only in the vicinity of the wiring layer 3 (the pad portion 322 and the pad portion 331).

The thermal heads A2, a21, a22 according to embodiment 2 and the modification thereof can suppress the occurrence of ion migration from the wiring layer 3 (the pad portion 322 of the individual wiring 32 and the pad portion 331 of the signal wiring 33) as in the thermal head A1. In the thermal heads A2 and a21, the 1 st resin layer 711 is in contact with the electrode bonding portions 611 and 621, so that ion migration from the cables 61 and 62 (the electrode bonding portions 611 and 621) can be suppressed. Further, in the thermal head a22, as shown in fig. 8, the contact area of the 2 nd resin layer 712 with respect to the head substrate 11, the protective layer 2, and the 2 nd resin member 72 is large. Therefore, the 1 st resin member 71 can be further prevented from being peeled off from the head substrate 11, the 2 nd resin member 72, and the like.

Fig. 9 shows a thermal head A3 according to embodiment 3. The thermal head A3 is different from the thermal head A1 in the following respects. That is, as shown in fig. 9, the 1 st resin member 71 of the thermal head A3 is laminated with the 3 rd resin layer 713, the 1 st resin layer 711, and the 2 nd resin layer 712 in this order from the side close to the substrate main surface 11a in the thickness direction z.

In the example shown in fig. 9, the wiring layer 3 (the pad portion 322 and the pad portion 331) is in contact with the 3 rd resin layer 713. Further, the electrode joint 611 of the cable 61 and the electrode joint 621 of the cable 62 are in contact with the 1 st resin layer 711. For example, when the possibility of ion migration is high in the electrode bonding portions 611 and 621 as compared with the wiring layer 3, the 1 st resin layer 711 may be disposed so as to contact the electrode bonding portions 611 and 621 as in the thermal head A3. In addition, in a case where the wiring layer 3 contains no silver, but contains gold, or the like, or in a case where the possibility of occurrence of ion migration from the wiring layer 3 is low, a resin layer of the same material as the 2 nd resin layer 712 may be formed instead of the 3 rd resin layer 713.

In the thermal head A3, as in the thermal head A1, the occurrence of ion migration from the conductive member (the wiring layer 3 and the cables 61 and 62) can be suppressed.

Fig. 10 shows a thermal head A4 according to embodiment 4. The thermal head A4 is different from the thermal head A1 in the following respects. That is, as shown in fig. 10, the protective resin 7 of the thermal head A4 does not include the 2 nd resin member 72, and includes the 1 st resin member 71.

In the example shown in fig. 10, since the protective resin 7 does not include the 2 nd resin member 72, the side surfaces of the 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 are exposed, respectively.

Fig. 11 shows a thermal head a41 according to a modification of embodiment 4. The thermal head a41 is different from the thermal head A4 in the following respects. That is, as shown in fig. 11, in the 1 st resin member 71 of the thermal head a41, the 3 rd resin layer 713 covers the entire 1 st resin layer 711, and the 2 nd resin layer 712 covers the entire 3 rd resin layer 713.

In the example shown in fig. 11, the 1 st resin layer 711 and the 3 rd resin layer 713 are not exposed to the outside. In the example shown in fig. 11, the 1 st resin layer 711, the 2 nd resin layer 712, and the 3 rd resin layer 713 are in contact with the protective layer 2.

The thermal heads A4 and a41 according to embodiment 4 and modifications thereof can suppress the occurrence of ion migration from the conductive members (the wiring layer 3 and the cables 61 and 62) as in the thermal head A1. In the thermal head a41, the 2 nd resin layer 712 and the 3 rd resin layer 713 are in contact with the protective layer 2. As a result, the thermal head a41 can suppress the 1 st resin member 71 from being peeled off from the head substrate 11, compared with the thermal head A4.

In the thermal heads A4 and a41 according to embodiment 4 and the modification thereof, the 1 st resin member 71 may include the 1 st resin layer 711 and the 2 nd resin layer 712, similarly to the thermal head A2.

Fig. 12 and 13 show a thermal head A5 according to embodiment 5. The thermal head A5 is different from the thermal head A1 in the following respects. That is, as shown in fig. 12 and 13, the substrate 1 of the thermal head A5 includes a head substrate 11 and a wiring substrate 12. Further, the thermal head A5 includes a heat radiating member 8.

As shown in fig. 12, the wiring board 12 is arranged upstream in the sub-scanning direction y with respect to the head board 11. The wiring board 12 is, for example, a printed circuit board. As shown in fig. 13, signal wiring 33 is formed on wiring board 12. The signal wiring 33 formed on the wiring board 12 may be a wiring made of other metal material such as copper or gold without containing silver. As shown in fig. 12, the connector 59 is mounted on the wiring board 12. For example, the wiring board 12 has a rectangular shape having the main scanning direction x as a longitudinal direction, and the main scanning direction x of the wiring board 12 has the same size as the main scanning direction x of the head board 11. The wiring board 12 has a board main surface 12a and a board rear surface 12b. The substrate main surface 12a is spaced apart from the substrate rear surface 11b in the thickness direction z. The substrate main surface 12a faces in the same direction as the substrate main surface 11a, and the substrate rear surface 12b faces in the same direction as the substrate rear surface 11 b. The signal wiring 33 is formed on the substrate main surface 11 a.

As shown in fig. 12, the heat sink 8 supports the substrate 1 (the head substrate 11 and the wiring substrate 12). The heat radiation member 8 radiates part of the heat generated by the plurality of heat generating portions 41 to the outside via the head board 11. The heat dissipation member 8 is a block-shaped member made of a metal such as aluminum. The head board 11 and the wiring board 12 are bonded to the surface of the heat dissipation member 8 above the thickness direction z.

As shown in fig. 12 and 13, the protective resin 7 is formed across the head substrate 11 and the wiring substrate 12. As shown in fig. 13, in the 2 nd resin member 72, an end edge extending in the main scanning direction x on the downstream side in the sub-scanning direction y is formed on the head substrate 11, and an end edge extending in the main scanning direction x on the upstream side in the sub-scanning direction y is formed on the wiring substrate 12.

Fig. 14 and 15 show a thermal head a51 according to a modification of embodiment 5. The thermal head a51 is different from the thermal head A5 in the following respects. That is, the IC chip 5 of the thermal head a51 is not mounted on the head substrate 11 but is mounted on the wiring substrate 12.

The thermal heads A5 and a51 according to embodiment 5 and its modifications can suppress the occurrence of ion migration from the conductive members (the wiring layer 3 and the cables 61 and 62) as in the thermal head A1. It is understood from the thermal heads A5 and a51 that the protective resin 7 may be formed on 1 substrate (the head substrate 11) or may be formed across 2 substrates (the head substrate 11 and the wiring substrate 12) in the thermal head of the present invention.

In embodiment 1 to embodiment 4, an example in which each IC chip 5 is connected to the wiring layer 3 via each cable 61, 62 is illustrated, and each IC chip 5 may be flip-chip bonded to the wiring layer 3. In this case, the upper surface electrode 51 is bonded to the pad portion 322 with a conductive bonding material, and the upper surface electrode 52 is bonded to the pad portion 331 with a conductive bonding material, whereby the cables 61, 62 are not required.

In embodiments 1 to 4, the formation range and the plan view shape of the wiring layer 3 formed on the head substrate 11 may be different from those of fig. 3. For example, the structure shown in fig. 16 and 17 may be adopted. Fig. 16 and 17 are enlarged plan views of main parts of a thermal head according to a modification. In fig. 16 and 17, the protective layer 2 is omitted. In the example shown in fig. 16, each band 311 and each band 321 are paired and arranged in the sub-scanning direction y. The plurality of heat generating portions 41 are disposed across the pair of belt portions 311 and 321 in the sub-scanning direction y. In the example shown in fig. 17, the wiring layer 3 includes a plurality of relay wirings 34. Each of the plurality of relay wirings 34 has 2 stripe-shaped portions extending in the sub-scanning direction y. One of the 2 band-shaped portions is opposed to the band-shaped portion 321 in the sub-scanning direction y, and the other of the 2 band-shaped portions is opposed to the band-shaped portion 311 in the sub-scanning direction y. The plurality of heat generating portions 41 respectively span the relay wiring 34 and the belt-shaped portion 321 and the relay wiring 34 and the belt-shaped portion 311. As can be understood from these modifications, in the thermal head of the present invention, the structure of the wiring layer 3 formed on the head substrate 11 is not limited at all.

The thermal head of the present invention is not limited to the above-described embodiments. The specific structure of each part of the thermal head of the present invention can be changed in various ways. For example, the present invention includes embodiments described in the following supplementary notes.

Supplementary note 1. A thermal printhead, comprising:

a substrate having one substrate main surface facing the thickness direction;

an IC chip mounted on the main surface of the substrate;

a conduction member that is electrically connected to the IC chip; and

a 1 st resin member covering the IC chip,

the conductive member may comprise silver and,

the 1 st resin member comprises a 1 st resin layer and a 2 nd resin layer,

the 1 st resin layer is connected to the conductive member,

the 2 nd resin layer covers the 1 st resin layer,

the hygroscopicity of the 1 st resin layer is lower than that of the 2 nd resin layer.

Appendix 2. The thermal printhead of appendix 1, wherein:

the 1 st resin layer and the 2 nd resin layer contain a resin material and a glass filler, respectively,

the content of the glass filler in the 1 st resin layer is larger than the content of the glass filler in the 2 nd resin layer.

The thermal printhead of appendix 3. Appendix 2, wherein:

the resin material is an epoxy resin.

The thermal printhead of any one of supplementary notes 4, wherein:

further comprises a frame-shaped 2 nd resin member surrounding the IC chip as viewed in the thickness direction,

the 1 st resin member is filled with the 2 nd resin member.

The thermal printhead of appendix 5. Appendix 4, wherein:

and a protective film formed on the main surface of the substrate,

the conductive member is exposed from the protective film on the inner side of the 2 nd resin member as viewed in the thickness direction.

The thermal printhead of appendix 6. Appendix 4 or 5, wherein:

the thickness direction dimension of the 2 nd resin member is larger than the thickness direction dimension of the IC chip,

the thickness direction dimension of the 1 st resin member is larger than the thickness direction dimension of the 2 nd resin member.

The thermal printhead of appendix 7. Appendix 4 or 5, wherein:

the 2 nd resin layer is in contact with the 2 nd resin member.

The thermal printhead of any one of supplementary notes 8, wherein:

the conductive member includes a wiring layer formed on the main surface of the substrate.

The thermal printhead of appendix 9. Appendix 8, wherein:

the 1 st resin part further comprises a 3 rd resin layer,

The 3 rd resin layer is provided between the 1 st resin layer and the 2 nd resin layer.

The thermal printhead of appendix 10. Appendix 9, wherein:

the IC chip has a chip main surface and a chip back surface facing opposite sides in the thickness direction,

the 1 st resin layer, the 3 rd resin layer and the 2 nd resin layer are laminated in the thickness direction,

the interface between the 1 st resin layer and the 3 rd resin layer is located between the chip main surface and the chip back surface in the thickness direction.

The thermal printhead of appendix 11. Appendix 10, wherein:

the chip main surface faces in the thickness direction in the same direction as the substrate main surface,

the interface between the 2 nd resin layer and the 3 rd resin layer is located on the one side in the thickness direction of the chip main surface than the chip main surface is in the thickness direction.

Supplementary note 12 the thermal printhead according to any one of supplementary notes 9 to 11, wherein:

the hygroscopicity of the 3 rd resin layer is higher than that of the 1 st resin layer and lower than that of the 2 nd resin layer.

The thermal printhead of any one of supplementary notes 1 to 12, wherein:

the IC chip has a chip main surface facing in the same direction as the substrate main surface in the thickness direction and an upper surface electrode formed on the chip main surface,

The conductive member includes a bonding cable including an electrode bonding portion bonded to the upper surface electrode.

The thermal printhead of appendix 14. Appendix 13, wherein:

the 1 st resin layer is in contact with at least the electrode bonding portion of the bonding cable.

Supplementary note 15 the thermal print head as set forth in supplementary note 14, wherein:

the conductive member includes a wiring layer formed on the main surface of the substrate,

the bonding cable includes a wire bonding portion bonded to the wire layer,

the 1 st resin layer is also in contact with the wire bonding portion.

The thermal printhead of any one of supplementary notes 16, wherein:

further comprises a resistor layer with a plurality of heating parts,

the substrate includes a head substrate for supporting the resistor layer,

the IC chip controls currents flowing to the plurality of heat generating portions.

Supplementary note 17. A thermal printer, comprising:

the thermal print head of any one of supplementary notes 1 to 16; and

a platen facing the thermal print head.

Description of the reference numerals

A1 to A5, a21, a22, a41, a51: thermal print head

1: substrate 11: head substrate

11a: substrate main surface 11b: back of substrate

111: substrate 112: enamel layer (glaze/glaze layer)

12: wiring board 12a: major surface of substrate

12b: substrate back surface 2: protective layer

29: opening 3: wiring layer

31: common wiring 311: band-shaped part

312: the connecting portion 32: independent wiring (individual wiring)

321: band portion 322: pad part (pad/solder part/pad part)

33: signal wiring 331: pad part

34: relay wiring 4: resistor layer

41: heating unit 5: IC chip

5a: chip main surface 5b: chip back

51: upper surface electrode 52: upper surface electrode

59: connectors 61, 62: cable with improved heat dissipation

611. 621: electrode joint portions 612, 622: wire bonding part

7: protective resin 71: 1 st resin part

711: resin 1 st layer 712: 2 nd resin layer

713: 3 rd resin layers 701, 702, 703: interface(s)

72: 2 nd resin member 8: heat dissipation part

91: embossing roller P1: printing medium

Pr: a thermal printer.

Claims

1. A thermal printhead, comprising:

a substrate having one substrate main surface facing the thickness direction;

an IC chip mounted on the main surface of the substrate;

a conductive member that is conductive with the IC chip; and

a 1 st resin member covering the IC chip,

the conductive member may comprise silver and,

the 1 st resin member comprises a 1 st resin layer and a 2 nd resin layer,

The 1 st resin layer is connected with the conducting component,

the 2 nd resin layer covers the 1 st resin layer,

2. The thermal printhead of claim 1, wherein:

the 1 st resin layer and the 2 nd resin layer respectively contain a resin material and a glass filler,

the content of the glass filler in the 1 st resin layer is greater than the content of the glass filler in the 2 nd resin layer.

3. The thermal printhead of claim 2, wherein:

the resin material is an epoxy resin.

4. The thermal printhead of claim 1, wherein:

further comprising a frame-like 2 nd resin member surrounding the IC chip as seen in the thickness direction,

the 1 st resin member is filled with the 2 nd resin member.

5. The thermal printhead of claim 4, wherein:

further comprising a protective film formed on the main surface of the substrate,

6. The thermal printhead of claim 4 or 5, wherein:

the dimension of the 2 nd resin member in the thickness direction is larger than the dimension of the IC chip in the thickness direction,

7. The thermal printhead of claim 4 or 5, wherein:

the 2 nd resin layer is in contact with the 2 nd resin member.

8. The thermal printhead of claim 1, wherein:

9. The thermal printhead of claim 8, wherein:

the 1 st resin part further comprises a 3 rd resin layer,

the 3 rd resin layer is disposed between the 1 st resin layer and the 2 nd resin layer.

10. The thermal printhead of claim 9, wherein:

the IC chip has a chip main surface and a chip back surface facing opposite sides to each other in the thickness direction,

11. The thermal printhead of claim 10, wherein:

12. The thermal printhead of any one of claims 9 to 11, wherein:

13. The thermal printhead of claim 1, wherein:

14. The thermal printhead of claim 13, wherein:

the 1 st resin layer is in contact with at least the electrode bonding portion in the bonding cable.

15. The thermal printhead of claim 14, wherein:

the conductive member includes a wiring layer formed on a main surface of the substrate,

the bonding cable includes a wire bond bonded to the wiring layer,

the 1 st resin layer is also in contact with the wire bonding portion.

16. The thermal printhead of claim 1, wherein:

further comprises a resistor layer with a plurality of heating parts,

the substrate includes a head substrate supporting the resistor layer,

the IC chip controls current flowing to the plurality of heat generating portions.