CN116936362A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
CN116936362A
CN116936362A CN202210360758.0A CN202210360758A CN116936362A CN 116936362 A CN116936362 A CN 116936362A CN 202210360758 A CN202210360758 A CN 202210360758A CN 116936362 A CN116936362 A CN 116936362A
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China
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layer
top electrode
substrate
electrode layer
dielectric
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CN202210360758.0A
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Chinese (zh)
Inventor
于志猛
何世坤
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CETHIK Group Ltd
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CETHIK Group Ltd
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Priority to CN202210360758.0A priority Critical patent/CN116936362A/en
Publication of CN116936362A publication Critical patent/CN116936362A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application provides a manufacturing method of a semiconductor device and the semiconductor device, wherein the method comprises the following steps: firstly, providing a substrate comprising a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer and a top electrode layer, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially laminated, the first dielectric layer comprises a first opening, the first opening exposes part of the storage material layer, and the top electrode layer is positioned in the first opening; then, removing part of the top electrode layer along the first direction, and forming a plurality of prepared top electrodes arranged at intervals by the residual top electrode layer; then, removing part of the prepared top electrodes along a second direction, so that each prepared top electrode forms a plurality of spaced top electrodes, and the second direction is perpendicular to the first direction; and finally, etching the storage material layer by taking the top electrode as a mask so as to expose part of the bottom electrode layer. By changing the removal area, the manufacture of a smaller top electrode is realized, and the size of the semiconductor device is ensured to meet the development requirement.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
The application relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor device and the semiconductor device.
Background
The memory structure of the current memory is that the memory cells are connected with two layers of metal wires through upper and lower electrodes, and along with the increasing requirement of future products on low writing current, the size of the memory cells is necessarily trend to be reduced.
The current MRAM (Magnetic Random Access Memory ) size is around 70nm, and the existing technology can still meet the requirements. However, as the memory cell size continues to shrink, the associated processes are limited, such as photolithography and etch dimensional accuracy, nested alignment accuracy, and metal material fill issues with smaller critical dimensions (CD, critical Dimension), and therefore a fabrication process is needed to ensure that the memory cell size meets the development requirements.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The application provides a manufacturing method of a semiconductor device and the semiconductor device, which are used for solving the problem that the size of a memory cell in the prior art cannot meet the development requirement due to the limitation of a manufacturing process.
According to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially laminated, the first dielectric layer comprises a first opening, part of the storage material layer is exposed through the first opening, and the top electrode layer is positioned in the first opening; removing a part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate; removing portions of the preliminary top electrodes along a second direction, such that each of the preliminary top electrodes forms a plurality of spaced top electrodes, the second direction being perpendicular to a direction of the substrate thickness, the second direction being perpendicular to the first direction; and etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and the rest of the storage material layer forms a storage layer.
Optionally, after etching the memory material layer with the top electrode as a mask, the method further includes: depositing a second preliminary dielectric layer on the exposed surface of the top electrode and on the sides of the storage layer; etching the bottom electrode layer and the second preparation medium layer so that part of the substrate is exposed, the top electrode and the storage layer are not exposed, the rest of the second preparation medium layer forms a second medium layer, and the rest of the bottom electrode layer forms a bottom electrode; forming a third dielectric layer on the exposed surface of the second dielectric layer and on the side surface of the bottom electrode; removing part of the second dielectric layer and part of the third dielectric layer, wherein the rest of the second dielectric layer forms a second dielectric part, and the rest of the third dielectric layer forms a third dielectric part; and forming a first metal wire on the second dielectric part and the third dielectric part, wherein the first metal wire is in contact with the top electrode.
Optionally, etching the bottom electrode layer and the second preliminary dielectric layer includes: the bottom electrode layer and the second preliminary dielectric layer are etched using a self-aligned process.
Optionally, providing a substrate, comprising: providing a substrate; sequentially depositing the bottom electrode layer, the storage material layer and a first preparation medium layer on the substrate; etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer; and filling electrode materials into the first opening to form the top electrode layer.
Optionally, providing a substrate; depositing a fourth dielectric layer on the substrate; etching the fourth dielectric layer to expose part of the substrate to form a second opening, wherein the rest of the fourth dielectric layer forms a fourth dielectric part; filling electrode materials into the second opening to form the bottom electrode layer; sequentially depositing the storage material layer and the first preparation medium layer on the exposed surfaces of the fourth medium part and the bottom electrode layer; etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer; and filling electrode materials into the first opening to form the top electrode layer.
Optionally, providing a substrate, comprising: providing a preliminary substrate, the preliminary substrate comprising a plurality of third openings; and filling a metal material into the third opening to obtain a second metal wire, and forming the substrate.
Optionally, the material of the first dielectric layer comprises SiN, siO 2 And at least one of SiON.
Optionally, etching the bottom electrode layer and the second preliminary dielectric layer includes: and etching the bottom electrode layer and the second preparation medium layer, and cleaning the side surface of the bottom electrode layer and the exposed surface of the second preparation medium layer.
Optionally, removing a portion of the top electrode layer along a first direction includes: removing a portion of the top electrode layer along the first direction by a photolithography and etching process; removing a portion of the preliminary top electrode along a second direction, comprising: and removing part of the prepared top electrode along the second direction through photoetching and etching processes.
According to another aspect of the present application, there is provided a semiconductor device fabricated using the method.
In the method for manufacturing the semiconductor device, firstly, a substrate comprising a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer and a top electrode layer is provided, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially stacked, the first dielectric layer comprises a first opening, part of the storage material layer is exposed through the first opening, and the top electrode layer is positioned in the first opening; then, removing part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate; thereafter, removing portions of the preliminary top electrodes along a second direction, the second direction being perpendicular to a direction of the substrate thickness, the second direction being perpendicular to the first direction, such that each of the preliminary top electrodes forms a plurality of spaced top electrodes; and finally, etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and the rest storage material layer forms a storage layer. Compared with the problem that the size of a memory cell cannot meet the development requirement due to the limitation of a manufacturing process in the prior art, the manufacturing method of the semiconductor device of the application forms a plurality of strip-shaped prepared top electrodes by removing part of the top electrode layer along the first direction, then removes part of the prepared top electrodes along the second direction perpendicular to the first direction, forms a plurality of block-shaped top electrodes, and ensures that the smaller top electrode layer is removed, the smaller the size of the residual prepared top electrode is, the larger the area of the removed prepared top electrode is, the smaller the size of the residual top electrode is, and the lower the requirement on equipment is due to the fact that the larger critical dimension is, the manufacturing method of the semiconductor device can realize the smaller top electrode by changing the removal area under the condition of large line width so as to ensure that the size of the semiconductor device meets the development requirement.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 2 to 14 respectively show structural schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present application after each process step;
fig. 15 to 28 respectively show structural schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present application after each process step;
fig. 29 to 31 respectively show schematic top-view structures of a method for manufacturing a semiconductor device according to an embodiment of the present application, which are obtained after each process step;
fig. 32 to 37 respectively show structural schematic diagrams of a method for manufacturing a semiconductor device according to still another embodiment of the present application, which are obtained after each process step.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a bottom electrode layer; 30. a layer of memory material; 40. a first dielectric layer; 50. a top electrode layer; 60. a second preliminary dielectric layer; 70. a third dielectric layer; 80. a first metal line; 90. a fourth dielectric layer; 100. a second metal line; 101. preparing a substrate; 102. a third opening; 110. a first photoresist layer; 120. a second photoresist layer; 130. a third photoresist layer; 140. a fourth photoresist layer; 150. a fifth dielectric layer; 151. a fifth medium section; 201. a bottom electrode; 202. preparing a bottom electrode; 203. a bottom electrode portion; 301. a storage layer; 401. a first opening; 402. a first preliminary dielectric layer; 501. preparing a top electrode; 502. a top electrode; 601. a second dielectric layer; 602. a second medium section; 701. a third medium section; 901. a second opening; 902. a fourth medium section; 903. a sub-medium portion.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in order to solve the problem that the size of the memory cell in the prior art cannot meet the development requirement due to the limitation of the manufacturing process, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device and a semiconductor device are provided.
According to an embodiment of the present application, a method of manufacturing a semiconductor device is provided.
Fig. 1 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 5, 6, 19 and 20, providing a base, wherein the base includes a substrate 10, a bottom electrode layer 20, a memory material layer 30, a first dielectric layer 40 and a top electrode layer 50, wherein the substrate 10, the bottom electrode layer 20, the memory material layer 30 and the first dielectric layer 40 are sequentially stacked, the first dielectric layer 40 includes a first opening 401, the first opening 401 exposes a portion of the memory material layer 30, and the top electrode layer 50 is located in the first opening 401;
step S102, as shown in fig. 8 and 22, of removing a portion of the top electrode layer 50 along a first direction, wherein the remaining top electrode layer 50 forms a plurality of spaced-apart preliminary top electrodes 501, and the first direction is perpendicular to the thickness direction of the substrate;
step S103, as shown in fig. 10 and 24, removing a portion of the preliminary top electrodes 501 along a second direction, such that each of the preliminary top electrodes 501 forms a plurality of spaced top electrodes 502, the second direction being perpendicular to a direction of the thickness of the substrate, the second direction being perpendicular to the first direction;
in step S104, as shown in fig. 11 and 25, the memory material layer 30 is etched using the top electrode 502 as a mask, so that a portion of the bottom electrode layer 20 is exposed, and the remaining memory material layer 30 forms a memory layer 301.
In the method for manufacturing a semiconductor device, first, a substrate including a substrate, a bottom electrode layer, a memory material layer, a first dielectric layer and a top electrode layer is provided, wherein the substrate, the bottom electrode layer, the memory material layer and the first dielectric layer are sequentially stacked, the first dielectric layer includes a first opening, the first opening exposes a portion of the memory material layer, and the top electrode layer is positioned in the first opening; then, removing part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate; then, removing part of the prepared top electrodes along a second direction, so that each prepared top electrode forms a plurality of spaced top electrodes, wherein the second direction is perpendicular to the thickness direction of the substrate, and the second direction is perpendicular to the first direction; and finally, etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and forming a storage layer by the rest of the storage material layer. Compared with the problem that the size of a memory cell in the prior art cannot meet the development requirement due to the limitation of a manufacturing process, the manufacturing method of the semiconductor device of the application forms a plurality of strip-shaped prepared top electrodes by removing part of the top electrode layer along the first direction, then removes part of the prepared top electrodes along the second direction perpendicular to the first direction, forms a plurality of block-shaped top electrodes, and ensures that the smaller size of the residual prepared top electrode is larger as the area of the removed top electrode is larger, the smaller size of the residual prepared top electrode is smaller as the critical dimension is larger, the process is easier to control, the requirement on equipment is lower as the critical dimension is larger, and the manufacturing method of the semiconductor device can realize the manufacturing of the smaller top electrode by changing the removed area under a large line width so that the size of the residual top electrode meets the actual requirement, thereby ensuring that the size of the semiconductor device meets the development requirement.
Specifically, as shown in fig. 7 and 21, before removing a portion of the top electrode layer 50 along the first direction, a first photoresist layer 110 needs to be formed, where the first photoresist layer 110 may form a coating layer with a fixed pattern on the top electrode layer 50, so as to ensure that a subsequent removed portion of the top electrode layer 50 may be removed according to a set pattern, as shown in fig. 9 and 23, before removing a portion of the preliminary top electrode 501 along the second direction, the second photoresist layer 120 needs to be formed, where the second photoresist layer 120 may form a coating layer with a fixed pattern on the preliminary top electrode 501, so as to ensure that a subsequent removed portion of the preliminary top electrode 501 may be removed according to a set pattern.
In a specific embodiment, as shown in fig. 29, the top electrode layer 50 is located in the first opening of the first dielectric layer 40, as shown in fig. 29 and 30, and is patterned by first photolithography along the first direction, so that a portion of the top electrode layer 50 is removed, a plurality of spaced-apart preliminary top electrodes 501 are formed, a portion of the memory material layer 30 is exposed, and as shown in fig. 30 and 31, is patterned by second photolithography along the second direction perpendicular to the first direction, so that a portion of the preliminary top electrodes 501 is removed, and a plurality of spaced-apart top electrodes 502 are formed. The shape of the top electrode can be changed according to actual requirements, and in order to ensure accurate pattern transfer in the first photoetching patterning process and the second photoetching patterning process, the etching pattern needs to be trimmed in the photoetching process.
According to an embodiment of the present application, after etching the memory material layer using the top electrode as a mask, the method further includes: as shown in fig. 11 and 25, a second preliminary dielectric layer 60 is deposited on the exposed surface of the top electrode 502 and the side surface of the memory layer 301; as shown in fig. 11, 12, 25, and 26, the bottom electrode layer 20 and the second preliminary dielectric layer 60 are etched so that a portion of the substrate is exposed and the top electrode 502 and the memory layer 301 are not exposed, the remaining second preliminary dielectric layer 60 forms a second dielectric layer 601, the remaining bottom electrode layer 20 forms a bottom electrode 201, and the remaining fourth dielectric portion 902 forms a sub-dielectric portion 903 as shown in fig. 26; as shown in fig. 13 and 27, a third dielectric layer 70 is formed on the exposed surface of the second dielectric layer 601 and the side surface of the bottom electrode 201, wherein in fig. 27, the third dielectric layer 70 also covers the side surface of the sub dielectric portion 903; as shown in fig. 13 and 14, or fig. 27 and 28, a part of the second dielectric layer 601 and a part of the third dielectric layer 70 are removed, the remaining second dielectric layer 601 forms a second dielectric portion 602, and the remaining third dielectric layer 70 forms a third dielectric portion 701; a first metal wire 80 is formed on the second dielectric portion 602 and the third dielectric portion 701, and the first metal wire 80 is in contact with the top electrode 502. By depositing a second preliminary dielectric layer on the exposed surface of the top electrode and on the side surface of the storage layer, it is ensured that the top electrode and the storage layer are not damaged during the subsequent etching of the bottom electrode layer, and by forming the third dielectric layer, it is ensured that the first metal wire can be formed in the third dielectric layer, and the contact between the finally formed first metal wire and the top electrode ensures that the performance of the semiconductor device can be achieved.
Specifically, part of the second dielectric layer and the third dielectric layer are removed through chemical mechanical planarization, and then the first metal wire is formed through a Damascus process. In one embodiment, the method can form a 20nm memory cell by adjusting the photolithography process.
According to another embodiment of the present application, etching the bottom electrode layer and the second preliminary dielectric layer includes: and etching the bottom electrode layer and the second preparation medium layer by using a self-alignment process. The bottom electrode layer and the second preparation medium layer are etched by using a self-alignment process, so that the bottom electrode, the top electrode and the storage layer can be on the same line, and the problem of OVL (Over Lay) deviation is avoided.
In a specific embodiment, in order to ensure that the memory material layer is not etched during the removal of a portion of the top electrode layer along the first direction, a predetermined element in the top electrode layer may be monitored during etching, and the etching process may be stopped when the predetermined element in the top electrode layer is not monitored, and similarly, the etching stop position may be controlled by monitoring the predetermined element in the preliminary top electrode layer during the etching of the preliminary top electrode layer along the second direction, and the etching stop position may be controlled by monitoring the predetermined element in the bottom electrode layer during the etching of the bottom electrode layer using a self-aligned process.
According to yet another embodiment of the present application, there is provided a substrate comprising: as shown in fig. 3, a substrate 10 is provided; as shown in fig. 4, the bottom electrode layer 20, the memory material layer 30, and a first preliminary dielectric layer 402 are sequentially deposited on the substrate 10; as shown in fig. 5, the first preliminary dielectric layer 402 is etched to form the first opening 401, and the remaining first preliminary dielectric layer 402 forms the first dielectric layer 40; as shown in fig. 6, an electrode material is filled in the first opening 401 to form the top electrode layer 50. The problem of limited filling capability in the process of directly using metal deposition is avoided by filling electrode material into the first opening with larger size to form the top electrode layer.
In a specific embodiment, the first preliminary dielectric layer is patterned by photolithography, with Pitch-CD as a line width and pitch+cd as a distance, where Pitch is a distance between center positions of two adjacent top electrodes 502, CD is a width of the top electrode 502, the formed pattern is in a shape of a via hole, the first opening is formed, and the electrode material is filled in the first opening, and then chemical mechanical polishing is performed.
Specifically, after the electrode material is filled into the first opening, the top electrode layer is formed through chemical mechanical planarization.
The bottom electrode layer may be formed by a method of forming the top electrode layer, and according to an embodiment of the present application, a substrate is provided, including: as shown in fig. 15, a substrate 10 is provided; depositing a fourth dielectric layer 90 on the substrate 10; as shown in fig. 16, the fourth dielectric layer 90 is etched so that a portion of the substrate 10 is exposed to form a second opening 901, and the remaining fourth dielectric layer 90 forms a fourth dielectric portion 902; as shown in fig. 17, an electrode material is filled in the second opening 901 to form the bottom electrode layer 20; as shown in fig. 18, the memory material layer 30 and the first preliminary dielectric layer 402 are sequentially deposited on the exposed surfaces of the fourth dielectric portion 902 and the bottom electrode layer 20; as shown in fig. 19, the first preliminary dielectric layer 402 is etched to form the first opening 401, and the remaining first preliminary dielectric layer 402 forms the first dielectric layer 40; as shown in fig. 20, an electrode material is filled in the first opening 401 to form the top electrode layer 50. The bottom electrode layer is formed by filling electrode materials into the second opening, and the top electrode layer is formed by filling electrode materials into the first opening with larger size, so that the problem that the filling capacity is limited in the process of directly using metal deposition can be avoided for both the bottom electrode layer and the top electrode layer.
Specifically, after electrode materials are filled in the first opening and the second opening, the top electrode layer and the bottom electrode layer are formed through chemical mechanical planarization.
In a specific embodiment, the height of the top electrode layer can be adjusted according to actual requirements, and the first metal line only needs to be in direct contact with the top electrode, so that the array region through hole in the prior art is avoided.
According to another embodiment of the present application, after filling the electrode material into the second opening to form the bottom electrode layer, the method further includes: as shown in fig. 32, a third photoresist layer 130 is formed, and the third photoresist layer 130 is formed with a cover layer having a fixed pattern on the bottom electrode layer 20; as shown in fig. 33, a plurality of preliminary bottom electrodes 202 are formed on the remaining bottom electrode layer 20 at intervals by removing a portion of the bottom electrode layer 20 along the first direction; as shown in fig. 34, a fourth photoresist layer 140 is formed, and the fourth photoresist layer 140 is formed with a coating layer having a fixed pattern on the preliminary bottom electrode 202; as shown in fig. 35, a portion of the preliminary bottom electrodes 202 is removed along the second direction such that each of the preliminary bottom electrodes 202 forms a plurality of spaced bottom electrode portions 203; as shown in fig. 36, a fifth dielectric layer 150 is formed on the surface of the bottom electrode 203 and the surface of the substrate 10; as shown in fig. 37, the fifth dielectric layer 150 is polished chemically and mechanically until a part of the bottom electrode 203 is exposed, and the remaining fifth dielectric layer 150 forms a fifth dielectric portion 151.
According to still another embodiment of the present application, there is provided a substrate including: as shown in fig. 2, a preliminary substrate 101 including a plurality of third openings 102 is provided; as shown in fig. 3, a metal material is filled in the third opening 102 to obtain a second metal line 100, thereby forming the substrate 10. The second metal line ensures that the performance of the semiconductor device can be achieved.
Specifically, after filling the third opening with a metal material, the second metal line is obtained by chemical mechanical planarization.
According to one embodiment of the present application, the first dielectric layer material comprises SiN, siO 2 And at least one of SiON.
In a specific embodiment, the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer include SiN, siO 2 And SiON, of course, other materials may be used according to actual requirements.
According to another embodiment of the present application, etching the bottom electrode layer and the second preliminary dielectric layer includes: etching the bottom electrode layer and the second preparation medium layer, and cleaning the side surface of the bottom electrode layer and the exposed surface of the second preparation medium layer.
Specifically, the bottom electrode layer and the second preparation medium layer are etched, and meanwhile, the side face of the bottom electrode layer and the exposed surface of the second preparation medium layer are cleaned, so that back sputtering of the side wall of the bottom electrode can be reduced, and the performance of the semiconductor device is guaranteed to be good.
According to still another embodiment of the present application, removing a portion of the top electrode layer along the first direction includes: removing part of the top electrode layer along the first direction through photoetching and etching processes; removing a portion of the preliminary top electrode along a second direction, comprising: and removing part of the prepared top electrode along the second direction through photoetching and etching processes.
According to an embodiment of the present application, there is further provided a semiconductor device fabricated by the above method.
In the semiconductor device of the present application, the plurality of strip-shaped top electrode layers are removed along the first direction to form a plurality of strip-shaped top electrode layers, and the plurality of block-shaped top electrodes are removed along the second direction perpendicular to the first direction to form a plurality of block-shaped top electrodes, wherein the larger the area of the top electrode layer is removed, the smaller the size of the remaining top electrode layers is, the larger the area of the removed top electrode layers is, and the smaller the size of the remaining top electrode is, and the larger the critical dimension is, the easier the process is to control, and the lower the requirements on equipment are, compared with the problem that the size of the memory cell in the prior art cannot meet the development requirements.
Example 1
Step 1: depositing the fourth dielectric layer on the surface of the substrate where the second metal wire is located;
step 2: carrying out photoetching patterning on the fourth dielectric layer, wherein the formed pattern is in a through hole shape, the second opening is formed, and the rest of the fourth dielectric layer forms the fourth dielectric part;
step 3: backfilling the second opening with a metal material, and performing chemical mechanical polishing to form the bottom electrode layer;
step 4: depositing the memory material layer and the first preliminary dielectric layer on the surfaces of the bottom electrode layer and the fourth dielectric portion in sequence;
step 5: carrying out photoetching patterning on the first preparation medium layer, wherein the formed pattern is in a through hole shape, the first opening is formed, and the rest of the first preparation medium layer forms the first medium layer;
step 6: backfilling the metal material of the first opening, and performing chemical mechanical polishing to form the top electrode layer;
step 7: performing a first one-dimensional lithography patterning on the top electrode layer in the first direction to form a plurality of strip-shaped prepared top electrodes;
step 8: performing a second photolithographic patterning in the second direction of the one-dimensional orthogonal direction to form the top electrode in the final metal hard mask block shape;
step 9: etching the storage material layer by taking the top electrode as a hard mask after removing the first dielectric layer by high selectivity etching to form the storage layer, and covering the second preparation dielectric layer;
step 10: etching the bottom electrode layer by a self-alignment process;
step 11: backfilling the third dielectric layer;
step 12: the above first metal lines are formed above, typically using a damascene process to create the upper circuit traces.
Example 2
The main difference between example 2 and example 1 is that example 2 forms a small-sized bottom electrode immediately before example 1.
Step 1: depositing the fourth dielectric layer on the surface of the substrate where the second metal wire is located;
step 2: carrying out photoetching patterning on the fourth dielectric layer, wherein the formed pattern is in a through hole shape, the second opening is formed, and the rest of the fourth dielectric layer forms the fourth dielectric part;
step 3: backfilling the second opening with a metal material, and performing chemical mechanical polishing to form the bottom electrode layer;
step 4: performing a first one-dimensional lithography patterning on the bottom electrode layer in the first direction to form a plurality of strip-shaped prepared bottom electrodes;
step 5: performing a second photolithographic patterning in the second direction of the one-dimensional orthogonal direction to form the bottom electrode portion in the final metal hard mask block shape;
step 6: removing the fourth dielectric part by high selectivity etching, and depositing the fifth dielectric layer;
step 7: the bottom electrode is exposed by chemical mechanical polishing to form a conductive connection.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing a semiconductor device according to the present application, first, a base including a substrate, a bottom electrode layer, a memory material layer, a first dielectric layer, and a top electrode layer is provided, wherein the substrate, the bottom electrode layer, the memory material layer, and the first dielectric layer are sequentially stacked, the first dielectric layer includes a first opening, the first opening exposes a portion of the memory material layer, and the top electrode layer is located in the first opening; then, removing part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate; then, removing part of the prepared top electrodes along a second direction, so that each prepared top electrode forms a plurality of spaced top electrodes, wherein the second direction is perpendicular to the thickness direction of the substrate, and the second direction is perpendicular to the first direction; and finally, etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and forming a storage layer by the rest of the storage material layer. Compared with the problem that the size of a memory cell in the prior art cannot meet the development requirement due to the limitation of a manufacturing process, the manufacturing method of the semiconductor device of the application forms a plurality of strip-shaped prepared top electrodes by removing part of the top electrode layer along the first direction, then removes part of the prepared top electrodes along the second direction perpendicular to the first direction, forms a plurality of block-shaped top electrodes, and ensures that the smaller size of the residual prepared top electrode is larger as the area of the removed top electrode is larger, the smaller size of the residual prepared top electrode is smaller as the critical dimension is larger, the process is easier to control, the requirement on equipment is lower as the critical dimension is larger, and the manufacturing method of the semiconductor device can realize the manufacturing of the smaller top electrode by changing the removed area under a large line width so that the size of the residual top electrode meets the actual requirement, thereby ensuring that the size of the semiconductor device meets the development requirement.
2) In the semiconductor device of the present application, compared with the prior art in which the size of the memory cell cannot meet the development requirement due to the limitation of the fabrication process, the fabrication method of the semiconductor device of the present application forms a plurality of stripe-shaped preliminary top electrodes by removing a portion of the top electrode layer along the first direction, and forms a plurality of block-shaped top electrodes by removing a portion of the preliminary top electrode along the second direction perpendicular to the first direction, wherein the larger the area of the top electrode layer is removed, the smaller the size of the remaining preliminary top electrode is, the larger the area of the removed preliminary top electrode is, the smaller the size of the remaining top electrode is, and the easier the control of the process is due to the larger critical dimension, and the lower the requirement on equipment is, and the fabrication method of the semiconductor device can realize the fabrication of smaller top electrode by changing the removal area under a large line width, so that the size of the remaining top electrode meets the actual requirement, and the size of the semiconductor device is ensured to meet the development requirement.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially laminated, the first dielectric layer comprises a first opening, part of the storage material layer is exposed through the first opening, and the top electrode layer is positioned in the first opening;
removing a part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate;
removing portions of the preliminary top electrodes along a second direction, such that each of the preliminary top electrodes forms a plurality of spaced top electrodes, the second direction being perpendicular to a direction of the substrate thickness, the second direction being perpendicular to the first direction;
and etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and the rest of the storage material layer forms a storage layer.
2. The method of claim 1, wherein after etching the memory material layer with the top electrode as a mask, the method further comprises:
depositing a second preliminary dielectric layer on the exposed surface of the top electrode and on the sides of the storage layer;
etching the bottom electrode layer and the second preparation medium layer so that part of the substrate is exposed, the top electrode and the storage layer are not exposed, the rest of the second preparation medium layer forms a second medium layer, and the rest of the bottom electrode layer forms a bottom electrode;
forming a third dielectric layer on the exposed surface of the second dielectric layer and on the side surface of the bottom electrode;
removing part of the second dielectric layer and part of the third dielectric layer, wherein the rest of the second dielectric layer forms a second dielectric part, and the rest of the third dielectric layer forms a third dielectric part;
and forming a first metal wire on the second dielectric part and the third dielectric part, wherein the first metal wire is in contact with the top electrode.
3. The method of claim 2, wherein etching the bottom electrode layer and the second preliminary dielectric layer comprises:
the bottom electrode layer and the second preliminary dielectric layer are etched using a self-aligned process.
4. The method of claim 1, wherein providing a substrate comprises:
providing a substrate;
sequentially depositing the bottom electrode layer, the storage material layer and a first preparation medium layer on the substrate;
etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer;
and filling electrode materials into the first opening to form the top electrode layer.
5. The method of claim 4, wherein providing a substrate comprises:
providing a substrate;
depositing a fourth dielectric layer on the substrate;
etching the fourth dielectric layer to expose part of the substrate to form a second opening, wherein the rest of the fourth dielectric layer forms a fourth dielectric part;
filling electrode materials into the second opening to form the bottom electrode layer;
sequentially depositing the storage material layer and the first preparation medium layer on the exposed surfaces of the fourth medium part and the bottom electrode layer;
etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer;
and filling electrode materials into the first opening to form the top electrode layer.
6. The method of claim 4, wherein providing a substrate comprises:
providing a preliminary substrate, the preliminary substrate comprising a plurality of third openings;
and filling a metal material into the third opening to obtain a second metal wire, and forming the substrate.
7. The method of any one of claims 1 to 6, wherein the material of the first dielectric layer comprises SiN, siO 2 And at least one of SiON.
8. The method of claim 2, wherein etching the bottom electrode layer and the second preliminary dielectric layer comprises:
and etching the bottom electrode layer and the second preparation medium layer, and cleaning the side surface of the bottom electrode layer and the exposed surface of the second preparation medium layer.
9. The method of claim 1, wherein removing portions of the top electrode layer along a first direction comprises:
removing a portion of the top electrode layer along the first direction by a photolithography and etching process;
removing a portion of the preliminary top electrode along a second direction, comprising:
and removing part of the prepared top electrode along the second direction through photoetching and etching processes.
10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.
CN202210360758.0A 2022-04-07 2022-04-07 Method for manufacturing semiconductor device and semiconductor device Pending CN116936362A (en)

Priority Applications (1)

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CN202210360758.0A CN116936362A (en) 2022-04-07 2022-04-07 Method for manufacturing semiconductor device and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210360758.0A CN116936362A (en) 2022-04-07 2022-04-07 Method for manufacturing semiconductor device and semiconductor device

Publications (1)

Publication Number Publication Date
CN116936362A true CN116936362A (en) 2023-10-24

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