CN116930670A - Chip-level electromagnetic interference conduction injection test method and device - Google Patents
Chip-level electromagnetic interference conduction injection test method and device Download PDFInfo
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- CN116930670A CN116930670A CN202311205204.4A CN202311205204A CN116930670A CN 116930670 A CN116930670 A CN 116930670A CN 202311205204 A CN202311205204 A CN 202311205204A CN 116930670 A CN116930670 A CN 116930670A
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- 238000010998 test method Methods 0.000 title claims abstract description 9
- 238000012360 testing method Methods 0.000 claims abstract description 96
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000011324 bead Substances 0.000 claims description 13
- 238000005070 sampling Methods 0.000 claims description 12
- 230000009466 transformation Effects 0.000 claims description 6
- 230000036039 immunity Effects 0.000 abstract description 6
- 230000008569 process Effects 0.000 description 6
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
- G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
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Abstract
The application provides a chip-level electromagnetic interference conduction injection test method and device, and belongs to the technical field of chip electromagnetic immunity test. The chip-level electromagnetic interference conduction injection testing method comprises the following steps: constructing a testing device; calibrating injection energy and waveform characteristics corresponding to different parameters of the testing device according to the current tested chip; connecting the current chip to be tested to a testing device; injecting electromagnetic interference to the current chip to be tested by adopting a testing device; different injection energy and waveform characteristics of the current chip to be tested and corresponding chip states are recorded. By the technical means, before the tested chip is tested, the energy and waveform characteristics of the tested chip injected when the testing device adopts different parameters are calibrated, then the tested chip is connected to the testing device for testing, finally the state of the tested chip and the corresponding injection energy and waveform characteristics are recorded, a data basis is provided for researching the influence of the interference injection energy and waveform characteristics on chip failure, and the method is wide in application range.
Description
Technical Field
The application relates to the technical field of chip electromagnetic immunity test, in particular to a chip-level electromagnetic interference conduction injection test method and a chip-level electromagnetic interference conduction injection test device.
Background
The chip in the fields of electric power, industry and the like works in a complex electromagnetic environment, is extremely easy to be influenced by the surrounding electromagnetic environment, and is seriously damaged or disabled, so that the reliability of equipment and systems is reduced. In recent years, with the reduction of the size of integrated circuits, chip-level electromagnetic compatibility testing is becoming an indispensable process before chip shipment, and the testing purpose is mainly to observe the working condition of a tested chip under electromagnetic interference, so as to judge the noise immunity level of the chip. In addition, with the complexity of the chip application environment, the anti-electromagnetic interference performance of the chip can determine the working performance of the whole system, so that the electromagnetic immunity test of the chip before application is more and more important.
The existing standard IEC 62215-3 (integrated circuit pulse immunity measurement part 3: asynchronous transient injection method) also specifies on-chip conducted electromagnetic immunity experimental methods, but only simple suggestions for experiments and injection methods are made, and no specification is made for experimental grades and injection energies. In addition, the difference between the injection energy and the waveform characteristics of the interference can generate different failure conditions on the chip, so that the injection energy and the waveform characteristics of the actual interference in the test process are necessary to be clear, and a data basis is provided for researching the influence of the injection energy and the waveform characteristics of the interference on the failure of the chip.
Disclosure of Invention
The application aims to provide a chip-level electromagnetic interference conduction injection test method and device, the method is used for calibrating the energy and waveform characteristics of a chip to be tested injected when different parameters are adopted by a test device in the test process, then the chip to be tested is connected to the test device for testing, finally the state of the chip to be tested and the corresponding injection energy and waveform characteristics are recorded, and a data basis is provided for researching the influence of the interference injection energy and waveform characteristics on chip failure.
In order to achieve the above object, a first aspect of the present application provides a chip-scale electromagnetic interference conduction injection test method, including:
constructing a testing device;
calibrating injection energy and waveform characteristics corresponding to different parameters of the testing device according to the current tested chip;
connecting the current chip to be tested to a testing device;
injecting electromagnetic interference to the current chip to be tested by adopting a testing device;
different injection energy and waveform characteristics of the current chip to be tested and corresponding chip states are recorded.
By the technical means, before the tested chip is tested, the energy and waveform characteristics of the tested chip injected when the testing device adopts different parameters are calibrated, then the tested chip is connected to the testing device for testing, finally the state of the tested chip and the corresponding injection energy and waveform characteristics are recorded, a data basis is provided for researching the influence of the interference injection energy and waveform characteristics on chip failure, and the method is wide in application range.
In an embodiment of the present application, the construction test apparatus includes:
connecting an interference injection port of the tested printed circuit board with an interference injection device by adopting a shielding cable;
connecting decoupling magnetic beads between an input interface and an interference injection port of a tested printed circuit board;
a shielded cable is used to connect the ground of the printed circuit board under test and the ground of the disturbance injection device with minimal circuitry.
The test device constructed by the method can prevent the space radiation field from interfering the injection signal, remove the high-frequency interference signal, realize decoupling of the injection interference signal, shorten the reflux path by the grounding end connected with the minimum loop, and ensure the accuracy of the signal.
In the embodiment of the application, according to different injection energy and waveform characteristics corresponding to the current chip calibration test device to be tested, the method comprises the following steps:
acquiring a signal attenuation curve of a corresponding pin of a current chip to be tested;
measuring first waveforms of the testing device under different parameters at the same sampling frequency;
and carrying out Fourier transformation and inverse transformation according to the signal attenuation curve and the first waveform to calculate injection energy and waveform characteristics corresponding to different parameters. And calculating the injection waveform of the chip pin through the acquired signal attenuation curve and the first waveform with the same frequency, and calibrating the injection waveform of the chip pin.
In the embodiment of the application, the acquisition of the signal attenuation curve of the corresponding pin of the current tested chip comprises the following steps:
a shielded cable is adopted to connect the vector network analyzer and an interference injection port of the tested printed circuit board;
connecting an interference injection port of the tested printed circuit board to a corresponding pin of the tested chip;
and acquiring a signal attenuation curve of a pin corresponding to the tested chip at a first sampling frequency through a vector network analyzer.
Through the technical means, the accurate signal attenuation curve of the corresponding pin of the tested chip can be directly obtained through the vector network analyzer.
In an embodiment of the present application, measuring a first waveform of a testing device under different parameters at the same sampling frequency includes:
connecting an oscilloscope with a load of 50 ohms to a waveform test interface of a tested printed circuit board;
the oscilloscope measures and acquires first waveforms of the testing device under different parameters at a first sampling frequency.
Through the technical means, the first waveform is acquired and used for calculating the injection energy and waveform characteristics of the chip pins.
In the embodiment of the present application, performing fourier transform and inverse transform according to the signal attenuation curve and the first waveform to calculate injection energy and waveform characteristics corresponding to different parameters, including:
performing discrete Fourier transform on the first waveforms under different parameters respectively to obtain full-band waveform characteristics of the injected waveforms under different parameters;
respectively calculating the difference value of the waveform characteristics of the full frequency band of each injection waveform and the signal attenuation curve;
and performing inverse discrete Fourier transform on each difference value to obtain injection energy and waveform characteristics corresponding to different parameters.
In an embodiment of the present application, connecting a current chip to be tested to a testing device includes:
connecting a test pin of a current chip to be tested to an interference injection port on a printed circuit board to be tested;
the grounding pin of the current chip to be tested is connected to the grounding end of the printed circuit board to be tested.
Through the technical means, the current chip to be tested is connected to the testing device, so that the injection energy and the waveform characteristics provided by the testing device in the testing process are effectively injected into the chip to be tested, and the chip testing is realized.
A second aspect of the present application provides a chip-scale electromagnetic interference conduction injection test apparatus, the chip-scale electromagnetic interference conduction injection test apparatus comprising: the device comprises a tested printed circuit board, decoupling magnetic beads, an interference injection device and a shielding cable; the tested printed circuit board is used for installing a tested chip;
the decoupling magnetic beads are connected between an input interface and an interference injection port of the tested printed circuit board, and the interference injection device is connected with the interference injection port of the tested printed circuit board through a shielding cable; the grounding end of the interference injection device is connected with the grounding end of the tested printed circuit board through a shielding cable in a minimum loop.
Through the technical means, the electromagnetic interference conduction injection testing device is provided, the device adopts decoupling magnetic beads to inhibit high-frequency interference signals, realizes decoupling of injection interference signals, can prevent space radiation fields from interfering the injection signals by adopting shielding cables, can shorten a reflux path by connecting a minimum loop with a grounding end, and ensures the accuracy of signals.
In the embodiment of the application, the interference injection device is an external interference source device or an antenna. When the interference injection device is an external interference source device, the interference signal is generated by the external interference source device, and when the interference injection device is an antenna, the interference signal is formed by electromagnetic interference signals in the form of antenna coupling radiation.
In the embodiment of the application, the characteristic impedance of the shielding cable is 50Ω. The characteristic impedance of the shielding cable is the same as that of the interference injection device, so that signal reflection is effectively prevented, and signal integrity is ensured.
According to the technical scheme, the energy and waveform characteristics of the chip to be tested, which are injected when the testing device adopts different parameters, are calibrated in the testing process, then the chip to be tested is connected to the testing device for testing, and finally the state of the chip to be tested and the corresponding injection energy and waveform characteristics are recorded, so that a data basis is provided for researching the influence of the interference injection energy and waveform characteristics on the chip failure.
Additional features and advantages of embodiments of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
FIG. 1 is a flow chart of a method for chip-scale electromagnetic interference (EMI) conduction injection testing according to an embodiment of the present application;
FIG. 2 is a flow chart illustrating calibration of a test device in a chip-scale electromagnetic interference (EMI) conduction injection test method according to an embodiment of the present application;
FIG. 3 is a block diagram of an on-chip EMI conduction injection testing apparatus according to an embodiment of the present application.
Detailed Description
The following describes specific embodiments of the present application in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
Fig. 1 is a flowchart of a chip-scale electromagnetic interference conduction injection test method according to an embodiment of the present application. As shown in fig. 1, the method for testing the chip-level electromagnetic interference conduction injection includes:
s1: in the embodiment of the application, the test device is constructed by the following steps:
the interference injection port of the tested printed circuit board is connected with the interference injection device by adopting the shielding cable, and the shielding cable can prevent the space radiation field from interfering injection signals through the connected cable;
connecting decoupling magnetic beads between an input interface and an interference injection port of a tested printed circuit board; the parameters of the decoupling magnetic beads are selected based on the frequency range of the injection interference, so that high-frequency interference signals can be removed, and decoupling of the injection interference signals can be realized.
The shielding cable is used for connecting the grounding end of the tested printed circuit board and the grounding end of the interference injection device in a minimum loop, and the grounding end connected in the minimum loop can shorten the reflux path, so that the accuracy of signals is ensured.
S2: according to the injection energy and waveform characteristics corresponding to different parameters of the current chip calibration test device to be tested, in the embodiment of the application, as shown in fig. 2, the calibration of different injection energy and waveform characteristics corresponding to the test device is performed in the following manner:
s201: acquiring a signal attenuation curve of a pin corresponding to a current chip to be tested, and in the embodiment of the application, acquiring the signal attenuation curve of the pin corresponding to the current chip to be tested by the following method:
a shielded cable is adopted to connect the vector network analyzer and an interference injection port of the tested printed circuit board; in the embodiment, the two ends of the shielding cable are SMA interfaces, the SMA interfaces are connected with the vector network analyzer and the interference injection port of the tested printed circuit board, the connection mode is simple and quick, and the SMA ports can prevent signal reflection.
The interference injection port of the tested printed circuit board is connected to the corresponding pin of the tested chip, and in the embodiment of the application, the 50 omega microstrip line is adopted to realize that the interference injection port of the tested printed circuit board is connected to the corresponding pin of the tested chip.
And acquiring a signal attenuation curve of a pin corresponding to the tested chip at a first sampling frequency through a vector network analyzer.
Through the technical means, the accurate signal attenuation curve of the corresponding pin of the tested chip can be directly obtained through the vector network analyzer.
S202: the first waveforms of the testing device under different parameters are measured at the same sampling frequency, and in the embodiment of the application, the first waveforms are obtained by the following modes:
connecting an oscilloscope with a load of 50 ohms to a waveform test interface of a tested printed circuit board;
the oscilloscope measures and acquires first waveforms of the testing device under different parameters at a first sampling frequency.
Through the technical means, the first waveform is acquired and used for calculating the injection energy and waveform characteristics of the chip pins. The first waveform is consistent with the sampling frequency of the signal attenuation curve, so that the injection energy and waveform characteristics can be calculated conveniently.
S203: according to the signal attenuation curve and the first waveform, fourier transformation and inverse transformation are carried out to calculate injection energy and waveform characteristics corresponding to different parameters, and in the embodiment of the application, the injection energy and waveform characteristics are calculated by the following modes:
performing discrete Fourier transform on the first waveforms under different parameters respectively to obtain full-band waveform characteristics of the injected waveforms under different parameters;
respectively calculating the difference value of the waveform characteristics of the full frequency band of each injection waveform and the signal attenuation curve;
and performing inverse discrete Fourier transform on each difference value to obtain injection energy and waveform characteristics corresponding to different parameters, wherein the calculation formula is as follows:
；
wherein S11 (ω) is a signal attenuation curve, V in-pcb (t) is a first waveform, V in-pin And (t) is the injection energy and waveform characteristics, and k is the attenuation multiple of the attenuator. And calculating the injection energy and the waveform characteristics through the acquired signal attenuation curve and the first waveform with the same frequency, and calibrating the injection energy and the waveform characteristics corresponding to different parameters of the testing device.
And calculating the injection waveform of the chip pin through the acquired signal attenuation curve and the first waveform with the same frequency, and calibrating the injection waveform of the chip pin.
S3: connecting the current chip to be tested to the testing device, in the embodiment of the application, the connecting the current chip to be tested to the testing device specifically comprises:
connecting a test pin of a current chip to be tested to an interference injection port on a printed circuit board to be tested;
the grounding pin of the current chip to be tested is connected to the grounding end of the printed circuit board to be tested.
Through the technical means, the current chip to be tested is connected to the testing device, so that the injection energy and the waveform characteristics provided by the testing device in the testing process are effectively injected into the chip to be tested, and the chip testing is realized.
S4: injecting electromagnetic interference to the current chip to be tested by adopting a testing device;
s5: different injection energy and waveform characteristics of the current chip to be tested and corresponding chip states are recorded.
By the technical means, before the tested chip is tested, the energy and waveform characteristics of the tested chip injected when the testing device adopts different parameters are calibrated, then the tested chip is connected to the testing device for testing, finally the state of the tested chip and the corresponding injection energy and waveform characteristics are recorded, a data basis is provided for researching the influence of the interference injection energy and waveform characteristics on chip failure, and the method is wide in application range.
A second aspect of the present application provides a chip-scale electromagnetic interference conduction injection test apparatus, as shown in fig. 3, comprising: the device comprises a tested printed circuit board, decoupling magnetic beads, an interference injection device and a shielding cable; the tested printed circuit board is used for installing a tested chip;
the decoupling magnetic beads are connected between an input interface and an interference injection port of the tested printed circuit board, and the interference injection device is connected with the interference injection port of the tested printed circuit board through a shielding cable; the grounding end of the interference injection device is connected with the grounding end of the tested printed circuit board through a shielding cable in a minimum loop.
In the embodiment of the application, the decoupling magnetic beads are connected between the input interface and the interference injection port of the tested printed circuit board by adopting the 50 omega microstrip line, the two ends of the shielding cable are provided with the SMA interfaces, the shielding cable is connected with the interference injection device and the interference injection port of the tested printed circuit board by the SMA interfaces, the connection mode is simple and quick, the SMA ports can prevent signal reflection, and the characteristic impedance of the microstrip line, the SMA interfaces and the shielding cable is 50 omega, so that the integrity of the injected signals is ensured. In the electromagnetic interference conduction injection testing device, the interference injection port in the tested printed circuit board can be directly connected with the corresponding pin of the tested chip, and the integrity of the system signal is ensured by adopting the 50 omega microstrip line and the connector of 50 omega.
Through the technical means, the electromagnetic interference conduction injection testing device is provided, the device adopts decoupling magnetic beads to inhibit high-frequency interference signals, realizes decoupling of injection interference signals, can prevent space radiation fields from interfering the injection signals by adopting shielding cables, can shorten a reflux path by connecting a minimum loop with a grounding end, and ensures the accuracy of signals.
In the embodiment of the application, the interference injection device is an external interference source device or an antenna. When the interference injection device is an external interference source device, the interference signal is generated by an interference source, and when the interference injection device is an antenna, the interference signal is formed by electromagnetic interference signals in the form of antenna coupling radiation.
By the technical mode, the injection energy and the waveform characteristics of the actually injected interference signals can be definitely and practically detected when the chip-level electromagnetic interference test is carried out, the chip states corresponding to the tested chip under the action of different interference signals are recorded through the test, and a data basis is provided for further researching the influence of the injection waveform characteristics and the energy on the chip failure condition.
Those skilled in the art will appreciate that all or part of the steps in a method for implementing the above embodiments may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a single-chip microcomputer, chip or processor (processor) to perform all or part of the steps in a method according to the embodiments of the application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The alternative embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the embodiments of the present application are not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the embodiments of the present application within the scope of the technical concept of the embodiments of the present application, and all the simple modifications belong to the protection scope of the embodiments of the present application. In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the various possible combinations of embodiments of the application are not described in detail.
In addition, any combination of the various embodiments of the present application may be made, so long as it does not deviate from the idea of the embodiments of the present application, and it should also be regarded as what is disclosed in the embodiments of the present application.
Claims (10)
1. The chip-level electromagnetic interference conduction injection test method is characterized by comprising the following steps of:
constructing a testing device;
calibrating injection energy and waveform characteristics corresponding to different parameters of the testing device according to the current tested chip;
connecting the current chip to be tested to a testing device;
injecting electromagnetic interference to the current chip to be tested by adopting a testing device;
different injection energy and waveform characteristics of the current chip to be tested and corresponding chip states are recorded.
2. The method of on-chip electromagnetic interference conduction injection testing as recited in claim 1, wherein said constructing a testing device comprises:
connecting an interference injection port of the tested printed circuit board with an interference injection device by adopting a shielding cable;
connecting decoupling magnetic beads between an input interface and an interference injection port of a tested printed circuit board;
a shielded cable is used to connect the ground of the printed circuit board under test and the ground of the disturbance injection device with minimal circuitry.
3. The method for testing on-chip electromagnetic interference conduction injection according to claim 1, wherein the method comprises the steps of:
acquiring a signal attenuation curve of a corresponding pin of a current chip to be tested;
measuring first waveforms of the testing device under different parameters at the same sampling frequency;
and carrying out Fourier transformation and inverse transformation according to the signal attenuation curve and the first waveform to calculate injection energy and waveform characteristics corresponding to different parameters.
4. The method for testing on-chip electromagnetic interference conduction injection according to claim 3, wherein obtaining a signal attenuation curve of a corresponding pin of a currently tested chip comprises:
a shielded cable is adopted to connect the vector network analyzer and an interference injection port of the tested printed circuit board;
connecting an interference injection port of the tested printed circuit board to a corresponding pin of the tested chip;
and acquiring a signal attenuation curve of a pin corresponding to the tested chip at a first sampling frequency through a vector network analyzer.
5. A method of on-chip electromagnetic interference conduction injection testing as claimed in claim 3, wherein measuring the first waveforms of the testing device at different parameters at the same sampling frequency comprises:
connecting an oscilloscope with a load of 50 ohms to a waveform test interface of a tested printed circuit board;
the oscilloscope measures and acquires first waveforms of the testing device under different parameters at a first sampling frequency.
6. The method of on-chip emi conduction injection testing as set forth in claim 3, wherein performing fourier transform and inverse transform on the signal attenuation curve and the first waveform to calculate injection energy and waveform characteristics corresponding to different parameters, includes:
performing discrete Fourier transform on the first waveforms under different parameters respectively to obtain full-band waveform characteristics of the injected waveforms under different parameters;
respectively calculating the difference value of the waveform characteristics of the full frequency band of each injection waveform and the signal attenuation curve;
and performing inverse discrete Fourier transform on each difference value to obtain injection energy and waveform characteristics corresponding to different parameters.
7. The method of on-chip electromagnetic interference (emi) conduction injection testing as set forth in claim 2, wherein connecting the chip under test to the testing device includes:
connecting a test pin of a current chip to be tested to an interference injection port on a printed circuit board to be tested;
the grounding pin of the current chip to be tested is connected to the grounding end of the printed circuit board to be tested.
8. A chip-scale electromagnetic interference conduction injection testing device, the chip-scale electromagnetic interference conduction injection testing device comprising:
the device comprises a tested printed circuit board, decoupling magnetic beads, an interference injection device and a shielding cable; the tested printed circuit board is used for installing a tested chip;
the decoupling magnetic beads are connected between an input interface and an interference injection port of the tested printed circuit board, and the interference injection device is connected with the interference injection port of the tested printed circuit board through a shielding cable; the grounding end of the interference injection device is connected with the grounding end of the tested printed circuit board through a shielding cable in a minimum loop.
9. The device of claim 8, wherein the device is an external source device or an antenna.
10. The on-chip electromagnetic interference conduction injection test apparatus of claim 8, wherein the shielded cable has a characteristic impedance of 50Ω.
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| CN107506664A (en) * | 2017-08-30 | 2017-12-22 | 北京银联金卡科技有限公司 | Trigger parameter adjustment system and method in chip error injection test |
| CN109406886A (en) * | 2018-11-27 | 2019-03-01 | 中国电力科学研究院有限公司 | One kind being used for printed circuit board transient state suppression common mode electromagnetic interference test method |
| US20210048466A1 (en) * | 2019-08-16 | 2021-02-18 | Shenzhen GOODIX Technology Co., Ltd. | Detection circuit of electromagnetic fault injection and security chip |
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