CN116914061A - Micro LED display assembly and preparation method thereof - Google Patents
Micro LED display assembly and preparation method thereof Download PDFInfo
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- CN116914061A CN116914061A CN202311169648.7A CN202311169648A CN116914061A CN 116914061 A CN116914061 A CN 116914061A CN 202311169648 A CN202311169648 A CN 202311169648A CN 116914061 A CN116914061 A CN 116914061A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000011800 void material Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000000463 material Substances 0.000 description 13
- 238000012545 processing Methods 0.000 description 10
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- 238000010586 diagram Methods 0.000 description 8
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- 230000001788 irregular Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
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- 239000007769 metal material Substances 0.000 description 2
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- 230000003190 augmentative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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Abstract
The invention provides a micro LED display assembly and a preparation method thereof, comprising the following steps: providing a semiconductor light emitting structure to be pixelated, wherein the surface of the semiconductor light emitting structure is divided into a pixel region for forming pixel units and a trench region formed between the pixel units; forming a corresponding first bonding layer on the surface of each pixel unit in the pixel area; providing a driving bottom plate, wherein mutually independent driving electrodes are arranged on the driving bottom plate, and a corresponding second bonding layer is formed on the surface of each driving electrode; bonding the semiconductor light emitting structure to second bonding layers of the driving base plate through the formed first bonding layers based on any position and/or angle, wherein each second bonding layer is in contact with at least one first bonding layer; and removing the growth substrate on the semiconductor light-emitting structure to finish the preparation of the micro LED display assembly. The bonding operation can be directly carried out on the premise of not needing bonding pre-alignment, so that the bonding efficiency is improved, and meanwhile, the working procedures are saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a micro LED display assembly and a preparation method thereof.
Background
The micro LED has the characteristics of high brightness, high efficiency, high reliability and the like, and is the future development direction of micro display technology. The size of the micro-display pixel unit is generally below 20 μm (micrometers), and the light-emitting pixel unit needs to be directly and physically connected with a driving electrode contact for controlling the pixel unit on the driving board, so that the requirements on the device processing technology are high, and particularly, when the size of the pixel unit is further reduced, how to realize the alignment of the pixel unit and the driving electrode contact brings great challenges to the photoetching and bonding (bonding) technology.
Currently, the pixel cell and the driving electrode contact are generally aligned in two ways:
1) And the pixel units are aligned with the driving electrode contacts one by one and then are subjected to bonding operation. The method has high precision requirements on pre-alignment, and has extremely high requirements on bonding materials, flatness, warpage and the like of the bonding surface, so that partial pixel units can not be lightened easily due to alignment deviation or local deviation.
2) Firstly, the luminous material is integrally bonded to the driving plate, then the photoetching and patterning treatment is carried out on the luminous material according to the mark points on the driving plate, and the pixel units are formed on the electrode contacts of the driving plate. The method requires more working procedures after bonding, and can have a certain influence on the performance of the driving plate.
Disclosure of Invention
In order to overcome the defects, the invention provides the micro LED display assembly and the preparation method thereof, which can directly carry out bonding operation on the premise of not needing bonding pre-alignment, improve bonding efficiency and save working procedures.
The technical scheme provided by the invention is as follows:
in one aspect, the invention provides a method for preparing a micro LED display assembly, comprising the following steps:
providing a semiconductor light emitting structure to be pixelated, wherein the semiconductor light emitting structure comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked on the surface of a growth substrate, and the surface of the semiconductor light emitting structure is divided into a pixel region for forming pixel units and a groove region formed between the pixel units;
forming a corresponding first bonding layer on the surface of each pixel unit in the pixel area;
providing a driving bottom plate, wherein mutually independent driving electrodes are arranged on the driving bottom plate, and a corresponding second bonding layer is formed on the surface of each driving electrode;
bonding the semiconductor light emitting structure to second bonding layers of a driving base plate through formed first bonding layers based on any position and/or angle, wherein each second bonding layer is at least in contact with one first bonding layer;
and removing the growth substrate on the semiconductor light-emitting structure to finish the preparation of the micro LED display assembly.
In another aspect, the present invention provides a micro led display assembly comprising:
the driving base plate is provided with mutually independent driving electrodes, and the surfaces of the driving electrodes are provided with corresponding second bonding layers;
the semiconductor light-emitting structure is bonded on the driving bottom plate based on any position and/or angle, and comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked, wherein pixel units are formed on the semiconductor light-emitting structure, and corresponding first bonding layers are formed on the surfaces of the pixel units; each second bonding layer is in contact with at least one first bonding layer.
According to the micro LED display assembly and the preparation method thereof, pre-alignment is not needed in the bonding process, the semiconductor light-emitting structure is bonded on the driving base plate based on any position and/or angle, at least one pixel unit can be driven by one driving electrode on the driving base plate, the same pixel unit cannot be driven by two driving electrodes at the same time, the working procedure in the bonding process is saved, and the pixel unit with higher pixel density can be prepared on the semiconductor light-emitting structure. After bonding is completed, the surface of the semiconductor light-emitting structure of the growth substrate is removed, so that the semiconductor light-emitting structure is smooth, further optical design is facilitated, and the semiconductor light-emitting structure is convenient to apply.
Drawings
FIG. 1 is a schematic view of a semiconductor light emitting structure formed on a surface of a growth substrate according to the present invention;
FIG. 2 is a schematic diagram of a pixel unit formed by etching a trench region along a second semiconductor layer until a first semiconductor layer is formed;
FIG. 3 is a schematic diagram illustrating formation of a first bonding layer in an example of forming a pixel unit using the method of FIG. 2 according to the present invention;
FIG. 4 is a schematic diagram of a driving chassis in accordance with the present invention;
FIG. 5 is a schematic diagram of an embodiment of a second bonding layer configuration according to the present invention;
FIG. 6 is a schematic diagram of another embodiment of a second bonding layer configuration according to the present invention;
FIG. 7 is a schematic diagram of a bonded structure in an example of the pixel unit formed by the method of FIG. 2;
FIG. 8 is a schematic view of a circular first bonding layer according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a square second bonding layer according to an embodiment of the present invention;
FIG. 10 is a schematic view of a structure of the first bonding layer shown in FIG. 8 and the second bonding layer shown in FIG. 9 after bonding;
FIG. 11 is a schematic view of another structure of the first bonding layer shown in FIG. 8 and the second bonding layer shown in FIG. 9 after bonding;
FIG. 12 is a schematic view of another structure of the first bonding layer shown in FIG. 8 and the second bonding layer shown in FIG. 9 after bonding;
FIG. 13 is a schematic diagram of a structure of a first bonding layer and a second bonding layer bonded according to another embodiment of the present invention;
FIG. 14 is a schematic view of another embodiment of the present invention after bonding the first bonding layer and the second bonding layer;
fig. 15 is a schematic view of another embodiment of the present invention after the first bonding layer and the second bonding layer are bonded.
Reference numerals:
10-growth substrate, 20-semiconductor light emitting structure, 21-first semiconductor layer, 22-second semiconductor layer, 30-trench, 40-pixel unit, 50-first bonding layer, 60-driving bottom plate, 70-second bonding layer.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
The preparation method of the micro LED display assembly provided by the invention comprises the following steps:
s10, providing a semiconductor light emitting structure 20 to be pixelated, wherein the semiconductor light emitting structure 20 includes a first semiconductor layer 21, a light emitting layer (not shown) and a second semiconductor layer 22 sequentially stacked on a surface of a growth substrate 10, and the semiconductor light emitting structure surface is divided into a pixel region for forming pixel units and a trench region formed between the pixel units, as shown in fig. 1.
The thickness of the semiconductor light emitting structure 20 is 1 μm to 10 μm, and can be prepared by selecting binary, ternary and quaternary materials of various wave bands, which are not particularly limited herein, and can be selected according to practical applications. The types of the first semiconductor layer 21 and the second semiconductor layer 22 may also be determined according to application requirements, such as an example in which the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer. The growth substrate may be a sapphire substrate, a silicon substrate, a Cu substrate, or the like.
The division of the pixel area and the groove area is also determined according to application requirements, groove positions are arranged among different pixel units, the pixel area is formed at the position of each pixel unit, and the groove area is formed at the position of each groove.
S20, forming a corresponding first bonding layer on the surface of each pixel unit in the pixel area.
For the subsequent bonding operation, a first bonding layer is formed on the surface of the pixel units, and before that, the pixel units on the semiconductor light-emitting structure are required to be insulated from each other, so that the current between the pixel units in the subsequent operation is ensured not to be laterally expanded.
In practical applications, if the second semiconductor layer in the semiconductor light emitting structure material has very high resistivity and difficult current lateral expansion, in this embodiment, only a corresponding ohmic contact electrode and a bonding layer (corresponding to the first bonding layer) are required to be formed on the surface of the pixel region according to the division of the pixel region and the trench region, where the ohmic contact electrode may be made of a material such as ITO, pt, ag, ni, and the bonding layer may be made of a conductive metal such as Sn, in, cu, au, or an alloy thereof. Before forming the first bonding layer, shallow grooves can be formed in the groove area of the surface of the semiconductor light-emitting structure in a photoetching or nano-imprinting mode so as to define the pixel area. The shape of the first bonding layer on the surface of the pixel unit can be determined according to requirements, for example, the first bonding layer can be in a regular shape such as a round shape, a square shape and the like; the size of the pixel units is generally 0.1-10 μm, and the width of the grooves between the pixel units is 0.01-5 μm. And the pixel cells formed are typically regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, a P-type ohmic contact layer and a bonding layer are formed directly along the surface of the P-type GaN layer.
In another embodiment, processing the trench region to obtain a pixel cell includes: etching the trench region along the second semiconductor layer 22 until the first semiconductor layer 21, forming trenches 30 between the pixel cells, so that the complete semiconductor light emitting structure is partitioned into independent micro cells, forming pixel cells 40, as shown in fig. 2; then, a corresponding ohmic contact electrode and bonding layer (corresponding to the first bonding layer 50 described above) are formed on the surface of the pixel unit 40, as shown in fig. 3. The ohmic contact electrode can be made of ITO, pt, ag, ni and the like, and the bonding layer can be made of Sn, in, cu, au and other conductive metals or alloys thereof. Prior to etching, shallow trenches may be formed in the trench regions of the semiconductor light emitting structure surface by means of photolithography or nanoimprinting to subsequently etch along the shallow trenches. The shape of the first bonding layer 50 on the surface of the pixel unit can be determined according to requirements, for example, the shape can be a regular shape such as a circle, a square, etc.; the size of the pixel units is generally 0.1 μm to 10 μm, the width of the trench 30 between the pixel units is 0.01 μm to 5 μm, and the depth of the trench 30 is 0.1 μm to 1 μm. And the formed pixel cells 40 are generally regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, the P-type GaN layer is etched until the N-type GaN layer forms a corresponding pixel cell, and then a P-type ohmic contact layer and a bonding layer are formed on the surface of the pixel cell.
In this embodiment, the angle between the sidewall of the pixel unit and the bottom of the trench region is greater than or equal to 90 °. When the sidewall of the pixel unit and the trench regionThe included angle between the bottoms is more than 90 degrees, the pixel units are in a positive trapezoid structure after etching is completed, and then the pixel units are turned over for 180 degrees and bonded to the driving bottom plate, and then the pixel units are in an inverted trapezoid structure on the driving bottom plate. On the basis of the above, the trench region is etched along the second semiconductor layer until reaching the first semiconductor layer, after the pixel unit is formed, a metal reflective layer is further formed on the sidewall of the pixel unit, and the trench region is filled with an insulating material (not exceeding the upper surface of the first bonding layer). The reflective layer material and the insulating material may be SiO 2 、SiN、Al 2 O 3 、Ti 2 O 3 And the like. Compared with the bonded pixel units which have a positive trapezoid or a vertical structure, the combination of the pixel units with the inverted trapezoid structure and the reflecting layer can improve the light emitting efficiency of the display assembly to a certain extent.
In another embodiment, processing the trench region to obtain a pixel unit includes: ion implantation (e.g., argon ion implantation, oxygen ion implantation, etc.) is performed along the trench region to form a pixel cell. In this process, the isolation trench is implanted along the trench region on the surface of the semiconductor light emitting structure, so that the complete semiconductor light emitting structure is partitioned into independent micro units, the resistivity between the second semiconductor layers below each pixel unit is improved, the current cannot be laterally spread between the second semiconductors, the purpose that each pixel unit can be driven is achieved, then a corresponding ohmic contact electrode and a bonding layer (corresponding to the first bonding layer) are formed on the surface of the pixel unit, the ohmic contact electrode can be made of ITO, pt, ag, ni and other materials, and the bonding layer can be made of Sn, in, cu, au and other conductive metals or their alloys. Prior to ion implantation, shallow trenches may be formed in the trench regions of the semiconductor light emitting structure surface by photolithography or nanoimprint to subsequently perform ion implantation and formation of the first bonding layer along the shallow trenches. The shape of the first bonding layer on the surface of the pixel unit can be determined according to requirements, for example, the first bonding layer can be in a regular shape such as a round shape, a square shape and the like; the size of the pixel units is generally 0.1-10 μm, and the width of the grooves between the pixel units is 0.01-5 μm. And the pixel cells formed are typically regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, an ion implantation operation is performed along the trench region of the P-type GaN layer, and then a P-type ohmic contact layer and a bonding layer are formed on the surface of the pixel unit.
S30, providing a driving bottom plate, wherein mutually independent driving electrodes are arranged on the driving bottom plate, and corresponding second bonding layers are formed on the surfaces of the driving electrodes, as shown in fig. 4.
The driving substrate 60 has a conductive circuit formed on the surface thereof for driving the pixel unit, and driving electrodes disposed thereon and independently of each other, and a second bonding layer 70 is formed on the surface of each driving electrode, wherein the driving electrodes may be made of a metal material such as Cu, al, au, W, and the second bonding layer 70 may be made of a conductive metal such as Sn, in, cu, au, or an alloy thereof.
In order to achieve the purpose that each second bonding layer can be at least contacted with one first bonding layer after bonding based on any position and/or angle, the configuration rules comprise: a second bonding layer can contact at least one first bonding layer when covering the surface of the largest gap area (formed by a plurality of first bonding layers) at any position and/or angle, and the gap between the adjacent second bonding layers is larger than the maximum value of the external dimension of the first bonding layer.
In practical applications, the pixel units are generally arranged regularly, and the largest void area is determined by the first bonding layers 50 on the surfaces of the 4 pixel units adjacent to each other in front, back, left and right, so that, in order to ensure that the second bonding layer 70 does not fall into the largest void area when bonding at any position and/or angle, the shape and size of the second bonding layer 70 are configured based on the largest void, theoretically, the second bonding layer 70 may be any shape and size, or even may be an irregular shape, so long as it covers the surface of the largest void area and ensures that at least one second bonding layer 50 contacts. In other embodiments, even if the arrangement of the pixel units is irregular, the maximum void area between the pixel units is determined based on the arrangement manner, and the outer shape and size of the second bonding layer 70 are configured based on the maximum void area, so that the object of the invention can be achieved. It should be understood that the above-described second bonding layer covering the surface of the largest void region does not mean that the second bonding layer completely covers the largest void region, and that the second bonding layer can be in contact with at least one first bonding layer at any position/angle when partially covered can achieve the object of the invention.
In one example, assuming that the first bonding layer 50 has a circular shape, the second bonding layer has a square shape and is uniformly arranged, there are cases where a1 and a2 are tangential to 4 circles at the same time as shown in fig. 5, and in the case of a1, the purpose of the invention can be achieved by only defining that the short side edge of the second bonding layer is longer than the minimum distance between the two first bonding layers diagonally; in the case of a2, it is sufficient to define that the short side length of the second bonding layer is larger on the basis of the square size (the long side length is equal, the short side length is slightly larger, or both sides are slightly larger).
In one example, assuming that the first bonding layer 50 has a square shape and the second bonding layer has a square shape, and the second bonding layers are uniformly arranged, there are cases where a3 and a4 are simultaneously connected to 4 squares as shown in fig. 6, and in the case of a3, the purpose of the invention can be achieved by only defining that the short side edge of the second bonding layer is longer than the minimum distance between the two first bonding layers in opposite angles; in the case of a4, if the second bonding layer is defined based on the size of the square, the object of the invention may not be achieved.
Based on two examples, it can be seen that the object of the invention can be achieved under the limiting condition that the short side of the smallest circumscribed rectangle of the second bonding layer is longer than the smallest distance between the diagonal first bonding layers if the shape of the second bonding layer is a convex structure. However, it should be understood that the above limitation does not necessarily achieve the object of the invention when the second bonding layer has a concave configuration in its outer shape. Therefore, the configuration of the second bonding layer in the above two applications is only given as an example, and parameters such as arrangement, size and shape of the second bonding layer in practical application need to be determined according to the condition of the first bonding layer, whether the pixel units are uniformly arranged or not, whether the first bonding layer is in a regular shape or not, and the second bonding layer is configured based on the first bonding layer, so that the preset condition is satisfied.
In addition, in order to avoid the same pixel unit being driven by two driving electrodes at the same time, the driving electrodes are damaged due to the short circuit phenomenon, it is further defined that the gap between the adjacent second bonding layers 70 is larger than the maximum value of the external dimensions of the first bonding layers 50, that is, at least one first bonding layer 50 can be accommodated between the gaps between the adjacent second bonding layers 70. The external dimension specifically refers to a dimension value on the external shape of the first bonding layer, and the specific value is determined by the shape of the first bonding layer: assuming that the first bonding layer is circular, its external dimension is its diameter, where the gap between the second bonding layers is larger than the diameter of the first bonding layer; assuming that the first bonding layer is rectangular, the maximum value of the external dimension is the long side length of the first bonding layer, and the gap between the second bonding layers is larger than the long side length of the first bonding layer; assuming that the first bonding layer is a regular hexagon, the maximum of its outer dimensions is the distance between the opposite vertices, and so on.
S40, bonding the semiconductor light emitting structure to the driving substrate based on any position and/or angle, each of the second bonding layers 70 is in contact with at least one of the first bonding layers 50.
In the bonding process, the semiconductor light emitting structure formed with the pixel unit is directly bonded to the driving bottom plate without performing pre-alignment operation, and based on the design of the first bonding layer 50 and the second bonding layers 70, each second bonding layer 70 is ensured to be at least in contact with one first bonding layer 50, and the same pixel unit is not driven by two driving electrodes at the same time. In the embodiment in which the grooves as shown in fig. 2 are formed between the pixel units, the bonded structure is as shown in fig. 7.
S50, removing the growth substrate on the semiconductor light-emitting structure, and completing preparation of the micro LED display assembly.
The method for removing the growth substrate is applied by adopting a corresponding removing method (laser peeling, dry etching, wet etching, etc.) according to the selected growth substrate, and in an example, when a silicon substrate is used as the growth substrate, after bonding the semiconductor light-emitting structure to the surface of the supporting substrate, the silicon substrate is peeled off by adopting laser.
In practical application, the micro LED display assembly prepared by the method can be used for rapidly detecting the performances of the driving electrode and the pixel unit and determining the defective driving electrode and pixel unit.
Corresponding to the preparation method, the invention also provides a micro LED display assembly, which comprises: the driving base plate is provided with mutually independent driving electrodes, and the surfaces of the driving electrodes are provided with corresponding second bonding layers; the semiconductor light-emitting structure comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked, pixel units are formed on the semiconductor light-emitting structure, and corresponding first bonding layers are formed on the surfaces of the pixel units; each second bonding layer is in contact with at least one first bonding layer.
In the micro LED display component, the thickness of the semiconductor light-emitting structure is 1-10 mu m, and the semiconductor light-emitting structure can be prepared from binary, ternary and quaternary materials with various wave bands, and the semiconductor light-emitting structure is not particularly limited and can be selected according to practical application. The types of the first semiconductor layer and the second semiconductor layer may also be determined according to application requirements, for example, in an example, the first semiconductor layer is an N-type GaN layer, and the second semiconductor layer is a P-type GaN layer.
The second semiconductor layers of each pixel unit are insulated from each other, and can be realized in various ways, including: a groove etched from the second semiconductor layer to the first semiconductor layer is formed between the pixel units in the semiconductor light-emitting structure, preset ions are injected into the second semiconductor layer of each pixel unit, and a high-resistivity semiconductor material is adopted.
In the embodiment in which the trenches etched from the second semiconductor layer to the first semiconductor layer are formed between the pixel cells in the semiconductor light emitting structure, the trench region is etched along the second semiconductor layer 22 to the first semiconductor layer 21, so that the complete semiconductor light emitting structure is partitioned into independent micro cells to form the pixel cells 40, as shown in fig. 2; then, a corresponding ohmic contact electrode and bonding layer (corresponding to the first bonding layer 50 described above) are formed on the surface of the pixel unit 40, as shown in fig. 3. The ohmic contact electrode can be made of ITO, pt, ag, ni and the like, and the bonding layer can be made of Sn, in, cu, au and other conductive metals or alloys thereof. Prior to etching, shallow trenches may be formed in the trench regions of the semiconductor light emitting structure surface by means of photolithography or nanoimprinting to subsequently etch along the shallow trenches. The shape of the first bonding layer 50 on the surface of the pixel unit can be determined according to requirements, for example, the shape can be a regular shape such as a circle, a square, etc.; the size of the pixel units is generally 0.1 μm to 10 μm, the width of the trench 30 between the pixel units is 0.01 μm to 5 μm, and the depth of the trench 30 is 0.1 μm to 1 μm. And the formed pixel cells 40 are generally regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, the P-type GaN layer is etched until the N-type GaN layer forms a corresponding pixel cell, and then a P-type ohmic contact layer and a bonding layer are formed on the surface of the pixel cell.
In this embodiment, the angle between the sidewall of the pixel unit and the bottom of the trench region is greater than or equal to 90 °. When the included angle between the side wall of the pixel unit and the bottom of the groove area is more than 90 degrees, the pixel unit presents a positive trapezoid structure after etching is completed, and then is turned over for 180 degrees to be bonded to the driving bottom plate, and the pixel unit presents an inverted trapezoid structure on the driving bottom plate. On the basis of the above, the trench region is etched along the second semiconductor layer until reaching the first semiconductor layer, after the pixel unit is formed, a metal reflective layer is further formed on the sidewall of the pixel unit, and the trench region is filled with an insulating material (not exceeding the upper surface of the first bonding layer). The reflective layer material and the insulating material may be SiO 2 、SiN、Al 2 O 3 、Ti 2 O 3 And the like. Therefore, the light emitting efficiency of the display component can be improved to a certain extent by combining the pixel units with the inverted trapezoid structures with the reflecting layer.
In an embodiment in which a predetermined ion is implanted into the second semiconductor layer of each pixel cell, the processing of the trench region includes: ion implantation (e.g., argon ion implantation, oxygen ion implantation, etc.) is performed along the trench region to form a pixel cell. In this process, the isolation trench is implanted along the trench region on the surface of the semiconductor light emitting structure, so that the complete semiconductor light emitting structure is partitioned into independent micro units, the resistivity between the second semiconductor layers below each pixel unit is improved, the current cannot be laterally spread between the second semiconductors, the purpose that each pixel unit can be driven is achieved, then a corresponding ohmic contact electrode and a bonding layer (corresponding to the first bonding layer) are formed on the surface of the pixel unit, the ohmic contact electrode can be made of ITO, pt, ag, ni and other materials, and the bonding layer can be made of Sn, in, cu, au and other conductive metals or their alloys. Prior to ion implantation, shallow trenches may be formed in the trench regions of the semiconductor light emitting structure surface by photolithography or nanoimprint to subsequently perform ion implantation and formation of the first bonding layer along the shallow trenches. The shape of the first bonding layer on the surface of the pixel unit can be determined according to requirements, for example, the first bonding layer can be in a regular shape such as a round shape, a square shape and the like; the size of the pixel units is generally 0.1-10 μm, and the width of the grooves between the pixel units is 0.01-5 μm. And the pixel cells formed are typically regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, an ion implantation operation is performed along the trench region of the P-type GaN layer, and then a P-type ohmic contact layer and a bonding layer are formed on the surface of the pixel unit.
In the embodiment using the high resistivity semiconductor material, the ohmic contact electrode and the bonding layer (corresponding to the first bonding layer) may be formed directly on the surface of the pixel region, and the ohmic contact electrode may be made of ITO, pt, ag, ni, and the bonding layer may be made of Sn, in, cu, au or other conductive metal or its alloy. Before forming the first bonding layer, shallow grooves can be formed in the groove area of the surface of the semiconductor light-emitting structure in a photoetching or nano-imprinting mode so as to define the pixel area. The shape of the first bonding layer on the surface of the pixel unit can be determined according to requirements, for example, the first bonding layer can be in a regular shape such as a round shape, a square shape and the like; the size of the pixel units is generally 0.1-10 μm, and the width of the grooves between the pixel units is 0.01-5 μm. And the pixel cells formed are typically regularly arranged on the growth substrate and the first semiconductor layer for subsequent processing. In the example where the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer, a P-type ohmic contact layer and a bonding layer are formed along the surface of the P-type GaN layer.
The surface of the driving bottom plate is provided with a conductive circuit for driving the pixel unit, the driving bottom plate is provided with mutually independent driving electrodes, the surfaces of the driving electrodes are respectively provided with a second bonding layer, the driving electrodes can be made of metal materials such as Cu, al, au, W, and the second bonding layers can be made of conductive metals such as Sn, in, cu, au or the like or alloys thereof.
In order to achieve the purpose that each second bonding layer can be at least contacted with one first bonding layer after bonding based on any position and/or angle, the configuration rules comprise: a second bonding layer can contact at least one first bonding layer when covering the surface of the largest gap area (formed by a plurality of first bonding layers) at any position and/or angle, and the gap between the adjacent second bonding layers is larger than the maximum value of the external dimension of the first bonding layer.
In practical applications, the pixel units are generally arranged regularly, and the largest void area is determined by the first bonding layers 50 on the surfaces of the 4 pixel units adjacent to each other in front, back, left and right, so that, in order to ensure that the second bonding layer 70 does not fall into the largest void area when bonding at any position and/or angle, the shape and size of the second bonding layer 70 are configured based on the largest void, theoretically, the second bonding layer 70 may be any shape and size, or even may be an irregular shape, so long as it covers the surface of the largest void area and ensures that at least one second bonding layer 50 contacts. In other embodiments, even if the arrangement of the pixel units is irregular, the maximum void area between the pixel units is determined based on the arrangement manner, and the outer shape and size of the second bonding layer 70 are configured based on the maximum void area, so that the object of the invention can be achieved. It should be understood that the above-described second bonding layer covering the surface of the largest void region does not mean that the second bonding layer completely covers the largest void region, and that the second bonding layer can be in contact with at least one first bonding layer at any position/angle when partially covered can achieve the object of the invention.
In order to avoid the same pixel unit being driven by two driving electrodes at the same time, the driving electrodes are damaged due to the short circuit phenomenon, it is further defined that the gap between the adjacent second bonding layers 70 is larger than the maximum value of the external dimensions of the first bonding layers 50, that is, at least one first bonding layer 50 can be accommodated between the gaps between the adjacent second bonding layers 70. The external dimension refers specifically to a dimension value on the external shape of the first bonding layer, and the specific value is determined by the shape of the first bonding layer.
Based on the design of the first bonding layer and the second bonding layer, each second bonding layer is ensured to be at least contacted with one first bonding layer, and the same pixel unit cannot be driven by two driving electrodes at the same time. In the embodiment in which the grooves as shown in fig. 2 are formed between the pixel units, the bonded structure is as shown in fig. 7.
In the obtained micro LED display assembly, at least 1 pixel unit corresponds to each driving electrode on the driving bottom plate, as the gap between every two adjacent second bonding layers is larger than the maximum value of the outer shape dimension of the first bonding layer, and the minimum value of the outer shape dimension of the second bonding layer is larger than the minimum distance between the diagonal first bonding layers, the current provided by the driving electrodes among the pixel units cannot generate transverse flow between the second semiconductor layers, so that the light emission of the pixel units is ensured, and the surface of the first semiconductor layer in the semiconductor light-emitting structure is a complete plane after the growth substrate is removed, thereby being beneficial to manufacturing the subsequent first semiconductor electrodes and other optical structures.
In addition, in the above embodiment, if the number of pixel units driven by different driving electrodes is different due to the offset in bonding, the correction can be compensated by the brightness correction of each pixel of the screen in applications such as AR (Augmented Reality ), VR (Virtual Reality), MR (Mixed Reality), and micro projector, so as to finally meet the requirement of brightness uniformity among each pixel of the screen.
Although the micro led display assembly in the above embodiment may have a situation that a part of the pixel units are not connected to any driving electrode, in the conventional bonding process, the driving electrode trench portion does not have a pixel unit that can be lightened, that is, the driving electrode trench portion does not have a pixel unit in terms of design, and in the above embodiment, the pixelation process before bonding not only achieves the purpose of the invention, but also does not need to further design the corresponding part of the driving electrode trench in the pixelation process, so that the whole process flow is simpler. And moreover, the pixel units with higher pixel density can be prepared on the semiconductor light-emitting structure, and the utilization rate of the semiconductor light-emitting structure can be improved to a certain extent.
By way of example, the following describes bonding conditions under different designs of the first bonding layer and the second bonding layer:
in one example, the pixel units are uniformly formed on the semiconductor light emitting structure, and the first bonding layer 50 is configured to have a circular shape, as shown in fig. 8. The second bonding layer 70 on the drive base plate is square as shown in fig. 9. After the semiconductor light emitting structure is bonded to the driving substrate, three bonding conditions may occur, as shown in fig. 10 to 12, in which bonding is performed at any position/angle, and the second bonding layer can drive at least one pixel unit.
In another example, the pixel units are uniformly formed on the semiconductor light emitting structure, and the first bonding layer 50 is configured to be circular. The second bonding layer on the driving bottom plate is square, and the size of the second bonding layer is far greater than that of the first bonding layer. After the semiconductor light emitting structure is bonded to the driving substrate, three bonding conditions may occur, as shown in fig. 13 to 15, in which bonding is performed at any position/angle, and the second bonding layer can drive a plurality of pixel units. In practical application, in order to reduce the difference caused by the offset in the bonding process, the difference between the dimensions of the second bonding layer and the first bonding layer can be configured, and the larger the difference between the dimensions of the two bonding layers is, the smaller the influence caused by the offset is.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. The preparation method of the micro LED display assembly is characterized by comprising the following steps of:
providing a semiconductor light emitting structure to be pixelated, wherein the semiconductor light emitting structure comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked on the surface of a growth substrate, and the surface of the semiconductor light emitting structure is divided into a pixel region for forming pixel units and a groove region formed between the pixel units;
forming a corresponding first bonding layer on the surface of each pixel unit in the pixel area;
providing a driving bottom plate, wherein mutually independent driving electrodes are arranged on the driving bottom plate, and a corresponding second bonding layer is formed on the surface of each driving electrode;
bonding the semiconductor light emitting structure to second bonding layers of a driving base plate through formed first bonding layers based on any position and/or angle, wherein each second bonding layer is at least in contact with one first bonding layer;
and removing the growth substrate on the semiconductor light-emitting structure to finish the preparation of the micro LED display assembly.
2. The method for manufacturing a micro led display device according to claim 1, wherein before forming the corresponding first bonding layer on the surface of each pixel unit in the pixel area, the method comprises: etching the groove area along the second semiconductor layer until reaching the first semiconductor layer to form a pixel unit; or performing ion implantation along the groove region to form a pixel unit.
3. The method for manufacturing a micro led display module according to claim 2, wherein the angle between the sidewall of the pixel unit and the bottom of the trench region is not less than 90 ° when the trench region is etched along the second semiconductor layer until the first semiconductor layer forms the pixel unit.
4. The method for manufacturing a micro led display assembly according to claim 3, wherein the etching the trench region along the second semiconductor layer until the first semiconductor layer is etched, and further comprising, after forming the pixel unit:
forming a metal reflecting layer on the side wall of the pixel unit;
and filling an insulating material in the groove area.
5. The method of manufacturing a micro led display assembly according to any one of claims 1 to 4, wherein before providing the driving chassis, the method comprises:
determining a maximum void region formed between the plurality of first bonding layers;
the outline and the size of the second bonding layer are configured based on preset rules, wherein the preset rules comprise: a second bonding layer can be in contact with at least one first bonding layer when the second bonding layer covers the surface of the largest gap area at any position and/or angle, and the gap between the adjacent second bonding layers is larger than the maximum value of the external dimension of the first bonding layer.
6. A micro led display assembly, comprising:
the driving base plate is provided with mutually independent driving electrodes, and the surfaces of the driving electrodes are provided with corresponding second bonding layers;
the semiconductor light-emitting structure is bonded on the driving bottom plate based on any position and/or angle, and comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked, wherein pixel units are formed on the semiconductor light-emitting structure, and corresponding first bonding layers are formed on the surfaces of the pixel units; each second bonding layer is in contact with at least one first bonding layer.
7. The micro led display assembly as recited in claim 6, wherein a trench etched from the second semiconductor layer to the first semiconductor layer is formed between the pixel cells in the semiconductor light emitting structure; or the second semiconductor layer of each pixel unit is implanted with preset ions.
8. The micro led display module according to claim 7, wherein when a trench is formed between the pixel units in the semiconductor light emitting structure from the second semiconductor layer to the first semiconductor layer, an angle between the sidewalls of the pixel units and the bottom of the trench region is not less than 90 °.
9. The micro led display assembly as recited in claim 8, wherein the sidewalls of the pixel cells are formed with a metal reflective layer and the trenches are filled with an insulating material.
10. The micro led display assembly of any one of claims 6-9, wherein a second bonding layer is capable of contacting at least one first bonding layer when at any position and/or angle overlying a surface of a largest void region formed between a plurality of first bonding layers, and wherein a gap between adjacent second bonding layers is greater than a maximum of an outer dimension of the first bonding layers.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120288995A1 (en) * | 2011-05-10 | 2012-11-15 | Ostendo Technologies, Inc. | Semiconductor Wafer Bonding Incorporating Electrical and Optical Interconnects |
| CN103928599A (en) * | 2013-01-14 | 2014-07-16 | 上海蓝光科技有限公司 | LED and manufacturing method thereof |
| CN105957938A (en) * | 2016-06-03 | 2016-09-21 | 扬州乾照光电有限公司 | AlGaInP-based light emitting diode wafer with high brightness and reversed polarity, and manufacturing method thereof |
| US20200343405A1 (en) * | 2019-04-23 | 2020-10-29 | Disco Corporation | Optical device layer transferring method |
| CN114824047A (en) * | 2022-04-25 | 2022-07-29 | 镭昱科技有限公司 | Micro light-emitting diode display chip and preparation method thereof |
| CN115101634A (en) * | 2022-06-07 | 2022-09-23 | 镭昱光电科技(苏州)有限公司 | Manufacturing method of micro light-emitting diode display structure and display device |
| CN218039270U (en) * | 2022-09-30 | 2022-12-13 | 镭昱光电科技(苏州)有限公司 | Micro-LED chip structure |
| CN115836341A (en) * | 2020-06-03 | 2023-03-21 | 上海显耀显示科技有限公司 | System and method for multi-color LED pixel cell with vertical emission |
| WO2023103606A1 (en) * | 2021-12-08 | 2023-06-15 | 镭昱光电科技(苏州)有限公司 | Micro-display led chip structure and manufacturing method therefor |
| CN116314240A (en) * | 2023-03-31 | 2023-06-23 | 湖南大学 | Semiconductor device and method for manufacturing the same |
| KR20230092671A (en) * | 2021-12-17 | 2023-06-26 | 삼성전자주식회사 | Micro LED display apparatus and method for manufacturing the same |
| WO2023116154A1 (en) * | 2021-12-20 | 2023-06-29 | 镭昱光电科技(苏州)有限公司 | Miniature light-emitting diode display device and manufacturing method therefor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020000378A1 (en) * | 2018-06-29 | 2020-01-02 | 长江存储科技有限责任公司 | Semiconductor structure and method for forming same |
| CN110491978B (en) * | 2019-09-19 | 2024-04-26 | 北京大学东莞光电研究院 | LED chip structure for mass transfer and preparation method thereof |
| WO2021237511A1 (en) * | 2020-05-27 | 2021-12-02 | 重庆康佳光电技术研究院有限公司 | Transfer substrate of micro-leds and preparation method therefor |
| CN116093217A (en) * | 2023-03-14 | 2023-05-09 | 湖南大学 | Micron light-emitting device and preparation method thereof |
-
2023
- 2023-09-12 CN CN202311169648.7A patent/CN116914061B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120288995A1 (en) * | 2011-05-10 | 2012-11-15 | Ostendo Technologies, Inc. | Semiconductor Wafer Bonding Incorporating Electrical and Optical Interconnects |
| CN103928599A (en) * | 2013-01-14 | 2014-07-16 | 上海蓝光科技有限公司 | LED and manufacturing method thereof |
| CN105957938A (en) * | 2016-06-03 | 2016-09-21 | 扬州乾照光电有限公司 | AlGaInP-based light emitting diode wafer with high brightness and reversed polarity, and manufacturing method thereof |
| US20200343405A1 (en) * | 2019-04-23 | 2020-10-29 | Disco Corporation | Optical device layer transferring method |
| CN115836341A (en) * | 2020-06-03 | 2023-03-21 | 上海显耀显示科技有限公司 | System and method for multi-color LED pixel cell with vertical emission |
| WO2023103606A1 (en) * | 2021-12-08 | 2023-06-15 | 镭昱光电科技(苏州)有限公司 | Micro-display led chip structure and manufacturing method therefor |
| KR20230092671A (en) * | 2021-12-17 | 2023-06-26 | 삼성전자주식회사 | Micro LED display apparatus and method for manufacturing the same |
| WO2023116154A1 (en) * | 2021-12-20 | 2023-06-29 | 镭昱光电科技(苏州)有限公司 | Miniature light-emitting diode display device and manufacturing method therefor |
| CN114824047A (en) * | 2022-04-25 | 2022-07-29 | 镭昱科技有限公司 | Micro light-emitting diode display chip and preparation method thereof |
| CN115101634A (en) * | 2022-06-07 | 2022-09-23 | 镭昱光电科技(苏州)有限公司 | Manufacturing method of micro light-emitting diode display structure and display device |
| CN218039270U (en) * | 2022-09-30 | 2022-12-13 | 镭昱光电科技(苏州)有限公司 | Micro-LED chip structure |
| CN116314240A (en) * | 2023-03-31 | 2023-06-23 | 湖南大学 | Semiconductor device and method for manufacturing the same |
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|---|---|
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