CN116914028A

CN116914028A - Solar cell, manufacturing method thereof and photovoltaic module

Info

Publication number: CN116914028A
Application number: CN202311021342.7A
Authority: CN
Inventors: 林全键
Original assignee: Jingke Energy Shangrao Co ltd
Current assignee: Jingke Energy Shangrao Co ltd
Priority date: 2023-08-14
Filing date: 2023-08-14
Publication date: 2023-10-20

Abstract

The embodiment of the disclosure relates to the field of photovoltaics, and provides a solar cell, a manufacturing method thereof and a photovoltaic module, wherein the manufacturing method of the solar cell comprises the following steps: providing a substrate, wherein the substrate is provided with a front surface and a back surface which are opposite, the front surface of the substrate is provided with an emitter, and first doping ions are doped in the emitter; the front sides of the two substrates are opposite, a single-groove double-insertion process is adopted, a semiconductor layer is formed on the back sides of the two substrates at the same time, and a winding plating layer is formed on the front sides of the substrates; after the semiconductor layer is formed, a mask layer is formed on the front surface, and the mask layer covers the surface of the wrapping plating layer; doping treatment is carried out, wherein the doping treatment is used for doping second doping ions into the semiconductor layer so as to form a conductive doping layer, and the first doping ions are different from the second doping ions; and removing the mask layer and the wrapping layer. At least the performance of the manufactured solar cell can be ensured while the efficiency of the solar cell manufacturing is improved.

Description

Solar cell, manufacturing method thereof and photovoltaic module

Technical Field

The embodiment of the disclosure relates to the field of photovoltaics, in particular to a solar cell, a manufacturing method thereof and a photovoltaic module.

Background

Tunneling oxidation passivation contact (TOPCon, tunnel Oxide Passivated Contact) batteries rely on the "tunneling effect" to realize rear surface passivation, and are becoming a point of entry for the industrialization of N-type high-efficiency batteries due to their excellent high efficiency and compatibility.

The back surface structure of the conventional TOPCON battery sequentially comprises a semiconductor substrate, a tunneling layer, a doped conductive layer and a back surface passivation layer from inside to outside. TOPCon cell front surface forms borosilicate glass (BSG, boron Silicon Glass) by boron diffusion as the emitter of the cell front surface.

However, the existing manufacturing method of the solar cell still has the problem that the production efficiency and the product performance cannot be simultaneously achieved.

Disclosure of Invention

The embodiment of the disclosure provides a solar cell, a manufacturing method thereof and a photovoltaic module, which are at least beneficial to improving the manufacturing efficiency of the solar cell and ensuring the performance of the manufactured solar cell.

According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a method for manufacturing a solar cell, including: providing a substrate having opposite front and back sides, the front side of the substrate having an emitter, the emitter being doped with first dopant ions; the front sides of the two substrates are opposite to each other, a single-groove double-insertion process is adopted, a semiconductor layer is formed on the back sides of the two substrates at the same time, and a wrapping plating layer is formed on the front sides of the substrates; forming a mask layer on the front surface after forming the semiconductor layer, wherein the mask layer covers the surface of the around plating layer; performing a doping process for doping a second doping ion into the semiconductor layer to form a conductive doping layer, the first doping ion being different from the second doping ion; and removing the mask layer and the wrapping coating.

In some embodiments, the process of the doping treatment is a thermal diffusion process, and the process temperature of the doping treatment is 800 ℃ to 1000 ℃.

In some embodiments, the doping treatment includes introducing a doping source gas to the surface of the semiconductor layer, where the doping source gas includes the second doping ions, and a flow rate of the doping source gas is 900sccm to 3000sccm.

In some embodiments, the semiconductor layer is formed using low pressure chemical vapor deposition.

In some embodiments, the doping process includes: and doping the second doping ions in the semiconductor layers on the back surfaces of the two substrates by adopting a single-groove double-insertion process to form the conductive doping layer.

In some embodiments, the doping process forms a wrap-around region in a partial region of the front side of the substrate, the wrap-around region having the second dopant ions therein, the wrap-around region being located in the mask layer and/or the wrap-around layer.

In some embodiments, the wrap-around coating is also located on a side of the substrate.

In some embodiments, removing the masking layer and the wrap-around layer comprises: immersing the front surface of the substrate in a first cleaning solution to remove at least part of the mask layer and at least part of the around plating layer, wherein the removed around plating layer is at least positioned on the side surface of the substrate; immersing the front surface of the substrate into a second cleaning solution to remove the mask layer and the wrapping coating.

In some embodiments, the first cleaning solution is an acidic cleaning solution; the second cleaning liquid is alkaline cleaning liquid.

In some embodiments, the mask layer is formed of a material including one or more of silicon, silicon nitride, and silicon oxide.

In some embodiments, the mask layer is formed to a thickness of 40nm-70nm.

In some embodiments, before forming the semiconductor layer on the back surface of the substrate, the method further comprises: and polishing the back surface of the substrate.

In some embodiments, forming the mask layer on the front side includes: and the back surfaces of the two substrates are opposite, and a single-groove double-insertion process is used for simultaneously forming the mask layers on the front surfaces of the two substrates.

According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a solar cell manufactured by the method for manufacturing a solar cell described in the above embodiments, including: a substrate having opposite front and back sides, the front side of the substrate having an emitter, the emitter being doped with first dopant ions; and the conductive doping layer is positioned on the back surface of the substrate.

According to some embodiments of the present disclosure, there is also provided, in another aspect, a photovoltaic module including: a battery string formed by connecting the solar cells according to the above embodiments; the packaging adhesive film is used for covering the surface of the battery string; and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the method for manufacturing the solar cell provided by the embodiment of the disclosure, a substrate with a front surface and a back surface which are opposite is provided, wherein the front surface of the substrate is provided with an emitter, and first doping ions are doped in the emitter; the front sides of the two substrates are opposite, a semiconductor layer is formed on the back sides of the two substrates simultaneously by adopting a single-groove double-insertion process, and a winding plating layer is formed on the front sides; forming a mask layer on the front surface, wherein the mask layer covers the surface of the plating layer; doping treatment is carried out, and second doping ions are doped into the semiconductor layer to form a conductive doping layer, wherein the first doping ions are different from the second doping ions; and removing the mask layer and the wrapping layer. Firstly, the single-groove double-insertion process is used for simultaneously forming the semiconductor layers on the back surfaces of the two substrates, so that the productivity of the solar cell manufacturing process can be improved, and the production efficiency of the solar cell is greatly improved; secondly, if the emitter is doped with second doping ions, the reaction rate of the emitter and the etching environment of the detour plating can be greatly improved, the emitter is easily over-etched in the detour plating process to damage the substrate, the mask layer formed by the method can cover the surface of the detour plating layer and the surface of the emitter, and when the semiconductor layer is doped, the second doping ions which are wound and expanded are doped into the mask layer and cannot be doped into the emitter, so that the over-etching in the detour plating process can be avoided, the substrate is prevented from being damaged, and the performance of the manufactured solar cell can be prevented from being influenced; in addition, the semiconductor layer is formed on the back surface of the substrate, and then the mask layer is formed on the front surface of the substrate, so that the quality of the semiconductor layer formed on the back surface of the substrate can be improved, oxidation or pollution of the back surface of the substrate before the semiconductor layer is formed can be avoided, and the situation that the mask layer is plated on the back surface of the substrate in a winding manner to cause the back surface of the substrate to be polluted to influence the quality of the semiconductor layer can be avoided, so that the performance of the manufactured solar cell can be further improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram corresponding to a step of providing a substrate in a method for manufacturing a solar cell provided in the present disclosure;

fig. 2 is a schematic structural diagram corresponding to a step of texturing a front surface of a substrate in the method for manufacturing a solar cell provided by the present disclosure;

fig. 3 is a schematic structural diagram corresponding to a polishing treatment step performed on a back surface of a substrate in the method for manufacturing a solar cell provided by the present disclosure;

fig. 4 is a schematic structural diagram corresponding to a step of forming a semiconductor layer in the method for manufacturing a solar cell provided in the present disclosure;

Fig. 5 is a schematic diagram of another structure corresponding to a step of forming a semiconductor layer in the method for manufacturing a solar cell according to the present disclosure;

fig. 6 is a schematic diagram corresponding to a step of forming a semiconductor layer in the method for manufacturing a solar cell according to the present disclosure;

fig. 7 is a schematic structural diagram corresponding to a step of forming a mask layer in the method for manufacturing a solar cell provided in the present disclosure;

fig. 8 is a schematic structural diagram corresponding to a doping treatment step in the method for manufacturing a solar cell according to the present disclosure;

fig. 9 is another schematic structural diagram corresponding to a doping treatment step in the method for manufacturing a solar cell provided in the present disclosure;

fig. 10 is a schematic structural diagram corresponding to a doping treatment step in the method for manufacturing a solar cell according to the present disclosure;

fig. 11 to 12 are schematic structural diagrams corresponding to steps of removing a mask layer and winding a plating layer in the method for manufacturing a solar cell provided by the present disclosure;

fig. 13 is a schematic structural diagram corresponding to a step of a subsequent process performed in the method for manufacturing a solar cell provided in the present disclosure;

fig. 14 is a schematic structural diagram corresponding to a step of forming a tunnel oxide layer after a subsequent process is performed in the method for manufacturing a solar cell provided in the present disclosure;

Fig. 15 is a schematic structural diagram of a solar cell according to an embodiment of the disclosure;

fig. 16 is a schematic structural view of a solar cell according to another embodiment of the present disclosure;

fig. 17 is a schematic structural view of a solar cell according to another embodiment of the present disclosure;

fig. 18 is a schematic structural diagram of a photovoltaic module according to an embodiment of the disclosure.

Detailed Description

As is clear from the background art, the conventional method for manufacturing a solar cell has a problem that it is difficult to ensure the performance of the solar cell while improving the manufacturing efficiency of the solar cell.

The embodiment of the disclosure provides a manufacturing method of a solar cell, which comprises the steps of firstly providing a substrate with a front surface and a back surface which are opposite, wherein the front surface of the substrate is provided with an emitter, and first doping ions are doped in the emitter; the front sides of the two substrates are opposite, a semiconductor layer is formed on the back sides of the two substrates simultaneously by adopting a single-groove double-insertion method, and a winding plating layer is formed on the front sides of the substrates; forming a mask layer on the front surface, wherein the mask layer covers the surface of the plating layer; doping treatment is carried out, second doping ions are doped in the semiconductor layer, a conductive doping layer is formed, and the first doping ions are different from the second doping ions; and removing the wrapping layer and the mask layer. Thus, the production efficiency can be improved, the substrate can be prevented from being damaged by over etching during the winding plating, and the quality of the conductive doped layer formed on the back surface of the substrate can be improved, so that the performance of the manufactured solar cell can be ensured.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Referring to fig. 1, a substrate 100 is provided having opposite front 101 and back 102 sides, the front side of the substrate having an emitter 110 doped with first dopant ions.

The substrate 100 is a region that absorbs incident photons to generate photogenerated carriers. In some embodiments, the substrate 100 is a silicon substrate, which may include one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also be silicon carbide, an organic material, or a multi-component compound. The multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like. Illustratively, the substrate 100 in the present disclosure may be a monocrystalline silicon substrate.

In some embodiments, for a single-sided cell, the front side 101 of the substrate 100 is the light-receiving side and the back side 102 of the substrate 100 is the backlight side; for a double sided cell, both the front side 101 and the back side 102 may act as light receiving surfaces to absorb incident light. The substrate 100 has a doping element therein, the doping element being of an N-type or a P-type, the N-type element being a group v element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, and the P-type element being a group iii element such As a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element. And the resistivity of the substrate 100 is 0.5 to 3 Ω·cm, alternatively, the resistivity of the substrate is 0.5 to 2 Ω·cm, and the resistivity of the substrate 100 may be specifically 0.53 Ω·cm, 0.89 Ω·cm, 1.29 Ω·cm, 1.53 Ω·cm, or 1.86 Ω·cm. For example, when the substrate 100 is a P-type substrate, the internal doping element type is P-type. For another example, when the substrate 100 is an N-type substrate 100, the internal doping element is of N-type. The TOPCon cell may be an N-type substrate 100, the front side of the substrate 100 may be doped with a P-type element, and the back side 102 of the substrate 100 may be doped with an N-type element.

In addition, in the actual production process, each substrate 100 is produced into one solar cell after a plurality of processes, and to increase the process yield, a plurality of substrates 100 may be processed simultaneously to form a plurality of solar cells. Specifically, the process of simultaneously processing the plurality of substrates 100 may be a single-slot double-insert process.

Referring to fig. 2, in some embodiments, the substrate 100 may be textured to form a textured surface on the surface of the substrate 100, so that the absorption and utilization of incident light by the substrate 100 may be enhanced. In some embodiments, the texture may be a pyramid texture, which is a common texture, not only reduces the reflectivity of the surface of the substrate 100, but also forms light traps, which enhances the absorption effect of the substrate 100 on incident light, and increases the conversion efficiency of the solar cell. For a single-sided battery, the front side 101 of the substrate 100 may be selectively textured, or the front side 101 and the back side 102 of the substrate 100 may be first textured on both sides, and then the back side 102 of the substrate 100 may be polished to preserve the texture of the front side 101 of the substrate 100. Fig. 2 is a schematic diagram showing only a structure in which the front surface 101 and the back surface 102 of the substrate 100 are subjected to double-sided texturing.

Specifically, in some embodiments, the substrate 100 is an N-type semiconductor substrate, and may be textured with an alkaline solution, such as NaOH solution, whose etching has anisotropy, which is advantageous for preparing pyramid-like structures. In some embodiments, the pyramidal pile surface may also be prepared by chemical etching, laser etching, mechanical methods, plasma etching, and the like.

The emitter 110 is a region of the solar cell that emits a large number of carriers in the absence of light. The first dopant ions doped in the emitter 110 are of the opposite dopant element type to the substrate 100. The emitter 110 and the substrate 100 form a PN junction. In some embodiments, the material of emitter 110 may be the same as the material of substrate 100.

Specifically, in some embodiments, the first dopant ions may include boron ions. The first doping ions doped on the front surface 101 of the substrate 100 are P-type ions, for example, the first doping ions on the front surface 101 of the substrate 100 may also be boron ions, aluminum ions, gallium ions, indium ions, or the like. When the first doping ion is boron ion, the substrate 100 can have better electronic characteristics, the resistivity of the substrate 100 is easy to control, and the influence of impurities can be effectively inhibited, so that the performance of the circuit is more stable.

In some embodiments, the process of forming the emitter 110 doped with the first dopant ions at the front surface 101 of the substrate 100 may include an ion implantation method.

Referring to fig. 3, in some embodiments, before forming the semiconductor layer 120 on the back surface 102 of the substrate 100, it may further include: the back surface 102 of the substrate 100 is subjected to a polishing process. If the front surface 101 and the back surface 102 of the substrate 100 are subjected to double-sided texturing in the pre-texturing step, the back surface 102 of the substrate 100 may be subjected to polishing treatment to remove the texture existing on the back surface 102 of the substrate 100. If the back surface 102 of the substrate 100 is not subjected to the texturing process in the pre-texturing step, the polishing process on the back surface 102 of the substrate 100 before the formation of the semiconductor layer 120 can remove oxides and other impurities possibly existing in the natural oxidation of the back surface 102 of the substrate 100, and the smoothness of the back surface 102 of the substrate 100 can be improved, so that a better interface environment can be provided for the semiconductor layer 120 to be formed in the subsequent step, and the quality of the subsequently formed semiconductor layer 120 can be improved.

In some embodiments, polishing the back surface 102 of the substrate 100 may comprise: the rear surface 102 of the substrate 100 is immersed in an alkaline polishing solution, and the rear surface 102 of the substrate 100 is subjected to polishing treatment.

Referring to fig. 4 to 6, the front surfaces 101 of the two substrates 100 are faced, a single-slot double-plug process is used, a semiconductor layer 120 is simultaneously formed on the rear surfaces 102 of the two substrates 100, and a wrap-around layer 121 is formed on the front surfaces 101 of the substrates 100.

In some embodiments, the material of the semiconductor layer 120 may include polysilicon.

The quality of the semiconductor layer 120 formed can be improved by directly forming the semiconductor layer 120 after polishing the back surface 102 of the substrate 100, and at this time, the back surface 102 of the substrate 100 has a better interface state after polishing, the oxide and impurities on the surface are all at a lower level, and the back surface 102 has a higher smoothness. If the mask layer 130 is formed on the front surface 101 of the substrate 100 and then the semiconductor layer 120 is formed on the back surface 102 of the substrate 100 in the subsequent steps, natural oxidation and other impurities may occur on the back surface 102 of the substrate 100 during the formation of the mask layer 130, and the formed mask layer 130 may also form a wraparound plating on the back surface 102 of the substrate 100, which may have a great influence on the quality of the semiconductor layer 120, and thus on the quality and performance of the manufactured solar cell. Therefore, in the present disclosure, after polishing the back surface 102 of the substrate 100, the semiconductor layer 120 is formed on the back surface 102 of the substrate 100, and then the mask layer 130 is formed on the front surface 101 of the substrate 100, so that the quality of the semiconductor layer 120 can be improved, thereby improving the quality and performance of the manufactured solar cell.

According to the LPCVD principle, if the LPCVD single-slot single-tab process is used, the semiconductor layer 120 may be formed only on the surface of the same substrate 100 in sequence, and the semiconductor layer 120 may be formed on both the front surface 101 and the back surface 102 of the substrate 100. If the LPCVD dual insert process is used, the semiconductor layer 120 may be formed on the surfaces of both substrates 100 at the same time, and each substrate 100 may only have the semiconductor layer 120 formed on one side surface. In the embodiment of the present invention, the mask layer 130 is formed on the front surface 101 of the substrate 100 in the subsequent step, and the mask layer 130 can play a role in protecting the emitter 110 from being doped by the second doping ions when the semiconductor layer 120 is doped, so that the semiconductor layer 120 is not required to be formed on both the front surface 101 and the back surface 102 of the substrate 100 by using a single-slot single-plug process, and the semiconductor layer 120 can be formed on both the back surfaces 102 of the two substrates 100 by directly using a single-slot double-plug process with higher production efficiency, thereby improving the productivity by more than one time.

Referring to fig. 4, in some embodiments, the front side 101 of the substrate 100 may not have the wrap-around layer 121 when the semiconductor layer 120 is formed on the back side 102 of the substrate 100 using a single-slot double-plug process, as desired.

Referring to fig. 5, in some embodiments, when the semiconductor layer 120 is formed on the back surface 102 of the substrate 100 using a single-slot dual-plug process, a wrap-around layer 121 is formed in a partial region of the front surface 101 of the substrate 100. The wrap-around layer 121 may cover a portion of the surface of the emitter 110 remote from the substrate 100. The wrapping layer 121 may affect the efficiency and yield of the manufactured solar cell. Therefore, if the plating layer 121 is present, a de-plating process is required in the subsequent step.

Referring to fig. 6, in some embodiments, the wrap 121 may also be located on the side of the substrate 100. The wrap-around plating layer 121 located at the side of the substrate 100 may cover a part of the surface of the side of the substrate 100, or the wrap-around plating layer 121 located at the side of the substrate 100 may cover the entire surface of the side of the substrate 100. If the wrap-around layer 121 is located on the side of the substrate 100, the wrap-around layer 121 may cover the side of the emitter 110, and when the semiconductor layer 120 is doped in a subsequent step, the second doping ions generated by the wrap-around may be doped into the wrap-around layer 121 on the side of the emitter 110 without being doped into the emitter 110 from the side of the emitter 110, thereby protecting the emitter 110 from over-etching during the de-wrap-around process, so that the substrate 100 is not damaged, and the quality and performance of the fabricated solar cell are ensured.

It should be noted that if the plating layer 121 is also located on the side of the substrate 100, the plating layer 121 located on the side of the substrate 100 is also removed in the subsequent process of removing the plating layer.

In some embodiments, the method of forming the semiconductor layer 120 may employ a Low Pressure Chemical Vapor Deposition (LPCVD). The formation of the semiconductor layer 120 by low pressure chemical vapor deposition can improve the compactness of the semiconductor layer 120 formed on the back surface 102 of the battery, and can reduce the problems of powder removal and film explosion. If the semiconductor layer 120 is formed by using the plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), the compactness of the formed semiconductor layer 120 is poor, and the formed semiconductor layer 120 has serious problems of powder removal and film explosion. In addition, the low-pressure chemical vapor deposition method can adopt a single-groove double-insertion implementation mode, and the semiconductor layers 120 can be formed on the back surfaces 102 of the two substrates 100 at the same time, so that the productivity of producing solar cells can be greatly improved.

Referring to fig. 7, after the semiconductor layer 120 is formed, a mask layer 130 is formed on the front surface, and covers the plating layer surface.

The mask layer 130 may cover the surface of the emitter 110 and the surface of the surrounding plating layer 121. A doping process is required for the semiconductor layer 120 in a subsequent step so that the second doping ions are doped into the semiconductor layer 120. In the doping process, the second doping ions may be diffused into a partial region outside the front surface 101 of the substrate 100 due to the round diffusion, and the second doping ions diffused into the front surface 101 of the substrate 100 may be doped into the mask layer 130 or the round plating layer 121, or the second doping ions diffused into the front surface 101 of the substrate 100 may be doped into the mask layer 130 and the round plating layer 121. The mask layer 130 may protect the emitter 110 so that the second dopant ions are not doped into the emitter 110. If the emitter 110 is doped with the first doping ion and the second doping ion, the reaction rate between the emitter 110 and the de-winding etching environment is extremely high, which is very likely to cause over-etching to the emitter 110 and even damage to the substrate 100 during the de-winding etching process, thereby affecting the quality and performance of the solar cell. Forming the mask layer 130 on the front surface 101 of the substrate 100 can avoid the second doping ion from being wrapped around the emitter 110, thereby ensuring the quality and performance of the solar cell.

The semiconductor layer 120 is formed on the back surface 102 of the substrate 100, and then the mask layer 130 is formed on the front surface 101 of the substrate 100, so that the quality of the formed semiconductor layer 120 can be improved, and the influence of oxidation and impurity pollution of the back surface 102 of the substrate 100 on the quality of the semiconductor layer 120 can be reduced.

In some embodiments, the material of the mask layer 130 formed may include one or more of silicon, silicon nitride, and silicon oxide. The material of the semiconductor layer 120 formed in the above-described steps may be polysilicon, and thus, the material of the plating layer 121 formed at the time of forming the semiconductor layer 120 may also be polysilicon. Therefore, if the material of the formed mask layer 130 is also silicon, the materials of the mask layer 130 and the plating around layer 121 may be the same, and the same etching solution may be used to remove the plating around layer 121 and the mask layer 130 when the plating around layer 121 is removed and the subsequent steps are performed, which is beneficial to simplifying the process flow and reducing the production cost.

In some embodiments, the mask layer 130 may be formed to a thickness of 40nm-70nm. For example, the thickness of the mask layer 130 may be 40nm, 46nm, 50nm, 57nm, 60nm, 64nm, 70nm, etc. If the thickness of the mask layer 130 is too large, material waste is caused, and a longer production time is required in the process of forming the too thick mask layer 130, so that the production efficiency is reduced; if the thickness of the mask layer 130 is smaller, when the semiconductor layer 120 is doped with the second doping ions, the second doping ions that are wound and expanded may still be doped into the emitter 110, and there is still a risk that the solar cell is damaged by over etching during the de-winding plating. Therefore, the thickness of the mask layer 130 needs to be selected in a proper range, and when the thickness of the mask layer 130 is 40nm-70nm, the emitter 110 is not doped by the second doping ions in the subsequent doping step, and no great waste is caused.

In some embodiments, forming the mask layer 130 on the front side 101 may include: the back sides 102 of the two substrates 100 are faced, and a single-slot double-plug process is used to simultaneously form the mask layer 130 on the front sides 101 of the two substrates 100. The single-slot double-insertion process can simultaneously form the mask layer 130 on the front sides 101 of the two substrates 100, and etching greatly improves the production efficiency, and the productivity of production is doubled. In addition, since the method of forming the mask layer 130 in this step and the method of forming the semiconductor layer 120 in the previous step can both use a single-slot double-insertion method, the formation of the semiconductor layer 120 and the formation of the mask layer 130 can be performed in the same equipment in the production process, so that the production cost can be reduced, the production process can be simplified, the manpower resources required for production can be reduced, and the production efficiency can be increased.

Referring to fig. 8, a doping process for doping second doping ions into the semiconductor layer 120 to form a conductive doping layer 122 is performed, the first doping ions being different from the second doping ions.

In some embodiments, the second dopant ions may be N-type dopant ions. For example, the second dopant ion may be phosphorus. The second dopant ions may also be doped into a partial region of the back surface 102 of the substrate 100.

In some embodiments, the process of the doping treatment may be a thermal diffusion process, and the process temperature of the doping treatment may be 800-1000 ℃. For example, the process temperature of the doping treatment may be 800 ℃, 810 ℃, 820 ℃, 850 ℃, 880 ℃, 900 ℃, 950 ℃, 1000 ℃, or the like. Doping the second dopant ions in the semiconductor layer 120 using a thermal diffusion process may allow for a more accurate doping depth and doping concentration. It should be noted that, when the second doping ions are doped into the semiconductor layer 120 by performing the thermal diffusion process, the material of the semiconductor layer 120 is amorphous silicon due to the effect of the high temperature, and the material of the conductive doping layer 122 after thermal diffusion is converted into polysilicon by high temperature recrystallization. If the process temperature of the doping process is too low, the doping depth and doping concentration may be low, and the doped conductive doped layer 122 may still have silicon in a single crystalline state or an amorphous state; if the temperature of the doping treatment is too high, the doping depth and the doping concentration are large, and a certain waste of thermal energy is caused. Therefore, the process temperature of the doping treatment can be selected to be in a proper range, when the process temperature of the doping treatment is 800-1000 ℃, the depth and the concentration of the doped second doping ions in the conductive doped layer 122 can be ensured to be proper, and the waste of thermal energy can not be caused.

In some embodiments, the doping process may include introducing a doping source gas to the surface of the semiconductor layer 120, where the doping source gas includes a second doping ion, and the flow rate of the doping source gas may be 900sccm to 3000sccm. For example, the flow rate of the dopant source gas may be 900sccm, 1000sccm, 2000sccm, 2500sccm, 3000sccm, or the like. If the flow of the doping source gas is too large, the utilization rate of the doping source gas is low, a certain waste is caused, the production cost is increased, and if the flow of the doping source gas is too small, the efficiency of doping treatment is low, the time of a process flow is increased, and the production efficiency is reduced. Therefore, the flow rate of the doping source gas needs to be selected in a proper range, and when the flow rate of the doping gas is 900sccm-3000sccm, the production cost can be reduced, and the production efficiency can be ensured.

In some embodiments, the dopant source gas may be phosphorus oxychloride, phosphorus pentachloride, or the like.

In some embodiments, the doping process may include: the mask layers 130 of the two substrates 100 are aligned, and a single-slot double-plug process is used to dope the second doping ions into the semiconductor layers 120 of the back surfaces 102 of the two substrates 100 at the same time, so as to form the conductive doping layer 122. The single-slot double-plug process can dope the semiconductor layer 120 on the back surface 102 of the two substrates 100 with the second doping ions at the same time, so that the doping efficiency is greatly improved, and the productivity of production is further improved. In addition, since the doping treatment in this step and the steps of forming the mask layer 130 and forming the semiconductor layer 120 in the foregoing steps may all be performed by a single-slot double-insertion method, the semiconductor layer 120, the mask layer 130 and the doping treatment may be performed in the same apparatus during the production process, so that the production cost may be further reduced, the production process may be simplified, the manpower resources required for the production may be reduced, and the production efficiency may be increased. In addition, the single-slot double-insertion process can only dope the semiconductor layer 120 on the back surface 102 of the substrate 100 with the second doping ions, so that the waste of a part of doping sources can be reduced, and the cost can be reduced.

Referring to fig. 9, in some embodiments, the doping process may form a surrounding region 131 in a partial region of the front surface of the substrate 100, the surrounding region 131 having second doping ions therein, the surrounding region 131 may be located in the mask layer 130 and/or the surrounding plating layer 121. Even if the second doping ions are doped only in the semiconductor layer 120 of the back surface 102 of the substrate 100 using the single-slot double-plug process, it is possible to form the surrounding extension 131 in a partial region of the front surface 101 of the substrate 100. The surrounding region 131 is a region doped with the second doping ions outside the semiconductor layer 120. The around-extension 131 may be located in the mask layer 130, in the around-plating layer 121, or the around-extension 131 may be located in the mask layer 130 and in the around-plating layer 121. Since the mask layer 130 is formed on the front surface 101 of the substrate 100 in advance, during the doping process, the surrounding region 131 will not be located in the emitter 110, that is, the second doping ions will not be doped into the emitter 110, so that the emitter 110 will not be over-etched in the subsequent process of removing the surrounding plating, and the substrate 100 will not be damaged, thereby affecting the quality and performance of the solar cell.

Note that the around-expansion region illustrated in fig. 9 only illustrates one case where the around-expansion region is located in the mask layer and the around-plating layer, and other cases are included.

Referring to fig. 10, in some embodiments, where the wrap 121 is also located on the side of the substrate 100, the wrap 131 may also be located within the wrap 121 on the side of the substrate 100. The wrap-around layer 121 on the side of the substrate 100 may cover the side of the emitter 110, and the wrap-around layer 121 on the side of the substrate 100 may protect the side of the emitter 110 during the doping process, so that the second doping ions wrapped around to the side of the substrate 100 may be doped into the wrap-around layer 121 without being doped into the emitter 110 through the side of the emitter 110. In the subsequent de-wrap plating step, the emitter 110 is not over-etched, and thus the substrate 100 is not damaged, so that the quality and performance of the manufactured solar cell can be ensured.

Referring to fig. 11 to 12, the mask layer 130 and the plating layer 121 are removed.

In some embodiments, removing masking layer 130 and plating layer 121 may be performed in the same step. The cleaning solution can etch away the material of the mask layer 130 and the material surrounding the plating layer 121. Since the second doping ions are not doped into the emitter 110 in the above steps, the reaction rate between the emitter 110 and the cleaning solution is low compared to the mask layer 130 and the surrounding plating layer 121, and the emitter 110 is not over-etched and does not damage the substrate 100, thereby not affecting the quality and performance of the solar cell.

In some embodiments, removing the mask layer 130 and the plating layer 121 may further include: referring to fig. 11, the front surface 101 of the substrate 100 is immersed in a first cleaning solution to remove at least part of the mask layer 130 and at least part of the plating layer 121, the removed plating layer 121 being located at least on the side surface of the substrate 100; referring to fig. 12, the front surface 101 of the substrate 100 is immersed in a second cleaning solution to remove the mask layer 130 and the plating layer 121. It is understood that the mask layer 130 and the plating layer 121 may be removed in two steps, and different cleaning solutions may be selected for the two steps.

Specifically, if the material of the mask layer 130 is different from the material of the plating layer 121, the first cleaning solution may select a cleaning solution having a higher reaction rate with the mask layer 130, the second cleaning solution may select a cleaning solution having a higher reaction rate with the plating layer 121, or the first cleaning solution may select a cleaning solution having a higher reaction rate with the plating layer 121, and the second cleaning solution may select a cleaning solution having a higher reaction rate with the mask layer 130. In this way, the mask layer 130 and the around-plating layer 121 can be removed respectively, so that the etching removal step is more complete for removing the mask layer 130 and the around-plating layer 121. If the material of the mask layer 130 is the same as the material of the plating layer 121, the first cleaning solution may be a solution having a relatively high reaction rate with the material of the mask layer 130 and the material of the plating layer 121, and in the cleaning process using the first cleaning solution, most of the mask layer 130 and the plating layer 121 may be removed, so that the removal efficiency is improved. In contrast, the second cleaning solution may be a solution having a smaller reaction rate with the material of the mask layer 130 and the material of the around-plating layer 121, and in the cleaning process using the second cleaning solution, the remaining mask layer 130 and around-plating layer 121 may be removed more slowly, so as to control the cleaning time, so that the cleaning is finished when the mask layer 130 and around-plating layer 121 are completely removed and no over-etching is performed on the emitter 110.

In some embodiments, the first cleaning fluid may be an acidic cleaning fluid; the second cleaning liquid may be an alkaline cleaning liquid. As can be seen from the above description, if the material of the mask layer 130 is the same as the material of the plating layer 121, the first cleaning solution may be an acidic cleaning solution with a fast reaction rate with the material of the mask layer 130 and the material of the plating layer 121, and the efficiency of the acidic cleaning solution in removing the mask layer 130 and the plating layer 121 is high, so that the production process can be accelerated, the production time can be reduced, and the production efficiency can be improved. In contrast, the second cleaning solution may be an alkaline cleaning solution with a slower reaction rate with the material of the mask layer 130 and the material of the around-plating layer 121, the efficiency of removing the mask layer 130 and the around-plating layer 121 by the alkaline cleaning solution is lower, so that the reaction time is convenient to control, after the second cleaning solution removes all the mask layer 130 and the around-plating layer 121, the cleaning process can be timely ended, and it is ensured that the over-etching is not caused to the emitter 110 while the mask layer 130 and the around-plating layer 121 are completely removed.

Referring to fig. 13, after removing the mask layer 130 and the plating layer 121, a first passivation layer 140 covering the surface of the emitter 110 remote from the substrate 100 may be further formed on the front surface 101 of the substrate 100, a second passivation layer 150 covering the surface of the conductive doped layer 122 remote from the substrate 100 is formed on the rear surface 102 of the substrate 100, and an electrode 160 is formed on the front surface 101 and the rear surface 102 of the battery through a screen printing process.

The material of the first passivation layer 140 may include silicon nitride or aluminum oxide, and the material of the second passivation layer 150 may include silicon nitride. The first passivation layer 140 and the second passivation layer 150 may further enhance the passivation effect of the solar cell.

Referring to fig. 14, in some embodiments, forming the semiconductor layer 120 on the back surface 102 of the substrate 100 may further include forming a tunnel oxide layer 170 on the back surface 102 of the substrate 100. The semiconductor layer 120 is located on a side surface of the tunnel oxide layer 170 away from the substrate 100. The material of the tunnel oxide layer 170 may include silicon oxide, and the second doping ions may be doped into the tunnel oxide layer 170 during the doping process.

The embodiment of the disclosure provides a manufacturing method of a solar cell, which comprises the steps of firstly providing a substrate with a front surface and a back surface which are opposite, wherein the front surface of the substrate is provided with an emitter, and first doping ions are doped in the emitter; the front sides of the two substrates are opposite, a semiconductor layer is formed on the back sides of the substrates simultaneously by adopting a single-groove double-insertion process, and a winding plating layer is formed on the front sides of the substrates; forming a mask layer on the front surface, wherein the mask layer covers the surface of the plating layer; doping treatment is carried out, and second doping ions are doped into the semiconductor layer to form a conductive doping layer, wherein the first doping ions are different from the second doping ions; and removing the mask layer and the wrapping layer. Therefore, the production efficiency can be improved, the substrate is prevented from being damaged due to over etching during the winding plating, the quality of the conductive doped layer formed on the back surface of the substrate can be improved, and the performance of the manufactured solar cell can be ensured.

Accordingly, another embodiment of the present disclosure also provides a solar cell, which may be manufactured by the method for manufacturing a solar cell described above. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be repeated in detail.

Referring to fig. 15, the solar cell includes: a substrate 100, the substrate 100 having a front side 101 and a back side 102 opposite to each other, the front side 101 of the substrate 100 having an emitter 110, the emitter 110 being doped with first dopant ions; conductive doped layer 122, conductive doped layer 122 is located on back surface 102 of substrate 100.

In some embodiments, for a single-sided cell, the front side 101 of the substrate 100 is the light-receiving side and the back side 102 of the substrate 100 is the backlight side; for a double sided cell, both the front side 101 and the back side 102 may act as light receiving surfaces to absorb incident light. For a TOPCON cell, the front side 101 of the substrate 100 is the light-receiving side.

Referring to fig. 16, in some embodiments, the front surface of the substrate 100 may be textured to form a textured surface on the surface of the substrate 100, so that the absorption and utilization of the incident light by the substrate 100 may be enhanced. In some embodiments, the texture may be a pyramid texture, which is a common texture, not only reduces the reflectivity of the surface of the substrate 100, but also forms light traps, which enhances the absorption effect of the substrate 100 on incident light, and increases the conversion efficiency of the solar cell.

Referring to fig. 17, the solar cell may further include: a first passivation layer 140, a second passivation layer 150, a tunnel oxide layer 170, and an electrode 160. The first passivation layer 140 covers the surface of the emitter 110 away from the substrate 100, the second passivation layer 150 covers the surface of the conductive doped layer 122 away from the substrate 100, the tunnel oxide layer 170 is located on the back surface 102 of the substrate 100, the semiconductor layer 120 covers the surface of the tunnel oxide layer 170 away from the substrate 100, and the electrode 160 is located on the front surface 101 and the back surface 102 of the substrate 100.

Correspondingly, another embodiment of the disclosure further provides a photovoltaic module. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be repeated in detail.

Referring to fig. 18, the photovoltaic module includes: a cell string 200 formed by connecting a plurality of solar cells; a packaging adhesive film 210 for covering the surface of the battery string 200; and a cover plate 220 for covering the surface of the encapsulation film 210 facing away from the battery string 200.

The battery string 200 is formed by electrically connecting a plurality of battery cells. In some embodiments, a plurality of battery cells, a solder strip connecting the plurality of battery cells, and a bus bar connecting the battery string with a junction box may be included in the battery string 200.

In some embodiments, the battery cells in the battery string 200 may be emitter and back passivation cells (PERC, passivated Emitter Rear Cell), oxidation passivation contact cells (TOPCon, tunnel Oxide Passivated Contact), intrinsic thin film heterojunction cells (HJT, heterojunction with Intrinsic Thin-film), interdigitated back contact cells (IBC, interdigitated Back Contact), and the like.

The packaging film 210 is used for bonding the battery string 200 and the cover plate 220. In some embodiments, the material of the encapsulation film 210 may include EVA, POE, PVB, etc. The packaging adhesive film 210 can protect the battery string, prevent the external environment from influencing the performance of the battery string 200, and has certain bonding strength.

In some embodiments, the material of the cover plate 220 may be glass. The glass has lower water permeability, and the glass cover plate 220 can effectively prevent water vapor in the external environment from entering the photovoltaic module through the cover plate 220, so that the corrosion of the water vapor to the battery strings 200 can be reduced, the hydrolysis of the water vapor to the packaging adhesive film 210 can be reduced, and the service life of the photovoltaic module can be prolonged to a certain extent.

In other embodiments, the cover 220 may be a composite film formed by laminating and bonding multiple polymer films, and mainly comprises three layers: fluorine-containing film (or glass substitute thereof) +PET layer (or substitute thereof) +EVA adhesive layer adhesive film (containing fluorine-containing film, modified EVA, PE, PET, etc.).

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A method for manufacturing a solar cell, comprising:

providing a substrate having opposite front and back sides, the front side of the substrate having an emitter, the emitter being doped with first dopant ions;

the front sides of the two substrates are opposite to each other, a single-groove double-insertion process is adopted, a semiconductor layer is formed on the back sides of the two substrates at the same time, and a wrapping plating layer is formed on the front sides of the substrates;

forming a mask layer on the front surface after forming the semiconductor layer, wherein the mask layer covers the surface of the around plating layer; performing a doping process for doping a second doping ion into the semiconductor layer to form a conductive doping layer, the first doping ion being different from the second doping ion;

And removing the mask layer and the wrapping coating.

2. The method of claim 1, wherein the doping process is a thermal diffusion process and the doping process is performed at a process temperature of 800 ℃ to 1000 ℃.

3. The method according to claim 1, wherein the doping treatment includes introducing a doping source gas including the second doping ions into the surface of the semiconductor layer, and wherein a flow rate of the doping source gas is 900sccm to 3000sccm.

4. The method of manufacturing according to claim 1, wherein the semiconductor layer is formed by low-pressure chemical vapor deposition.

5. The method of manufacturing according to claim 1, wherein the doping process includes:

and doping the second doping ions in the semiconductor layers on the back surfaces of the two substrates by adopting a single-groove double-insertion process to form the conductive doping layer.

6. The method of claim 5, wherein the doping process forms a wrap-around region in a partial region of the front side of the substrate, the wrap-around region having the second dopant ions therein, the wrap-around region being located in the mask layer and/or the wrap-around layer.

7. The method of manufacturing according to claim 1, wherein the wrap-around layer is also located on the side of the substrate.

8. The method of manufacturing of claim 7, wherein removing the masking layer and the wrap-around layer comprises: immersing the front surface of the substrate in a first cleaning solution to remove at least part of the mask layer and at least part of the around plating layer, wherein the removed around plating layer is at least positioned on the side surface of the substrate;

immersing the front surface of the substrate into a second cleaning solution to remove the mask layer and the wrapping coating.

9. The method of manufacturing according to claim 8, wherein the first cleaning liquid is an acidic cleaning liquid; the second cleaning liquid is alkaline cleaning liquid.

10. The method of claim 1, wherein the mask layer is formed of a material comprising one or more of silicon, silicon nitride, and silicon oxide.

11. The method of manufacturing according to claim 1 or 10, wherein the mask layer is formed to have a thickness of 40nm to 70nm.

12. The method of manufacturing according to claim 1, further comprising, before forming the semiconductor layer on the back surface of the substrate:

And polishing the back surface of the substrate.

13. The method of manufacturing of claim 1, wherein forming the mask layer on the front surface comprises:

and the back surfaces of the two substrates are opposite, and a single-groove double-insertion process is used for simultaneously forming the mask layers on the front surfaces of the two substrates.

14. A solar cell manufactured by the method of manufacturing a solar cell according to any one of claims 1 to 13, comprising:

a substrate having opposite front and back sides, the front side of the substrate having an emitter, the emitter being doped with first dopant ions;

and the conductive doping layer is positioned on the back surface of the substrate.

15. A photovoltaic module, comprising:

a cell string formed by connecting a plurality of solar cells according to claim 14;

the packaging adhesive film is used for covering the surface of the battery string;

and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.