CN116913909A - Optical device, method for manufacturing optical device, and electronic apparatus - Google Patents

Optical device, method for manufacturing optical device, and electronic apparatus Download PDF

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Publication number
CN116913909A
CN116913909A CN202310905848.8A CN202310905848A CN116913909A CN 116913909 A CN116913909 A CN 116913909A CN 202310905848 A CN202310905848 A CN 202310905848A CN 116913909 A CN116913909 A CN 116913909A
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CN
China
Prior art keywords
groove
photosensitive
light
chip
optical device
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CN202310905848.8A
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Chinese (zh)
Inventor
蒙凯
杨望来
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to CN202310905848.8A priority Critical patent/CN116913909A/en
Publication of CN116913909A publication Critical patent/CN116913909A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Led Device Packages (AREA)

Abstract

The embodiment of the application discloses an optical device, a manufacturing method of the optical device and electronic equipment; the optical device comprises a substrate, a photosensitive chip and a light-emitting chip; the substrate is provided with a groove, the bottom of the groove is provided with a spacing part extending towards the notch of the groove, and the bottom of the groove is also provided with a first through hole and a second through hole; the photosensitive chip is arranged in the groove and is propped against the spacing part, the photosensitive chip comprises a non-photosensitive area and a photosensitive area, and the photosensitive area faces the first through hole; and the light emitting chips are stacked in the non-photosensitive area and are separated from the photosensitive area by the spacing parts, and the light emitting chips face the second through holes.

Description

Optical device, method for manufacturing optical device, and electronic apparatus
Technical Field
The application belongs to the technical field of chip packaging, and particularly relates to an optical device, a manufacturing method of the optical device and electronic equipment.
Background
With the continuous development of mobile terminals, wearable devices and artificial intelligence, there is an increasing demand for various optical sensing devices. In the existing optical induction device, the light emitting chip and the photosensitive chip are generally integrated and packaged, and in the current packaging scheme, the light emitting chip and the photosensitive chip are required to be respectively attached to a PCB, and the packaging size is larger due to the large size of the induction chip, so that the packaging thickness is increased, which is unfavorable for the miniaturization development trend of the whole device.
Disclosure of Invention
The application aims to provide an optical device, a manufacturing method of the optical device and electronic equipment, and solves the problem that the size of the existing optical device is bigger after packaging.
In order to solve the technical problems, the application is realized as follows:
in a first aspect, an embodiment of the present application provides an optical device. The optical device includes:
the substrate is provided with a groove, the bottom of the groove is provided with a spacing part extending towards the notch of the groove, and the bottom of the groove is also provided with a first through hole and a second through hole;
the photosensitive chip is arranged in the groove and is propped against the spacing part, the photosensitive chip comprises a non-photosensitive area and a photosensitive area, and the photosensitive area faces the first through hole;
and the light emitting chips are stacked in the non-photosensitive area and are separated from the photosensitive area by the spacing parts, and the light emitting chips face the second through holes.
In a second aspect, an embodiment of the present application provides a method for manufacturing an optical device. The manufacturing method of the optical device comprises the following steps:
providing a substrate, forming a groove on the substrate, wherein a spacing part extending towards a groove opening of the groove is formed at the bottom of the groove, and forming a first through hole and a second through hole at the bottom of the groove;
forming a metal circuit layer on the bottom of the groove, and enabling the metal circuit layer to extend to the outer side of the notch along the groove wall;
stacking the light emitting chips in a non-photosensitive area of the photosensitive chips, arranging the photosensitive chips in the grooves, and enabling the photosensitive chips to abut against one end, close to the notch, of the spacing part so as to enable the light emitting chips to be mutually separated from the photosensitive areas on the photosensitive chips; wherein, the photosensitive area is directed towards the first through hole, and the light emitting chip is directed towards the second through hole; electrically connecting the photosensitive chip and the light emitting chip to the metal circuit layer;
filling light-transmitting materials in the grooves, the first through holes and the second through holes, and filling light-proof materials in the third through holes;
and forming an RDL circuit layer on one side of the substrate provided with the groove, and electrically connecting the metal circuit layer to the RDL circuit layer.
In a third aspect, an embodiment of the present application provides an electronic device. The electronic device comprising an optical device as described in the first aspect.
According to the optical device provided by the embodiment of the application, the light emitting chips are stacked on the non-photosensitive area of the photosensitive chips, so that a chip layout mode of a stacked structure is formed, the space of the photosensitive chips is reasonably utilized to stack and place the light emitting chips, the characteristic of greatly reducing the packaging size can be obtained, and the miniaturization of the whole optical device is facilitated.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is one of the schematic structural diagrams of an optical device provided according to an embodiment of the present application;
FIG. 2 is a second schematic diagram of an optical device according to an embodiment of the present application;
fig. 3 to 8 are flowcharts of a method for manufacturing an optical device according to an embodiment of the present application.
Reference numerals:
1. a substrate; 2. a groove; 3. a spacer; 4. a first through hole; 5. a second through hole; 6. a photosensitive chip; 7. a light receiving surface; 8. a non-photosensitive region; 9. a photosensitive region; 10. a light emitting chip; 11. an RDL line layer; 12. a metal circuit layer; 13. a first electrical connection; 14. a second electrical connection; 15. welding the convex points; 16. a third through hole; 17. a light-transmitting material; 18. an opaque material; 19. a light emitting region; 20. solder balls; 21. a first groove; 22. a second groove; 23. a third groove; 24. a first surface; 25. a second surface.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The features of the application "first", "second" and the like in the description and in the claims may be used for the explicit or implicit inclusion of one or more such features. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
The optical device, the manufacturing method of the optical device and the electronic equipment provided by the embodiment of the application are further described below with reference to the accompanying drawings.
According to one aspect of an embodiment of the present application, an optical device is provided. The optical device may be an optical sensing device such as an infrared photosensitive device that may be used for proximity detection and screen brightness adjustment. Such devices are required for electronic devices having essentially a display screen. The basic principle is as follows: the light is emitted by the light emitting chip, the light is reflected when being blocked, the reflected light enters the light sensing chip, and related signals can be output after the light is received by the light sensing area of the light sensing chip.
Referring to fig. 1 and 2, an optical device provided in an embodiment of the present application includes a substrate 1, a photosensitive chip 6, and a light emitting chip 10. The substrate 1 is provided with a groove 2, a bottom of the groove 2 is provided with a spacing part 3 extending towards a notch of the groove 2, and a first through hole 4 and a second through hole 5 are further arranged at the bottom of the groove 2. The photosensitive chip 6 is arranged in the groove 2, the photosensitive chip 6 is propped against the spacing part 3, the photosensitive chip 6 comprises a non-photosensitive area 8 and a photosensitive area 9, and the photosensitive area 9 faces the first through hole 4. The light emitting chip 10 is stacked on the non-photosensitive area 8 and separated from the photosensitive area 9 by the spacer 3, and the light emitting chip 10 faces the second through hole 5.
According to the optical device provided by the above embodiment of the present application, by stacking the light emitting chips 10 on the non-photosensitive region 8 of the photosensitive chip 6, a 3D stacked chip structure is formed. The design utilizes the characteristic that the size of the photosensitive chip 6 is large, but the area of the photosensitive area 9 on the photosensitive chip only occupies a small part of the total area of the whole photosensitive chip 6, and fully utilizes the space on the photosensitive chip 6 to stack and place the light emitting chips 10, namely fully utilizes the space of the non-photosensitive area 8. Compared with the scheme that the light emitting chip and the photosensitive chip are arranged on the substrate in parallel, the packaging size is greatly reduced.
In addition, in the scheme provided by the embodiment of the application, the photosensitive chip 6 and the light-emitting chip 10 are integrally embedded in the substrate 1 after being stacked, and the thickness space of the substrate 1 is fully utilized to accommodate the chips, so that the thickness dimension of the optical device is not increased, the thickness dimension of the optical device is reduced, and the light and thin design of the optical device can be realized.
On the existing mobile terminal and wearable equipment, due to the limitation of the structural size of the electronic product, the size of the auxiliary optical sensing device is required to be made as small as possible and thinned, and the package size of the device can be effectively reduced just by the scheme provided by the embodiment of the application, so that the electronic product is very suitable for being applied to the electronic products such as the mobile terminal, the wearable equipment and the like.
According to the optical device provided by the embodiment of the application, the light emitting chip 10 is stacked on the non-photosensitive area 8 of the photosensitive chip 6, so that a stacked structure chip layout mode is formed, and the space of the photosensitive chip is reasonably utilized, so that the characteristic of greatly reduced package size can be obtained, and the light and thin and miniaturized whole chip package structure is facilitated. When the optical device provided by the embodiment of the application is applied to the mobile terminal and the wearable equipment, the optical device does not occupy excessive space, and is also beneficial to the layout of other electronic devices.
Referring to fig. 1, the optical device provided by the embodiment of the application has the following working principle: the light-emitting chip 10 can emit light, the light is emitted through the second through hole 5, the light is reflected when being blocked, the reflected light is projected to the photosensitive area 9 of the photosensitive chip 6 through the first through hole 4, and the photosensitive area 9 can output related signals after receiving the light. Thus, the first through hole 4 and the second through hole 5 form a passage through which light passes.
Referring to fig. 1, a spacer 3 is disposed in a groove 2 on a substrate 1, and the spacer 3 can set a space in the whole groove 2 as two cavities, so that a photosensitive area 9 and a non-photosensitive area 8 of a photosensitive chip 6 can be separated, and when the light emitting chip 10 is stacked and disposed in the non-photosensitive area 8 of the photosensitive chip 6, the light emitting chip 10 and the photosensitive area 9 of the photosensitive chip 6 can be separated, so that light can be isolated, and the problem of light crosstalk can be avoided.
In some examples of the present application, referring to fig. 1 and 2, the bottom of the groove 2 is provided with a metal circuit layer 12, the metal circuit layer 12 extends to the outside of the notch along the wall of the groove 2, and the metal circuit layer 12 also extends to the outer wall of the spacer 3; the light sensing chip 6 and the light emitting chip 10 are electrically connected to the metal wiring layer 12.
Fig. 3 shows a side view and a top view, respectively, of the recess 2, the first through hole 4 and the second through hole 5 provided in the substrate 1.
Referring to fig. 3, the grooves 2 on the substrate 1 include a first groove 21, a second groove 22, and a third groove 23; wherein the third groove 23 is located between the first groove 21 and the second groove 22, and the groove depth of the third groove 23 is smaller than the groove depths of the first groove 21 and the second groove 22, the design can form a spacing part 3 extending from the groove bottom to the notch in the groove 2. The spacer 3 may be used to position and support the photosensitive chip 6.
Referring to fig. 3, a first through hole 4 penetrating the substrate 1 is disposed at the bottom of the first groove 21, and is configured to be opposite to the photosensitive region 9 of the photosensitive chip 6, so that light can be incident on the photosensitive region 9 of the photosensitive chip 6 through the first through hole 4. A second through hole 5 penetrating through the substrate 1 is provided at the bottom of the second groove 22, and is configured to face the light emitting chip 10, and the light emitted by the light emitting chip 10 may exit through the second through hole 5.
With continued reference to fig. 3, the surfaces of the bottoms of the first groove 21 and the second groove 22 are defined as a first surface 24, and the surface of the bottom of the third groove 23 is defined as a second surface 25. On this basis, the surface of the bottom of the recess 2 comprises a first surface 24 and a second surface 25. For example, a metal wiring layer 12 is formed on at least the first surface 24, and the metal wiring layer 12 extends along the wall of the groove 2 up to the outside of the notch. The metal wiring layer 12 is also wrapped around the outer wall of the spacer 3.
The metal circuit layer 12 may be used to lead out the electrical connection structure of the photosensitive chip 6 and the light emitting chip 10 embedded in the groove 2, so as to facilitate the electrical connection between the photosensitive chip and the light emitting chip and the external electrical device.
In one example, the stacked photosensitive chips 6 and the light emitting chips 10 are embedded in the groove 2 formed on the substrate 1, the photosensitive chips 6 have a light receiving surface 7, and referring to fig. 1, the light receiving surface 7 is one surface of the photosensitive chips 6, and the light receiving surface 7 faces the surface of the bottom of the groove 2, and since the light emitting chips 10 are located on the light receiving surface 7, the photosensitive chips 6 and the light emitting chips 10 can be electrically connected with the metal circuit layer 12 on the bottom surface of the groove 2 conveniently and in a short distance.
In some examples of the present application, referring to fig. 1 and 2, the first through hole 4 and the second through hole 5 are filled with a light-transmitting material 17, and the light-transmitting material 17 filled in the first through hole 4 and the second through hole 5 forms a light-guiding column.
According to the above example, the photosensitive chip 6 and the light emitting chip 10 are 3D stacked and have a light guiding column.
In the solution provided in the present application, the photosensitive area 9 of the photosensitive chip 6 corresponds to the first through hole 4, the non-photosensitive area 8 of the photosensitive chip 6 is stacked with a light emitting chip 10, the light emitting chip 10 corresponds to the second through hole 5, and light guiding columns can be fabricated at the two through hole positions. The light guiding column in the second through hole 5 may be used to receive the light transmitted by the light emitting chip 10, and the light may be transmitted to the photosensitive area 9 through the light guiding column in the first through hole 4 after being reflected. The use of the light guide column can avoid the loss of light in the propagation, increase the light-emitting rate of the light-emitting chip 10, and improve the light efficiency.
Optionally, the first through hole 4 and the second through hole 5 are respectively filled with a light-permeable filler. This design avoids the introduction of foreign bodies into the recess 2 during the encapsulation of the optical device.
Alternatively, the light-transmitting material 17 is, for example, a resin material that can transmit light.
In some examples of the present application, referring to fig. 2, the end surface of the light guiding column away from the photosensitive chip 6 is an arc-shaped end surface.
According to the above example, after the first through hole 4 and the second through hole 5 are filled with the light-permeable filler to form the light guide column, the end surface of the light guide column away from the photosensitive chip 6 may be designed to be an arc-shaped end surface, as shown in fig. 2. The design may increase the Field of View (FOV) of the device.
Of course, the end surface of the light guide pillar away from the photosensitive chip 6 may be a plane, see fig. 1, which is only an example.
In some examples of the present application, referring to fig. 1 and 2, the optical device further includes an RDL circuit layer 11, where the RDL circuit layer 11 is located on a side of the substrate 1 where the groove 2 is located, the groove 2 is filled with a light-transmitting material 17, and the RDL circuit layer 11 covers a notch of the groove 2; the photosensitive chip 6 and the light emitting chip 10 are electrically connected with the RDL circuit layer 11 through the metal circuit layer 12, respectively.
According to the above example, the 3D stacked photosensitive chip 6 and the light emitting chip 10 are embedded in the substrate 1 with the groove 2, and the RDL circuit layer 11 is fabricated on the back surface of the photosensitive chip 6, so that the wafer-level size packaging of the optical device is realized, the size of the optical device in the thickness direction can be greatly reduced, and the formed optical device can be made to be lighter and thinner.
The RDL routing layer is also referred to as a rewiring layer (Redistribution Layer). The RDL circuit layer is, for example, a metal layer and a dielectric layer deposited on the wafer surface and corresponding metal wiring patterns are formed, so as to re-layout the I/O ports of the packaged chip.
According to the above example, a light-permeable filler may be filled in the recess 2 of the substrate 1. It should be noted that the filler in the recess 2 may be the same as the filler in the first through hole 4 and the second through hole 5, so that the packaging process may be simplified. Besides, the light-permeable filler filled in the groove 2 can also have a good protection effect on the 3D stacked photosensitive chip 6 and the light-emitting chip 10.
In some examples of the present application, referring to fig. 1 and 5, the photosensitive chip 6 is disposed in the groove 2, and the photosensitive chip 6 abuts against one end of the spacer 3 near the notch; the photosensitive region 9 is electrically connected to the metal wiring layer 12 through a first electrical connection portion 13, and the light emitting chip 10 is electrically connected to the metal wiring layer 12 through a second electrical connection portion 14.
In one example, the photosensitive chip 6 is horizontally disposed in the groove 2 on the substrate 1, one surface of the photosensitive chip 6 is a light receiving surface 7, and referring to fig. 1, the light receiving surface 7 is horizontally disposed downward to face the bottom of the groove 2, and the light receiving surface 7 abuts against one end of the spacer 3 near the notch. Referring to fig. 5, the spacing portion 3 separates the control in the recess 2 into a first cavity and a second cavity, the photosensitive area 9 is located in the first cavity, the non-photosensitive area 8 and the light emitting chip 10 are stacked and located in the second cavity, and the bottoms of the first cavity and the second cavity are both provided with the metal circuit layer 12. The periphery of the photosensitive region 9 may be electrically connected to the metal circuit layer 12 on the bottom of the first cavity through a plurality of first electrical connection portions 13, and the surface of the light emitting chip 10 facing away from the non-photosensitive region 8 is electrically connected to the metal circuit layer 12 on the bottom of the second cavity through a plurality of second electrical connection portions 14.
The space part 3 in the groove 2 can play a role in positioning and supporting the photosensitive chip 6, meanwhile, the space part 3 can divide the groove 2 into two cavities and respectively accommodate the photosensitive area 9 on the photosensitive chip 6 and the light-emitting chip 10 stacked in the non-photosensitive area 8, so that the photosensitive area 9 and the light-emitting chip 10 can be mutually separated, light can be effectively isolated, and the problem that the measurement precision is affected due to mutual crosstalk between light is avoided.
The light emitting chip 10 includes a light emitting area 19, referring to fig. 5, the light emitting area 19 is disposed on a supporting layer, and the supporting layer may be directly attached to the non-light sensing area 8 of the light sensing chip 6 and electrically connected to the metal circuit layer 12 through the second electrical connection portion 14.
In some examples of the present application, the first electrical connection portion 13 and the second electrical connection portion 14 are solder balls or metal pieces.
For the photosensitive chip 6, the light emitting chips 10 may be stacked on the non-photosensitive region 8 thereon, for example, by mounting. The non-photosensitive region 8 may be electrically connected to the metal circuit layer 12 by, for example, at least one solder ball, and the light emitting chip 10 may be connected to the metal circuit layer 12 by, for example, at least one solder ball. Wherein, the solder balls are solder balls.
Of course, the first electrical connection portion 13 and the second electrical connection portion 14 may also be metal pieces to achieve electrical conduction between different functional devices.
In some examples of the present application, a plurality of solder bumps 15 are disposed on the RDL routing layer 11, and each solder bump 15 is led with a solder ball 20.
According to the above example, a plurality of solder bumps 15 are disposed at intervals on the RDL wiring layer 11, and each solder bump 15 may lead out one solder ball 20 for electrical connection with an external device.
The RDL routing layer 11 may re-route the I/O ports of the packaged stacked chips.
In some examples of the present application, a third through hole 16 is provided on the spacer 3, and the third through hole 16 is filled with an opaque material 18 to form a barrier layer between the light emitting chip 10 and the photosensitive region 9.
In the traditional scheme, a light emitting chip and a light sensing chip are respectively attached to the same substrate, transparent adhesive tapes are covered above a light sensing area of the light sensing chip and the light emitting chip for protection, two glue injection openings are formed in the substrate, black glue flows into the substrate through the glue injection openings to seal the chips in a plastic mode, and the black glue is used for separating the light sensing area from the light emitting chip. However, there is a greater thermal stress inside the package due to the difference between the thermal expansion coefficients CTE (Coefficient of thermal expansion) of the two colloids, which presents a reliability risk. In addition, the two plastic packages have the technological risks of colloid rupture, glue overflow and the like, and the requirement on the die is high.
According to the above example, the present application is configured such that the protruding spacer 3 is designed in the groove 2, and the third through hole 16 on the spacer 3 is filled with the light-impermeable material 18, so that a blocking layer is formed between the light emitting chip 10 and the photosensitive region 9, thereby more effectively isolating light and avoiding the problem of crosstalk. Meanwhile, the defects caused by the traditional scheme can be avoided, the difficulty of a packaging process can be reduced, and the product yield is improved.
In some examples of the application, the substrate 1 is a silicon plate.
According to the optical device provided by the embodiment of the application, the 3D stacked chip is placed in the silicon-based carrier plate provided with the groove 2, and is led out through the metal circuit layer 12, and the RDL circuit layer 11 is manufactured on the back surface of the photosensitive chip 6, so that wafer-level size packaging is realized.
According to another embodiment of the present application, a method for manufacturing an optical device is provided, which can be used to manufacture the optical device mentioned in the above embodiment, and the optical device formed can be seen in fig. 1 and 2.
In the optical device shown in fig. 1, the end surfaces of the light guide columns formed in the first through hole 4 and the second through hole 5, which are far away from the photosensitive chip 6, are planes. In the optical device shown in fig. 2, the end surfaces of the light guide columns formed in the first through hole 4 and the second through hole 5, which are far away from the photosensitive chip 6, are arc-shaped end surfaces.
Referring to fig. 3 to 8, the method for manufacturing an optical device according to the embodiment of the present application includes:
step 1, providing a substrate 1 and forming a groove 2 on the substrate 1, wherein a spacer 3 extending towards the notch of the groove 2 is formed at the bottom of the groove 2, and a first through hole 4, a second through hole 5 and a third through hole 16 are formed at the bottom of the groove 2, see fig. 3.
Fig. 3 shows a cross-sectional view and a plan view, which have a correspondence relationship.
In step 1, the substrate 1 is, for example, a silicon plate.
When the groove 2 is formed on the substrate 1, in order to form the spacer 3 extending from the groove bottom to the notch in the groove 2, three grooves may be formed, namely, a first groove 21 and a second groove 22 located at two sides, and a third groove 23 located between the first groove 21 and the second groove 22, where the groove depth of the third groove 23 is smaller than the first groove 21 and the second groove 22 at two sides. In this way, a third groove 23 communicating both of the first groove 21 and the second groove 22 is formed, while a spacer 3 separating the first groove 21 and the second groove 22 is also formed.
The first recess 21 may form a first cavity for accommodating the light sensing region 9 of the light sensing chip 6, and the second recess 22 may form a second cavity for accommodating the light emitting chip 10.
Wherein, the first through hole 4 and the second through hole 5 can pass light. The first through-hole 4 communicates, for example, with the first recess 21, and the second through-hole 5 communicates, for example, with the second recess 22.
Step 2, referring to fig. 4, a metal circuit layer 12 is formed on the bottom of the groove 2, and the metal circuit layer 12 extends to the outside of the notch along the groove wall.
Specifically, a metal wiring layer 12 is formed on the bottom surface of the recess 2, and the metal wiring layer 12 is also designed to extend along the wall of the recess 2 up to the upper surface of the substrate 1. The metal wiring layer 12 is also wrapped around the outer wall of the spacer 3. The metal circuit layer 12 may lead out the electrical connection structure of each chip embedded in the groove 2.
Step 3, referring to fig. 5, stacking the light emitting chips 10 on the non-photosensitive area 8 of the photosensitive chip 6, disposing the photosensitive chip 6 in the groove 2, and abutting the photosensitive chip 6 against one end of the spacer 3 near the notch, so that the light emitting chips 10 are separated from the photosensitive area 9 on the photosensitive chip 6; wherein the photosensitive region 9 is directed to the first through hole 4, and the light emitting chip 10 is directed to the second through hole 5; the photosensitive chip 6 and the light emitting chip 10 are electrically connected to the metal wiring layer 12.
According to the step 3, the light emitting chips 10 are stacked in the non-photosensitive area 8 of the photosensitive chip 6, and the stacked chip assembly is embedded in the recess 2, wherein the light emitting chips 10 and the photosensitive area 9 of the photosensitive chip 6 are respectively opposite to the first through hole 4 and the second through hole 5 at the bottom of the recess 2. In this way, the light emitted from the light emitting area of the light emitting chip 10 can be conducted through the second through hole 5, reflected and projected to the light sensing area 9 through the first through hole 4.
Step 4, referring to fig. 6 and 7, a light-transmitting material is filled in the groove 2, the first through hole 4 and the second through hole 5, and a light-impermeable material is filled in the third through hole 16.
Wherein, the first through hole 4 and the second through hole 5 are filled with a light-permeable filler, and at this time, the filler in the two through holes becomes a light guide column.
For example, referring to fig. 6, the end surface of the light guide pillar, which is formed away from the photosensitive chip 6, is a plane.
For another example, referring to fig. 7, the end surface of the light guiding column far from the photosensitive chip 6 is an arc-shaped end surface.
Preferably, the end surface of the formed light guide column far away from the photosensitive chip 6 is an arc end surface, which is equivalent to forming a convex lens, so as to facilitate increasing the field angle FOV of the device, see fig. 7.
Wherein, the third through hole 16 is filled with a light-proof filler to form a barrier layer. Thus, the non-photosensitive area 8 and the photosensitive area 9 of the photosensitive chip 6 can be better optically isolated, and optical crosstalk is avoided.
And 5, forming an RDL circuit layer 11 on one side of the substrate 1 provided with the groove 2, and electrically connecting the metal circuit layer 12 to the RDL circuit layer.
According to the above step 5, an RDL wiring layer 11 covering the recess 2 is formed on the substrate 1, and solder bumps 15 for electrical connection are disposed at different positions on the RDL wiring layer 11 and solder balls are fabricated to facilitate electrical connection with external electrical devices.
According to yet another embodiment of the present application, an electronic device is provided.
The electronic device comprises an optical device as described above.
The electronic device may include, for example, a mobile terminal, a wearable device, and the like.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.

Claims (12)

1. An optical device, comprising:
the substrate is provided with a groove, the bottom of the groove is provided with a spacing part extending towards the notch of the groove, and the bottom of the groove is also provided with a first through hole and a second through hole;
the photosensitive chip is arranged in the groove and is propped against the spacing part, the photosensitive chip comprises a non-photosensitive area and a photosensitive area, and the photosensitive area faces the first through hole;
and the light emitting chips are stacked in the non-photosensitive area and are separated from the photosensitive area by the spacing parts, and the light emitting chips face the second through holes.
2. The optical device according to claim 1, wherein a bottom of the groove is provided with a metal wiring layer extending along a wall of the groove to an outside of the notch, the metal wiring layer further extending to an outer wall of the spacer;
the photosensitive chip and the light emitting chip are electrically connected to the metal circuit layer.
3. The optical device of claim 1, wherein the first and second through holes are filled with a light transmissive material, and wherein the light transmissive material filled in the first and second through holes forms a light guide post.
4. The optical device of claim 3, wherein an end surface of the light guide post remote from the light sensing chip is an arc-shaped end surface.
5. The optical device of claim 2, further comprising an RDL routing layer on a side of the substrate where the grooves are located, the grooves being filled with a light transmissive material, the RDL routing layer covering the notches of the grooves;
the photosensitive chip and the light emitting chip are respectively and electrically connected with the RDL circuit layer through the metal circuit layer.
6. The optical device of claim 5, wherein the light sensing chip is disposed within the recess and the light sensing chip abuts an end of the spacer adjacent the notch;
the light-sensitive area is electrically connected with the metal circuit layer through a first electric connection part, and the light-emitting chip is electrically connected with the metal circuit layer through a second electric connection part.
7. The optical device of claim 6, wherein the first electrical connection and the second electrical connection are solder balls or metal pieces.
8. An optical device as claimed in claim 6, wherein a plurality of solder bumps are provided on the RDL routing layer, each solder bump having a solder ball lead.
9. An optical device as claimed in claim 1, wherein a third through hole is provided in the spacer, and the third through hole is filled with an opaque material to form a barrier layer between the light emitting chip and the light sensing region.
10. The optical device of claim 1, wherein the substrate is a silicon plate.
11. A method of fabricating an optical device according to any one of claims 1 to 10, comprising:
providing a substrate, forming a groove on the substrate, wherein a spacing part extending towards a groove opening of the groove is formed at the bottom of the groove, and forming a first through hole, a second through hole and a third through hole at the bottom of the groove;
forming a metal circuit layer on the bottom of the groove, and enabling the metal circuit layer to extend to the outer side of the notch along the groove wall;
stacking the light emitting chips in a non-photosensitive area of the photosensitive chips, arranging the photosensitive chips in the grooves, and enabling the photosensitive chips to abut against one end, close to the notch, of the spacing part so as to enable the light emitting chips to be mutually separated from the photosensitive areas on the photosensitive chips; wherein, the photosensitive area is directed towards the first through hole, and the light emitting chip is directed towards the second through hole; electrically connecting the photosensitive chip and the light emitting chip to the metal circuit layer;
filling light-transmitting materials in the grooves, the first through holes and the second through holes, and filling light-proof materials in the third through holes;
and forming an RDL circuit layer on one side of the substrate provided with the groove, and electrically connecting the metal circuit layer to the RDL circuit layer.
12. An electronic device, comprising:
the optical device of any one of claims 1-10.
CN202310905848.8A 2023-07-21 2023-07-21 Optical device, method for manufacturing optical device, and electronic apparatus Pending CN116913909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310905848.8A CN116913909A (en) 2023-07-21 2023-07-21 Optical device, method for manufacturing optical device, and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310905848.8A CN116913909A (en) 2023-07-21 2023-07-21 Optical device, method for manufacturing optical device, and electronic apparatus

Publications (1)

Publication Number Publication Date
CN116913909A true CN116913909A (en) 2023-10-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310905848.8A Pending CN116913909A (en) 2023-07-21 2023-07-21 Optical device, method for manufacturing optical device, and electronic apparatus

Country Status (1)

Country Link
CN (1) CN116913909A (en)

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