CN116913905A - Multi-chip stacking packaging structure and packaging method thereof - Google Patents

Multi-chip stacking packaging structure and packaging method thereof Download PDF

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Publication number
CN116913905A
CN116913905A CN202311027864.8A CN202311027864A CN116913905A CN 116913905 A CN116913905 A CN 116913905A CN 202311027864 A CN202311027864 A CN 202311027864A CN 116913905 A CN116913905 A CN 116913905A
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China
Prior art keywords
chip
functional area
electrically connected
substrate
sub
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CN202311027864.8A
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Chinese (zh)
Inventor
柳家乐
岳茜峰
邱冬冬
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Changjiang Electronics Technology Chuzhou Co Ltd
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Changjiang Electronics Technology Chuzhou Co Ltd
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Priority to CN202311027864.8A priority Critical patent/CN116913905A/en
Publication of CN116913905A publication Critical patent/CN116913905A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a multi-chip stacked package structure and a forming method, the multi-chip stacked package structure comprises: a substrate having a bearing surface; the first chip is arranged on the bearing surface and is electrically connected with the substrate, and one surface of the first chip, which is away from the substrate, is provided with a first functional area and a second functional area which is arranged at the periphery of the first functional area; the second chip is arranged on the first chip, a surface of the second chip, which is away from the first chip or faces the first chip, is provided with a third functional area, the second chip covers the first functional area of the first chip, the third functional area is electrically connected with the first functional area, and the second functional area is exposed to the second chip; the third chip is arranged on the second chip in a flip-chip manner, is electrically connected with the third functional area of the second chip and is electrically connected with the second functional area of the first chip; the plastic package body covers the bearing surface of the substrate and covers the first chip, the second chip and the third chip, and at least part of the top surface of the third chip is exposed to the plastic package body.

Description

Multi-chip stacking packaging structure and packaging method thereof
Technical Field
The present invention relates to the field of semiconductor packaging, and in particular, to a multi-chip stacked package structure and a packaging method thereof.
Background
With the development of electronic technology, miniaturization of size, high integration of structure and function have become a trend of electronic components. Currently, a three-dimensional (3D) stacking technology is widely used, that is, a chip is stacked on the front surface of a substrate, and then interconnection between chips is completed by means of bonding wires. However, in the three-dimensional stacked package structure formed by the technology, the stacked area of the lower chip is blocked by the upper chip, so that the stacked area of the lower chip cannot be provided with a functional area, and the functional high integration of the product is affected; in addition, the packaging structure only dissipates heat at the substrate side, namely, only one-side heat dissipation can be realized, the heat dissipation performance is poor, the impedance of the packaging structure is increased due to heating of the packaging structure, and the electrical performance of the packaging structure is affected.
Therefore, the utilization rate of chips in the stacked package structure and the heat dissipation performance of the stacked package structure are improved, and the method has important significance for the development of high integration of the stacked package structure.
Disclosure of Invention
An embodiment of the present invention provides a multi-chip stacked package structure, including:
a substrate having a bearing surface;
the first chip is arranged on the bearing surface and is electrically connected with the substrate, and one surface of the first chip, which is away from the substrate, is provided with a first functional area and a second functional area which is arranged at the periphery of the first functional area;
The second chip is arranged on the first chip, a surface of the second chip, which is away from the first chip or faces the first chip, is provided with a third functional area, the second chip covers the first functional area of the first chip, the third functional area is electrically connected with the first functional area, and the second functional area is exposed to the second chip;
the third chip is arranged on the second chip in a flip-chip manner, and is electrically connected with the third functional area of the second chip and the second functional area of the first chip;
and the plastic package body covers the bearing surface of the substrate and covers the first chip, the second chip and the third chip, and at least part of the top surface of the third chip is exposed to the plastic package body.
In an embodiment, the second chip further includes a through silicon via penetrating the second chip, and the third chip is further electrically connected to the first functional region of the first chip through the through silicon via.
In an embodiment, the multi-chip stacked package structure further includes an elastic ring, the elastic ring is disposed on a top surface of the third chip and has elasticity along a direction perpendicular to the top surface of the third chip, the plastic package body covers an outer portion of the elastic ring, and an inner portion of the elastic ring exposes the top surface of the third chip.
In one embodiment, the elastic ring includes:
the first annular piece is fixed on the top surface of the third chip;
the second annular piece is arranged opposite to the first annular piece in the direction perpendicular to the top surface of the third chip;
the annular side piece extends along the direction vertical to the top surface of the third chip and has elasticity in the direction vertical to the top surface of the third chip, and the annular side piece is arranged between the first annular piece and the second annular piece so as to connect and support the first annular piece and the second annular piece;
and the plastic package body is filled in the space among the first annular piece, the second annular piece and the annular side piece outside the elastic ring.
In an embodiment, the multi-chip stack package structure further includes a conductive strip, and the third chip is electrically connected to the second functional region of the first chip through the conductive strip.
In an embodiment, one end of the conductive strip is electrically connected to the second functional area of the first chip, the other end is fixed on the surface of the second chip facing away from the first chip, and the bonding pad of the third chip is electrically connected to the other end of the conductive strip.
In an embodiment, the multi-chip stacked package structure further includes a conductive lead, one end of the conductive lead is electrically connected to the second functional area of the first chip, and the other end of the conductive lead is electrically connected to the substrate.
In an embodiment, the plastic package further includes:
the first sub-plastic package body covers the bearing surface of the substrate and covers the first chip and the second chip;
the second sub-plastic package body covers the first sub-plastic package body and coats the third chip, and part of the top surface of the third chip is exposed to the second sub-plastic package body.
In an embodiment, the multi-chip stacked package structure further includes a redistribution layer, the redistribution layer is disposed on a surface of the second chip facing away from the first chip and electrically connected to at least a portion of the third functional area of the second chip, the third chip is disposed on the redistribution layer and electrically connected to the second chip through the redistribution layer, and the plastic package further covers the redistribution layer.
Another embodiment of the present invention further provides a packaging method of a multi-chip stacked package structure, including:
providing a substrate, wherein the substrate is provided with a bearing surface;
A first chip and a second chip are arranged, the first chip is arranged on the bearing surface and is electrically connected with the substrate, one surface of the first chip, which is away from the substrate, is provided with a first functional area and a second functional area which is arranged on the periphery of the first functional area, the second chip is arranged on the first chip, one surface of the second chip, which is away from the first chip, or one surface of the second chip, which is towards the second chip, is provided with a third functional area, the second chip covers the first functional area of the first chip, the third functional area is electrically connected with the first functional area, and the second functional area is exposed to the second chip;
a third chip is arranged on the second chip in a flip-chip manner, and is electrically connected with the third functional area of the second chip and the second functional area of the first chip;
and (3) plastic packaging to form a plastic packaging body, wherein the plastic packaging body covers the bearing surface of the substrate and covers the first chip, the second chip and the third chip, and part of the top surface of the third chip is exposed to the plastic packaging body.
In one embodiment, the step of disposing the first chip and the second chip includes:
Mounting the first chip on the bearing surface of the substrate;
flip-chip mounting the second chip on the first chip, wherein a bonding pad on the surface of the second chip facing the first chip is electrically connected with the first functional area of the first chip;
and electrically connecting the second functional area of the first chip with the substrate through a conductive lead by adopting a wire bonding process.
In an embodiment, the second chip further includes a through silicon via penetrating the second chip, and in the step of flip-chip mounting the second chip on the first chip, the first functional region of the first chip is further electrically connected to the through silicon via;
in the step of disposing the third chip, the third chip is further electrically connected to the first functional region of the first chip through the through silicon via.
In an embodiment, before or after the step of electrically connecting the second functional area of the first chip and the substrate through the conductive wire using a wire bonding process, the method further includes:
the area, which needs to be electrically connected with a third chip, of the second functional area of the first chip is led out to the surface, which is away from the first chip, of the second chip through a conductive strip by adopting a strip bonding process;
In the step of disposing the third chip, the third chip is electrically connected to the conductive strip for electrically connecting to the second functional region of the first chip.
In an embodiment, the step of disposing the first chip and the second chip further includes: forming a rewiring layer, wherein the rewiring layer is arranged on the surface, away from the first chip, of the second chip and is electrically connected with at least part of the third functional area of the second chip;
the step of providing a third chip includes: the third chip is arranged on the rewiring layer and is electrically connected with the second chip through the rewiring layer.
In one embodiment, the step of disposing the first chip and the second chip includes: performing primary plastic packaging to form a first sub-plastic packaging body, wherein the first sub-plastic packaging body covers the bearing surface of the substrate and coats the first chip and the second chip;
after the first sub-plastic package body is formed, executing the step of setting the third chip;
the step of disposing the third chip further includes: and performing secondary plastic packaging to form a second sub-plastic packaging body, wherein the second sub-plastic packaging body covers the first sub-plastic packaging body and coats the third chip, part of the top surface of the third chip is exposed to the second sub-plastic packaging body, and the first sub-plastic packaging body and the second sub-plastic packaging body form the plastic packaging body.
In an embodiment, the step of forming the molded body further includes:
an elastic ring is arranged on the top surface of the third chip, and the elastic ring is arranged on the top surface of the third chip and has elasticity along the direction perpendicular to the top surface of the third chip;
and in the step of forming the plastic package body, the plastic package material covers the outer part of the elastic ring, and the inner part of the elastic ring exposes the top surface of the third chip.
In the package structure provided by the embodiment of the invention, the first chip is provided with the functional area (namely, the second functional area which is not shielded by the second chip and can be at least electrically connected with the third chip) and the functional area (namely, the first functional area which is at least electrically connected with the second chip) in the area shielded by the second chip (namely, the stacking area), so that the utilization rate of the chips in the package structure is improved, and the high integration of the functions of the package structure is facilitated; meanwhile, the third chip is arranged on the surface of the second chip in a flip-chip manner and can be electrically connected with the second functional area of the first chip and the third functional area of the second chip, so that the number of stacked chips is increased, and the high integration of the functions of the packaging structure is facilitated; and at least part of the top surface of the third chip is exposed to the plastic package body, so that the multi-chip stacked package structure can dissipate heat through the substrate and the top surface of the third chip, namely, double-sided heat dissipation can be realized, the heat dissipation performance of the multi-chip stacked package structure is greatly improved, and the electrical performance of the multi-chip stacked package structure is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a multi-chip stacked package structure according to an embodiment of the present invention;
FIG. 2 is a top view of a spring ring in a multi-chip stacked package structure according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view taken along line A-A1 of FIG. 2;
FIG. 4 is a schematic diagram illustrating steps of a method for forming a chip stack package structure according to an embodiment of the present invention;
fig. 5A to 5I are process flow diagrams of a method for forming a multi-chip stacked package structure according to an embodiment of the invention.
Detailed Description
The following describes in detail the specific embodiments of the multi-chip stacked package structure and the package method thereof provided by the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a multi-chip package-on-package structure according to an embodiment of the invention, referring to fig. 1, the multi-chip package-on-package structure includes a substrate 100, a first chip 110, a second chip 120, a third chip 130, and a plastic package 140. The substrate 100 has a bearing surface 100A. The first chip 110 is disposed on the carrying surface 100A and electrically connected to the substrate 100, and a surface of the first chip 110 facing away from the substrate 100 has a first functional area 111 and a second functional area 112 disposed at a periphery of the first functional area 111. The second chip 120 is disposed on the first chip 110, and the second chip 120 covers the first functional area 111 of the first chip 110 and is electrically connected to the first functional area 111, the second functional area 112 is exposed to the second chip 120, and a surface of the second chip 120 facing away from the first chip 110 has a third functional area 121. The third chip 130 is flip-chip disposed on the second chip 120, and the third chip 130 is electrically connected to the third functional region 121 of the second chip 120 and electrically connected to the second functional region 112 of the first chip 110. The plastic package body 140 covers the carrying surface 100A of the substrate 100, and encapsulates the first chip 110, the second chip 120 and the third chip 130, and a portion of the top surface of the third chip 130 is exposed to the plastic package body 140.
In the package structure provided in the embodiment of the present invention, the first chip 110 is provided with a functional area (i.e., the second functional area 112) in an area not covered by the second chip 120, where the second functional area 112 can be at least electrically connected with the third chip 130, and is also provided with a functional area (i.e., the first functional area 111) in an area covered by the second chip 120 (i.e., the stacking area), where the first functional area 111 can be at least electrically connected with the second chip 120, so that the utilization rate of chips in the package structure is improved, and the high integration of the functions of the package structure is facilitated; meanwhile, the third chip 130 is flip-chip arranged on the surface of the second chip 120, and can be electrically connected with the second functional area 112 of the first chip 110 and the third functional area 121 of the second chip 120, so that the number of stacked chips is increased, and the high integration of the functions of the package structure is facilitated; and, at least part of the top surface of the third chip 130 is exposed to the plastic package body 140, so that the multi-chip stacked package structure can dissipate heat through the top surfaces of the substrate 100 and the third chip 130, i.e. can realize double-sided heat dissipation, thereby greatly improving the heat dissipation performance of the multi-chip stacked package structure and the electrical performance of the multi-chip stacked package structure.
The substrate 100 may be a conventional ceramic substrate, or a lead frame, or a laminated substrate, or a MIS (Molded Interconnect System) plastic package interconnection substrate, or a redistribution stack layer, etc., and has a relatively flat upper surface and a lower surface with an electrically conductive circuit layer therebetween. In this embodiment, the upper surface of the substrate 100 is the carrying surface 100A for carrying a chip.
The first chip 110 can implement the related functions of the package structure. The first chip 110 includes a back surface and a front surface provided with a circuit; in the present embodiment, the back surface of the first chip 110 is fixed on the carrying surface 100A of the substrate 100 by a Surface Mount Technology (SMT); the front surface of the first chip 110 is a surface of the first chip 110 facing away from the substrate 100, and has a first functional area 111 and a second functional area 112 disposed at the periphery of the first functional area 111. The first functional area 111 and the second functional area 112 each have a plurality of pads for electrically leading out the circuit on the front side of the first chip 110. It will be appreciated that in some embodiments, the first functional region 111 and the second functional region 112 are only used to distinguish different regions of the front surface of the first chip 110, and no actual isolation line exists on the surface of the first chip 110.
In some embodiments, the functional area of the first chip 110 is electrically connected to the substrate 100, for example, the functional area of the first chip 110 is electrically connected to the substrate 100 through conductive leads 150 or conductive strips. In this embodiment, the multi-chip stacked package structure further includes a conductive lead 150, where one end of the conductive lead 150 is electrically connected to the second functional area 112 of the first chip 110, and the other end is electrically connected to the substrate 100, so as to electrically connect the second functional area 112 of the first chip 110 to the substrate 100. Further, in the present embodiment, one end of the conductive lead 150 is electrically connected to the pad of the second functional region 112 of the first chip 110, and the other end of the conductive lead 150 is electrically connected to the pad of the substrate 100. The conductive leads 150 include, but are not limited to, metal leads such as gold wires, copper wires, aluminum wires.
The second chip 120 can implement the related functions of the package structure. The second chip 120 includes a back surface and a front surface provided with a circuit; in this embodiment, the second chip 120 is disposed on the front surface of the first chip 110 by flip chip (flip chip), where the surface of the second chip 120 facing the first chip 110 is the front surface of the second chip 120, and a third functional area 121 is disposed on the front surface, that is, the surface of the second chip 120 facing the first chip 110 has the third functional area 121; the surface of the second chip 120 facing away from the first chip 110 is a back surface of the second chip 120, and a pad is disposed on the back surface, where the pad can be electrically connected to the circuit of the third functional area 121 through a conductive interconnection layer disposed in the second chip 120. A plurality of bonding pads are further disposed on the front surface of the third functional area 121, and are used for electrically leading out the circuit on the front surface of the second chip 120.
In another embodiment, a surface of the second chip 120 facing away from the first chip 110 has the third functional area 121, that is, the second chip 120 is disposed on the front surface of the first chip 110 by flip chip (flip chip) technology, the surface of the second chip 120 facing toward the first chip 110 is a back surface of the second chip 120, and the surface of the second chip 120 facing away from the first chip 110 is a front surface of the second chip 120.
In this embodiment, the second chip 120 further includes a through silicon via (Through Silicon Via, TSV) 122 penetrating through the second chip 120, and the through silicon via 122 penetrates from the front surface of the second chip 120 to the back surface of the second chip 120, so that the chip or the conductive structure disposed on the back surface of the second chip 120 can be electrically connected with the chip or the conductive structure disposed on the front surface of the second chip 120 through the through silicon via 122.
The third chip 130 can perform the related functions of the package structure. The third chip 130 includes a back surface and a front surface provided with a circuit; in this embodiment, the third chip 130 is disposed on the back surface of the second chip 120 by flip chip (flip chip), the surface of the third chip 130 facing the second chip 120 is the front surface of the third chip 130, a fourth functional area 131 is disposed on the front surface, and a plurality of pads are further disposed in the fourth functional area 131 for electrically leading out the circuit on the front surface of the third chip 130, and the fourth functional area 131 may be electrically connected to the third functional area 121 of the second chip 120 through the pads; the surface of the third chip 130 facing away from the second chip 120 is the back surface of the third chip 130 (i.e., the top surface of the third chip 130), which is at least partially exposed to the plastic package body 140, so as to serve as a heat dissipation surface of the multi-chip stacked package structure, thereby improving the heat dissipation performance of the multi-chip stacked package structure.
In some embodiments, the third chip 130 is electrically connected to the second functional region 112 of the first chip 110. For example, the third chip 130 is electrically connected to a region of the second functional region 112 that is not electrically connected to the substrate 100.
In some embodiments, the third chip 130 is electrically connected to the second functional region 112 of the first chip 110 by conductive leads or strips. In this embodiment, the third chip 130 is electrically connected to the second functional region 112 of the first chip 110 through a conductive strip 160. Specifically, the multi-chip stack package structure further includes a conductive strip 160, and the third chip 130 is electrically connected to the second functional region 112 of the first chip 110 through the conductive strip 160. The conductive strip 160 is used to connect the third chip 130 and the second chip 120, so as to reduce the package resistance of the package structure and improve the electrical performance of the package structure. The conductive strips 160 include, but are not limited to, metal strips, e.g., gold strips, copper strips, aluminum strips.
Further, in this embodiment, one end of the conductive strip 160 is electrically connected to the second functional area 112 of the first chip 110, the other end is fixed on the surface of the second chip 120 facing away from the first chip 110, and the bonding pad of the third chip 130 is electrically connected to the other end of the conductive strip 160, so that the second chip 120 can be used to support the conductive strip 160, thereby improving the reliability of the multi-chip stacked package structure.
The plastic package 140 is used to protect the package structure from physical damage and corrosion, and its materials include, but are not limited to, plastics or epoxy compounds. In this embodiment, the molding body 140 includes two parts, which are formed in different molding steps, respectively. Specifically, the plastic package body 140 includes a first sub-plastic package body 141 and a second sub-plastic package body 142; the first sub-plastic package 141 covers the carrying surface 100A of the substrate 100 and encapsulates the first chip 110 and the second chip 120; the second sub-plastic package body 142 covers the first sub-plastic package body 141 and encapsulates the third chip 130, and a portion of the top surface of the third chip 130 is exposed to the second sub-plastic package body 142.
The top surface of the third chip 130 is not covered by the plastic package body 140, so that the multi-chip stacked package structure can dissipate heat through the top surface of the third chip 130 and the substrate 100, thereby increasing the heat dissipation area of the multi-chip stacked package structure and improving the heat dissipation performance of the multi-chip stacked package structure.
In this embodiment, the multi-chip stack package structure further includes an elastic ring 170, where the elastic ring 170 is disposed on the top surface of the third chip 130 and has elasticity along a direction perpendicular to the top surface of the third chip 130 (e.g. the Z direction in the drawing), the plastic package body 140 covers the outer portion of the elastic ring 170, and the inner portion of the elastic ring 170 exposes the top surface of the third chip 130. The multi-chip stacked package structure limits the plastic package body 140 through the arrangement of the elastic ring 170, so that a partial area of the top surface of the third chip 130 is not covered by the plastic package body 140, and further, the heat dissipation area of the multi-chip stacked package structure is increased. In this embodiment, the elastic ring 170 is in a closed structure, so that the plastic package body 140 is blocked by the elastic ring 170 and cannot enter the space enclosed by the elastic ring 170, thereby avoiding the top surface of the third chip 130 from being covered by the plastic package body 140.
In some embodiments, the elastic ring 170 is a metal ring, and the heat dissipation performance of the metal is better than that of the plastic package, so that the heat inside the multi-chip stacked package structure can be further dissipated through the elastic ring 170.
The elastic ring 170 having elasticity in a direction perpendicular to the top surface of the third chip 130 means that the elastic ring 170 itself has elasticity in a direction perpendicular to the top surface of the third chip 130, and in some embodiments, after the plastic package body 140 covers the outside of the elastic ring 170, the elastic ring 170 is fixed by the plastic package body 140, which has no elasticity any more.
By way of example, an embodiment of the present invention also provides a construction of the elastic ring 170. Referring to fig. 1, 2 and 3, fig. 2 is a top view of the elastic ring 170, and fig. 3 is a cross-sectional view along line a-A1 in fig. 2, wherein the elastic ring 170 includes a first annular plate 171, a second annular plate 172 and annular side plates 173.
The first ring-shaped sheet 171 is fixed on the top surface of the third chip 130. The first ring-shaped sheet 171 is a closed structure, and may be adhered to the top surface of the third chip 130 by using an adhesive layer or the like. The first ring-shaped sheet 171 may be in the shape of a circular ring, a rectangular ring, a triangular ring, an irregular pattern ring, or the like.
In a direction perpendicular to the top surface of the third chip 130 (in the Z direction in the drawing), the second ring-shaped piece 172 is opposite to the first ring-shaped piece 171, and the second ring-shaped piece 172 is in a closed structure. In the present embodiment, the first ring-shaped piece 171 and the second ring-shaped piece 172 have the same shape and the same size, and in other embodiments, the first ring-shaped piece 171 and the second ring-shaped piece 172 have the same shape and different sizes. For example, the width of the second ring-shaped piece 172 is greater than the width of the first ring-shaped piece 171 along a direction parallel to the top surface of the second chip 120 (such as the X direction in the drawing), so as to further increase the heat dissipation area of the multi-chip stacked package structure.
The annular side pieces 173 extend in a direction perpendicular to the top surface of the third chip 130 and have elasticity in a direction perpendicular to the top surface of the third chip 130, and the annular side pieces 173 are disposed between the first and second annular pieces 171 and 172 to connect and support the first and second annular pieces 171 and 172. The annular side piece 173 may be a spring piece having a bend so that the annular side piece 173 has elasticity in a direction perpendicular to the top surface of the third chip 130.
The annular side pieces 173 connect the first annular piece 171 and the second annular piece 172, so that the enclosed area of the elastic ring 170 is a closed area, and the plastic package body 140 does not enter the closed area. Outside the elastic ring 170, the plastic package 140 is further filled in the space between the first ring-shaped piece 171, the second ring-shaped piece 172 and the ring-shaped side piece 173, so as to further support the elastic ring 170, and prevent the elastic ring from falling off to affect the reliability of the multi-chip stacked package structure.
In some embodiments, the first ring-shaped sheet 171, the second ring-shaped sheet 172 and the ring-shaped side sheet 173 are integrally formed, for example, a sheet of metal is punched to form the first ring-shaped sheet 171, the second ring-shaped sheet 172 and the ring-shaped side sheet 173; in other embodiments, the first ring-shaped sheet 171, the second ring-shaped sheet 172, and the ring-shaped side sheet 173 may be manufactured separately, and the ring-shaped side sheet 173 is connected to the first ring-shaped sheet 171 and the second ring-shaped sheet 172 by a welding process.
With continued reference to fig. 1, in some embodiments, the multi-chip stacked package structure further includes a redistribution layer 180, the redistribution layer 180 is disposed on a surface of the second chip 120 facing away from the first chip 110 and is electrically connected to at least a portion of the third functional area 121 of the second chip 120, the third chip 130 is disposed on the redistribution layer 180 and is electrically connected to the second chip 120 through the redistribution layer 180, and the plastic package body 140 further covers the redistribution layer 180. The redistribution layer 180 is configured to lead out the third functional area 121 of the second chip 120.
In some embodiments, the redistribution layer 180 may have a single-layer or multi-layer structure, and has conductive interconnects therein to achieve electrical extraction of the third functional region 121. For example, in this embodiment, the redistribution layer 180 is a dual-layer structure, and includes a first sub-redistribution layer 181 and a second sub-redistribution layer 182, where the first sub-redistribution layer 181 is disposed on a surface of the second chip 120 facing away from the first chip 110 and is electrically connected to at least a portion of the third functional area 121 of the second chip 120, and the second sub-redistribution layer 182 is disposed on a surface of the first sub-redistribution layer 181 and is electrically connected to the first sub-redistribution layer 181.
The multi-chip stacking packaging structure reduces the volume of the packaging structure through multi-chip stacking arrangement, conforms to the trend of miniaturization and integration of packaging, improves the data transmission speed, and reduces signal interference; the multi-chip stacked package structure can radiate heat on two sides, so that the heat radiation of the package structure is enhanced, and the influence of thermal resistance on the electrical property of the package structure is reduced.
The embodiment of the invention also provides a forming method of the multi-chip stacking packaging structure. Fig. 4 is a schematic step diagram of a method for forming a chip stack package structure according to an embodiment of the invention, where the method includes: step S40, providing a substrate 100, wherein the substrate 100 is provided with a bearing surface 100A; step S41, a first chip 110 and a second chip 120 are provided, the first chip 110 is disposed on the carrying surface 100A and is electrically connected to the substrate 100, a surface of the first chip 110 facing away from the substrate 100 has a first functional area 111 and a second functional area 112 disposed at the periphery of the first functional area 111, the second chip 120 is disposed on the first chip 110, a surface of the second chip 120 facing away from the first chip 110 or a surface facing toward the second chip 120 has a third functional area 121, the second chip 120 covers the first functional area 111 of the first chip 110, and the third functional area 121 is electrically connected to the first functional area 111, and the second functional area 112 is exposed to the second chip 120; step S42, a third chip 130 is disposed, the third chip 130 is flip-chip disposed on the second chip 120, and the third chip 130 is electrically connected to the third functional area 121 of the second chip 120 and electrically connected to the second functional area 112 of the first chip 110; in step S43, a plastic package body 140 is formed, the plastic package body 140 covers the carrying surface 100A of the substrate 100 and encapsulates the first chip 110, the second chip 120 and the third chip 130, and a portion of the top surface of the third chip 130 is exposed to the plastic package body 140.
Fig. 5A to 5I are process flow diagrams of a method for forming a multi-chip stacked package structure according to an embodiment of the invention.
Referring to fig. 4 and 5A, in step S40, a substrate 100 is provided, where the substrate 100 has a bearing surface 100A.
Referring to fig. 4, 5B to 5D, in step S41, a first chip 110 and a second chip 120 are disposed, the first chip 110 is disposed on the carrying surface 100A and is electrically connected to the substrate 100, a surface of the first chip 110 facing away from the substrate 100 has a first functional area 111 and a second functional area 112 disposed on the periphery of the first functional area 111, the second chip 120 is disposed on the first chip 110, a surface of the second chip 120 facing away from the first chip 110 or a surface facing the second chip 120 has a third functional area 121, the second chip 120 covers the first functional area 111 of the first chip 110, the third functional area 121 is electrically connected to the first functional area 111, and the second functional area 112 is exposed to the second chip 120.
As an example, an embodiment of the present invention provides a method for disposing the first chip 110 and the second chip 120. Specifically, the method comprises:
Referring to fig. 5B, the first chip 110 is mounted on the carrying surface 100A of the substrate 100. In this step, the first chip 110 is mounted on the carrying surface 100A of the substrate 100 by a Surface Mount Technology (SMT), and the back surface of the first chip 110 is fixed to the carrying surface 100A by an adhesive layer. The front surface of the first chip 110 having the circuit faces away from the substrate 100, and the front surface is provided with the first functional area 111 and the second functional area 112. In this step, a plurality of first chips 110 may be disposed on the substrate 100, and a single multi-chip stack package structure may be formed through a dicing process after the molding compound 140 is formed.
Referring to fig. 5C, the second chip 120 is flip-chip mounted on the first chip 110, and the bonding pads on the surface of the second chip 120 facing the first chip 110 are electrically connected to the first functional regions 111 of the first chip 110. Specifically, the method comprises the following steps: printing solder, such as solder paste, on the front surface of the first chip 110, wherein the printing position of the solder corresponds to the bonding pad of the second chip 120; the second chip 120 is flip-chip mounted on the first chip 110, and electrical connection of the first functional region 111 of the first chip 110 and the third functional region 121 of the second chip 120 is performed by reflow.
In some embodiments, the second chip 120 further includes a through silicon via 122 (Through Silicon Via, TSV) penetrating the second chip 120, and in the step of flip-chip disposing the second chip 120 on the first chip 110, the first functional region 111 of the first chip 110 is further electrically connected to the through silicon via 122 by solder.
Referring to fig. 5D, the second functional region 112 of the first chip 110 is electrically connected to the substrate 100 through conductive leads 150 using a Wire Bonding (Wire Bonding) process. In this step, the pads of the second functional region 112 of the first chip 110 and the pads on the substrate 100 are electrically connected by the conductive leads 150 using a wire bonding process. The wire bonding process uses heat, pressure, ultrasonic energy, etc. to tightly bond the conductive leads 150 to the pads.
Further, in some embodiments, before or after the step of electrically connecting the second functional region 112 of the first chip 110 with the substrate 100 through the conductive leads 150 using a wire bonding process, further comprising: the area of the second functional area 112 of the first chip 110, which needs to be electrically connected to the third chip 130, is led out to the surface of the second chip 120 facing away from the first chip 110 by a conductive stripe 160 using a stripe bonding (Clip Bond) process. In this step, all or part of the bonding pads of the second functional area 112 of the first chip 110, which are not connected to the conductive leads 150, are led out to the surface of the second chip 120 facing away from the first chip 110 through the conductive strips 160 by a ribbon bonding process, and in the subsequent step of connecting the third chip 130 to the conductive strips 160, the second chip 120 can provide support, so as to reduce the process difficulty. Wherein, in some embodiments, the conductive strip 160 is insulated from the second chip 120, i.e., the conductive strip 160 is not electrically connected to the second chip 120.
In some embodiments, the step of disposing the first chip and the second chip further comprises: a redistribution layer 180 is formed (see fig. 5F), where the redistribution layer 180 is disposed on a surface of the second chip 120 facing away from the first chip 110 and is electrically connected to at least a portion of the third functional area 121 of the second chip 120.
In some embodiments, the step of disposing the first chip 110 and the second chip 120 further includes: a first molding is performed to form a first sub-molding body 141 (see fig. 5E), where the first sub-molding body 141 covers the bearing surface 100A of the substrate 100 and encapsulates the first chip 110 and the second chip 120.
As an example, an embodiment of the present invention provides a method for forming the redistribution layer 180 and the first sub-plastic package 141, in this embodiment, the redistribution layer 180 has a dual-layer structure, which includes a first sub-redistribution layer 181 and a second sub-redistribution layer 182. The method comprises the following steps:
before the step of flip-chip disposing the second chip 120, the method further includes: a first sub-re-wiring layer 181 is formed (refer to fig. 5C), where the first sub-re-wiring layer 181 is disposed on a surface of the second chip 120 facing away from the first chip 110 and is electrically connected to at least a portion of the third functional area 121 of the second chip 120 through the through-silicon vias 122, that is, the first sub-re-wiring layer 181 leads out at least a portion of the third functional area 121 of the second chip 120. The first sub-re-wiring layer 181 includes conductive interconnect structures and an insulating layer filled between the conductive interconnect structures. The first sub-re-wiring layer 181 has a single-layer or multi-layer structure.
In some embodiments, the conductive strip 160 is disposed on the surface of the first sub-rewiring layer 181, that is, all or part of the pads of the second functional area 112 of the first chip 110 are led out to the first sub-rewiring layer 181 through the conductive strip 160.
After the step of disposing the first chip 110 and the second chip 120, the method further includes: referring to fig. 5E, a first molding process is performed to form a first sub-molding body 141, where the first sub-molding body 141 covers the bearing surface 100A of the substrate 100 and encapsulates the first chip 110 and the second chip 120. This step performs pre-molding to protect the internal structure, enhance stability, and prevent the stress of the lower chip from affecting the function of the package structure when the third chip 130 is flip-chip mounted. The material of the first sub-plastic package 141 includes, but is not limited to, plastic or epoxy. In this embodiment, the first sub-plastic package 141 covers the side surface of the first sub-redistribution layer 181, and does not cover the top surfaces of the first sub-redistribution layer 181 and the conductive strips 160.
After the step of forming the first sub-plastic package 141, the method further includes: referring to fig. 5F, a second sub-re-wiring layer 182 is formed, the second sub-re-wiring layer 182 is disposed on the surface of the first sub-re-wiring layer 181 and electrically connected to the first sub-re-wiring layer 181, and the first sub-re-wiring layer 181 and the second re-wiring layer 182 form the re-wiring layer 180. The second sub-re-wiring layer 182 includes conductive interconnect lines electrically connected to the first sub-re-wiring layer 181.
In this embodiment, the second sub-redistribution layer 182 is not disposed on the upper surface of the conductive strip 160, and in another embodiment, the second redistribution layer 182 is also disposed on the upper surface of the conductive strip 160.
Referring to fig. 4 and 5G, in step S42, a third chip 130 is disposed, the third chip 130 is flip-chip disposed on the second chip 120, and the third chip 130 is electrically connected to the third functional region 121 of the second chip 120 and electrically connected to the second functional region 112 of the first chip 110. In this step, the third chip 130 is disposed on the second chip 120 using flip chip technology. Specifically, the third chip 130 is disposed on the rewiring layer 180 (see fig. 5F) using flip chip technology. The third chip 130 is electrically connected to the third functional region 121 of the second chip 120 through the redistribution layer 180, and is electrically connected to the first functional region 111 of the first chip 110 through the redistribution layer 180 and the through-silicon via 122. In this embodiment, the third chip 130 is further electrically connected to the conductive strip 160 for electrically connecting to the second functional region 112 of the first chip 110.
Further, referring to fig. 2, 3 and 5H, in one embodiment, before the step of molding, the step of forming the molded body 140 further includes: an elastic ring 170 is disposed on the top surface of the third chip 130, and the elastic ring 170 is disposed on the top surface of the third chip 130 and has elasticity along a direction perpendicular to the top surface of the third chip 130. The elastic ring 170 may be adhered to the top surface of the third chip 130 by an adhesive layer or the like. In an embodiment, the elastic ring 170 includes a first ring-shaped sheet 171, a second ring-shaped sheet 172 and a ring-shaped side sheet 173, wherein the first ring-shaped sheet 171 is fixed on the top surface of the third chip 130, the second ring-shaped sheet 172 is opposite to the first ring-shaped sheet 171 in a direction perpendicular to the top surface of the third chip 130 (as in the Z direction in the figure), the ring-shaped side sheet 173 extends in a direction perpendicular to the top surface of the third chip 130 and has elasticity in a direction perpendicular to the top surface of the third chip 130, and the ring-shaped side sheet 173 is disposed between the first ring-shaped sheet 171 and the second ring-shaped sheet 172 to connect and support the first ring-shaped sheet 171 and the second ring-shaped sheet 172.
In an embodiment, the elastic ring 170 is a metal ring, and the heat dissipation performance of the metal is better than that of the plastic package, and the heat inside the multi-chip stacked package structure can be further dissipated through the elastic ring 170.
Referring to fig. 4 and 5I, in step S43, a molding body 140 is formed by molding, the molding body 140 covers the carrying surface 100A of the substrate 100 and encapsulates the first chip 110, the second chip 120 and the third chip 130, and a portion of the top surface of the third chip 130 is exposed to the molding body 140.
In this embodiment, a second molding is performed at this step to form a second sub-molded body 142, where the second sub-molded body 142 covers the first sub-molded body 141 and encapsulates the third chip 130, a portion of the top surface of the third chip 130 is exposed to the second sub-molded body 142, and the first sub-molded body 141 and the second sub-molded body 142 form the molded body 140. The material of the second sub-plastic package 142 includes, but is not limited to, plastic or epoxy.
In this embodiment, the elastic ring 170 is a closed structure, and if the surrounding area of the elastic ring 170 is a closed area, the elastic ring 170 can limit the flow of molding compound, so that the molding compound does not flow into the surrounding area of the elastic ring 170, the formed second sub-molding body 142 only covers the outer portion of the elastic ring 170, the inner portion of the elastic ring 170 exposes out of the top surface of the third chip 130, and the multi-chip stacked package structure can directly dissipate heat to the air through the top surface of the third chip 130, so as to enhance the heat dissipation function of the product. In this embodiment, the plastic package 140 is further filled in the space between the first ring-shaped piece 171, the second ring-shaped piece 172 and the ring-shaped side piece 173 outside the elastic ring 170, so as to further support the elastic ring 170, and prevent the elastic ring from falling off to affect the reliability of the multi-chip stack package structure.
Further, when the plastic packaging step is performed, if the encapsulating mold directly abuts against the top surface of the third chip 130 during mold closing, the mold closing extrusion force may cause the deformation of the bonding pad of the third chip 130, which affects the function of the packaging structure, and since the elastic ring 170 has elasticity along the direction perpendicular to the top surface of the third chip 130, it can play a role of buffering and protecting when the plastic packaging step is performed, the encapsulating mold may not directly abut against the top surface of the third chip 130, and the bonding pad of the third chip 130 may be prevented from being deformed.
Further, after the plastic packaging step is performed, a dicing step is performed to form individual multi-chip stacked package structures, see fig. 1.
In the multi-chip stacked package structure formed by the packaging method of the present invention, the first chip 110 not only has a functional area (i.e., the second functional area 112, at least the second functional area 112 can be electrically connected with the third chip 130) in an area not covered by the second chip 120, but also has a functional area (i.e., the first functional area 111, at least the first functional area 111 can be electrically connected with the second chip 120) in an area covered by the second chip 120, thereby improving the utilization rate of chips in the package structure and being beneficial to the high integration of the functions of the package structure; meanwhile, the third chip 130 is flip-chip arranged on the surface of the second chip 120, and can be electrically connected with the second functional area 112 of the first chip 110 and the third functional area 121 of the second chip 120, so that the number of stacked chips is increased, and the high integration of the functions of the package structure is facilitated; and, at least part of the top surface of the third chip 130 is exposed to the plastic package body 140, so that the multi-chip stacked package structure can dissipate heat through the top surfaces of the substrate 100 and the third chip 130, i.e. can realize double-sided heat dissipation, thereby greatly improving the heat dissipation performance of the multi-chip stacked package structure and the electrical performance of the multi-chip stacked package structure.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present invention and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. The term "one or more" depends at least in part on the context and may be used to describe a feature, structure, or characteristic in a singular sense or may be used to describe a feature, structure, or combination of features in a plural sense. The term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but may instead, also depend at least in part on the context, allow for other factors to be present that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (16)

1. A multi-chip stacked package structure, comprising:
a substrate having a bearing surface;
the first chip is arranged on the bearing surface and is electrically connected with the substrate, and one surface of the first chip, which is away from the substrate, is provided with a first functional area and a second functional area which is arranged at the periphery of the first functional area;
the second chip is arranged on the first chip, a surface of the second chip, which is away from the first chip or faces the first chip, is provided with a third functional area, the second chip covers the first functional area of the first chip, the third functional area is electrically connected with the first functional area, and the second functional area is exposed to the second chip;
the third chip is arranged on the second chip in a flip-chip manner, and is electrically connected with the third functional area of the second chip and the second functional area of the first chip;
And the plastic package body covers the bearing surface of the substrate and covers the first chip, the second chip and the third chip, and at least part of the top surface of the third chip is exposed to the plastic package body.
2. The multi-chip stacked package structure of claim 1, wherein the second chip further comprises a through silicon via extending through the second chip, the third chip further being electrically connected to the first functional region of the first chip through the through silicon via.
3. The multi-chip stack package structure of claim 1, further comprising an elastic ring disposed on a top surface of the third chip and having elasticity in a direction perpendicular to the top surface of the third chip, wherein the plastic package body covers an outer portion of the elastic ring, and an inner portion of the elastic ring exposes the top surface of the third chip.
4. The multi-chip stack package structure of claim 3, wherein the elastic ring comprises:
the first annular piece is fixed on the top surface of the third chip;
the second annular piece is arranged opposite to the first annular piece in the direction perpendicular to the top surface of the third chip;
The annular side piece extends along the direction vertical to the top surface of the third chip and has elasticity in the direction vertical to the top surface of the third chip, and the annular side piece is arranged between the first annular piece and the second annular piece so as to connect and support the first annular piece and the second annular piece;
and the plastic package body is filled in the space among the first annular piece, the second annular piece and the annular side piece outside the elastic ring.
5. The multi-chip stacked package structure of any one of claims 1-4, further comprising a conductive strip, wherein the third chip is electrically connected to the second functional region of the first chip through the conductive strip.
6. The multi-chip stacked package structure of claim 5, wherein one end of the conductive strip is electrically connected to the second functional region of the first chip, the other end is fixed on a surface of the second chip facing away from the first chip, and a pad of the third chip is electrically connected to the other end of the conductive strip.
7. The multi-chip stacked package structure of any one of claims 1-4, further comprising a conductive lead having one end electrically connected to the second functional region of the first chip and the other end electrically connected to the substrate.
8. The multi-chip stack package structure according to any one of claims 1 to 4, wherein the plastic package body further comprises:
the first sub-plastic package body covers the bearing surface of the substrate and covers the first chip and the second chip;
the second sub-plastic package body covers the first sub-plastic package body and coats the third chip, and part of the top surface of the third chip is exposed to the second sub-plastic package body.
9. The multi-chip stacked package structure of any one of claims 1-4, further comprising a redistribution layer disposed on a surface of the second chip facing away from the first chip and electrically connected to at least a portion of the third functional area of the second chip, wherein the third chip is disposed on the redistribution layer and electrically connected to the second chip through the redistribution layer, and wherein the plastic package further covers the redistribution layer.
10. A packaging method of a multi-chip stacked package structure, comprising:
providing a substrate, wherein the substrate is provided with a bearing surface;
a first chip and a second chip are arranged, the first chip is arranged on the bearing surface and is electrically connected with the substrate, one surface of the first chip, which is away from the substrate, is provided with a first functional area and a second functional area which is arranged on the periphery of the first functional area, the second chip is arranged on the first chip, one surface of the second chip, which is away from the first chip, or one surface of the second chip, which is towards the second chip, is provided with a third functional area, the second chip covers the first functional area of the first chip, the third functional area is electrically connected with the first functional area, and the second functional area is exposed to the second chip;
A third chip is arranged on the second chip in a flip-chip manner, and is electrically connected with the third functional area of the second chip and the second functional area of the first chip;
and (3) plastic packaging to form a plastic packaging body, wherein the plastic packaging body covers the bearing surface of the substrate and covers the first chip, the second chip and the third chip, and part of the top surface of the third chip is exposed to the plastic packaging body.
11. The packaging method of claim 10, wherein the step of providing the first chip and the second chip comprises:
mounting the first chip on the bearing surface of the substrate;
flip-chip mounting the second chip on the first chip, wherein a bonding pad on the surface of the second chip facing the first chip is electrically connected with the first functional area of the first chip;
and electrically connecting the second functional area of the first chip with the substrate through a conductive lead by adopting a wire bonding process.
12. The method of packaging of claim 11, wherein the second chip further comprises a through-silicon via extending therethrough, the first functional region of the first chip further being electrically connected to the through-silicon via in the step of flip-chip mounting the second chip on the first chip;
In the step of disposing the third chip, the third chip is further electrically connected to the first functional region of the first chip through the through silicon via.
13. The method of packaging of claim 11, wherein the step of electrically connecting the second functional region of the first chip to the substrate via conductive leads using a wire bonding process further comprises, before or after:
the area, which needs to be electrically connected with a third chip, of the second functional area of the first chip is led out to the surface, which is away from the first chip, of the second chip through a conductive strip by adopting a strip bonding process;
in the step of disposing the third chip, the third chip is electrically connected to the conductive strip for electrically connecting to the second functional region of the first chip.
14. The method of packaging of claim 10, wherein the step of providing the first chip and the second chip further comprises: forming a rewiring layer, wherein the rewiring layer is arranged on the surface, away from the first chip, of the second chip and is electrically connected with at least part of the third functional area of the second chip; the step of providing a third chip includes: the third chip is arranged on the rewiring layer and is electrically connected with the second chip through the rewiring layer.
15. The packaging method of claim 10, wherein the step of disposing the first chip and the second chip comprises: performing primary plastic packaging to form a first sub-plastic packaging body, wherein the first sub-plastic packaging body covers the bearing surface of the substrate and coats the first chip and the second chip;
after the first sub-plastic package body is formed, executing the step of setting the third chip;
the step of disposing the third chip further includes: and performing secondary plastic packaging to form a second sub-plastic packaging body, wherein the second sub-plastic packaging body covers the first sub-plastic packaging body and coats the third chip, part of the top surface of the third chip is exposed to the second sub-plastic packaging body, and the first sub-plastic packaging body and the second sub-plastic packaging body form the plastic packaging body.
16. The method of any one of claims 10 to 15, wherein the step of molding, prior to the step of forming the molded body, further comprises:
an elastic ring is arranged on the top surface of the third chip, and the elastic ring is arranged on the top surface of the third chip and has elasticity along the direction perpendicular to the top surface of the third chip;
and in the step of forming the plastic package body, the plastic package material covers the outer part of the elastic ring, and the inner part of the elastic ring exposes the top surface of the third chip.
CN202311027864.8A 2023-08-15 2023-08-15 Multi-chip stacking packaging structure and packaging method thereof Pending CN116913905A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311027864.8A CN116913905A (en) 2023-08-15 2023-08-15 Multi-chip stacking packaging structure and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311027864.8A CN116913905A (en) 2023-08-15 2023-08-15 Multi-chip stacking packaging structure and packaging method thereof

Publications (1)

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CN116913905A true CN116913905A (en) 2023-10-20

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