CN116909951A - Chip and control method thereof - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The application provides a chip and a control method thereof, wherein the chip comprises: the system comprises a data receiving and transmitting module and a state machine module, wherein the state machine module is in communication connection with the data receiving and transmitting module; the data receiving and transmitting module is used for receiving and converting operation instructions and report data sent by the upper computer, and the operation instructions comprise: a mode switching instruction and a data receiving and transmitting instruction; the state machine module is used for analyzing the operation instruction, and when the operation instruction is a mode switching instruction, the working mode of the chip is switched according to the operation instruction; the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in a read-write mode, the state machine module performs data read-write operation on the corresponding chip functional module according to the analyzed data receiving-transmitting instruction; when the chip is in the baud rate updating mode, the state machine module updates the baud rate of the data receiving and transmitting module according to the analyzed mode switching instruction. The application can enable the upper computer to flexibly control the chips with various specifications.
Description
Technical Field
The application relates to the technical field of chip debugging, in particular to a chip and a control method thereof.
Background
For the universal serial interface, the most popular method is that the upper computer is connected with the UART interface of the ASIC (application specific integrated circuit) chip through a USB (universal serial bus) to UART (asynchronous receiving and transmitting transmitter) switching circuit. In the data transmission process, the upper computer installs serial port debugging software to send data, UART inside the ASIC chip converts serial data into parallel data, and CPU (central processing unit) starts to process parallel data after receiving UART interrupt; or UART makes parallel-to-serial conversion to the parallel data sent back by CPU and sends the converted serial data to upper computer. However, in this process, the ASIC chip needs to include a CPU and the CPU is in a working state, and for the ASIC chip without the CPU, data cannot be transmitted and received with the upper computer, so as to realize flexible control of the ASIC chip by the upper computer.
Therefore, how to flexibly control chips with various specifications by the host computer becomes a difficult problem to be solved.
Disclosure of Invention
In order to solve the problems, the chip and the control method thereof provided by the application can realize the control of the upper computer on the chip without arranging a CPU on the chip through the data receiving and transmitting module and the state machine module, and can flexibly control the working mode of the chip.
In a first aspect, the present application provides a chip comprising: the system comprises a data receiving and transmitting module and a state machine module, wherein the state machine module is in communication connection with the data receiving and transmitting module;
the data transceiver module is used for receiving and converting the operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module for analysis; receiving and converting the report data sent by the state machine module, so as to send the report data to the upper computer, wherein the operation instruction comprises: a mode switching instruction and a data receiving and transmitting instruction;
the state machine module is used for analyzing the operation instruction, controlling the chip function module on the chip according to the operation instruction when the operation instruction is a data receiving and transmitting instruction, and switching the working mode of the chip according to the operation instruction when the operation instruction is a mode switching instruction;
the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in the read-write mode, the state machine module performs data read-write operation on the corresponding chip functional module according to the parsed data receiving-transmitting instruction; and when the chip is in the baud rate updating mode, the state machine module updates the baud rate of the data receiving and transmitting module according to the analyzed mode switching instruction.
Optionally, the chip further comprises: a communication interface module;
the data transceiver module comprises a software control unit, the communication interface module is in communication connection with the software control unit, and the state machine module is in communication connection with the communication interface module;
the communication interface module is used for receiving the baud rate updating value sent by the state machine module and writing the baud rate updating value into the software control unit so as to update the baud rate of the data receiving and transmitting module.
Optionally, the chip further comprises: the state machine module is in communication connection with the data receiving and transmitting module through the loop control module, receives the converted operation instruction through the loop control module, and sends the report data to the upper computer through the loop control module;
the working mode of the chip further comprises the following steps: a loop mode, the operating instructions further comprising: a loop instruction, wherein the loop instruction is different from the data format or/and the data content of the mode switching instruction;
the loop control module is used for receiving the loop instruction after conversion when the chip is in the loop mode, and sending the loop instruction after conversion to the upper computer through the data receiving and sending module.
Optionally, the data transceiver module further includes: a serial-to-parallel conversion unit and a parallel-to-serial conversion unit;
the serial-parallel conversion unit and the parallel-serial conversion unit are both in communication connection with the loop control module; the serial-parallel conversion unit is used for converting the serial operation instruction sent by the upper computer into the parallel operation instruction and sending the parallel operation instruction to the loop control module; the parallel-serial conversion unit is used for receiving the parallel reported data, converting the parallel reported data into serial reported data and sending the serial reported data to the upper computer;
the loop control module is further configured to receive the parallel loop instruction sent by the serial-parallel conversion unit when the chip is in the loop mode, and send the parallel loop instruction as the parallel report data to the parallel-serial conversion unit.
Optionally, the loop control module includes: a multiplexer;
the state machine module includes: the system comprises a state machine unit, a character analysis unit and a character sending unit, wherein the state machine unit is respectively in communication connection with the character analysis unit and the character sending unit;
the multiplexer includes: the output end is selectively in communication connection with the first input end and the second input end;
the output end is in communication connection with the parallel-serial conversion unit, the first input end and the character analysis unit are in communication connection with the serial-parallel conversion unit together, and the second input end is connected with the character sending unit;
the state machine unit is used for performing data read-write operation on the corresponding chip functional module according to the parsed data receiving-transmitting instruction when the chip is in the read-write mode; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module according to the analyzed mode switching instruction;
the character analysis unit is used for analyzing the operation instruction;
the character transmitting unit is used for transmitting the read data on the corresponding chip function module to the data receiving and transmitting module through the second input end;
the multiplexer is used for communicating the output end with the second input end when the chip is in the read-write mode; when the chip is in the loop-back mode, the output end is communicated with the first input end, and the converted loop-back instruction is sent to the upper computer through the first input end.
Optionally, the state machine module further comprises: a mode register;
the mode register is respectively connected with the multiplexer and the state machine unit in a communication way;
the mode register is used for providing mode zone bits under at least two working modes, and updating the numerical value of the mode zone bit under the corresponding working mode according to the data in the analyzed mode switching instruction.
Optionally, the data transceiving instruction includes: a data write instruction and a data read instruction;
the data receiving and transmitting module is used for reading data on the corresponding chip functional module through the state machine module according to the analyzed operation instruction when the operation instruction is a data reading instruction; when the operation instruction is a data writing instruction, writing corresponding target data into a corresponding chip function module through a state machine module according to the analyzed operation instruction;
the data format of the data writing instruction comprises: writing address character string, writing address ending character, target data information and writing instruction ending character;
the data format of the data reading instruction comprises: a read address string, a read address terminator, length information of read data, and a read instruction terminator;
the data format of the mode switching instruction includes: predefined characters, different working modes correspond to different predefined characters;
the read-write mode includes: a first-in first-out mode and an address increment mode, wherein when the chip is in the first-in first-out mode, the state machine module fixes the starting address of data transmission so as to ensure that the first-in first-out entry is hit and complete the reading and writing operation of data on the corresponding chip functional module; when the chip is in the address increment mode, the state machine module automatically accumulates the starting address of data transmission after each data transmission so as to finish the data read-write operation of the corresponding chip functional module.
In a second aspect, the present application provides a method for controlling a chip, including:
receiving and converting a serial operation instruction sent by an upper computer, wherein the types of the operation instruction comprise: a mode switching instruction and a data receiving and transmitting instruction;
judging the type of an operation instruction, controlling a chip function module on a chip according to the operation instruction when the operation instruction is a data receiving and transmitting instruction, and switching the working mode of the chip according to the operation instruction when the operation instruction is a mode switching instruction;
the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in the read-write mode, performing data read-write operation on the corresponding chip functional module through a state machine module according to the parsed data receiving-transmitting instruction; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module through a state machine module according to the analyzed mode switching instruction; the data transceiver module is used for receiving and converting the operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module for analysis; and receiving and converting the reported data sent by the state machine module so as to send the reported data to the upper computer.
Optionally, the operation instruction further includes: a loop instruction, wherein the loop instruction is different from the data format or/and the data content of the mode switching instruction;
the method further comprises the steps of: and when the chip is in the loop-back mode, receiving the converted loop-back instruction, and sending the converted loop-back instruction to the upper computer through the data receiving and sending module.
Optionally, the chip includes: the device comprises a serial-parallel conversion unit, a parallel-serial conversion unit, a multiplexer, a state machine unit, a character analysis unit and a character sending unit;
the state machine unit is respectively connected with the character analysis unit and the character sending unit in a communication way, and the multiplexer comprises: the output end is selectively in communication connection with the first input end and the second input end;
the output end is in communication connection with the parallel-serial conversion unit, the first input end and the character analysis unit are in communication connection with the serial-parallel conversion unit together, and the second input end is connected with the character sending unit;
the method further comprises the steps of: when the chip is in the read-write mode, the output end is communicated with the second input end; when the chip is in the loop-back mode, the output end is communicated with the first input end, so that the converted loop-back instruction is sent to the upper computer through the first input end.
According to the chip and the control method thereof provided by the embodiment of the application, the chip can be controlled by the upper computer without arranging the CPU on the chip through the data receiving and transmitting module and the state machine module, so that the upper computer can control the chips with various specifications, meanwhile, the diversity of the chip control by the upper computer is enriched through the switching of the working modes of the chips, the flexibility of the chip control by the upper computer is further increased, the baud rate of the data receiving and transmitting module can be updated when the chip modulates the baud rate updating mode, and a user can change the baud rate according to the performance and the control content of the chip, so that the flexibility, the efficiency and the quality of the chip control are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic block diagram of a chip according to an embodiment of the application;
fig. 2 is a schematic flow chart of a control method of a chip according to an embodiment of the application.
Reference numerals
1. A data receiving and transmitting module; 11. a software control unit; 12. a serial-parallel conversion unit; 13. parallel-serial conversion unit; 2. a state machine module; 21. a state machine unit; 22. a character analysis unit; 23. a character transmitting unit; 24. a mode register; 3. a communication interface module; 4. and a loop control module.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
It will be understood that when an element is referred to as being "fixedly connected" to another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
In a first aspect, an embodiment of the present application provides a chip, referring to fig. 1, the chip includes: a data transceiver module 1 and a state machine module 2. The data transceiver module 1 is in communication connection with the upper computer through a serial port, the state machine module 2 is in communication connection with the data transceiver module 1, and the state machine module 2 is in communication connection with a plurality of chip function modules on the same chip through a transmission bus.
The data transceiver module 1 is used for receiving and converting an operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module 2 for analysis; receiving and converting the report data sent by the state machine module 2 to send the report data to the upper computer, wherein the operation instruction comprises: a mode switching instruction and a data receiving and transmitting instruction;
the state machine module 2 is used for analyzing the operation instruction, controlling the chip function module on the chip according to the operation instruction when the operation instruction is a data receiving and transmitting instruction, and switching the working mode of the chip according to the operation instruction when the operation instruction is a mode switching instruction;
the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in a read-write mode, the state machine module 2 performs data read-write operation on the corresponding chip functional module according to the analyzed data receiving-transmitting instruction; when the chip is in the baud rate updating mode, the state machine module 2 updates the baud rate of the data transceiver module 1 according to the analyzed mode switching instruction.
Specifically, the chip further includes: a communication interface module 3. The data transceiver module 1 includes: a software control unit 11, a serial-parallel conversion unit 12 and a parallel-serial conversion unit 13. The communication interface module 3 is in communication connection with the software control unit 11, and the state machine module 2 is in communication connection with the communication interface module 3.
The serial-parallel conversion unit 12 is used for converting serial operation instructions sent by the upper computer into parallel operation instructions; the parallel-serial conversion unit 13 is configured to receive parallel report data, convert the parallel report data into serial report data, and send the serial report data to the upper computer.
After the upper computer sends a mode switching instruction to the chip to switch the working mode of the chip to the baud rate updating mode, the state machine module 2 analyzes the baud rate updating value in the mode switching instruction and sends the baud rate updating value to the communication interface. After receiving the baud rate update value sent by the state machine module 2, the communication interface module 3 writes the baud rate update value into the software control unit 11 to update the baud rate of the data transceiver module 1.
In this embodiment, the data transceiver module 1 is a UART, the state machine module 2 is a finite state machine, the state machine module 2 is in communication connection with a plurality of chip function modules on the same chip through an AMBA (advanced microcontroller bus architecture) protocol bus, the communication interface module 3 is a register interface, and the software control unit 11 is a software register, but is not limited thereto.
In an alternative embodiment, the chip further comprises: and a loop control module 4. The state machine module 2 is in communication with the data transceiver module 1 through the loop control module 4. The state machine module 2 receives the converted operation instruction through the loop control module 4, and sends report data to the upper computer through the loop control module 4.
It should be noted that, the operation modes of the chip further include: loop back mode. The operation instructions further include: a loop instruction. Wherein the loop instruction is different from the data format or/and the data content of the mode switching instruction. The loop control module 4 is configured to receive parallel loop instructions sent by the serial-parallel conversion unit 12 when the chip is in a loop mode, and send the parallel loop instructions as parallel report data to the parallel-serial conversion unit 13. By limiting the difference between the loop instruction and the mode switching instruction, when the mode switching instruction is received in the loop mode of the chip, the loop control module 4 can be prevented from mistakenly sending the mode switching instruction as loop data to the upper computer directly through the parallel-serial conversion unit 13.
Specifically, the loop control module 4 includes: a multiplexer. The multiplexer includes: an output, a first input and a second input. The state machine module 2 includes: a state machine unit 21, a character parsing unit 22, and a character transmitting unit 23.
The state machine unit 21 is communicatively connected to the character parsing unit 22 and the character transmitting unit 23, respectively. The output is selectively communicatively coupled to the first input and the second input. The output is communicatively connected to the parallel to serial conversion unit 13. The first input and the character parsing unit 22 are commonly connected in communication with the serial-parallel conversion unit 12. The second input is connected to the character transmitting unit 23.
The state machine unit 21 is configured to perform data read-write operation on the corresponding chip function module according to the parsed data transceiving instruction when the chip is in the read-write mode; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module 1 according to the analyzed mode switching instruction;
the serial-parallel conversion unit 12 is used for sending the parallel operation instruction to the loop control module 4;
the character parsing unit 22 is used for parsing the operation instruction; the character sending unit 23 is configured to send the read data on the corresponding chip function module to the data transceiver module 1 through the second input terminal;
the multiplexer is used for communicating the output end with the second input end when the chip is in a read-write mode; when the chip is in the loop mode, the output end is communicated with the first input end, and the converted loop instruction is sent to the upper computer through the first input end.
The loop control module 4 is arranged to test the data transmission path on the chip effectively, so that the effectiveness of chip control in other modes is ensured.
In an alternative embodiment, the state machine module 2 further comprises: a mode register 24. The mode register 24 is communicatively connected to the enable of the multiplexer and the state machine unit 21, respectively. The mode register 24 is used for providing mode flag bits in at least two working modes, and updating the values of the mode flag bits in the corresponding working modes according to the data in the parsed mode switching instruction.
Taking the mode register 24 as an example to provide the mode flags for three modes of operation, the value of the corresponding mode flag in the current mode of operation is set, while the values of the mode flags in the other modes of operation are reset. Specifically, when the state machine unit 21 sends the parsed mode switching instruction to the mode register 24, the mode register 24 sets the mode flag bit corresponding to the loop mode according to the data in the mode switching instruction, resets the mode flag bits of the other two working modes, and simultaneously sends an enabling signal to the multiplexer, so that the multiplexer communicates the output end with the first input end, and the converted loop instruction is sent to the upper computer through the first input end.
In this alternative embodiment, the mode switch instruction includes: a read-write switching instruction, a baud rate switching instruction and a loop switching instruction. After the upper computer sends a read-write switching instruction to the chip, the state machine unit 21 switches the chip to a read-write mode after analyzing the read-write switching instruction; after the upper computer sends the baud rate switching instruction to the chip, the state machine unit 21 switches the chip to the baud rate updating mode after analyzing the baud rate switching instruction; after the host computer sends the loop-back switching instruction to the chip, the state machine unit 21 switches the chip to the loop-back mode after analyzing the loop-back switching instruction.
Also, in this alternative embodiment, the mode register 24 provides mode flags for both the read-write mode and the loop-back mode. Specifically, when the chip is powered on and is in a loop mode by default, all characters sent by the upper computer can be returned to the upper computer as loop instructions through the UART without any change except for the operation of switching the working modes of the chip. When the upper computer sends an operation instruction for switching the working mode of the chip to the read-write mode to the chip, the mode register 24 sets a mode flag bit according to data in the mode switching instruction, and simultaneously sends a disable signal to the multiplexer so that the multiplexer communicates the output end with the second input end. When the upper computer sends an operation instruction for switching the working mode of the chip to the loop-back mode to the chip, the mode register 24 resets the value of the mode flag bit according to the data in the mode switching instruction.
When the baud rate switching command is sent to the chip, the state machine unit 21 directly initiates the operation of updating the baud rate to the software control unit 11 through the communication interface module 3 according to the data content in the analyzed baud rate switching command after receiving the analyzed baud rate switching command.
In an alternative embodiment, the data transceiving instructions comprise: a data write instruction and a data read instruction.
The data transceiver module 1 is used for reading data on the corresponding chip functional module through the state machine module according to the analyzed operation instruction when the operation instruction is a data reading instruction; when the operation instruction is a data writing instruction, corresponding target data is written into the corresponding chip function module through the state machine module according to the analyzed operation instruction.
The data format of the data writing instruction consists of a writing address character string, a writing address ending symbol, target data information and a data writing instruction ending symbol; the data format of the data reading instruction consists of a reading address character string, a reading address ending symbol, length information of reading data and a data reading instruction ending symbol; the data format of the mode switching instruction is composed of predefined characters, and different working modes correspond to different predefined characters. It should be noted that the predefined character may be a single character or may be a character string composed of a plurality of characters.
The write address terminator and the read address terminator may be punctuation marks or mathematical symbols in ASCII characters, which may be the same character or different characters. Taking a 36-bit address AHB (advanced high performance bus) read operation as an example, in a read mode, the serial port software of the upper computer sends character strings of 0x912345678 and 0x8000 carriage returns, wherein the carriage returns is a symbol triggered by a carriage return key on a keyboard, and after the character strings are analyzed, the state machine module 2 can read back 32KB data from the 0x912345678 address to the upper computer. Meanwhile, the '0 x0 space 0x8000 carriage return' can also be sent, wherein 'space' is a character triggered by a space key on a keyboard, and the state machine module 2 can read back 32KB data from a 0x0 address to an upper computer after analyzing the character string. In both examples, the chip may automatically recognize a "comma" or a "space" in an ASCII character as an indication of the end of the corresponding address.
The read-write mode includes: a first-in first-out (FIFO) mode and an address increment mode. When the chip is in the first-in first-out mode, the state machine module 2 fixes the starting address of data transmission so as to ensure that the first-in first-out entrance is hit and complete the reading and writing operation of data on the corresponding chip functional module; when the chip is in the address increment mode, the state machine module 2 automatically accumulates the initial address of data transmission after each data transmission so as to complete the data reading and writing operation of the corresponding chip functional module.
Specifically, in the FIFO mode, the hardware on the chip fixes the start address of AMBA transmission, and ensures that the FIFO entry is hit, so as to automatically complete the SoC address space read-write operation of the given data length of the user. In the address increment mode, the hardware starts to send AMBA bus transmission from the initial address, and automatically accumulates the initial address of AMBA transmission after each transmission, so as to complete SoC address space read-write operation of the given data length of the user.
In this alternative embodiment, the predefined characters use ASCII characters as keywords, and the host computer can switch to a predetermined working mode by sending corresponding ASCII characters, and then the software on the host computer only needs to send corresponding payload data corresponding to the operation in the working mode.
For example, character A is used to control the chip to switch the operation mode to FIFO mode, character A is followed by 0 or 1, and is used to switch the operation mode to the read sub-mode or write sub-mode in the FIFO mode. In the reading mode, the upper computer gives out the initial address and the data length and adds the carriage back, and the hardware on the chip automatically completes the reading operation and returns all the read data to the upper computer. In the writing mode, the upper computer gives out the initial address and all writing data and returns, and the hardware on the chip can automatically complete writing operation.
For another example, the character Z is followed by 0xHex for controlling the chip to update the baud rate, the character Y is followed by 0 for controlling the chip to enter the read-write mode, and the character Y is followed by 1 for controlling the chip to exit the read-write mode, i.e. controlling the chip to enter the loop-back mode.
When "Z0xHex" is input to the chip by the host computer, it means that the baud rate division coefficient of the data transceiver module 1 is updated to "Hex". Wherein, "Hex" refers to the baud rate division factor, which needs to be calculated according to the working clock frequency of UART and the target baud rate. The target baud rate is a value after the chip updates the baud rate.
In this alternative embodiment, the default chip has an initial baud value of 115200 baud.
Meanwhile, a specific character can be followed by 0, 1 or 2, so that the corresponding data width in the reading sub-mode or the writing sub-mode can be set to be 8 bits, 16 bits or 32 bits.
The chip provided by the application has a simple structure, supports a plurality of other working modes such as a FIFO mode and an address increment mode while supporting batch data read-write operation, realizes high-efficiency and quick software operation, and improves the flexibility of accessing the chip by an upper computer through software; the baud rate in the upper computer configurable chip further gives enough flexibility to the software regulation chip, and simultaneously gives consideration to the stability and speed of chip regulation; the chip supports the support of loop test, is favorable for quick positioning and eliminating the problem of interconnection among an upper computer, the chip and a board level, and improves the regulation and control efficiency.
In a second aspect, an embodiment of the present application provides a control method of a chip, referring to fig. 2, where the control method is applied to a chip as in the first aspect, and specifically includes steps S101 to S102:
step S101: and receiving and converting a serial operation instruction sent by the upper computer.
The types of the operation instructions include: a mode switching instruction and a data transceiving instruction.
Step S102: judging the type of the operation instruction, controlling the chip function module on the chip according to the operation instruction when the operation instruction is a data receiving and transmitting instruction, and switching the working mode of the chip according to the operation instruction when the operation instruction is a mode switching instruction.
The working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in a read-write mode, performing data read-write operation on the corresponding chip functional module through the state machine module 2 according to the analyzed data receiving-transmitting instruction; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module 1 through the state machine module 2 according to the analyzed mode switching instruction; the data transceiver module 1 is used for receiving and converting an operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module 2 for analysis; and receiving and converting the reported data sent by the state machine module 2 so as to send the reported data to the upper computer.
In an alternative embodiment, the operation mode of the chip further includes: a loop mode; the operation instructions further include: a loop instruction. The loop instruction is different from the data format or/and the data content of the mode switching instruction;
the method further comprises the steps of: when the chip is in the loop mode, the converted loop instruction is received, and the converted loop instruction is sent to the upper computer through the data transceiver module 1.
In an alternative embodiment, in conjunction with fig. 1, the chip includes: a serial-parallel conversion unit 12, a parallel-serial conversion unit 13, a multiplexer, a state machine unit 21, a character parsing unit 22, and a character transmitting unit 23;
the state machine unit 21 is communicatively connected to the character parsing unit 22 and the character transmitting unit 23, respectively, and the multiplexer comprises: the output end is selectively in communication connection with the first input end and the second input end;
the output end is in communication connection with the parallel-serial conversion unit 13, the first input end and the character analysis unit 22 are jointly in communication connection with the serial-parallel conversion unit 12, and the second input end is connected with the character transmission unit 23;
the method further comprises the steps of: when the chip is in a read-write mode, the output end is communicated with the second input end; when the chip is in the loop mode, the output end is communicated with the first input end, so that the converted loop instruction is sent to the upper computer through the first input end.
The control method can flexibly control the chip by only sending an operation instruction to the chip through software, realizes the read-write operation of the chip functional module on the chip, and can also switch the working mode of the chip, wherein the baud rate of the chip is adjusted, the flexibility of the software on chip regulation is ensured, and meanwhile, the stability of the software on chip regulation is also ensured.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A chip, the chip comprising: the system comprises a data receiving and transmitting module and a state machine module, wherein the state machine module is in communication connection with the data receiving and transmitting module;
the data transceiver module is used for receiving and converting the operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module for analysis; receiving and converting the report data sent by the state machine module, so as to send the report data to the upper computer, wherein the operation instruction comprises: a mode switching instruction and a data receiving and transmitting instruction;
the state machine module is used for analyzing the operation instruction; when the operation instruction is a data receiving and transmitting instruction, controlling a chip function module on the chip according to the operation instruction; when the operation instruction is a mode switching instruction, switching the working mode of the chip according to the operation instruction;
the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in the read-write mode, the state machine module performs data read-write operation on the corresponding chip functional module according to the parsed data receiving-transmitting instruction; and when the chip is in the baud rate updating mode, the state machine module updates the baud rate of the data receiving and transmitting module according to the analyzed mode switching instruction.
2. The chip of claim 1, wherein the chip further comprises: a communication interface module;
the data transceiver module comprises a software control unit, the communication interface module is in communication connection with the software control unit, and the state machine module is in communication connection with the communication interface module;
the communication interface module is used for receiving the baud rate updating value sent by the state machine module and writing the baud rate updating value into the software control unit so as to update the baud rate of the data receiving and transmitting module.
3. The chip of claim 1, wherein the chip further comprises: the state machine module is in communication connection with the data receiving and transmitting module through the loop control module, receives the converted operation instruction through the loop control module, and sends the report data to the upper computer through the loop control module;
the working mode of the chip further comprises the following steps: a loop mode, the operating instructions further comprising: a loop instruction, wherein the loop instruction is different from the data format or/and the data content of the mode switching instruction;
the loop control module is used for receiving the loop instruction after conversion when the chip is in the loop mode, and sending the loop instruction after conversion to the upper computer through the data receiving and sending module.
4. The chip of claim 3, wherein the data transceiver module further comprises: a serial-to-parallel conversion unit and a parallel-to-serial conversion unit;
the serial-parallel conversion unit and the parallel-serial conversion unit are both in communication connection with the loop control module; the serial-parallel conversion unit is used for converting the serial operation instruction sent by the upper computer into the parallel operation instruction and sending the parallel operation instruction to the loop control module; the parallel-serial conversion unit is used for receiving the parallel reported data, converting the parallel reported data into serial reported data and sending the serial reported data to the upper computer;
the loop control module is further configured to receive the parallel loop instruction sent by the serial-parallel conversion unit when the chip is in the loop mode, and send the parallel loop instruction as the parallel report data to the parallel-serial conversion unit.
5. The chip of claim 4, wherein the loop back control module comprises: a multiplexer;
the state machine module includes: the system comprises a state machine unit, a character analysis unit and a character sending unit, wherein the state machine unit is respectively in communication connection with the character analysis unit and the character sending unit;
the multiplexer includes: the output end is selectively in communication connection with the first input end and the second input end;
the output end is in communication connection with the parallel-serial conversion unit, the first input end and the character analysis unit are in communication connection with the serial-parallel conversion unit together, and the second input end is connected with the character sending unit;
the state machine unit is used for performing data read-write operation on the corresponding chip functional module according to the parsed data receiving-transmitting instruction when the chip is in the read-write mode; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module according to the analyzed mode switching instruction;
the character analysis unit is used for analyzing the operation instruction;
the character transmitting unit is used for transmitting the read data on the corresponding chip function module to the data receiving and transmitting module through the second input end;
the multiplexer is used for communicating the output end with the second input end when the chip is in the read-write mode; when the chip is in the loop-back mode, the output end is communicated with the first input end, and the converted loop-back instruction is sent to the upper computer through the first input end.
6. The chip of claim 5, wherein the state machine module further comprises: a mode register;
the mode register is respectively connected with the multiplexer and the state machine unit in a communication way;
the mode register is used for providing mode zone bits under at least two working modes, and updating the numerical value of the mode zone bit under the corresponding working mode according to the data in the analyzed mode switching instruction.
7. The chip of claim 1, wherein the data transceiving instructions comprise: a data write instruction and a data read instruction;
the data receiving and transmitting module is used for reading data on the corresponding chip functional module through the state machine module according to the analyzed operation instruction when the operation instruction is a data reading instruction; when the operation instruction is a data writing instruction, writing corresponding target data into a corresponding chip function module through the state machine module according to the analyzed operation instruction;
the data format of the data writing instruction comprises: writing address character string, writing address ending character, target data information and data writing instruction ending character;
the data format of the data reading instruction comprises: a read address string, a read address terminator, length information of read data, and a data read instruction terminator;
the data format of the mode switching instruction includes: predefined characters, different working modes correspond to different predefined characters;
the read-write mode includes: a first-in first-out mode and an address increment mode, wherein when the chip is in the first-in first-out mode, the state machine module fixes the starting address of data transmission so as to ensure that the first-in first-out entry is hit and complete the reading and writing operation of data on the corresponding chip functional module; when the chip is in the address increment mode, the state machine module automatically accumulates the starting address of data transmission after each data transmission so as to finish the data read-write operation of the corresponding chip functional module.
8. A method for controlling a chip, comprising:
receiving and converting a serial operation instruction sent by an upper computer, wherein the types of the operation instruction comprise: a mode switching instruction and a data receiving and transmitting instruction;
judging the type of an operation instruction, controlling a chip function module on a chip according to the operation instruction when the operation instruction is a data receiving and transmitting instruction, and switching the working mode of the chip according to the operation instruction when the operation instruction is a mode switching instruction;
the working modes of the chip comprise: a read-write mode and a baud rate update mode; when the chip is in the read-write mode, performing data read-write operation on the corresponding chip functional module through a state machine module according to the parsed data receiving-transmitting instruction; when the chip is in the baud rate updating mode, updating the baud rate of the data receiving and transmitting module through a state machine module according to the analyzed mode switching instruction; the data transceiver module is used for receiving and converting the operation instruction sent by the upper computer, and sending the converted operation instruction to the state machine module for analysis; and receiving and converting the reported data sent by the state machine module so as to send the reported data to the upper computer.
9. The method of claim 8, wherein the operational instructions further comprise: a loop instruction, wherein the loop instruction is different from the data format or/and the data content of the mode switching instruction;
the method further comprises the steps of: and when the chip is in the loop-back mode, receiving the converted loop-back instruction, and sending the converted loop-back instruction to the upper computer through the data receiving and sending module.
10. The method of claim 9, wherein the chip comprises: the device comprises a serial-parallel conversion unit, a parallel-serial conversion unit, a multiplexer, a state machine unit, a character analysis unit and a character sending unit;
the state machine unit is respectively connected with the character analysis unit and the character sending unit in a communication way, and the multiplexer comprises: the output end is selectively in communication connection with the first input end and the second input end;
the output end is in communication connection with the parallel-serial conversion unit, the first input end and the character analysis unit are in communication connection with the serial-parallel conversion unit together, and the second input end is connected with the character sending unit;
the method further comprises the steps of: when the chip is in the read-write mode, the output end is communicated with the second input end; when the chip is in the loop-back mode, the output end is communicated with the first input end, so that the converted loop-back instruction is sent to the upper computer through the first input end.
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