CN116895231A

CN116895231A - Gamma voltage generator, source driver and display device

Info

Publication number: CN116895231A
Application number: CN202310272374.8A
Authority: CN
Inventors: 罗吉逸
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2022-03-30
Filing date: 2023-03-20
Publication date: 2023-10-17
Also published as: CN116895230A

Abstract

Provided are a gamma voltage generator, a source driver, and a display device. The gamma voltage generator includes: a gamma voltage generating circuit having a plurality of voltage input terminals and a plurality of voltage output terminals, the plurality of voltage output terminals outputting a predetermined number of gamma voltages based on input voltages from the plurality of voltage input terminals; and a plurality of buffers, each buffer having an input terminal receiving a corresponding gamma reference voltage and an output terminal connected to a corresponding voltage input terminal, wherein the gamma voltage generation circuit includes a plurality of resistor units connected in series, and a connection node of adjacent resistor units is used as or connected to one voltage output terminal, each resistor unit being configured such that a second resistance value when operating in the second mode is smaller than a first resistance value when operating in the first mode.

Description

Gamma voltage generator, source driver and display device

The present application claims priority and benefit from U.S. provisional application serial No. 63/325,152 filed 3/2022, 30, which is incorporated by reference for all purposes as if fully set forth herein.

Technical Field

The present application relates generally to the field of display technology, and more particularly, to a gamma voltage generator, a source driver including the gamma voltage generator, and a display device.

Background

The display device includes a display panel and a driver. The display panel includes scan lines, data lines, and pixels. The driver may include a gate driver and a source driver. Each pixel may emit light of a luminance corresponding to a data voltage supplied through a corresponding data line in response to a gate signal supplied through the corresponding gate line. A gamma voltage generator (e.g., included in a source driver integrated circuit IC) in the source driver may generate a plurality of gamma voltages respectively corresponding to the plurality of gray values based on the gamma reference voltages, and may convert gray scale values of display data into data voltages using the respective gamma voltages, so that each pixel displays based on the corresponding data voltages.

Accordingly, it is very important to rapidly establish and stabilize the respective gamma voltages for generating the data voltages to secure the display effect.

Disclosure of Invention

According to an aspect of the present application, there is provided a gamma voltage generator connected to the gamma voltage generator for outputting a predetermined number of gamma voltages, and each channel circuit selects at least one gamma voltage according to input display data to generate a corresponding data voltage, wherein the gamma voltage generator includes: the gamma voltage generating circuit is provided with a plurality of first voltage input terminals, a plurality of second voltage input terminals and a plurality of voltage output terminals; the input end of each basic buffer receives a corresponding gamma reference voltage, and the output end of each basic buffer is connected to a corresponding first voltage input endpoint; and a plurality of dynamic buffers, each of the dynamic buffers having an input terminal receiving a corresponding gamma reference voltage and an output terminal connected to a corresponding second voltage input terminal and configured to operate in a first mode or a second mode, wherein each dynamic buffer does not output a buffer voltage when in the first mode and outputs a buffer voltage to the connected second voltage input terminal when in the second mode, wherein at least a portion of the plurality of dynamic buffers are switched from the first mode to the second mode based on an update or change of the display data.

According to another aspect of the present application, there is also provided a gamma voltage generator including: a gamma voltage generating circuit having a plurality of voltage input terminals and a plurality of voltage output terminals, the plurality of voltage output terminals outputting a predetermined number of gamma voltages based on input voltages from the plurality of voltage input terminals; and a plurality of buffers electrically connected to the plurality of voltage input terminals, respectively, wherein the gamma voltage generating circuit includes a plurality of resistor units connected in series, and a connection node of adjacent resistor units is connected to one voltage output terminal, each resistor unit being configured such that a second resistance value when operated in the second mode is smaller than a first resistance value when operated in the first mode.

According to another aspect of the present application, there is also provided a source driver including: a gamma voltage generator as described above; and a plurality of channel circuits connected to the gamma voltage generator for generating respective data voltages corresponding to the input display data using the gamma voltages output from the gamma voltage generator.

According to another aspect of the present application, there is also provided a display apparatus including: a display panel; the source driver is used for driving the display panel.

The gamma voltage generator according to the embodiment of the application can reduce the offset of the generated gamma voltage relative to the expected gamma voltage and improve the driving capability of the gamma voltage output by the gamma voltage generating circuit when the gamma voltage (for example, the update or change of the display data) needs to be reestablished and stabilized by introducing the dynamic buffer and/or the variable resistor unit, and simultaneously accelerate the process of establishing and stabilizing the gamma voltage, thereby ensuring the display effect. In addition, by changing the operation mode of the dynamic buffer only when the display data is changed, the total power consumption can be saved. In addition, under the condition that the plurality of source driver circuits drive the same display panel, the plurality of source driver circuits all adopt the gamma voltage generator of the embodiment of the application, so that the display color difference can be reduced, and the display effect is improved.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

Fig. 1A-1B show schematic block diagrams of display devices according to embodiments of the present disclosure.

Fig. 2 is an exemplary block diagram of a source driver included in the display device of fig. 1A-1B.

Fig. 3A-3B are exemplary circuit diagrams of a gamma voltage generator included in the source driver of fig. 2.

Fig. 4 is an exemplary circuit diagram of a gamma voltage generator according to an embodiment of the present application.

Fig. 5 illustrates a mode switching timing diagram based on a change of display data according to an embodiment of the present application.

Fig. 6 shows a mode switching timing diagram based on updating of display data according to an embodiment of the present application.

Fig. 7 illustrates another mode switching timing diagram based on updating of display data according to an embodiment of the present application.

Fig. 8-11 illustrate example structures of dynamic buffers according to embodiments of the present application.

Fig. 12A shows a schematic diagram of another gamma voltage generator according to an embodiment of the present application.

Fig. 12B shows an example circuit configuration of the resistor unit.

Fig. 13 shows a schematic diagram of another gamma voltage generator according to an embodiment of the present application.

Fig. 14-15 show schematic diagrams of a source driver including two source driver circuits according to an embodiment of the present application.

Detailed Description

It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless otherwise limited, the term "connected" and variations thereof herein are used broadly and encompass both direct and indirect connections, and may include electrical or physical connections.

Fig. 1A-1B show schematic block diagrams of display devices according to embodiments of the present disclosure. Referring to fig. 1A, a display device 10 according to an exemplary embodiment of the inventive concept may include a display driving device 20 and a display panel 30. In some embodiments of the present disclosure, the display panel 30 may be a Liquid Crystal Display (LCD) panel or an Organic Light Emitting Diode (OLED) panel, but the display panel 30 is not limited to any particular type of display panel.

As shown in fig. 1B, the display driving apparatus 20 may include: a gate driver 21 and a source driver 22 for inputting display data received from an external processor or the like to the display panel 30; a timing controller 23 for controlling the gate driver and the source driver. The timing controller 23 may control the gate driver and the source driver according to the vertical synchronization signal and the horizontal synchronization signal. The display panel 30 may include a plurality of pixels PX arranged along a plurality of gate lines G1 to Gm and a plurality of data lines S1 to Sn.

The display device 10 may display an image in units of frames. The time required to display one frame may be referred to as a vertical period, and the vertical period may be determined by the frame rate of the display device 10. During one vertical period, the gate driver 21 may sequentially scan the plurality of gate lines G1 to Gm. The time for the gate driver 21 to scan each of the plurality of gate lines G1 to Gm may be referred to as a horizontal period. During one horizontal period (pulse interval of two horizontal synchronization signals (Hsync)), the source driver 22 may input a data voltage to the pixels PX on the respective data lines S1 to Sn. The data voltage may be a voltage output by the source driver 22 based on the display data, and the luminance of each pixel PX may be determined by its corresponding data voltage.

The processor for transmitting the display data to the display driving device 20 may be an Application Processor (AP) in the case of a mobile device, or a Central Processing Unit (CPU) or a system on chip (SoC) in the case of a desktop computer, a laptop computer, a television, or the like. In detail, a processor may be understood as a processing device having an arithmetic function. The processor may generate display data to be displayed by the display device 10 or receive display data from a memory, a communication module, or the like and transmit the display data to the display driving device 20.

Referring to fig. 2, the source driver 22 may include a gamma voltage generator 201 and a plurality of channel circuits CH. Each channel circuit CH includes a shift register 210, a latch circuit 220, a digital-to-analog converter DAC 230, a source buffer BF 240, and the like. Each element included in the source driver 22 is not limited to the embodiment shown in fig. 2, and may be variously modified in other embodiments.

The gamma voltage generator 201 generates a plurality of gamma voltages VG and supplies the plurality of gamma voltages VG to each channel circuit CH. The gamma voltage generator 201 may determine the number of the plurality of gamma voltages VG based on the number of bits of the display data. For example, when the display data is 8-bit data, the number of the plurality of gamma voltages VG may be 256 or less, and when the display data is 10-bit data, the number of the plurality of gamma voltages VG may be 1024 or less. In other words, when the display data is data having n bits, the plurality of gamma voltages VG may have at most 2 ⁿ A different voltage value. It should be appreciated that the specific values of the plurality of gamma voltages VG may be selected according to practical situations.

After the shift register 210 receives the corresponding display data RGB and extracts the display data RGB according to the time sequence, the latch circuit 220 can sample and hold the display data according to the shift sequence of the shift register 210. The latch circuit 220 may output the latched display data RGB to the digital-to-analog converter DAC 230.

The digital-to-analog converter DAC 230 in each channel circuit CH may generate the data voltage Vdata from the plurality of gamma voltages VG. The digital-analog converter DAC 230 may select at least one of the plurality of gamma voltages VG in response to the latched display data RGB from the latch circuit, and may output the selected voltage as the data voltage Vdata. The digital-to-analog converter DAC 230 may include a plurality of switching elements for selecting at least one of a plurality of gamma voltages. For example, the digital-analog converter DAC 230 may output the data voltage Vdata corresponding to the gray value by using a separate lookup table defining a relationship between the gray value and the plurality of gamma voltages, or by performing a logic process on the gray value. For example, the data voltage Vdata may have 256 voltage levels corresponding to 8-bit gray scale values. The data voltage Vdata corresponding to each gray value may be located on the gamma curve. More specifically, the digital-to-analog converter DAC 230 may output the data voltage Vdata corresponding to the gamma curve through a logic process of a plurality of gamma voltages that are linear. Alternatively, in some cases, the data voltage may be generated based on the selected two or more gamma voltages.

The source buffer 240 in each channel circuit CH may be connected to a corresponding one of the data lines provided in the display panel. The source buffer 240 may receive and amplify the data voltage Vdata from the digital-to-analog converter DAC 230, and may apply the amplified data voltage Vdata to a corresponding data line. The data voltages Vdata mentioned later refer to the amplified data voltages Vdata.

Fig. 3A is an exemplary circuit diagram of a gamma voltage generator included in the source driver 22 of fig. 2. The source driver may include a source driver circuit, such as an Integrated Circuit (IC).

As shown in fig. 3A, the gamma voltage generator 201 of the source driver includes a plurality of buffers 311 and a gamma voltage generating circuit 312, and the source driver 22 may further include a gamma reference voltage circuit 310. The gamma reference voltage circuit 310 may be internal or external to the gamma voltage generator 201.

The gamma reference voltage circuit 310 provides a plurality of gamma reference voltages for generating gamma voltages, and each buffer has an input terminal receiving one gamma reference voltage and an output terminal outputting a buffer voltage to the gamma voltage generating circuit 312. The gamma voltage generation circuit 312 generates a plurality of gamma voltages from the plurality of buffer voltages output from the plurality of buffers. Each buffer may be implemented with an operational amplifier (OP), for example, having one input connected to its output and the other input connected to the gamma reference voltage circuit 310 to receive a corresponding gamma reference voltage.

As an example, the gamma reference voltage circuit 310 may take the form of a resistor string (which may be referred to as a source resistor string) composed of a plurality of resistors connected in series to divide an input voltage inputted to both ends of the resistor string to obtain the plurality of gamma reference voltages. Also, the gamma voltage generation circuit 312 may also take the form of a resistor string (may be referred to as a gamma resistor string) to divide an input voltage input to both ends of the resistor string to generate a plurality of gamma voltages, wherein a plurality of buffer voltages output from a plurality of buffers are respectively supplied to partial connection nodes between adjacent resistors of the gamma resistor string, and at least a part of the connection nodes of the gamma resistor string may be connected to or as output terminals (also referred to as output terminal nodes or nodes, etc. for connection) of the gamma voltage generation circuit 312. It should be noted that one resistor symbol shown in the figure may represent a plurality of resistors.

As described above, the rapid establishment and stabilization of the respective gamma voltages is critical to secure the display effect, and thus a corresponding solution is required. For example, in the case of a high frame rate display operation, the display time allocated to each frame is relatively short, so the setup time requirement for the gamma voltages is high, and stable respective gamma voltages are also advantageous for generating accurate data voltages.

In addition, as the size of the display panel increases, it may be necessary to drive the same display panel using two or more source driver circuits (e.g., source driver integrated circuits ICs). However, due to limitations of manufacturing and design processes, there may be a difference in gamma voltages generated by gamma voltage generators included in each of two or more source driver circuits driving the same display panel, thereby possibly causing non-uniformity of display of the display panel, for example, a significant color difference between display areas controlled by different source driver circuits.

In this regard, an example in which two source driver circuits are included in a source driver (for example, each source driver circuit may be integrated into one IC) so that the two source driver circuits commonly drive the same display panel is shown in fig. 3B. Of course, the source driver may include more than two source driver circuits.

As shown in FIG. 3B, the first source driver circuit 31 (IC 1) and the second source driver circuit 32 (IC 2) have the same circuit configuration, and each of the gamma voltage generators 201 includes a plurality of buffers (311; 321) and a gamma voltage generating circuit (312; 322). Each source driver circuit (31; 32) may also include a gamma reference voltage circuit (310; 320), such as a source resistor string, for providing the required gamma reference voltages to the gamma voltage generator 201, respectively.

At least one power transmission terminal P of the first source driver circuit 31 (IC 1) is electrically connected to at least one corresponding power transmission terminal P' of the second source driver circuit 32 (IC 2) to form an electrical connection between the source driver circuit 31 (IC 1) and the source driver circuit 32 (IC 2). The number of electrical connections between the power transmission terminals of the first source driver circuit 31 (IC 1) and the second source driver circuit 32 (IC 2) is determined according to design requirements, and the present disclosure is not limited to a specific number.

According to the embodiment of the present disclosure, the first source driver circuit 31 (IC 1) serves as a master circuit and the second source driver circuit 32 (IC 2) serves as a slave circuit, all buffers in the second source driver circuit 32 (IC 2) may be turned off, or all buffers other than the buffers providing the maximum and minimum gamma reference voltages (same as the maximum and minimum gamma reference voltages in the first source driver) to the second gamma voltage generating circuit according to a circuit structure such as a connection manner of the source resistor string and the gamma resistor string may be turned off. In this case, the at least one power transmission terminal P included in the first source driver circuit 31 (IC 1) may supply the buffer voltages output from the output end of at least one buffer inside the first source driver circuit 31 (IC 1) to the at least one power transmission terminal P' as the input terminal of the second source driver circuit 32 (IC 2) via an electrical connection between the power transmission terminals of the first source driver circuit 31 (IC 1) and the second source driver circuit 32 (IC 2) to supply the buffer voltages to the gamma voltage generator inside the second source driver circuit 32 (IC 2); and vice versa.

As shown in fig. 3B, the off buffers are shown in gray, the on buffers are shown in white, and in the second source driver circuit 32, only the uppermost and lowermost two buffers are enabled, and the other buffers are turned off. In this way, through the electrical connection between the power transmission terminals of the two source driver circuits described above, the plurality of buffer voltages of the plurality of buffers in the first source driver circuit are also supplied to the gamma voltage generation circuit of the second source driver circuit (or more source driver circuits, if any). Accordingly, it is possible to achieve a reduction in voltage difference between gamma reference voltages used by two source driver circuits and a reduction in voltage difference between generated gamma voltages because the second source driver circuit can generate a plurality of gamma voltages using the same plurality of buffer voltages, the maximum gamma reference voltage, and the minimum gamma reference voltage as the first source driver circuit, so that display uniformity can be improved to some extent when two or more source driver Integrated Circuits (ICs) drive the same display panel, thereby improving display effects.

Since in the gamma voltage generator of fig. 3A-3B, the gamma voltages at the partial output terminals in the gamma resistor string are established and stabilized by the plurality of buffer voltages outputted from the plurality of buffers, since the gamma voltages at the partial output terminals are provided by the buffer voltages outputted from the partial buffers for the gamma resistor string, the voltages at the respective divided nodes can be obtained quickly, that is, the gamma voltages at all the output terminals can be established and stabilized as quickly as possible, and the driving capability of the generated gamma voltages can be improved. However, since the number of gamma voltages required to be generated is generally large, for example 256, 512 or 1024, etc., according to the number of bits of gray values, and the number of buffers is much smaller than that (since the buffers may also cause errors in gamma voltages due to process mismatch, too many buffers may cause large errors in gamma voltages), the setup and settling time of gamma voltages may still be long, which may not satisfy the current requirements, particularly under high frame rate display operation. Further, even though in fig. 3B, the voltage difference between the gamma reference voltages used by the two source driver circuits and the voltage difference between the generated gamma voltages can be reduced, the setup and settling time of the gamma voltages in the slave circuits is slower relative to the master circuits due to parasitic resistance of the wires connected between the power transmission terminals of the two source driver circuits, which may cause color difference problems in the display images, particularly in the case where the setup and settling time requirements are more stringent, particularly in the high frame rate display operation.

Accordingly, there is a need for a gamma voltage generator capable of rapidly establishing and stabilizing gamma voltages to secure a display effect of a display panel. Further, it is also desirable that even when two or more source driver circuits (including two or more gamma voltage generators, respectively) drive the same display panel, a uniform display effect of the display panel can be ensured based on such gamma voltage generators.

Fig. 4 shows a schematic diagram of a gamma voltage generator according to an embodiment of the present application.

As shown IN fig. 4, the gamma voltage generator 400 includes a gamma voltage generating circuit 410, a plurality of elementary buffers (420-IN 1/IN2, 420-1, 420-2, …, 420-N1, hereinafter collectively referred to as 420), and a plurality of dynamic buffers (430-1, 430-2, …, 430-N2, hereinafter collectively referred to as 430). The gamma voltage generator 400 may be included in a source driver circuit (IC), such as IC1 or IC2 shown in fig. 3B.

The gamma voltage generating circuit 410 has a plurality of first voltage input terminals IN1, a plurality of second voltage input terminals IN2, and a plurality of voltage output terminals O for outputting a predetermined number of gamma voltages. Alternatively, the gamma voltage generation circuit 410 may be a gamma resistor string composed of a plurality of resistors connected IN series, each connection node between the resistors IN the gamma resistor string may be regarded as or connected to one voltage output terminal, and each of the plurality of first voltage input terminals IN1 and the plurality of second voltage input terminals IN2 may be connected to a corresponding one of the voltage output terminals O so that a buffer voltage may be outputted from the corresponding one of the voltage output terminals O (and each buffer voltage may be regarded as one gamma voltage). For illustration IN fig. 4, the plurality of first voltage input terminals IN1 and the plurality of second voltage input terminals IN2 are each shown separately from the corresponding voltage output terminals O, but it should be understood that each voltage input terminal and the corresponding voltage output terminal may be the same terminal, for example, a connection node between adjacent resistors IN a gamma resistor string. In addition, one resistor symbol between an adjacent pair of voltage input terminals is shown in fig. 4 for illustration only, which may actually include a plurality of resistors (e.g., connected in series) and is not limited to the number illustrated for outputting gamma voltages at respective connection nodes (connected to or as a plurality of voltage output terminals) by the plurality of resistors.

Each of the elementary buffers 420 has a respective input terminal receiving a corresponding gamma reference voltage (e.g., connected to a corresponding one of the output nodes of the gamma reference voltage circuit), and an output terminal connected to a corresponding one of the plurality of first voltage input terminals; and an input of each dynamic buffer 430 receives a corresponding gamma reference voltage (e.g., connected to a corresponding one of the output nodes of the gamma reference voltage circuit), an output connected to a corresponding one of the plurality of second voltage input terminals, and configured to operate in either the first mode or the second mode. Each dynamic buffer outputs no buffer voltage in the first mode and outputs a buffer voltage to the connected second voltage input terminal in the second mode.

For example, for the dynamic buffer 430-1, when IN the first mode, the dynamic buffer 430-1 is turned off, and the voltage at its input is not output to the output, so its output does not provide the buffer voltage to the connected second voltage input terminal IN 2; when IN the second mode, the dynamic buffer 430-1 is turned on, and the voltage at its input is output to the output, so that its output provides the buffer voltage to the connected second voltage input terminal IN 2. The other dynamic buffers also operate synchronously with dynamic buffer 430-1, so in the first mode, the dynamic buffers may be considered inactive.

In this way, in the case where the gamma voltage generator 400 is not connected to other gamma voltage generators, or the gamma voltage generator 400 needs to output buffer voltages to other gamma voltage generators (as a main circuit in the case of two or more source driver circuits to be described later), the gamma voltage generator 400 may output a plurality of gamma voltages VGM at a plurality of voltage output terminals O based on the buffer voltages of a plurality of basic buffers and optionally the buffer voltages of a plurality of dynamic buffers. Also, in the case where the gamma voltage generator 400 is connected to other gamma voltage generators but does not need to output buffer voltages to other gamma voltage generators (as a slave circuit in the case of two or more source driver circuits to be described later), the plurality of basic buffers are not enabled, or only two basic buffers providing the maximum gamma reference voltage and the minimum gamma reference voltage may be enabled.

For example, the first mode is standby (standby) mode and the second mode is Boost (Boost) mode. The trigger mode is adapted for a period before the generated predetermined number of gamma voltages stabilize (i.e., a plurality of buffer voltages need to be continued to establish and stabilize the plurality of gamma voltages at the output terminal of the gamma voltage generator), and the standby mode is adapted for a period after the generated predetermined number of gamma voltages stabilize.

Accordingly, based on the gamma voltage generator 400 shown in fig. 4, the plurality of dynamic buffers may be operated in the second mode when the gamma voltage needs to be established and stabilized, so that the plurality of basic buffers and the plurality of dynamic buffers each supply the buffer voltage to the gamma voltage generating circuit 410, whereby the rate of establishment and stabilization of the gamma voltage may be increased, and the plurality of dynamic buffers may be operated in the first mode after the gamma voltage is established and stabilized, to avoid an excessive buffer from introducing an error of the undesired gamma voltage.

Further, in some embodiments, when it is desired to establish and stabilize the gamma voltage, only a portion of the plurality of dynamic buffers may be operated in the second mode, without having to operate all of the dynamic buffers in the second mode. For example, in one embodiment, only the dynamic buffer outputting the gamma voltage having a lower value is turned on for a particular image mode. In addition, although an alternating arrangement of the dynamic buffers and the basic buffers is illustrated in fig. 4, this is merely exemplary, and the dynamic buffers may not be arranged between every two basic buffers, or one or more dynamic buffers may be arranged such that at least one second voltage input terminal exists between each pair of adjacent first voltage input terminals among the plurality of first voltage input terminals of the gamma voltage generating circuit, or no second voltage input terminal exists. The deployment of dynamic buffers and the number of dynamic buffers that need to operate in the second mode may be determined in an appropriate manner according to system requirements.

As described with reference to fig. 2, the gamma voltage generator is connected to a plurality of channel circuits, each of which generates a data voltage by selecting at least one gamma voltage from a plurality of gamma voltages output from the gamma voltage generator according to display data (referred to as pixel data) for a certain pixel currently applied to the channel circuit. Each channel circuit is used for sequentially supplying data voltages to a column of pixels on one data line in the order of row scanning. For example, for data writing of the first row of pixels, the plurality of channel circuits need to output Vdata1, vdata2, … to the respective corresponding data lines. Thus, for example, in order to generate Vdata1, the first channel circuit needs to select at least one gamma voltage according to display data (e.g., a gray-scale value or a data code, also referred to as pixel data) for a pixel of the first row and the first column (pixel PX (1, 1)), thereby obtaining a corresponding data voltage Vdata1; in order to generate Vdata2, the second channel circuit needs to select at least one gamma voltage according to display data (pixel data) for pixels (pixels PX (1, 2)) of the first row and the second column, thereby obtaining a corresponding data voltage Vdata2. The operation of the other channel circuits for the pixels of the first row is also similar. The operation of the multiple channel circuits is similar when writing data to pixels of other rows.

Thus, reference to an update or change of display data in the context of the present application may refer to an update or change of pixel data loaded to a channel circuit or circuits. For example, after the end of the scanning period of the current row of pixels, display data for the next row of pixels is loaded into the plurality of channel circuits to output a plurality of data voltages (the same number as the number of channel circuits) to the next row of pixels on the panel. For each channel circuit, the display data (i.e., pixel data) for the pixel loaded into that channel circuit is updated (the value of the pixel data may also change). That is, the updating of the display data may refer to switching between two pixel data for two adjacent pixels of the same column loaded to any one channel circuit, regardless of whether the two pixel data are changed; also, the change of the display data may mean that switching occurs between two pixel data of two adjacent pixels for the same column loaded to any one of the channel circuits, and the two pixel data have a change, for example, two gradation values corresponding to the two pixel data have a change.

During display, if the display data changes, the data voltage output by one or more channel circuits changes. Since the plurality of channel circuits are connected to the voltage output terminals of the gamma voltage generator, the plurality of gamma voltages output from the gamma voltage generator may be affected by the change of the data voltage, for example, the channel circuits need to draw current from the gamma resistor string generating the plurality of gamma voltages, and thus the plurality of gamma voltages may be disturbed, while the plurality of gamma voltages output from the gamma voltage generator may not be affected if the display data is updated but not changed.

That is, when display data is changed, that is, pixel data applied to any channel circuit is changed (a change in data voltage is caused so that the plurality of gamma voltages are disturbed), it is necessary to newly and rapidly establish and stabilize the plurality of gamma voltages output from the gamma voltage generator. Thus, with the gamma voltage generator shown in fig. 4, at least a portion of the plurality of dynamic buffers may be operated in the second mode when display data is changed, so that the at least a portion of the plurality of dynamic buffers may also provide buffer voltages to the gamma voltage generating circuit 410, so that the buffer voltages output by a plurality of basic buffers (included in the same gamma voltage generator or other gamma voltage generators) may be combined, and thus the speed of establishment and stabilization of the plurality of gamma voltages output by the gamma voltage generator may be increased, and after the plurality of gamma voltages are established and stabilized (e.g., for a predetermined period of time, the predetermined time may be determined according to the structure of the gamma voltage generating circuit and the empirical value, as long as the plurality of gamma voltages are allowed to be established and stabilized), the at least a portion of the plurality of dynamic buffers may be returned to the first mode operation so as to avoid an error of an excessive buffer introducing an undesired gamma voltage.

Fig. 5 shows a mode switching timing chart based on a change in display data.

As shown in fig. 5, if updated display data (e.g., pixel data) is the same as the value of its previous display data, e.g., display data D2 for the i (i is an integer of 1 or more) th row 1 column pixel (pixel PX (i, 1)) is the same as display data D3 for the i+1th row pixel 1 column pixel (pixel PX (i+1, 1)), i.e., the display data is unchanged, the plurality of dynamic buffers may not be switched from the first mode to the second mode, but remain operated in the first mode (i.e., the buffer voltage is not output).

For example, this implementation is very advantageous for an always display (AOD) mode in which only a small portion of the screen displays an AOD image, and the pixels of the area where the image is not displayed remain unchanged when data is written, which can be seen as not changing between two display data for two adjacent pixels of the same column of the area, so that the plurality of dynamic buffers can remain operated in the first mode during the scan period corresponding to the pixels of the area, which can save overall power consumption.

Accordingly, the dynamic buffer may operate in the second mode to output the buffer voltage only when the display data is changed, which saves the total power consumption because the dynamic buffer operates in the first mode so as not to output the buffer voltage for a case where the display data is not changed (e.g., a large-area black image).

In addition, in some cases, even if the display data is changed, the plurality of gamma voltages output from the gamma voltage generator may be less affected, and it may not be necessary to reestablish and stabilize the plurality of gamma voltages. In these cases, it may be determined whether the plurality of dynamic buffers need to operate in the second mode according to a difference between an actual value and an expected value of some gamma voltages. For example, since the gamma reference voltage circuit is capable of providing accurate voltage values (expected values) at the inputs of the plurality of dynamic buffers, at least some of the plurality of dynamic buffers may be configured to switch to operate IN the second mode IN response to the voltage at the input of any one of the plurality of dynamic buffers being different from the voltage at the connected second voltage input terminal IN2 (also an actual gamma voltage output at one voltage output node), and to switch to operate IN the first mode after a predetermined period of time, or IN response to the voltage at the input of the plurality of dynamic buffers being the same as the voltage at the second voltage input terminal IN 2.

Further, in other embodiments, in order to more easily control the mode switching of the plurality of dynamic buffers, the plurality of dynamic buffers may be caused to switch from the first mode to the second mode according to the update of the display data, that is, the plurality of dynamic buffers (or a portion thereof) may be caused to switch modes even if they are not changed as long as the display data is updated. The update of the display data is synchronized with the shift of the horizontal synchronization signal (Hsync) or the scan signal, i.e., the update period of the display data is the same as the scan period.

As shown in fig. 6, the switching from the first mode (standby mode) to the second mode (trigger mode) is synchronized with the updating of the display data, i.e. when the display data is updated, for example, from the display data D1 to the display data D2, or from the display data D2 to the display data D3, or from the display data D3 to the display data D4, the plurality of dynamic buffers may enter the second mode, and then exit the second mode and enter the first mode after a period of time. The period of time may have a predetermined duration configured to allow the plurality of gamma voltages output by the gamma voltage generating circuit to be established and stabilized in the second mode.

In this case, since the update of the display data is synchronized with the shift of the horizontal synchronization signal (Hsync) or the scan signal, the mode switching of the plurality of dynamic buffers may be controlled according to the horizontal synchronization signal (Hsync) or the scan signal.

In this embodiment, switching from the first mode (standby mode) to the second mode (trigger mode) is completed before updating of the display data to perform a required plurality of gamma voltage establishment and stabilization in advance. It should be noted that since the update of the display data may involve a change in the value of the display data, which may cause a transition of the data voltages, which has a larger influence on the plurality of gamma voltages at the time of the data voltage transition, the predetermined duration of the second mode preferably overlaps with the time for the data voltage transition corresponding to the update or change of the display data, i.e., the predetermined duration of the second mode is continued at least until the data voltage transition time is completed.

In the embodiment shown in fig. 7, the switching from the first mode to the second mode is performed at a point of time of a predetermined length of time before the updating of the display data. Since the source driver processes the timing of the display data update, the mode switching can be well controlled, and the duration of the second mode can be fixed, or the duration of the second mode can be controlled according to whether the data voltage conversion is completed (the duration of the second mode is not fixed), for example, whether the data voltage conversion is completed can be judged by detecting the voltage difference of the input and output terminals of the dynamic buffer as described above, because the gamma voltage will be less affected after the data voltage conversion is completed, i.e., the detected voltage difference is small.

Several example structures for dynamic buffers are described below in connection with fig. 8-11.

In some embodiments, each dynamic buffer includes a buffer and a switching module, and the components included in the same dynamic buffer may be considered to correspond to each other. Each switching module is configured to disable the corresponding buffer output buffer voltage in the first mode and to enable the corresponding buffer output buffer voltage in the second mode.

Alternatively, the dynamic buffer may include a buffer having the same structure as a general buffer, or may have the same structure as a basic buffer, for example, but not limited thereto, and may be formed of an operational amplifier.

In fig. 8, each switching module includes one switch SW, and a first terminal of the switch SW is connected to an output terminal of a corresponding operational amplifier (OP), and a second terminal is connected to a corresponding second voltage input terminal to which an output terminal of a dynamic buffer including the operational amplifier is connected, wherein the switch SW is turned off in the first mode so that the dynamic buffer does not output a buffer voltage, and is turned on in the second mode so that the dynamic buffer outputs a buffer voltage.

In fig. 9, each switching module includes a first switch SW1, a second switch SW2 and a third switch SW3, wherein: the first switch SW1 has a first end connected to the output terminal of the corresponding operational amplifier and a second end connected to a corresponding second voltage input terminal of the corresponding dynamic buffer including the operational amplifier; the first end of the second switch SW2 and the first end of the third switch SW3 are commonly connected to one input terminal of a corresponding operational amplifier, the second end of the second switch SW2 is connected to an output terminal of the corresponding operational amplifier, and the second end of the third switch SW3 is connected to the corresponding second voltage input terminal (the other input terminal of the corresponding operational amplifier is used for receiving the gamma reference voltage). In the first mode, the first switch SW1 and the third switch SW3 are simultaneously turned off so that the dynamic buffer does not output a buffer voltage (the second switch SW2 may be turned on or off), and in the second mode, the first switch SW1 and the third switch SW3 are simultaneously turned on and the second switch SW2 is turned off so that the dynamic buffer outputs a buffer voltage. In this embodiment, the feedback control of the dynamic buffer (the connection loop of the input terminal and the output terminal of the operational amplifier) may be not affected by the parasitic resistance of the switch SW1 connected between the output terminal of the operational amplifier and the gamma voltage generating circuit, thereby allowing the gamma voltage to be more accurately and rapidly established and stabilized.

In fig. 10, each dynamic buffer includes a buffer, wherein the buffer is configured to switch between an enabled and a disabled state according to an enable signal such that the dynamic buffer switches between a first mode and a second mode. For example, the operational amplifier may be enabled or disabled in response to an enable signal EN from, for example, a controller, MCU, microprocessor, etc. within the IC, such that the dynamic buffer outputs or does not output a buffer voltage.

In addition, as described above, in the case where the dynamic buffer can be switched from the first mode to the second mode in response to the voltage at the input terminal of any one of the dynamic buffers being different from the voltage at the connected second voltage input terminal (i.e., at one voltage output terminal), the dynamic buffer may further include a voltage difference detection module in addition to the buffer (e.g., an operational amplifier) and the switching module. Alternatively, the voltage difference detection module may comprise a comparator.

As shown in fig. 11, a first detection end of each voltage difference detection module DET is connected to a first input end of a corresponding operational amplifier, a second detection end is connected to a second voltage input end point connected to a corresponding dynamic buffer, and an output end of each voltage difference detection module outputs a switching control signal.

Each switching module is configured to enable or disable the output terminal of the corresponding operational amplifier to output the buffer voltage to one of the second voltage input terminals connected to the corresponding dynamic buffer in the second mode based on the switching control signal of the corresponding voltage difference detection module or the switching control signal of the other voltage difference detection module.

For example, if the voltage difference detection module in any one or more dynamic buffers detects that the input voltages at the two input terminals thereof are different, for example, the voltage difference exceeds a predetermined threshold (0 or other value), the gamma voltages generated by the gamma voltage generation circuit may be inaccurate, and the gamma voltages need to be re-established and stabilized, so the voltage difference detection module may output a switching control signal to control the dynamic buffers or a part thereof to work together in the second mode to re-establish and stabilize the gamma voltages.

In fig. 11, the switching module of the dynamic buffer may also adopt the structure of the switching module as previously described with reference to fig. 8 to 10, for example, one switch, three-switch embodiments, and embodiments in which the dynamic buffer is responsive to an enable signal, as shown in fig. 8 to 10.

In this way, the voltage difference detection module controls the mode switching of the dynamic buffer by detecting the difference between the actual gamma voltage and the desired gamma voltage. Accordingly, the duration of the second mode (e.g., the on time of the switch SW in fig. 8) may be adjusted based on the stable behavior of the respective gamma voltages output from the gamma voltage generator. For example, if the data voltage is changed at a greater level such that more current is drawn from the resistor string of the gamma voltage generation circuit, thus causing the actual gamma voltage to deviate more from the desired gamma voltage, it may be necessary to control the duration of operating the dynamic buffer in the second mode longer to provide a higher driving capability such that the actual gamma voltage is the same as the desired gamma voltage.

Alternatively, although the structure of each dynamic buffer in each source driver circuit is the same in many cases, this is not required in other cases as long as these dynamic buffers can perform mode switching synchronously. For example, it is not necessary to provide a voltage difference detection module in each dynamic buffer, and some dynamic buffers may employ a structure as described in fig. 8-10, for example.

The gamma voltage generator described above with reference to fig. 4 and fig. 5 to 11 is capable of improving the driving capability of the gamma voltage output from the gamma voltage generating circuit and the setup and stabilization speed of the gamma voltage by making the dynamic buffer output the buffer voltage when the gamma voltage needs to be re-established and stabilized, and making the dynamic buffer not output the buffer voltage after the gamma voltage is setup and stabilized to avoid the introduction of an undesired error of the gamma voltage by introducing the dynamic buffer. In addition, by changing the operation mode of the dynamic buffer only when the display data is changed, that is, switching from the first mode to the second mode, and not changing the operation mode of the dynamic buffer when the display data is not changed, the total power consumption can be saved.

The above embodiment of introducing the dynamic buffer may be considered as increasing the driving capability of the gamma voltage output from the gamma voltage generating circuit, which may be equivalently implemented by decreasing the resistance value of the resistor string in other embodiments in which the gamma voltage generating circuit includes the resistor string.

As shown in fig. 12A, the gamma voltage generator 1200 (which may be the gamma voltage generator in fig. 2) includes a gamma voltage generating circuit 1210, a plurality of buffers (1220-1, 1220-2, …, 1220-N, hereinafter collectively referred to as 1220). The gamma voltage generator 1200 may be included in an Integrated Circuit (IC) of a source driver.

The gamma voltage generation circuit 1210 has a plurality of voltage input terminals IN for outputting a predetermined number of gamma voltages based on input voltages from the plurality of voltage input terminals IN and a plurality of voltage output terminals O. In some embodiments (multiple resistor units in series in this embodiment) in which the gamma voltage generation circuit is a gamma resistor string, each voltage input terminal may be connected to a corresponding voltage output terminal, and each voltage input terminal and corresponding voltage output terminal may be the same terminal, for example, a connection node between adjacent resistor units in the gamma resistor string.

The plurality of buffers 1220 (1220-1, 1220-2, …, 1220-N) are electrically connected to the plurality of voltage input terminals IN, respectively. In this way, in a case where the gamma voltage generator 1200 is not connected to other gamma voltage generators, or the gamma voltage generator 1200 needs to output buffer voltages to other gamma voltage generators (as a main circuit in a case of two or more source driver circuits to be described later), the gamma voltage generator 1200 can output a plurality of gamma voltages at a plurality of voltage output terminals O based on the buffer voltages of a plurality of buffers. Also, in a case where the gamma voltage generator 1200 is connected to other gamma voltage generators but does not need to output buffer voltages to other gamma voltage generators (as a slave circuit in a case of two or more source driver circuits to be described later), the plurality of buffers may not be enabled or only enable two buffers providing the maximum reference voltage and the minimum reference voltage.

In order to improve the driving capability of the gamma voltage, the gamma voltage generating circuit includes a plurality of resistor units RVA connected in series, and connection nodes of adjacent resistor units RVA are connected to or serve as one voltage output terminal, each resistor unit being configured to have a first resistance value in a first mode, a second resistance value in a second mode, and the second resistance value being smaller than the first resistance value. The combination of a plurality of resistor units RVA is schematically shown by one resistor symbol RS. The number of the series-connected resistor units RVA represented by each resistor symbol RS may be determined according to the number of gamma voltages required to be output, not limited to the number illustrated.

In this way, the gamma voltage generating circuit outputs the predetermined number of gamma voltages for a first period of time when each resistor unit RVA has a first resistance value, which is longer than a second period of time when each resistor unit RVA has a second resistance value.

The first mode of the resistor unit in this embodiment is also a standby mode and the second mode is a trigger mode corresponding to the first mode and the second mode of the previous dynamic buffer. For example, in a case where the gamma voltage outputted from the gamma voltage generator needs to be re-established and stabilized, the resistor unit operates in the trigger mode, and after the gamma voltage outputted from the gamma voltage generator is established and stabilized, that is, the gamma voltage does not need to be established and stabilized, the resistor unit operates in the standby mode.

In this way, in the trigger mode (second mode), each resistor unit RVA in the gamma voltage generating circuit may be configured to have a smaller resistance value, so that more current may rapidly flow through the plurality of resistor units connected in series to more rapidly establish and stabilize the gamma voltage. In the standby mode (first mode), each resistor unit RVA may be configured to have a larger resistance value, and thus the overall power consumption may be reduced.

Alternatively, fig. 12B shows an example circuit structure of one resistor unit. Alternatively, the resistance values of all the resistor units in the gamma voltage generating circuit in the first mode are the same, and the resistance values in the second mode are also the same, for example, all the resistor units may have the same circuit structure.

As shown in fig. 12B, the resistor unit may include a bypass switch SWB and a plurality of resistors connected in series, the bypass switch SWB being connected in parallel with at least one (two are shown in the drawing) of the plurality of resistors, wherein the bypass switch is configured to be turned on in the second mode and turned off in the first mode. It can be seen that the resistance value (second resistance value) of the resistors connected in series in the resistor unit in the second mode is smaller than the resistance value (first resistance value) of the resistors connected in series in the resistor unit in the first mode.

Alternatively, switching from the first mode to the second mode may also be controlled in response to an update or change in display data, similar to that described above with reference to fig. 4-11.

For example, when display data input to the plurality of channel circuits is updated, the plurality of resistor units connected in series may be switched to operate in the second mode to quickly reestablish and stabilize the gamma voltage, and the plurality of resistor units connected in series are returned to operate in the first mode after a predetermined period of time.

Alternatively, as described previously, the display data input to the plurality of channel circuits is periodically updated (e.g., based on the horizontal synchronization signal Hsync or the scan signal), so at a point of time a predetermined length of time before the start point of each update period, the plurality of resistor units connected in series may be switched to operate in the second mode to quickly reestablish and stabilize the gamma voltage, and the plurality of resistor units connected in series are returned to operate in the first mode after a predetermined period of time.

Alternatively, as described above, when the display data input to the plurality of channel circuits is changed, the plurality of resistor units are switched to operate in the second mode and are returned to operate in the first mode after a predetermined period of time. In this way, the overall power consumption can be further reduced. In some embodiments, a processor internal to the source driver may determine changes between display data.

Accordingly, in the gamma voltage generator described with reference to fig. 12A to 12B, by making the resistance value of the resistor unit in the first mode larger than that in the second mode, so that in the second mode, more current in the gamma voltage generating circuit can flow through the plurality of resistor units in series more quickly to establish and stabilize the gamma voltage, and after the gamma voltage is established and stabilized, returning to operate in the first mode, the overall power consumption can be reduced.

According to still other embodiments, a plurality of dynamic buffers and a plurality of resistor units having variable resistance values as previously described may be commonly combined into the same gamma voltage generator, for example, as shown in fig. 13, a gamma voltage generator 1200 includes not only a plurality of dynamic buffers (shown in gray patterns) and a plurality of basic buffers (shown in white), but also a gamma circuit generating circuit 1210 including a plurality of resistor units RVA (having variable resistance values) connected in series. The operation timing and specific structure of the dynamic buffer and the resistor unit have been described in detail in the foregoing, and thus are not repeated here.

Thus, in the second mode, the plurality of dynamic buffers may be connected to the gamma voltage generating circuit 1210 (including a plurality of resistor units connected in series) together with the basic buffer, while the plurality of resistor units included in the gamma voltage generating circuit 1210 may have smaller resistance values (e.g., bypass switches are turned on). In this way, the scheme of combining the dynamic buffer and the resistor unit having the variable resistance value can further reduce the setup and stabilization time of the gamma voltage and improve the driving capability of the gamma voltage output from the gamma voltage generator. Such an embodiment may allow the display device to operate at an ultra-high frame rate.

According to another aspect of the present application, a source driver is provided, which may include a gamma voltage generator as previously described (e.g., described with reference to fig. 4-13), for example, which may be integrated into a source driver circuit (IC).

In addition, in some other application scenarios, such as folding cell phones with flexible display screens, the display screen is increasingly larger in size, so the source driver may include more than two source driver circuits (each including a gamma voltage generator) to drive the same display panel, for example as shown in fig. 3B.

Where the source driver may include more than two source driver circuits, the gamma voltage generator in at least one of the source drivers may employ the structure of the gamma voltage generator as described with reference to fig. 4, and accordingly, the mode switching timing and switching manner described with reference to fig. 5 to 11, etc. may be utilized. The source driver circuit that supplies the buffer voltage to the other source driver circuits via the wiring between the power transmission terminals of the source driver circuits may be regarded as a master circuit, and the other source driver circuits may be regarded as slave circuits.

For example, in a dynamic buffer-based scheme, as shown in fig. 14, the source driver 1400 may include a first source driver circuit (IC 1) and a second source driver circuit (IC 2). The first source driver circuit may be regarded as a master circuit and the second source driver circuit may be regarded as a slave circuit.

At least one of the gamma voltage generator 1400-1 (first gamma voltage generator) included in the first source driver circuit (IC 1) and the second gamma voltage generator 1400-2 included in the second source driver circuit (IC 2) may employ the structure of the gamma voltage generator 400 described with reference to fig. 4.

In fig. 14, a case where the first gamma voltage generator 1400-1 adopts the structure of the gamma voltage generator 400 described with reference to fig. 4 is exemplarily shown, while the second gamma voltage generator 1400-2 may adopt the structure of the gamma voltage generator 201 described with reference to fig. 4 or adopt other structures (e.g., a structure in which all buffers adopted as in the related art are basic buffers). It should be understood that in other embodiments, the second gamma voltage generator 1400-2 may employ the structure of the gamma voltage generator 201 described with reference to fig. 4, while the first gamma voltage generator 1400-1 employs the structure of the gamma voltage generator 201 described with reference to fig. 4 or other structures. According to the embodiment of the present disclosure, the two gamma voltage generators may be different in structure, but the number and voltage values of the gamma voltages they output should be the same. Alternatively, the source driver circuit as a slave circuit may not even include a basic buffer (or only include two basic buffers that provide the maximum gamma reference voltage and the minimum gamma reference voltage to the gamma voltage generating circuit included therein) since the buffer voltage may be received from the source driver circuit as a master circuit. Considering that in the case where the structures of the gamma voltage generators of the two source driver circuits are different, the setup and stabilization times of the gamma voltages output by the gamma voltage generators in the two source driver circuits may be inconsistent, which may cause a color difference problem in the display image; further, in consideration of production costs and design complexity, the gamma voltage generators of the respective source driver circuits generally included in the same source driver have the same structure, and thus, the first gamma voltage generator 1400-1 and the second gamma voltage generator 1400-2 may have the same structure of the gamma voltage generator.

Thus, as an example, when both the first and second gamma voltage generators 1400-1 and 1400-2 employ the structure of the gamma voltage generator described with reference to fig. 4, the plurality of elementary buffers included in the first gamma voltage generator 1400-1 may output a first set of buffer voltages to the corresponding plurality of first voltage input terminals and transfer to the second gamma voltage generator 1400-2, and then the second gamma voltage generator 1400-2 may be configured to receive the first set of buffer voltages from the first gamma voltage generator 1400-1 (e.g., via the electrical connection between the power transmission terminals P-P' as described previously) for outputting a second predetermined number of gamma voltages. Since the plurality of basic buffers included in the first gamma voltage generator 1400-1 maintain the output of the first set of buffer voltages, the first set of buffer voltages may be continuously supplied to the second gamma voltage generator 1400-2. It should be noted that each power transmission terminal P (as an output terminal) of the first source driver circuit (IC 1) is connected to a corresponding voltage output terminal of the gamma voltage generation circuit 1411 and a corresponding first voltage input node, so that a buffer voltage can be received from a corresponding one of the basic buffers and taken as an output voltage at the power transmission terminal P.

The second gamma voltage generator 1400-2 has the same structure as the first gamma voltage generator 1400-1, and includes: the second gamma voltage generating circuit 1412, a plurality of basic buffers (i.e., a second set of basic buffers), and a plurality of dynamic buffers (i.e., a second set of dynamic buffers). The second gamma voltage generating circuit 1412 has a first voltage input terminal of the second set, a second voltage input terminal of the second set, and a voltage output terminal of the second set; the input ends of the basic buffers of the second set respectively receive corresponding gamma reference voltages, and the output ends of the basic buffers of the second set are respectively connected to the first voltage input end points of the second set; and the inputs of the second set of dynamic buffers respectively receive the corresponding gamma reference voltages, the outputs are respectively connected to the second voltage input terminals of the second set, and are configured to operate in the first mode or the second mode in synchronization with the plurality of dynamic buffers in the first gamma voltage generator 1400-1. It should be noted that the expression of some element of the "second set" is used in the present application to distinguish from the expression of a plurality of corresponding elements (i.e., some element of the "first set") included in the first gamma voltage generating circuit 1411.

The second gamma voltage generator 1400-2 includes a first voltage input terminal of the second set of the second gamma voltage generating circuit 1412 that receives the first set of buffer voltages from the first gamma voltage generator 1400-1 and the second set of dynamic buffers outputs the second set of buffer voltages to a second voltage input terminal of the second set in a second mode, the second set of buffer voltages is not output in the first mode, and the second gamma voltage generating circuit 1412 outputs the second predetermined number of gamma voltages at a voltage output terminal of the second set of the second gamma voltage generator 1400-2 based on the first set of buffer voltages and the second set of buffer voltages (in the second mode) or based on the first set of buffer voltages (in the first mode).

That is, in case that the gamma voltages need to be re-established and stabilized, the dynamic buffers (all or a part, set according to system requirements) in the first and second gamma voltage generators 1400-1 and 1400-2 operate in the second mode to output buffer voltages, and the first set of buffer voltages output from the basic buffer of the first gamma voltage generator 1400-1 is supplied to the second gamma voltage generator 1400-2, so that the second gamma voltage generator 1400-2 can generate gamma voltages based on the second set of buffer voltages output from the dynamic buffers included itself and the first set of buffer voltages from the first gamma voltage generator 1400-1, whereby the second gamma voltage generator 1400-2 can accelerate the establishment and stabilization speeds of gamma voltages to some extent with respect to the case of only the first set of buffer voltages from the first gamma voltage generator 1400-1, and thus the establishment and stabilization times of voltages in the two source driver circuits can be approximated, and thus display color differences can be reduced, thereby improving the display effect.

For another example, in a scheme based on a resistor unit having a variable resistance value, at least one of the gamma voltage generator 1500-1 (first gamma voltage generator) included in the first source driver circuit (IC 1) and the second gamma voltage generator 1500-2 included in the second source driver circuit (IC 2) may employ the structure of the gamma voltage generator 201 described with reference to fig. 12A-12B, and accordingly, the mode switching timing and switching manner described with reference to fig. 5-11, and the like may be utilized. The source driver circuit that supplies the buffer voltage to the other source driver circuits via the wiring between the power transmission terminals of the source driver circuits may be regarded as a master circuit, and the other source driver circuits may be regarded as slave circuits.

A case where the first gamma voltage generator 1500-1 adopts the structure of the gamma voltage generator 1200 described with reference to fig. 12A-12B is exemplarily shown in fig. 15, while the second gamma voltage generator 1500-2 may adopt the structure of the gamma voltage generator 1200 described with reference to fig. 12A-12B, or adopt other structures. It should be appreciated that in other embodiments, the second gamma voltage generator 1500-2 may employ the structure of the gamma voltage generator 1200 described with reference to fig. 12A-12B, while the first gamma voltage generator 1500-1 employs the structure of the gamma voltage generator 1200 described with reference to fig. 12A-12B or other structures (e.g., a resistor string structure as employed in the related art). The two gamma voltage generators may be different in structure, but the number and voltage values of gamma voltages they output should be the same. Alternatively, the source driver circuit as a slave circuit may not even include a buffer (or include only two buffers that provide the maximum and minimum gamma reference voltages to the gamma voltage generating circuit that it includes) since the buffer voltage may be received from the source driver circuit as a master circuit.

Similarly, as described above, the first and second gamma voltage generators 1500-1 and 1500-2 may employ the same structure of gamma voltage generators for display effect as well as production cost and design complexity.

Thus, as an example, when both the first and second gamma voltage generators 1500-1 and 1500-2 employ the structure of the gamma voltage generator described with reference to fig. 12A-12B, the plurality of buffers included in the first gamma voltage generator 1500-1 may output the first set of buffer voltages to the corresponding plurality of voltage input terminals, and then the second gamma voltage generator 1500-2 may be configured to receive the first set of buffer voltages from the first gamma voltage generator 1500-1 for outputting the second predetermined number of gamma voltages.

The second gamma voltage generator 1500-2 has the same structure as the first gamma voltage generator 1500-1, and includes: the second gamma voltage generation circuit is provided with a voltage input end point of the second set and a voltage output end point of the second set; the input ends of the buffers of the second set respectively receive corresponding gamma reference voltages, and the output ends of the buffers of the second set are respectively connected to voltage input endpoints of the second set; the second set of voltage input terminals receives the buffer voltage from the first gamma voltage generator 1500-1, and wherein the second gamma voltage generating circuit 1500-2 includes a second set of resistor units connected in series, and the connection nodes of adjacent resistor units are connected to or serve as one voltage output terminal, each resistor unit being configured to switch between the first mode and the second mode in synchronization with the resistor units in the first gamma voltage generator 1500-1.

That is, in the case where the gamma voltage needs to be re-established and stabilized, the resistor unit in the second gamma voltage generator 1500-2 operates in the second mode to generate the gamma voltage based on the buffer voltage from the first gamma voltage generator 1500-1 with a smaller resistance value, so that the second gamma voltage generator 1500-2 can accelerate the establishment and stabilization speed of the gamma voltage to some extent with respect to the case where the resistor unit having a variable resistance value is not provided, and thus the establishment and stabilization time of the gamma voltage in the two source driver circuits can be approximated, and thus the display color difference can be reduced, so that the display is more uniform, thereby improving the display effect.

Further, it should be noted that while it is described in fig. 14-15 by way of example that where a source driver may include two source driver circuits, at least one of the source driver circuits employs a dynamic buffer-based scheme or a variable resistor unit-based scheme, it should be understood that a source driver may include more source driver circuits, and at least one of the source driver circuits employs a dynamic buffer-based scheme or a variable resistor unit-based scheme. Further, the at least one source driver circuit may employ both a dynamic buffer-based scheme and a variable resistor unit-based scheme, for example, the at least one source driver circuit may include a gamma voltage generator as shown in fig. 13.

In addition, if the speed of the gamma voltage generator inside each source driver circuit to establish and stabilize the gamma voltage is sufficiently fast, the difference in time between the gamma voltage generators of the source driver circuits to establish and stabilize the gamma voltage is also small, which can be regarded as uniform. Thus, when the source driver may include at least two source driver circuits, each source driver circuit may be randomly set to any one of a dynamic buffer-based scheme (e.g., fig. 4), a variable resistor cell-based scheme (e.g., fig. 12), and a dynamic buffer and variable resistor cell-based scheme (e.g., fig. 13).

It should be appreciated that the source driver may further include other circuits configured to cooperate with the gamma voltage generator of each of the source driver circuits to generate gamma voltages and to drive the display panel. Those skilled in the art will understand the structure and operation of other circuits as shown in fig. 2 to 15, and thus detailed descriptions about the other circuits are omitted herein.

Accordingly, another aspect of the present application also provides a display device, which may be the display device shown in fig. 1, and which includes a display panel and a source driver, wherein the source driver may include one gamma voltage generator as described with reference to fig. 4 to 13, or at least two gamma voltage generators, wherein at least one gamma voltage generator of the at least two gamma voltage generators is the gamma voltage generator as described with reference to fig. 4 to 13, or both of the at least two gamma voltage generators are the gamma voltage generators as described with reference to fig. 4 to 13.

Those skilled in the art will appreciate that various modifications and changes may be made to the structures of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A gamma voltage generator, comprising:

a gamma voltage generating circuit having a plurality of voltage input terminals and a plurality of voltage output terminals, the plurality of voltage output terminals outputting a predetermined number of gamma voltages based on input voltages from the plurality of voltage input terminals; and

a plurality of buffers, each buffer having an input for receiving a corresponding gamma reference voltage and an output connected to a corresponding voltage input terminal,

wherein the gamma voltage generating circuit includes a plurality of resistor units connected in series, and a connection node of adjacent resistor units is used as or connected to one voltage output terminal, each resistor unit being configured such that a second resistance value when operating in the second mode is smaller than a first resistance value when operating in the first mode.

2. The gamma voltage generator of claim 1, wherein the first mode is a standby mode and the second mode is a trigger mode,

Wherein the trigger mode is applied to a period before the generated predetermined number of gamma voltages stabilize, and the standby mode is applied to a period after the generated predetermined number of gamma voltages stabilize.

3. The gamma voltage generator of claim 1, wherein each resistor unit comprises a bypass switch and a plurality of resistors connected in series, the bypass switch being connected in parallel with at least one of the plurality of resistors,

wherein the bypass switch is configured to be on in the second mode and off in the first mode.

4. The gamma voltage generator of claim 1, wherein,

the gamma voltage generating circuit is connected with a plurality of channel circuits, each channel circuit is used for selecting at least one of the predetermined number of gamma voltages according to the input display data to generate a corresponding data voltage.

5. The gamma voltage generator of claim 4 wherein,

the plurality of resistor units are switched to operate in the second mode when display data input to the plurality of channel circuits is updated, and are switched to operate in the first mode after lasting for a predetermined period of time.

6. The gamma voltage generator of claim 4, wherein the display data inputted to the plurality of channel circuits is periodically updated,

the plurality of resistor units are switched to operate in the second mode at a point of time a predetermined length of time before a start point of each update period, and are switched to operate in the first mode after lasting for a predetermined period of time.

7. The gamma voltage generator of claim 4 wherein,

the plurality of resistor units are switched to operate in the second mode when display data input to the plurality of channel circuits is changed, and are switched to operate in the first mode after lasting for a predetermined period of time.

8. The gamma voltage generator of claim 1, wherein the plurality of resistor units included in the gamma voltage generation circuit are synchronously switched between the first and second modes.

9. The gamma voltage generator of claim 1 wherein the gamma voltage generation circuit further has a plurality of second voltage input terminals;

the gamma voltage generator further includes:

and a plurality of dynamic buffers, each of which has an input terminal receiving a corresponding gamma reference voltage and an output terminal connected to a corresponding second voltage input terminal, and wherein each of the dynamic buffers does not output a buffer voltage when the plurality of resistor units are operated in the first mode and outputs the buffer voltage to the connected second voltage input terminal when the plurality of resistor units are operated in the second mode.

10. The gamma voltage generator of claim 9, wherein each dynamic buffer comprises a buffer and a switching module,

the switching module of each dynamic buffer is configured to: the plurality of resistor units are disabled when operating in the first mode and the plurality of resistor units are enabled when operating in the second mode, the dynamic buffer comprising a buffer that outputs a buffered voltage to a second voltage input terminal to which the dynamic buffer is connected.

11. The gamma voltage generator of claim 9, wherein each dynamic buffer comprises a buffer, a switching module, and a voltage difference detection module,

the first detection end of the voltage difference detection module of each dynamic buffer is connected with the first input end of the buffer included in the dynamic buffer, the second detection end is connected with the second voltage input end point connected with the dynamic buffer, and the output end outputs a switching control signal; and

the switching module of each dynamic buffer is configured to enable or disable the buffer comprised by the dynamic buffer from outputting a buffer voltage to a second voltage input terminal to which the dynamic buffer is connected when the plurality of resistor units are operated in the second mode or when the plurality of resistor units are operated in the first mode based on a switching control signal of the voltage difference detection module or other voltage difference detection module comprised by the dynamic buffer,

Wherein the plurality of resistor units switch between the second mode and the first mode in response to a switching control signal of the voltage difference detection module of each dynamic buffer.

12. The gamma voltage generator of claim 9, each dynamic buffer comprising a buffer, wherein the buffer switches between enabled and disabled states according to an enable signal to output or not output a buffer voltage to a second voltage input terminal to which the dynamic buffer is connected.

13. A source driver, comprising:

the gamma voltage generator of claim 1; and

and a plurality of channel circuits connected to the gamma voltage generator for generating respective data voltages corresponding to the inputted display data using the gamma voltages outputted from the gamma voltage generator.

14. A display device, comprising:

a display panel;

the source driver of claim 13, for driving the display panel.