CN116888708A - Semiconductor element, power conversion device, and method for manufacturing semiconductor element - Google Patents
Semiconductor element, power conversion device, and method for manufacturing semiconductor element Download PDFInfo
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- CN116888708A CN116888708A CN202280016917.3A CN202280016917A CN116888708A CN 116888708 A CN116888708 A CN 116888708A CN 202280016917 A CN202280016917 A CN 202280016917A CN 116888708 A CN116888708 A CN 116888708A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 238000000034 method Methods 0.000 title claims description 58
- 238000006243 chemical reaction Methods 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 210
- 238000007747 plating Methods 0.000 claims description 149
- 229910052759 nickel Inorganic materials 0.000 claims description 105
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 60
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 59
- 229910052737 gold Inorganic materials 0.000 claims description 59
- 239000010931 gold Substances 0.000 claims description 59
- 229910052763 palladium Inorganic materials 0.000 claims description 30
- 229910000838 Al alloy Inorganic materials 0.000 claims description 28
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 239000011574 phosphorus Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 4
- 229910001096 P alloy Inorganic materials 0.000 claims description 3
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 claims description 3
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 150
- 238000007772 electroless plating Methods 0.000 description 25
- 230000008569 process Effects 0.000 description 18
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 12
- 229910052725 zinc Inorganic materials 0.000 description 12
- 239000011701 zinc Substances 0.000 description 12
- 238000005260 corrosion Methods 0.000 description 11
- 230000007797 corrosion Effects 0.000 description 11
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 230000007774 longterm Effects 0.000 description 10
- 239000003638 chemical reducing agent Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 239000000243 solution Substances 0.000 description 9
- 230000000873 masking effect Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 238000001556 precipitation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000006467 substitution reaction Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000005238 degreasing Methods 0.000 description 3
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- 230000001678 irradiating effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- ACVYVLVWPXVTIT-UHFFFAOYSA-N phosphinic acid Chemical compound O[PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-N 0.000 description 3
- 230000009257 reactivity Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
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- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
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- 239000011800 void material Substances 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- PTFCDOFLOPIGGS-UHFFFAOYSA-N Zinc dication Chemical compound [Zn+2] PTFCDOFLOPIGGS-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 239000004411 aluminium Substances 0.000 description 1
- -1 and therefore Chemical compound 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
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- 230000006698 induction Effects 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- 239000003381 stabilizer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The semiconductor element is provided with: a semiconductor chip (1); an electrode (4) provided on at least one main surface of the semiconductor chip (1); a 1 st bonding electrode (6) provided on the electrode (4); and a 2 nd bonding electrode (7) provided on the 1 st bonding electrode (6), wherein the electrode (4) has a convex portion on a surface of the 1 st bonding electrode (6) side, the surface of the 2 nd bonding electrode (7) side is smooth in the 1 st bonding electrode (6), and the surface of the 2 nd bonding electrode (7) opposite to the 1 st bonding electrode (6) is smooth.
Description
Technical Field
The present disclosure relates to a semiconductor element, a power conversion device, and a method of manufacturing the semiconductor element.
Background
When a semiconductor element (particularly, a power element for power conversion such as an IGBT or a diode) having a front surface and a back surface on the other hand is mounted on a semiconductor substrate, the back surface side of the semiconductor element is bonded to the semiconductor substrate by soldering, and an electrode (front electrode) made of an aluminum alloy or the like is bonded to a wiring circuit or the like by wire bonding of aluminum or the like on the front surface side of the semiconductor element.
However, conventionally, in order to shorten the manufacturing time and reduce the material cost, a mounting method in which an electrode made of an aluminum alloy, copper, or the like is directly soldered to the front surface side of a semiconductor element or a wire bonding method of copper is employed. In order to alleviate stress at the time of solder bonding and to prevent electrode consumption, it is desirable to form a bonding electrode layer of nickel, gold, copper, or the like thicker than 1 μm on an electrode (front electrode) of an aluminum alloy or the like on the front surface of the semiconductor element.
However, in the case of forming the bonding electrode layer on the front surface side of the semiconductor element by a vacuum film forming method such as vapor deposition or sputtering, it is difficult to pattern and form a film only on the electrode of aluminum alloy or the like. Further, the thickness of the film formed by the vacuum film forming method is usually 1.0 μm or less, and if the thickness of the electrode layer for bonding is to be increased, the film forming takes a longer time than the plating method, and therefore the manufacturing cost increases. Therefore, attention has been paid to an electroless plating method which enables to selectively form an electrode layer for bonding on an electrode made of an aluminum alloy or the like and to form an electrode layer for bonding thicker than 1.0 μm at a low cost and at a high speed.
In patent document 1 (japanese patent application laid-open No. 2005-19829), a contact hole formed through an interlayer insulating film is intentionally provided between a semiconductor substrate and an electrode, and by using this shape, a recess having the same shape as the contact hole is formed on the surface of the electrode.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open publication No. 2005-19829
Disclosure of Invention
Problems to be solved by the invention
In the method described in patent document 1, when the uneven portion is formed on the surface of the electrode, the uneven portion is formed on the surfaces of the nickel plating layer and the gold plating layer, and as a result, a void is formed when the nickel plating layer and the gold plating layer are bonded, and the adhesion of the bonding portion is lowered, so that it is considered that it is difficult to improve the long-term reliability of the semiconductor element.
The present disclosure has been made to solve the above-described problems, and an object thereof is to improve the long-term reliability of a semiconductor element.
Means for solving the problems
The semiconductor element is provided with:
a semiconductor chip;
an electrode provided on at least one main surface of the semiconductor chip;
a 1 st bonding electrode provided on the electrode; and
a 2 nd bonding electrode provided on the 1 st bonding electrode,
the electrode has a convex portion on the surface of the 1 st electrode for bonding,
in the 1 st bonding electrode, the surface of the 2 nd bonding electrode side is smooth,
in the 2 nd bonding electrode, a surface of a side opposite to the 1 st bonding electrode is smooth.
Effects of the invention
According to the present disclosure, the long-term reliability of the semiconductor element can be improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor element according to embodiment 1 and embodiment 2.
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to embodiment 1 and embodiment 2.
Fig. 3 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to embodiment 1 and embodiment 2.
Fig. 4 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to embodiment 1 and embodiment 2.
Fig. 5 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to embodiment 1 and embodiment 2.
Fig. 6 is a flowchart of electroless plating according to embodiment 1 and embodiment 3.
Fig. 7 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to embodiment 1.
Fig. 8 is a schematic cross-sectional view of a conventional semiconductor element according to embodiment 1 and embodiment 2.
Fig. 9 is a flowchart of electroless plating according to embodiment 2 and embodiment 4.
Fig. 10 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to embodiment 2.
Fig. 11 is a schematic cross-sectional view of the semiconductor element of embodiment 3 and embodiment 4.
Fig. 12 is a flowchart of a method for manufacturing a semiconductor device according to embodiment 3 and embodiment 4.
Fig. 13 is a schematic cross-sectional view of a conventional semiconductor element according to embodiment 3 and embodiment 4.
Fig. 14 is a schematic cross-sectional view of the semiconductor element of embodiment 5.
Fig. 15 is a flowchart of electroless plating according to embodiment 5.
Fig. 16 is a schematic cross-sectional view of a conventional semiconductor element according to embodiment 5.
Fig. 17 is a block diagram showing the structure of the power conversion system according to embodiment 6.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described. In the drawings, dimensional relationships such as length, width, thickness, and depth are appropriately changed for the sake of illustration and simplification, and do not represent actual dimensional relationships.
Embodiment 1.
Semiconductor device
Referring to fig. 1, the semiconductor element of the present embodiment includes:
a semiconductor chip 1;
an electrode 4 (electrode layer) provided on the front side (one main surface) of the semiconductor chip 1 as a wiring layer;
a 1 st bonding electrode 6 provided on the electrode 4 (surface on the opposite side of the semiconductor chip 1); and
and a 2 nd bonding electrode 7 provided on the 1 st bonding electrode 6 (the surface on the opposite side of the semiconductor chip 1).
The electrode 4 has a convex portion on the surface of the 1 st bonding electrode 6 side,
in the 1 st bonding electrode 6, the surface on the 2 nd bonding electrode 7 side is smooth,
in the 2 nd bonding electrode 7, the surface on the opposite side to the 1 st bonding electrode 6 is smooth.
In fig. 1, a back electrode 5 (back electrode layer) is provided on the back surface (surface opposite to the electrode 4) of the semiconductor chip 1.
The height of the protruding portion of the electrode 4 is preferably 1.0 μm or more. The height of the convex portion of the electrode 4 can be calculated by the following method. That is, an arbitrary cross section obtained by irradiating a gallium ion beam with a focused ion beam device (FIB device) was observed at 5000 times by a Scanning Electron Microscope (SEM). The height of any 10 points in the observed convex portion can be measured, and the average value thereof can be regarded as the height of the convex portion of the electrode 4.
The surface of the 1 st bonding electrode 6 on the 2 nd bonding electrode 7 side and the surface of the 2 nd bonding electrode 7 on the opposite side to the 1 st bonding electrode 6 are substantially smooth, and may be not completely smooth, or may have some level difference. In this case, the height difference is preferably 0.5 μm or less.
The above-described level difference can be calculated by the following method. That is, an arbitrary cross section obtained by irradiating a gallium ion beam with a focused ion beam device (FIB device) was observed at 5000 times by a Scanning Electron Microscope (SEM). The difference between the highest point and the lowest point can be measured with an arbitrarily determined measurement point as a reference point in the range of 20 μm in the horizontal direction of the observed surface, and the average value thereof can be regarded as the difference in height between the surface of the 1 st bonding electrode 6 on the 2 nd bonding electrode 7 side and the surface of the 2 nd bonding electrode 7 on the opposite side of the 1 st bonding electrode 6.
The gate oxide film 2 may be provided between the semiconductor chip 1 and the electrode 4, or the gate electrode 3 may be provided in the gate oxide film 2. In this case, the convex portion of the electrode 4 is located above the gate oxide film 2.
The semiconductor chip 1 is made of silicon carbide, for example. The constituent material of the semiconductor chip 1 is not limited to silicon carbide, and may be silicon, gallium arsenide, gallium nitride, or the like, or may be a semiconductor element having a front-surface and rear-surface conductive type such as an IGBT or a diode. In such a case, the same effect can be expected. The size of the semiconductor chip 1 is, for example, about 7mm×14 mm.
The electrode 4 preferably comprises aluminum or an aluminum alloy. Examples of the aluminum alloy include aluminum alloys containing aluminum, si, silicon, copper, and the like.
The 1 st bonding electrode 6 preferably contains nickel, nickel phosphorus, or nickel boron. The 1 st bonding electrode 6 is, for example, an electroless nickel plating layer.
The 2 nd bonding electrode 7 preferably contains gold or palladium. Examples of the 2 nd bonding electrode 7 include an electroless gold plating layer and an electroless palladium plating layer.
The 1 st bonding electrode 6 and the 2 nd bonding electrode 7 are not limited to a nickel plating layer, a gold plating layer, and a palladium plating layer, and may be any plating layer that enables bonding of the electrode 4, the 1 st bonding electrode 6, and the 2 nd bonding electrode 7. For example, even if an electrolytic copper plating layer or the like is used as such a plating layer, the same effect can be expected.
The 1 st bonding electrode 6 and the 2 nd bonding electrode 7 are preferably formed by electroless plating.
The gate oxide film 2 is made of an insulating material such as silicon oxide.
The gate electrode 3 is made of a conductive material such as polysilicon.
The back electrode 5 is composed of a plurality of metal layers. Since the back electrode 5 may serve the purpose of bonding, it is preferable to use an electrode formed by plating nickel or gold with excellent bondability on an electrode formed of nickel or a nickel alloy including silicon, copper, or the like as the back electrode 5.
The semiconductor element shown in fig. 1 is a front-side and back-side conductive semiconductor element including a front electrode (electrode 4) and a back electrode 5. That is, the electrode 4 is a front electrode of the front-back conductive semiconductor element.
In the present embodiment, the electrode 4 has a convex portion on the 1 st bonding electrode 6 side, the 2 nd bonding electrode 7 side surface is smooth in the 1 st bonding electrode 6, and the 2 nd bonding electrode 7 side surface opposite to the 1 st bonding electrode 6 is smooth. This suppresses occurrence of voids when the 1 st bonding electrode 6 and the 2 nd bonding electrode 7 are bonded, and improves the close-fitting property of the bonded portion. Therefore, the long-term reliability of the semiconductor element can be improved.
Method for manufacturing semiconductor device
The method for manufacturing a semiconductor element according to the present embodiment includes:
step 1 (electrode forming step) of forming an electrode on at least one main surface of a semiconductor chip;
a step 2 (step 1 of forming a bonding electrode) of forming a bonding electrode 1 on the electrode; and
and a step 3 (step 2 of forming a bonding electrode) of forming a bonding electrode 2 on the bonding electrode 1.
In step 1, a convex portion is formed on the surface of the electrode on the 1 st bonding electrode side.
In step 2, the surface of the 1 st bonding electrode on the 2 nd bonding electrode side is formed to be smooth.
In step 3, the surface of the electrode for bonding 2 on the opposite side to the electrode for bonding 1 is formed to be smooth.
An example of a method for manufacturing a semiconductor device according to the present embodiment will be described below with reference to fig. 2.
In the method for manufacturing a semiconductor element according to the present embodiment, the formation of the electrode 4 on the semiconductor chip 1 (step 1), the formation of the back electrode 5, the masking of the back electrode 5, the electroless plating treatment (step 2 and step 3), and the masking and peeling are mainly performed in this order.
Fig. 3 to 5 are schematic cross-sectional views showing a flow of a process for manufacturing the semiconductor element shown in fig. 1. Fig. 3 shows a cross-sectional structure of the semiconductor element before the electrode 4, the back electrode 5, the 1 st bonding electrode 6, and the 2 nd bonding electrode 7 are formed in embodiment 1.
A specific method for manufacturing the semiconductor element shown in fig. 1 will be described below with reference to fig. 2 to 5. In addition, from the viewpoint of manufacturing efficiency, it is preferable that all the steps of embodiment 1 be performed in a wafer state.
(formation of gate oxide film and gate electrode)
Referring to fig. 3, in the case where the semiconductor element of the present embodiment includes the gate oxide film 2 and the gate electrode 3, the gate oxide film 2 including the gate electrode 3 is formed by first forming silicon oxide as an insulating material into the gate oxide film 2 by a deposition method such as a thermal oxidation method or chemical vapor deposition method, and then patterning the silicon oxide film by, for example, photolithography or etching, to form a lower portion of the gate oxide film 2 (a portion closer to the semiconductor chip 1 than the gate electrode 3 in fig. 3). Next, polysilicon as a conductive material is formed into the gate electrode 3 by the above-described method, and then patterned by the above-described method, forming the gate electrode 3. Then, silicon oxide is formed by the above method in such a manner as to cover the gate electrode 3, and then patterning is performed by the above method, forming the gate oxide film 2.
The thickness of the gate oxide film 2 including the gate electrode 3 is preferably, for example, 1.0 μm or more and 3.0 μm or less.
(step 1: electrode Forming step)
Referring to fig. 4, in the electrode forming step (step 1), in order to form an electrode having high adhesion on the semiconductor chip 1, an aluminum alloy having low resistance is patterned by sputtering, for example, which is easy to control the process. In the case where the semiconductor element of the present embodiment includes the gate oxide film 2 and the gate electrode 3, the electrode 4 is formed while maintaining the irregularities generated by the gate oxide film 2 and the gate electrode 3, and therefore, the convex portion is formed on the upper surface of the electrode 4. In addition, a titanium compound such as titanium or titanium nitride may be formed as a barrier metal between the semiconductor chip 1 and the aluminum alloy, and between the gate oxide film 2 and the aluminum alloy, depending on the application.
The thickness of the electrode 4 is, for example, preferably 0.5 μm or more and 5.0 μm or less, and the height of the protruding portion of the electrode 4 is preferably 1.0 μm or more. In the case where the semiconductor chip 1 is made of silicon carbide, in order to further improve the adhesion to the semiconductor chip 1, for example, si of about 1 mass%, copper of about 0.5 mass%, or the like may be added to the electrode 4 in addition to aluminum, and the concentration thereof is preferably constant in the electrode.
(Back electrode formation)
Referring to fig. 5, in the back electrode forming step, in order to form the back electrode 5 composed of a plurality of metal layers on the semiconductor chip 1 opposite to the surface on which the electrode 4 is formed, for example, nickel is patterned by sputtering which facilitates control of the process, and then gold is patterned by sputtering which facilitates control of the process. In addition, depending on the application, a barrier metal such as a titanium alloy or a nickel alloy may be formed between the semiconductor chip 1 and nickel.
The thickness of the back electrode 5 is, for example, preferably 0.3 μm or more and 5.0 μm or less, and the thickness of the gold layer is preferably 0.01 μm or more and 0.2 μm or less.
(Back electrode masking)
Next, back electrode masking is performed so that the back electrode 5 is not damaged in the subsequent film formation process of the 1 st bonding electrode 6 and the 2 nd bonding electrode 7. The peeling is performed by adhering a film coated with an adhesive that can be peeled off by irradiation of ultraviolet light.
(electroless plating)
Next, an electroless plating process is performed. The process is described later with additional reference to fig. 6.
(masking and stripping)
Finally, the masking tape adhered to the back electrode surface of the wafer is peeled off. Specifically, for example, the masking tape is peeled off by irradiating the back surface of the wafer, which has been subjected to the electroless plating treatment, with ultraviolet rays, and then peeling off the masking tape.
(electroless plating Process)
Details of the electroless plating process will be described below.
Referring to fig. 6, degreasing, pickling, 1 st zincate, zincate stripping, 2 nd zincate, electroless nickel plating, and electroless gold plating are sequentially performed in a process of forming 1 st bonding electrode 6 and 2 nd bonding electrode 7 on electrode 4 on a wafer by an electroless plating method. In this case, care should be taken to ensure a sufficient washing time between the steps, and the treatment liquid or residue from the preceding step should not be carried to the next step.
Next, an outline of each step will be described.
First, degreasing is performed. Degreasing is performed to remove light organic contamination, oil and fat components, oxide films, and the like remaining on the surface of the electrode 4, and to impart wettability to the surface of the electrode 4. The residue is preferably saponified with an alkaline chemical solution having a strong etching power for aluminum alloy or the like.
Next, acid washing was performed. The purpose of the acid washing is to neutralize the surface of the electrode 4, and to etch the surface of the electrode 4, thereby improving the reactivity with a zincate solution described later, and improving the adhesion of plating.
Next, zincate treatment was performed. Zincate treatment refers to the following treatment: an oxide film (e.g., aluminum oxide film) is removed while etching the surface of an electrode (e.g., aluminum alloy electrode), and a zinc or other coating film is formed on the electrode surface. In general, when an aluminum alloy is immersed in an aqueous solution in which zinc is dissolved as an ion, the standard redox potential of zinc is higher than that of aluminum, and therefore, aluminum is dissolved as an ion, and zinc ions receive electrons at the surface of the aluminum alloy by electrons generated at this time, and a zinc coating film is formed on the surface of aluminum.
Then, the zinc-coated aluminum alloy was immersed in nitric acid to temporarily dissolve zinc. Then, the aluminum alloy is immersed in the zincate solution again, thereby removing the oxide film of aluminum and uniformly covering zinc. By this operation, the surface of aluminum becomes smooth. The more the number of times the more uniform the surface of the aluminium is, the better the coating is completed, and therefore at least 2 times, preferably 3 times zincate treatment is performed. When a uniform zinc coating is formed on the surface of the electrode 4 by this zincate treatment, a solid plating layer can be attached in the subsequent electroless plating treatment.
Next, electroless nickel plating will be described as an example of the 2 nd step (1 st bonding electrode forming step).
When the aluminum alloy covered with zinc is immersed in the electroless nickel plating solution, zinc and nickel are replaced by a difference in standard oxidation-reduction potential, and nickel is deposited on the aluminum alloy. Then, nickel is autocatalytically precipitated on the nickel by the action of the reducing agent contained in the plating solution.
In this autocatalytic precipitation, the electroless nickel plating layer becomes an alloy because the components of the reducing agent are taken into the plating layer. In general, hypophosphorous acid is used as a reducing agent, and this phosphorus is taken into the plating layer, so that phosphorus is contained in the electroless nickel plating layer.
In this case, in order to increase the degree of formation of irregularities (filling property) of the aluminum alloy, the initial nickel deposition rate is intentionally reduced. As shown in fig. 7, when the precipitation rate of nickel is reduced, the reactivity is reduced at the convex portions of the electrode 4 due to the action of the stabilizer and the complexing agent contained in the plating solution, but the accelerator is concentrated at the concave portions of the electrode 4, and the reactivity is higher than that of the convex portions, so that the electroless nickel plating layer is smoothly formed. In order to reduce the precipitation rate of nickel, it is effective to lower the temperature of the nickel plating bath or to suppress the supply of the nickel source and the reducing agent to the reaction surface. In this case, the deposition rate of nickel is preferably 4.0 μm/hr or more and 10 μm/hr or less, more preferably 6.0 μm/hr or more and 8.0 μm/hr or less. As described later, the electroless nickel plating is performed at this speed until the electroless nickel plating becomes smooth.
On the other hand, when the deposition rate of nickel is reduced by the above method, not only is productivity reduced, but also variation in the supply of nickel to the reaction surface occurs, and uneven film thickness in the wafer surface occurs. Therefore, after the irregularities of the electroless nickel plating layer are removed by the initial precipitation of nickel, the nickel precipitation rate is increased by raising the temperature of the nickel plating bath or promoting diffusion of the nickel source and the reducing agent to the reaction surface, so that a smooth electroless nickel plating layer is precipitated with respect to the aluminum alloy having the irregularities. In this case, the deposition rate of nickel is preferably 10 μm/hr or more and 15 μm/hr or less, more preferably 11 μm/hr or more and 13 μm/hr or less.
The electroless nickel plating layer preferably has a thickness of, for example, 1.0 μm or more and 7.0 μm or less. In the case where there is a level difference on the surface of the electroless nickel plating layer, it is preferably 0.5 μm or less.
Then, the 3 rd step (the 2 nd bonding electrode forming step) is finally performed. As an example of the 3 rd step, electroless gold plating will be described.
The electroless gold plating used herein is usually a displacement type, and gold plating is deposited by displacement of nickel and gold. The substitution electroless gold plating is performed on the electroless nickel plating layer, and the action of the complexing agent contained in the plating solution is used to replace nickel and gold. Since the substitution type is used, when the surface of nickel is covered with gold, the reaction is stopped, and thus the plating layer is not easily thickened, and is usually about 0.05 μm.
In addition, when the surface of the electroless nickel plating layer has irregularities, the electroless gold plating is performed, and nickel is locally corroded at the concave portion to become rich in phosphorus, so that the bonding strength is lowered and the bonding reliability is lowered. Therefore, the electroless nickel plating of the substrate is preferably smooth.
In the process flow described above, a semiconductor element in which the 1 st bonding electrode 6 (nickel plating layer) and the 2 nd bonding electrode 7 (gold plating layer) are deposited on the surface of the electrode 4 having the convex portion smoothly can be obtained by the electroless plating method.
The obtained semiconductor element can suppress localized corrosion as compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 8. Further, compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 8, the resulting semiconductor element can suppress the occurrence of voids in the concave portions at the time of solder bonding. Therefore, the semiconductor element of the present embodiment can be expected to have an effect of a longer operation life even in a power cycle test when assembled in a power module.
As described above, in the present embodiment, even when the electrode 4 has irregularities, the surfaces of the 1 st bonding electrode 6 and the 2 nd bonding electrode 7 are smoothly formed, so that the occurrence of localized nickel corrosion and voids can be suppressed, and therefore the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
Embodiment 2.
In embodiment 2, CMP (Chemical Mechanical Polishing: chemical mechanical polishing) is additionally performed in the electroless plating step of the manufacturing method shown in embodiment 1. The constituent elements of the semiconductor element of the present embodiment have already been described in embodiment 1, and thus, duplicate description thereof is omitted.
Hereinafter, electroless nickel plating and CMP will be described, and since other steps are the same as in embodiment 1, redundant description will be omitted.
Fig. 9 is a flowchart of the 1 st bonding electrode forming step (2 nd step) of embodiment 2. In embodiment 2, the steps up to the 2 nd zincate treatment are the same as those in embodiment 1, but electroless nickel plating and CMP are sequentially performed after the 2 nd zincate treatment. First, electroless nickel plating will be described.
When the aluminum alloy covered with zinc is immersed in the electroless nickel plating solution, zinc and nickel are replaced by a difference in standard oxidation-reduction potential, and nickel is deposited on the aluminum alloy. Then, nickel is autocatalytically precipitated on the nickel by the action of the reducing agent contained in the plating solution.
In this autocatalytic precipitation, the electroless nickel plating layer becomes an alloy because the components of the reducing agent are taken into the plating layer. In general, hypophosphorous acid is used as a reducing agent, and this phosphorus is taken into the plating layer, so that phosphorus is contained in the electroless nickel plating layer.
At this time, as shown in fig. 10, the nickel plating layer is affected by the uneven surface of the aluminum alloy, so the upper surface of the electroless nickel plating layer has an uneven shape. In addition, it is preferable that the electroless nickel plating layer is formed in advance to be thicker than the final desired electroless nickel plating layer, in view of the reduction of 1.0 μm in CMP in the subsequent steps.
Next, CMP is performed. CMP is a process of planarizing irregularities by improving mechanical polishing performance by surface chemical action of a polishing liquid. When the electroless nickel plating layer is subjected to CMP, the polishing liquid collides with the step of the uneven surface to generate heat energy, and thus the chemical reaction is promoted by the step. Thus, the convex portion is selectively etched to eliminate the step, thereby planarizing the electroless nickel plating. In this embodiment, the electroless nickel plating layer of the convex portion is polished by CMP to 1.0 μm, whereby a smooth surface shape can be obtained. Then, as in embodiment 1, a smooth electroless gold plating layer is formed by electroless gold plating. In addition, as in embodiment 1, the case where the 2 nd bonding electrode is an electroless gold plating layer is merely an example, and the 2 nd bonding electrode may be an electroless palladium plating layer, for example.
In the process flow described above, a semiconductor element in which the 1 st bonding electrode (nickel plating layer) and the 2 nd bonding electrode (gold plating layer) are deposited smoothly can be obtained by the electroless plating method.
The obtained semiconductor element can suppress localized corrosion as compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 8. Further, compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 8, the resulting semiconductor element can suppress the occurrence of voids in the concave portions at the time of solder bonding. Therefore, the semiconductor element of the present embodiment can be expected to have an effect of a longer operation life even in a power cycle test when assembled in a power module.
As described above, in the present embodiment, even when the electrode has irregularities, the surfaces of the 1 st bonding electrode 6 and the 2 nd bonding electrode 7 are smoothly formed, so that the occurrence of localized nickel corrosion and voids can be suppressed, and therefore the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
Embodiment 3.
Referring to fig. 11, in the semiconductor element of the present embodiment, the 1 st bonding electrode 61 and the 2 nd bonding electrode 71 are also formed on the back electrode 5 (on the opposite side of the semiconductor chip 1) as in the electrode 4 (front electrode) of embodiment 1. Since the other components have already been described in embodiment 1, a repetitive description thereof is omitted.
In the present embodiment, in order to enable the back electrode 5 to be plated by electroless plating, for example, aluminum (the same material as the electrode 4) or an aluminum alloy containing Si, silicon, copper, or the like is used.
Referring to fig. 12, in the method for manufacturing a semiconductor element according to the present embodiment, the formation of the electrode 4 on the semiconductor chip 1, the formation of the back electrode 5, and the electroless plating process are mainly performed in this order.
In this embodiment, by performing electroless nickel plating as described in embodiment 1, a smooth electroless nickel plating layer is deposited simultaneously with respect to the electrode 4 having the uneven portion and the smooth back electrode 5. Then, by performing electroless gold plating, a smooth electroless gold plating layer is deposited simultaneously with respect to the electroless nickel plating layer on the electrode 4 and the electroless nickel plating layer on the back electrode 5. In addition, as in embodiment 1, the case where the 2 nd bonding electrode is an electroless gold plating layer is merely an example, and the 2 nd bonding electrode may be an electroless palladium plating layer, for example.
In the process flow described above, the semiconductor element in which the 1 st bonding electrodes 6 and 61 and the 2 nd bonding electrodes 7 and 71 are formed on the front and back surfaces of the semiconductor chip 1 can be obtained by the electroless plating method.
The obtained semiconductor element can suppress localized corrosion as compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 13. Further, compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 13, the obtained semiconductor element can suppress the generation of voids in the concave portions at the time of solder bonding. Therefore, the semiconductor element of the present embodiment can be expected to have an effect of a longer operation life even in a power cycle test when assembled in a power module.
As described above, in the present embodiment, even when the electrode has irregularities, the surfaces of the 1 st bonding electrode and the 2 nd bonding electrode are smoothly formed, so that the occurrence of localized nickel corrosion and voids can be suppressed, and therefore the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
Embodiment 4.
In embodiment 4, the semiconductor element having the structure shown in embodiment 3 is formed, but the 1 st bonding electrode 6 is formed on the electrode 4 by the manufacturing method shown in embodiment 2, and the 1 st bonding electrode 61 is formed on the back electrode 5 by the manufacturing method shown in embodiment 2 except that CMP is not performed. Since the other components have already been described in embodiment 1 and embodiment 3, the duplicate description is omitted.
In the present embodiment, in order to enable the back electrode 5 to be plated by electroless plating, for example, aluminum (the same material as the electrode 4) or an aluminum alloy containing Si, silicon, copper, or the like is used.
Referring to fig. 12, in the method for manufacturing a semiconductor element according to the present embodiment, the formation of the electrode 4 on the semiconductor chip 1, the formation of the back electrode 5, and the electroless plating process are mainly performed in this order.
In this embodiment, electroless nickel plating and CMP are performed as shown in embodiment 2, whereby a smooth electroless nickel plating layer is deposited on the electrode 4 having the uneven portion, whereas electroless nickel plating is performed without performing CMP as shown in embodiment 2, whereby a smooth electroless nickel plating layer is deposited on the smooth back electrode 5. Then, by performing electroless gold plating, a smooth electroless gold plating layer is deposited simultaneously with respect to the electroless nickel plating layer on the electrode 4 and the electroless nickel plating layer on the back electrode 5. In addition, as in embodiment 1, the case where the 2 nd bonding electrode is an electroless gold plating layer is merely an example, and the 2 nd bonding electrode may be an electroless palladium plating layer, for example.
In the process flow described above, the semiconductor element in which the 1 st bonding electrodes 6 and 61 and the 2 nd bonding electrodes 7 and 71 are formed on the front and back surfaces of the semiconductor chip 1 can be obtained by the electroless plating method.
The obtained semiconductor element can suppress localized corrosion as compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 13. Further, compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer and the electroless gold plating layer as shown in fig. 13, the obtained semiconductor element can suppress the generation of voids in the concave portions at the time of solder bonding. Therefore, the semiconductor element of the present embodiment can be expected to have an effect of a longer operation life even in a power cycle test when assembled in a power module.
As described above, in the present embodiment, even when the electrode has irregularities, the surfaces of the 1 st bonding electrode and the 2 nd bonding electrode are smoothly formed, so that the occurrence of localized nickel corrosion and voids can be suppressed, and therefore the solderability is improved, and the long-term reliability of the semiconductor element can be ensured.
Embodiment 5.
In embodiment 5, in any of the semiconductor elements of embodiments 1 to 4, the 2 nd bonding electrode 7 is formed of a plurality of layers. Since the other components have already been described in embodiments 1 to 4, the overlapping description is omitted.
Referring to fig. 14, in the semiconductor element of the present embodiment, the 2 nd bonding electrode has a two-layer structure composed of the 1 st layer 7a and the 2 nd layer 7 b. Layer 1, layer 7a, preferably comprises palladium, palladium phosphorus or a palladium alloy. The 1 st layer 7a is, for example, an electroless palladium plating layer. Layer 2, layer 7b, preferably comprises gold. The 2 nd layer 7b may be, for example, an electroless gold plating layer.
However, the 1 st layer 7a and the 2 nd layer 7b are not limited to the palladium plating layer and the gold plating layer, and may be any plating layer that can bond the 1 st bonding electrode 6, the 1 st layer 7a, and the 2 nd layer 7 b. For example, even if an electrolytic copper plating layer or the like is used as such a plating layer, the same effect can be expected.
The 1 st layer 7a and the 2 nd layer 7b are preferably formed by an electroless plating method.
Fig. 15 is a flowchart of electroless plating of the present embodiment. In this embodiment, the steps up to electroless nickel plating are the same as those in embodiment 1, but electroless palladium plating and electroless gold plating are sequentially performed after electroless nickel plating. Hereinafter, electroless palladium plating and electroless gold plating will be described, and since other steps have been described in embodiments 1 to 4, a repetitive description thereof will be omitted.
The electroless palladium plating used herein is usually a displacement type, and palladium plating is precipitated by displacement of nickel and palladium. Formic acid and hypophosphorous acid are used as reducing agents. The thickness of the 1 st layer 7a is preferably, for example, 0.1 μm or more and 1.0 μm or less.
By disposing the electroless palladium plating layer between the electroless nickel plating layer and the electroless gold plating layer, diffusion of nickel to the surface of the gold plating layer due to heat can be suppressed.
Next, electroless gold plating is performed. As described above, electroless gold plating is usually a substitution type, but may be a substitution reduction type, or may be a substitution type and a reduction type which are continuously performed.
On the other hand, whichever method is used to carry out electroless gold plating, the electroless gold plating layer will locally corrode the electroless nickel plating layer by the electroless palladium plating layer. In addition, if there is a surface roughness of the electroless nickel plating layer, if there is an electroless palladium plating layer, localized corrosion of the concave portion is promoted by galvanic action. Therefore, in the case where an electroless palladium plating layer is present, it is preferable that the electroless nickel plating layer of the substrate be smooth.
In the process flow described above, a semiconductor element in which the 1 st bonding electrode 6 (nickel plating layer) and the 1 st layer 7a (palladium plating layer) and the 2 nd layer 7b (gold plating layer) which are the 2 nd bonding electrode 7 can be deposited on the surface of the electrode 4 having the convex portion can be obtained by electroless plating.
The structure of the 2 nd bonding electrode 7 is not limited to two layers, and may be 3 layers or more. In this case, among the 2 nd bonding electrodes 7, the layer in contact with the 1 st bonding electrode 6, i.e., the lowermost layer, preferably contains palladium, palladium phosphorus, or palladium alloy, and the layer farthest from the 1 st bonding electrode 6, i.e., the uppermost layer, preferably contains gold. For example, when the 2 nd bonding electrode 7 is constituted of 3 layers, the lowermost layer is an electroless palladium plating layer, the uppermost layer is a reduced electroless gold plating layer, and the layer between the uppermost layer and the lowermost layer, that is, the intermediate layer is a substituted electroless gold plating layer.
The obtained semiconductor element can suppress localized corrosion as compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer, the electroless palladium plating layer, and the electroless gold plating layer as shown in fig. 16. Further, by smoothing the electroless palladium plating layer, nickel can be prevented from diffusing to the surface of the electroless gold plating layer, and the bonding strength with the solder can be improved. Further, compared with the case where uneven portions are present on the surfaces of the electroless nickel plating layer, the electroless palladium plating layer, and the electroless gold plating layer as shown in fig. 16, the resulting semiconductor element can suppress the occurrence of voids in the concave portions at the time of solder bonding. Therefore, the semiconductor element of the present embodiment can be expected to have an effect of a longer operation life even in a power cycle test when assembled in a power module.
As described above, in the present embodiment, even when the electrode has irregularities, the 1 st bonding electrode and the 1 st and 2 nd layer surfaces as the 2 nd bonding electrodes are smoothly formed, so that localized nickel corrosion and void generation can be suppressed, and therefore, the solderability is improved, and long-term reliability of the semiconductor element can be ensured.
Embodiment 6.
The present embodiment applies any of the semiconductor elements of embodiments 1 to 5 described above to a power conversion device. The present disclosure is not limited to a specific power conversion device, and a case where the present disclosure is applied to a three-phase inverter will be described below as embodiment 6.
Fig. 17 is a block diagram showing the configuration of a power conversion system to which the power conversion device of the present embodiment is applied.
The power conversion system shown in fig. 17 is configured by a power source 100, a power conversion device 200, and a load 300. The power supply 100 is a dc power supply, and supplies dc power to the power conversion device 200. The power supply 100 may be configured by various power supplies, for example, a direct current system, a solar cell, or a battery, or may be configured by a rectifier circuit or an AC/DC converter connected to an alternating current system. The power supply 100 may be configured by a DC/DC converter that converts direct-current power output from a direct-current system into predetermined power.
The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, and converts dc power supplied from the power supply 100 into ac power to supply the ac power to the load 300. As shown in fig. 17, the power conversion device 200 includes: a main conversion circuit 201 that converts direct-current power into alternating-current power and outputs the same; and a control circuit 203 that outputs a control signal that controls the main conversion circuit 201 to the main conversion circuit 201.
The load 300 is a three-phase motor driven by ac power supplied from the power conversion device 200. The load 300 is not limited to a specific application, and is used as a motor mounted on various electric devices, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes a switching element (not shown) and a flywheel diode (not shown), and the switching element switches to convert dc power supplied from the power supply 100 into ac power and supplies the ac power to the load 300. The main converter circuit 201 of the present embodiment has various specific circuit configurations, but the main converter circuit 201 of the present embodiment is a two-level three-phase full-bridge circuit, and may be configured of 6 switching elements and 6 flywheel diodes connected in anti-parallel to the respective switching elements. At least one of the switching elements and the flywheel diodes of the main conversion circuit 201 is a switching element or flywheel diode included in the semiconductor device 202 corresponding to any of the semiconductor elements in embodiments 1 to 5. The 6 switching elements are connected in series for every 2 switching elements to constitute upper and lower arms, and each of the upper and lower arms constitutes each phase (U-phase, V-phase, and W-phase) of the full bridge circuit. The load 300 is connected to the output terminals of the upper and lower arms, that is, to 3 output terminals of the main conversion circuit 201.
The main conversion circuit 201 includes a driving circuit (not shown) for driving each switching element, and the driving circuit may be incorporated in the semiconductor device 202 or may be provided separately from the semiconductor device 202. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 201, and supplies the driving signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. The drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element when the switching element is maintained in the on state, and is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element when the switching element is maintained in the off state.
The control circuit 203 controls the switching elements of the main conversion circuit 201 to supply desired power to the load 300. Specifically, the time (on time) for which each switching element of the main conversion circuit 201 should be in the on state is calculated from the electric power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control in which the on time of the switching element is modulated according to the voltage to be output. Then, a control command (control signal) is output to the driving circuit provided in the main conversion circuit 201, so that an on signal is output to the switching element to be turned on at each timing, and an off signal is output to the switching element to be turned off. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element based on the control signal.
In the power conversion device 200 of the present embodiment, any one of the semiconductor elements of embodiments 1 to 5 is applied as the semiconductor device 202 constituting the main conversion circuit 201, and therefore, the power conversion device 200 of the present embodiment can achieve improved long-term reliability.
In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, the power conversion device is provided with two levels, but the power conversion device may be provided with three or more levels, and the present disclosure may be applied to a single-phase inverter when power is supplied to a single-phase load. Further, in the case of supplying electric power to a direct current load or the like, the present disclosure may also be applied to a DC/DC converter or an AC/DC converter.
The power conversion device to which the present disclosure is applied is not limited to the case where the load is an electric motor, and may be used as a power source device of an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system, and may be used as a power conditioner of a solar power generation system, a power storage system, or the like, for example.
The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Description of the reference numerals
1: a semiconductor chip; 2: a gate oxide film; 3: a gate electrode; 4: an electrode; 5: a back electrode; 6. 61: 1 st bonding electrode; 7. 71: a 2 nd bonding electrode; 7a: layer 1; 7b: layer 2; 100: a power supply; 200: a power conversion device; 201: a main conversion circuit; 202: a semiconductor device; 203: a control circuit; 300: and (3) loading.
Claims (20)
1. A semiconductor element, wherein the semiconductor element comprises:
a semiconductor chip;
an electrode provided on at least one main surface of the semiconductor chip;
a 1 st bonding electrode provided on the electrode; and
a 2 nd bonding electrode provided on the 1 st bonding electrode,
the electrode has a convex portion on the surface of the 1 st electrode for bonding,
in the 1 st bonding electrode, the surface of the 2 nd bonding electrode side is smooth,
in the 2 nd bonding electrode, a surface of a side opposite to the 1 st bonding electrode is smooth.
2. The semiconductor device according to claim 1, wherein,
the electrode comprises aluminum or an aluminum alloy,
the 1 st bonding electrode comprises nickel, nickel phosphorus or nickel boron,
the 2 nd bonding electrode includes gold.
3. The semiconductor element according to claim 1 or 2, wherein,
the 2 nd bonding electrode is composed of a plurality of layers.
4. The semiconductor device according to claim 3, wherein,
the lowermost layer of the plurality of layers in the 2 nd bonding electrode contains palladium, palladium phosphorus or palladium alloy,
the uppermost layer of the plurality of layers in the 2 nd bonding electrode includes gold.
5. The semiconductor element according to any one of claims 1 to 4, wherein,
the height of the protruding part is more than 1.0 μm.
6. The semiconductor element according to any one of claims 1 to 5, wherein,
the semiconductor element further includes:
a gate oxide film provided between the semiconductor chip and the electrode; and
a gate electrode provided in the gate oxide film,
the convex portion is located above the gate oxide film.
7. The semiconductor element according to any one of claims 1 to 6, wherein,
the semiconductor element is a front-side and back-side conductive semiconductor element having a front-side electrode and a back-side electrode, and the electrode includes the front-side electrode.
8. The semiconductor device according to claim 7, wherein,
the 1 st bonding electrode and the 2 nd bonding electrode are also provided on the back electrode.
9. A power conversion device, wherein the power conversion device includes:
a main conversion circuit having the semiconductor element according to any one of claims 1 to 8, and converting and outputting the input electric power; and
and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
10. A manufacturing method of a semiconductor element, comprising:
a step 1 of forming an electrode on at least one main surface of a semiconductor chip;
a step 2 of forming a 1 st bonding electrode on the electrode; and
a step 3 of forming a 2 nd bonding electrode on the 1 st bonding electrode,
in the step 1, a convex portion is formed on the surface of the electrode on the 1 st bonding electrode side,
in the step 2, the surface of the 1 st bonding electrode on the 2 nd bonding electrode side is formed to be smooth,
in the 3 rd step, the surface of the 2 nd bonding electrode opposite to the 1 st bonding electrode is formed to be smooth.
11. The manufacturing method according to claim 10, wherein,
the electrode comprises aluminum or an aluminum alloy,
the 1 st bonding electrode comprises nickel, nickel phosphorus or nickel boron,
the 2 nd bonding electrode includes gold.
12. The manufacturing method according to claim 10 or 11, wherein,
the 2 nd bonding electrode is composed of a plurality of layers.
13. The manufacturing method according to claim 12, wherein,
the lowermost layer of the plurality of layers in the 2 nd bonding electrode contains palladium, palladium phosphorus or palladium alloy,
the uppermost layer of the plurality of layers in the 2 nd bonding electrode includes gold.
14. The manufacturing method according to any one of claims 10 to 13, wherein,
the height of the protruding part is more than 1.0 μm.
15. The manufacturing method according to any one of claims 10 to 14, wherein,
the method also comprises the following steps: forming a gate oxide film between the semiconductor chip and the electrode, and forming a gate electrode within the gate oxide film,
in the step 1, the convex portion is formed above the gate oxide film.
16. The manufacturing method according to any one of claims 10 to 15, wherein,
the semiconductor element is a front-side and back-side conductive semiconductor element having a front electrode and a back electrode,
The electrode includes the front electrode.
17. The manufacturing method according to claim 16, wherein,
the 1 st bonding electrode and the 2 nd bonding electrode are also formed on the back electrode.
18. The manufacturing method according to any one of claims 10 to 17, wherein,
the 1 st bonding electrode is formed by electroless nickel plating and is performed at a nickel deposition rate of 4.0 μm/hr or more and 10 μm/hr or less until the surface of the 2 nd bonding electrode side is smoothed.
19. The manufacturing method according to any one of claims 10 to 17, wherein,
the 1 st bonding electrode is formed by sequentially performing electroless nickel plating and CMP.
20. A semiconductor element, wherein the semiconductor element is manufactured by the manufacturing method according to any one of claims 10 to 19.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2021032617 | 2021-03-02 | ||
| JP2021-032617 | 2021-03-02 | ||
| PCT/JP2022/008577 WO2022186192A1 (en) | 2021-03-02 | 2022-03-01 | Semiconductor element, electric power conversion device, and manufacturing method for semiconductor element |
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| JP5707709B2 (en) * | 2009-03-23 | 2015-04-30 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| JP5649322B2 (en) * | 2010-04-12 | 2015-01-07 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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