JP2022054004A - Method for producing semiconductor device, semiconductor device and power conversion device - Google Patents

Abstract

To provide a method for producing a semiconductor device that can prevent a pinhole being formed in an electroless gold plating film, a semiconductor device and a power conversion device.SOLUTION: A method for producing a semiconductor device SD includes following steps of: forming a nickel (Ni) oxide film 2 on a nickel (Ni) electrode 3 so as to expose part of a nickel (Ni) electrode 3; and forming, by electroless plating, an electroless gold (Au) plating film 1 on the nickel (Ni) oxide film.SELECTED DRAWING: Figure 14

Description

The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device, and a power conversion device.

For example, in a power semiconductor device using a silicon carbide (SiC) wafer, gold (Au) plating is performed after nickel (Ni) plating in the final step of electrode formation. For example, Japanese Patent No. 4490542 (Patent Document 1) describes a terminal in which a nickel (Ni) plating layer is coated with a gold (Au) plating layer.

Japanese Patent No. 4490542

In electrodes where electroless gold (Au) plating is performed after nickel (Ni) plating, nickel (Ni) elutes from the underlying nickel (Ni) plating layer when electroless gold (Au) plating is performed. , Pinholes are formed in the gold (Au) plating layer (electrolytic gold plating film). If water remains in the pinholes formed in the gold (Au) plating layer when gold (Au) plating is performed, nickel (Ni) and nickel (Ni) oxide will be gold (Ni) through the pinholes. Au) Elutes on the plating layer. As a result, the nickel (Ni) plating layer (nickel electrode) is corroded.

The present disclosure has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device, a semiconductor device, and a power change device capable of preventing the formation of pinholes in an electroless gold plating film. It is to be.

The method for manufacturing a semiconductor device of the present disclosure includes the following steps. A nickel oxide film is formed on the nickel electrode so as to expose a part of the nickel electrode. An electroless gold plating film is formed on the nickel oxide film by electroless plating.

According to the method for manufacturing a semiconductor device of the present disclosure, an electroless gold plating film is formed on a nickel oxide film formed on a nickel electrode so as to expose a part of the nickel electrode. Therefore, pinholes in the electroless gold plating film due to the elution of nickel ions are not formed. Therefore, it is possible to prevent the formation of pinholes in the electroless gold plating film.

It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. 3 is a cross-sectional view taken along the line II-II of FIG. It is a top view which shows one step of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which shows the next process of the process shown in FIG. 4 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 5 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 6 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 7 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 8 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 9 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 10 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 11 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 12 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the next process of the process shown in FIG. 13 of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. FIG. 3 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment. It is sectional drawing which follows the XVI-XVI line of FIG. It is a block diagram which shows the structure of the power conversion system to which the power conversion apparatus which concerns on Embodiment 3 is applied.

Hereinafter, embodiments will be described with reference to the drawings. In the following, the same or corresponding parts shall be designated by the same reference numerals, and duplicate explanations will not be repeated.

Embodiment 1.
The configuration of the semiconductor device SD according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view schematically showing the configuration of the semiconductor device SD according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line II-II of FIG.

In the present embodiment, the semiconductor device SD is, for example, a power semiconductor device. The semiconductor device SD is, for example, a silicon carbide semiconductor device using a silicon carbide (SiC) substrate. The semiconductor device SD is, for example, a Schottky barrier diode (SBD).

In the present embodiment, the semiconductor device SD includes a electroless gold (Au) plating film (gold film) 1, a nickel (Ni) oxide film 2, a nickel (Ni) electrode 3, and a Schottky electrode layer (first). Electrode layer (4), protective film 5, interlayer insulating layer (insulating film) 6, epitaxial substrate 9, backside electrode layer (second electrode layer) 10, and front surface electrode layer (metal electrode) 11. Have.

The epitaxial substrate 9 has a drift layer (semiconductor layer) 7 and a silicon carbide (SiC) substrate 8. The drift layer 7 has a surface S1 and a surface S2 opposite to the surface S1. The silicon carbide (SiC) substrate 8 has a surface S3 facing the surface S2 of the drift layer 7 and a surface S4 opposite to the surface S3. The silicon carbide (SiC) substrate 8 is a single crystal substrate. The drift layer 7 is an epitaxial layer formed on a silicon carbide (SiC) substrate 8. The drift layer 7 has an n-type. The silicon carbide (SiC) substrate 8 has an n-type. The silicon carbide (SiC) substrate 8 has a high impurity concentration as compared with the impurity concentration of the drift layer 7. Therefore, the impurity concentration of the drift layer 7 is lower than the impurity concentration of the silicon carbide (SiC) substrate 8. The drift layer 7 may have a multi-layer structure. For example, the drift layer 7 may have a first drift region forming the surface S2 and a second drift region arranged on the first drift region and forming the surface S1. The impurity concentration in the first drift region and the impurity concentration in the second drift region may be different from each other.

The Schottky electrode layer 4 is Schottky bonded to the drift layer 7. The shotkey electrode layer 4 is arranged away from the edge of the surface S1 of the drift layer 7 and forms an interface with a part of the surface S1. Of the surface S1, the region where this interface is provided is the cell region, and the region around it is the outer peripheral region. The cell region has an element function intended by the semiconductor device SD. Specifically, this element function is a rectifying function. The outer peripheral region has a function of suppressing destruction of the semiconductor device SD due to electric discharge at the outer peripheral portion of the epitaxial substrate 9.

The surface electrode layer 11 is provided on the shotkey electrode layer 4. The material of the surface electrode layer 11 is, for example, aluminum, an aluminum alloy containing silicon, nickel, or the like.

The nickel (Ni) electrode 3 is provided on the surface electrode layer (metal electrode) 11. The nickel (Ni) electrode 3 is provided in the region surrounded by the protective film 5. That is, the nickel (Ni) electrode 3 is provided on the surface electrode layer 11 in a region where the protective film 5 is not arranged. The nickel (Ni) electrode 3 includes a first region R1 exposed from the nickel (Ni) oxide film 2 and a second region R2 covered with the nickel (Ni) oxide film 2. In the first region R1, the nickel (Ni) electrode 3 is exposed. In the second region R2, a nickel (Ni) oxide film 2 is provided on the nickel (Ni) electrode 3. The first region R1 of the nickel (Ni) electrode 3 is smaller than the second region R2 of the nickel (Ni) electrode 3. That is, on the surface of the nickel (Ni) electrode 3, the area of the first region R1 is smaller than the area of the second region R2. Specifically, the nickel (Ni) oxide film 2 is provided on most of the surface of the nickel (Ni) electrode 3.

The nickel (Ni) oxide film 2 is provided on the nickel (Ni) electrode 3 so as to expose a part of the nickel (Ni) electrode 3. The nickel (Ni) oxide film 2 is provided on a part of the nickel (Ni) electrode 3. The nickel (Ni) oxide film 2 is not provided in the first region R1 of the nickel (Ni) electrode 3. The nickel (Ni) oxide film 2 is provided in the second region R2 of the nickel (Ni) electrode 3.

The electroless gold (Au) plating film 1 is provided on the nickel (Ni) oxide film 2. No pinholes are formed in the electroless gold (Au) plating film 1.

The interlayer insulating layer 6 is provided around the shot key electrode layer 4 on the surface S1 of the drift layer 7. The interlayer insulating layer 6 is in contact with the Schottky electrode layer 4. Typically, the Schottky electrode layer 4 has an end portion arranged on the interlayer insulating layer 6 and is in contact with the drift layer 7 at the opening of the interlayer insulating layer 6.

The protective film 5 may be provided as the outermost structure on the surface S1 of the drift layer 7. The protective film 5 is made of an insulator. The material of the protective film 5 is, for example, a resin.

The back surface electrode layer 10 is provided on the surface S4 of the silicon carbide (SiC) substrate 8. In the present embodiment, the back surface electrode layer 10 is provided on the entire surface S4 of the silicon carbide (SiC) substrate 8. The back surface electrode layer 10 is ohmically bonded to the surface S4 of the silicon carbide (SiC) substrate 8. The back surface electrode layer 10 faces the shotkey electrode layer 4 in the vertical direction. Therefore, the main current of the semiconductor device SD flows along the vertical direction in FIG. Therefore, the semiconductor device SD is a vertical semiconductor device, in other words, a front-back conduction type semiconductor device. Each of the nickel (Ni) electrode 3 and the backside electrode layer 10 may be wired to the outside of the semiconductor device SD by a suitable member such as wire bonding or soldering.

Next, a method of manufacturing the semiconductor device SD according to the first embodiment will be described with reference to FIGS. 3 to 14. FIG. 3 is a plan view schematically showing the first step of the method for manufacturing the semiconductor device SD according to the first embodiment. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 5 to 14 are cross-sectional views schematically showing the second to eleventh steps of the method for manufacturing the semiconductor device SD according to the first embodiment.

With reference to FIGS. 3 and 4, an epitaxial wafer WA having an n-type impurity is prepared. The size of the epitaxial wafer WA in a plan view is larger than the size in a plan view of the semiconductor device SD (see FIG. 1). In mass production, a plurality of semiconductor device SDs are finally cut out from the epitaxial wafer WA by dicing. The epitaxial wafer WA is silicon carbide (SiC) having a drift layer 7 having a surface S1 and a surface S2 opposite to the surface S1, a surface S3 facing the surface S2 of the drift layer 7, and a surface S4 opposite to the surface S3. It has a substrate 8. The epitaxial wafer WA is obtained by epitaxially growing the drift layer 7 by epitaxial growth on the surface S3 of the silicon carbide (SiC) substrate 8 in the form of a wafer, that is, before dicing. Epitaxy is typically carried out by deposition of silicon carbide (SiC), with impurities added as needed.

The drift layer 7 may be formed in a multilayer structure by changing the film forming conditions during the epitaxial growth. For example, a first drift region is formed on the surface S3 of the silicon carbide (SiC) substrate 8. After that, a second drift region may be formed on the first drift region. For example, after the first drift region is epitaxially grown at the first growth temperature, the second drift region is epitaxially grown at a second growth temperature lower than the first growth temperature.

With reference to FIG. 5, the interlayer insulating layer 6 is formed on the surface S1 of the drift layer 7. As a film forming method, for example, a thermal oxidation method or a deposition method is used. As the deposition method, for example, a chemical vapor deposition (CVD) method is used.

Further, referring to FIG. 6, a pattern is applied to the interlayer insulating layer 6. This patterning is performed so that the interlayer insulating layer 6 is arranged around the Schottky electrode layer 4 at the time of completion of the semiconductor device SD (see FIG. 2). Specifically, first, an etching mask (not shown) made of a resist or the like is formed on the interlayer insulating layer 6 by using photoengraving. Next, an unnecessary portion of the interlayer insulating layer 6 is removed by dry etching using plasma, wet etching using a chemical solution, or the like. After that, the etching mask is removed by plasma ashing, wet treatment, or the like. This gives the structure shown in FIG.

Impurities may be added on the surface S1 of the drift layer 7 before or after the formation of the interlayer insulating layer 6. For example, in order to improve the withstand voltage of the semiconductor device SD, an impurity layer may be formed on the portion of the surface S1 where the interlayer insulating layer 6 is arranged by adding impurities. The addition of impurities is carried out, for example, by ion implantation and activation. As the acceptor impurity, for example, boron (B) or aluminum (Al) is used. As the donor impurities, for example, phosphorus (P) or nitrogen (N) is used.

With reference to FIG. 7, the shotkey electrode layer 4 is then formed. Specifically, first, a wet treatment containing hydrofluoric acid and a cleaning treatment are performed on the surface S1 on which the shotkey electrode layer 4 is to be formed, if necessary. For the cleaning treatment, for example, a mixed solution of ammonia and hydrogen peroxide solution, a mixed solution of sulfuric acid and hydrogen peroxide solution, and a mixed solution of hydrochloric acid and hydrogen peroxide solution are used. Next, the shotkey electrode layer 4 is formed into a film. As the material, titanium (Ti), nickel (Ni), iridium (Ir), platinum (Pt) or the like can be appropriately selected. After that, a pattern is applied to the shot key electrode layer 4. This patterning is performed so that the shotkey electrode layer 4 forms an interface with a part of the surface S1 of the drift layer 7. Specifically, first, an etching mask (not shown) made of a resist or the like is formed on the shotkey electrode layer 4 by using photoengraving. Next, an unnecessary portion of the shotkey electrode layer 4 is removed by dry etching using plasma, wet etching using a chemical solution, or the like. After that, the etching mask is removed by plasma ashing, wet treatment, or the like. This gives the structure shown in FIG. If necessary, heat treatment may be performed to further secure the electrical connection between the shotkey electrode layer 4 and the drift layer 7.

With reference to FIG. 8, the surface electrode layer 11 is formed on the Schottky electrode layer 4. Specifically, first, the film to be the surface electrode layer 11 is formed by a sputtering method, a vapor deposition method, or the like. The deposited material is, for example, aluminum, an aluminum alloy containing silicon, nickel, or the like. Next, a pattern is imparted to this film. Specifically, first, an etching mask (not shown) made of a resist or the like is formed on this film by using photoengraving. Next, an unnecessary portion of the film is removed by dry etching using plasma, wet etching using a chemical solution, or the like.

After that, as shown by the broken line in FIG. 8, the thickness of the silicon carbide (SiC) substrate 8 may be reduced by processing the silicon carbide (SiC) substrate 8 on the surface S4. For example, a grindstone composed of alumina abrasive grains or diamond abrasive grains is used to grind the surface S4.

With reference to FIG. 9, the back surface electrode layer 10 is formed on the surface S4 of the silicon carbide (SiC) substrate 8. For example, titanium, a titanium alloy, aluminum, an aluminum alloy containing silicon, nickel, or the like is deposited. The back surface electrode layer 10 may be provided with a multilayer structure. For example, even if an antioxidant film made of a silver alloy containing gold, platinum, silver, or palladium is formed on the outermost surface of the back surface electrode layer 10 in order to prevent the electrode material from being oxidized during soldering. good.

With reference to FIG. 10, the protective film 5 is subsequently formed. Specifically, first, a film made of silicon nitride (SiN), polyimide, or the like is formed. As the film forming method, for example, a CVD method, or a coating method using spin coating or inkjet can be used. Next, a pattern is imparted to this film.

With reference to FIG. 11, a nickel (Ni) electrode 3 is formed by plating on the surface electrode layer 11. Specifically, first, the plating pretreatment is performed as follows.

Plasma cleaning using, for example, plasma is performed on the surface electrode layer 11. Plasma cleaning is a treatment method for purifying the surface by oxidatively decomposing or knocking out organic residue that has been burned onto the surface electrode layer 11 and cannot be removed by general plating pretreatment.

Next, a degreasing treatment is performed to remove mild organic contamination and an oxide film remaining on the surface of the surface electrode layer 11.

Next, acid cleaning is performed to neutralize the surface of the surface electrode layer 11, etch the surface to roughen the surface, increase the reactivity of the treatment liquid in the subsequent step, and improve the adhesive force of the plating.

Next, a zincate treatment (zinc base treatment) for forming a zinc (Zn) film is performed on the surface of the surface electrode layer 11. The zincate treatment is a treatment of immersing in an aqueous solution in which zinc (Zn) is dissolved as ions to form a zinc (Zn) film on the surface of the surface electrode layer 11.

As described above, the plating pretreatment is performed. Sufficient washing time is secured between each process. As a result, it is possible to prevent the treatment liquid and the residue from the previous step from being brought into the next step.

Next, the nickel (Ni) electrode 3 is formed by performing electroless nickel (Ni) plating. Specifically, when the surface electrode layer 11 coated with zinc (Zn) is immersed in a non-electrolytic nickel (Ni) plating solution, zinc (Zn) is initially more standard oxidation than nickel (Ni). Since the reduction potential is low, zinc (Zn) becomes ions and elutes, and nickel (Ni) is deposited on the surface electrode layer 11. Subsequently, when the surface is covered with nickel (Ni), nickel (Ni) is automatically and catalytically precipitated by the action of the reducing agent contained in the plating solution. However, at the time of this automatic catalytic precipitation, the component of the reducing agent is incorporated into the plating film, so that the nickel (Ni) electrode 3 becomes an alloy, and if the concentration of the reducing agent is high, it becomes amorphous. Since hypophosphorous acid is generally used as a reducing agent, phosphorus (P) is contained in the nickel (Ni) electrode 3. The nickel (Ni) electrode 3 is formed on a portion where zinc (Zn) ions are eluted and nickel (Ni) is deposited, that is, on the surface electrode layer 11 and not covered by the protective film 5.

Subsequently, with reference to FIG. 12, a nickel (Ni) oxide film 2 is formed on the nickel (Ni) electrode 3. Specifically, the nickel (Ni) oxide film 2 is formed by a method of oxidizing the surface of the nickel (Ni) electrode 3. After the nickel (Ni) electrode 3 is formed by electroless nickel (Ni) plating, the nickel (Ni) electrode 3 is washed with ozone water. Ozone water is made by dissolving ozone generated by an ozone generator in water. Since ozone water has the effect of oxidizing the metal surface, the surface of the nickel (Ni) electrode 3 is oxidized when the nickel (Ni) electrode 3 is immersed in ozone water. As a result, the nickel (Ni) oxide film 2 is formed. As a method for oxidizing the surface of the nickel (Ni) electrode 3, a method of washing with boiling water, a method of drying with warm air after washing with water, a method of drying with oxygen after washing with water, and the like may be used.

Next, with reference to FIG. 13, a part of the nickel (Ni) oxide film 2 is removed by laser irradiation. As a result, a part of the nickel (Ni) electrode 3 is exposed from the nickel (Ni) oxide film 2. Specifically, the laser beam irradiates a part of the nickel (Ni) oxide film 2. A part of the nickel (Ni) oxide film is removed by evaporating the nickel (Ni) oxide film 2 by the heat generated by the laser beam. As a result, a part of the nickel (Ni) electrode 3 is exposed from the nickel (Ni) oxide film 2. When the laser beam is irradiated, the inert gas is injected, so that the generated nickel (Ni) electrode 3 is suppressed from being oxidized again. As the inert gas, for example, nitrogen (N ₂ ), argon (Ar) and the like are used. In this way, the nickel (Ni) oxide film 2 is formed on the nickel (Ni) electrode 3 so as to expose a part of the nickel (Ni) electrode 3. In the step of forming the nickel (Ni) oxide film 2, the first region R1 of the nickel (Ni) electrode 3 is exposed from the nickel (Ni) oxide film 2, and the second region R2 of the nickel (Ni) electrode 3 is nickel (Ni). Ni) Covered with oxide film 2. The first region R1 is smaller than the second region R2.

Subsequently, with reference to FIG. 14, an electroless gold (Au) plating film 1 is formed on the nickel (Ni) oxide film 2. Specifically, when a part of the nickel (Ni) electrode 3 exposed from the nickel (Ni) oxide film 2 and the nickel (Ni) oxide film 2 is immersed in the electroless gold (Au) plating solution, nickel (Ni) is used. ) Has a lower standard oxidation-reduction potential than the nickel (Ni) oxide film, so nickel (Ni) elutes as ions and gold (Au) is deposited on the nickel (Ni) oxide film 2. .. As a result, the electroless gold (Au) plating film 1 is formed. When the electroless gold (Au) plating film 1 is formed, nickel (Ni) ions are not eluted from the nickel (Ni) oxide film 2, so that the electroless gold (Au) due to the elution of nickel (Ni) ions is formed. ) No pinholes are formed in the plating film 1. Since the nickel (Ni) oxide film 2 has conductivity, it has no influence as a device for passing an electric current. In this way, the electroless gold (Au) plating film 1 is formed on the nickel (Ni) oxide film by electroless plating. In the step of forming the electroless gold (Au) plating film 1, nickel is eluted from the first region R1 of the nickel (Ni) electrode 3, and nickel is not eluted from the nickel (Ni) oxide film 2.

Since the pinholes are not formed in the electroless gold (An) plating film 1, it is possible to suppress the corrosion of the nickel (Ni) electrode 3 due to the residual plating solution in the pinholes. Therefore, deterioration of the solder wettability to the electroless gold (Au) plating film 1 is suppressed.

A plurality of devices formed on the epitaxial wafer WA shown in FIG. 14 are divided into a single device by dicing. As a result, the semiconductor device SD shown in FIG. 2 is completed.

Although the case where the epitaxial substrate 9 is n-type has been described in detail above, the epitaxial substrate 9 may be p-type.

Next, the action and effect of this embodiment will be described.
According to the method for manufacturing the semiconductor device SD according to the first embodiment, on the nickel (Ni) oxide film 2 formed on the nickel (Ni) electrode 3 so as to expose a part of the nickel (Ni) electrode 3. The electroless gold (Au) plating film 1 is formed. In electroless plating, a part of the nickel (Ni) oxide film 2 and the nickel (Ni) electrode 3 exposed from the nickel (Ni) oxide film 2 is immersed in the electroless gold (Au) plating solution. Since nickel (Ni) has a lower standard redox potential than nickel (Ni) oxide film, nickel (Ni) becomes ions and elutes, and gold (Au) is placed on the nickel (Ni) oxide film 2. Precipitates. As a result, the electroless gold (Au) plating film 1 is formed. When the electroless gold (Au) plating film 1 is formed, nickel (Ni) ions are not eluted from the nickel (Ni) oxide film 2, so that the electroless gold (Au) due to the elution of nickel (Ni) ions is formed. ) No pinholes are formed in the plating film 1. Therefore, it is possible to prevent the pin pole from being formed on the electroless gold (Au) plating film 1.

Since the pinholes are not formed in the electroless gold (An) plating film 1, it is possible to prevent the nickel (Ni) electrode 3 from being corroded due to the residual plating solution in the pinholes. Since the nickel (Ni) electrode 3 is not corroded, deterioration of the solder wettability to the electroless gold (Au) plating film 1 is suppressed. Therefore, the solder bonding is good. This improves the reliability of the semiconductor device SD.

According to the method for manufacturing the semiconductor device SD according to the first embodiment, the first region R1 of the nickel (Ni) electrode 3 is smaller than the second region R2. Therefore, it is easy to use the first region R1 as a sacrificial place. This sacrificial part may be a part where nothing is formed, or may be a wire bonding part.

According to the method for manufacturing the semiconductor device SD according to the first embodiment, nickel is eluted from the first region R1 of the nickel (Ni) electrode 3, and nickel is not eluted from the nickel (Ni) oxide film 2. Therefore, it is possible to concentrate the elution of nickel in the first region R1 of the nickel (Ni) electrode 3 and create a situation in which nickel is not eluted from the nickel (Ni) oxide film 2.

According to the semiconductor device SD according to the first embodiment, the electroless gold (Ni) oxide film provided on the nickel (Ni) electrode 3 is provided so as to expose a part of the nickel (Ni) electrode 3. Au) The plating film 1 is provided. In electroless plating, a part of the nickel (Ni) oxide film 2 and the nickel (Ni) electrode 3 exposed from the nickel (Ni) oxide film 2 is immersed in the electroless gold (Au) plating solution. Since nickel (Ni) has a lower standard redox potential than nickel (Ni) oxide film, nickel (Ni) becomes ions and elutes, and gold (Au) is placed on the nickel (Ni) oxide film 2. Precipitates. As a result, the electroless gold (Au) plating film 1 is formed. When the electroless gold (Au) plating film 1 is formed, nickel (Ni) ions are not eluted from the nickel (Ni) oxide film 2, so that the electroless gold (Au) due to the elution of nickel (Ni) ions is formed. ) No pinholes are formed in the plating film 1. Therefore, it is possible to prevent the pin pole from being formed on the electroless gold (Au) plating film 1.

Since the pinholes are not formed in the electroless gold (An) plating film 1, it is possible to prevent the nickel (Ni) electrode 3 from being corroded due to the residual plating solution in the pinholes. Since the nickel (Ni) electrode 3 is not corroded, deterioration of the solder wettability to the electroless gold (Au) plating film 1 is suppressed. Therefore, the solder bonding is good. This improves the reliability of the semiconductor device SD.

According to the semiconductor device SD according to the first embodiment, the first region R1 of the nickel (Ni) electrode 3 is smaller than the second region R2. Therefore, it is easy to use the first region R1 as a sacrificial place. This sacrificial part may be a part where nothing is formed, or may be a wire bonding part.

Subsequently, a modified example of the present embodiment will be described.
In the above, the Schottky barrier diode (SBD) is formed by using the epitaxial wafer WA (see FIG. 3), but the semiconductor device SD is not limited to the Schottky barrier diode (SBD) and is not limited to other types. It may be a semiconductor device. Depending on this type, the epitaxial wafer WA is desired by forming an insulating film and a metal film, patterning using photoengraving and etching, and forming an impurity layer by ion implantation and activation. It suffices if the semiconductor chip of the above is formed. Depending on the type of semiconductor device, an ohmic electrode layer is provided as the first electrode layer instead of the Schottky electrode layer 4 (see FIG. 2). Further, depending on the type of the semiconductor device, the conductive type of the silicon carbide (SiC) substrate 8 and the conductive type of the drift layer 7 may be opposite to each other.

Specifically, the semiconductor device SD may be a diode of another type other than the Schottky barrier diode (SBD). Further, the semiconductor device SD is not limited to the diode, and may be, for example, a semiconductor switching element such as a transistor. The transistor is, for example, a MISFET (Metal Insulator Semiconductor Shield Transistor) such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an IGBT Transistor. For example, in order to obtain an n-channel MISFET, an n-type drain region is configured by a silicon carbide substrate, and an n-type drift layer provided with a p-type base region and an n-type source region is configured by the semiconductor layer on this substrate. Will be done. The n-type source region is arranged on the first surface of the semiconductor layer. The p-type base region separates the n-type source region and the n-type drift layer. The impurity concentration of the n-type drift layer is smaller than the impurity concentration of the n-type drain region. The first electrode layer constitutes a source electrode electrically connected to the n-type source region. The second electrode layer constitutes a drain electrode electrically connected to the n-type drain region. If the conductive type of each configuration is replaced, the conductive type of the channel is also opposite. In order to obtain an IGBT, for example, the conductive type of the silicon carbide substrate in the above-mentioned MISFET may be reversed. In that case, each of the first electrode layer and the second electrode layer functions as an emitter electrode and a collector electrode.

Each of the above-mentioned silicon carbide substrate and semiconductor layer is typically a silicon carbide substrate prepared in advance and a semiconductor layer formed by epitaxial growth on the silicon carbide substrate. However, the silicon carbide substrate and the semiconductor layer are not necessarily limited to those prepared in this way. For example, two layers may be formed on a previously prepared single crystal substrate, and these two layers may be used as a silicon carbide substrate and a semiconductor layer. In this case, the single crystal substrate may be removed during the manufacture of the silicon carbide semiconductor device.

Embodiment 2.
Unless otherwise specified, the second embodiment has the same configuration, manufacturing method, and action and effect as those of the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will not be repeated.

The configuration of the semiconductor device SD according to the second embodiment will be described with reference to FIGS. 15 and 16. FIG. 15 is a plan view schematically showing the configuration of the semiconductor device SD according to the second embodiment. FIG. 16 is a cross-sectional view taken along the line XVI-XVI of FIG.

In the semiconductor device SD according to the second embodiment, the protective film 5 is formed between the region where the electroless gold (Au) plating film 1 is formed and the region where the nickel (Ni) electrode 3 is exposed. .. The protective film 5 is provided on the surface electrode layer (metal electrode) 11. The nickel (Ni) electrode 3 is provided on the surface electrode layer (metal electrode) 11. The protective film 5 is arranged between the first region R1 and the second region R2 of the nickel (Ni) electrode 3. The region provided with the electroless gold (Au) plating film 1 and the nickel (Ni) oxide film 2 and the region where the nickel (Ni) electrode 3 is exposed are separated by the protective film 5.

Next, a method of manufacturing the semiconductor device SD according to the second embodiment will be described.
An epitaxial wafer WA on which the front surface electrode layer 11 and the back surface electrode layer 10 are formed is prepared by the same steps as in the first embodiment. After that, when the protective film 5 of the first embodiment is formed, the protective film 5 is also between the region where the electroless gold (Au) plating film 1 is formed and the region where the nickel (Ni) electrode 3 is exposed. Is formed. After that, a part of the nickel (Ni) oxide film 2 is removed by laser irradiation. As a result, a part of the nickel (Ni) electrode 3 is exposed from the nickel (Ni) oxide film 2. A part of the nickel (Ni) electrode 3 may be exposed from the nickel (Ni) oxide film 2 in at least one region of the plurality of regions separated by the protective film 5.

Next, the action and effect of this embodiment will be described.
According to the semiconductor device SD according to the second embodiment, the protective film 5 is arranged between the first region R1 and the second region R2. Therefore, the first region R1 and the second region R2 can be separated by the protective film 5.

Embodiment 3.
In this embodiment, the semiconductor device according to the above-described first or second embodiment is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as the third embodiment.

FIG. 17 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 17 includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be configured with various things, for example, it can be configured with a DC system, a solar cell, a storage battery, or it can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. May be good. Further, the power supply 100 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 17, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And have.

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200. The load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.

Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and by switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes. At least one of each switching element and each freewheeling diode of the main conversion circuit 201 is a switching element or a freewheeling diode included in the semiconductor device 202 corresponding to the semiconductor device according to any one of the above-described first and second embodiments. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

Further, although the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element, the drive circuit may be built in the semiconductor device 202, or the drive circuit may be provided separately from the semiconductor device 202. It may be provided. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) in which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the electric power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit provided in the main conversion circuit 201 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Is output. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device according to the present embodiment, since the semiconductor device according to the first and second embodiments is applied as the semiconductor device 202 constituting the main conversion circuit 201, the power conversion device can be miniaturized and simplified. It can be realized to connect to.

In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is disclosed to a single-phase inverter. You may apply it. Further, when supplying electric power to a DC load or the like, the present disclosure can be applied to a DC / DC converter or an AC / DC converter.

Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device of a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present disclosure is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 Electrolytic gold plating film, 2 Nickel (Ni) oxide film, 3 Nickel (Ni) electrode, 4 Shotkey electrode layer, 5 Protective film, 6 Interlayer insulation layer, 7 Drift layer, 8 Silicon carbide (SiC) substrate, 9 Epitaxial substrate, 10 back electrode layer, 11 front electrode layer, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202, SD semiconductor device, 203 control circuit, 300 load, R1 first region, R2 second region.

Claims (7)

A step of forming a nickel oxide film on the nickel electrode so as to expose a part of the nickel electrode, and
A method for manufacturing a semiconductor device, comprising a step of forming an electroless gold plating film on the nickel oxide film by electroless plating. In the step of forming the nickel oxide film, the first region of the nickel electrode is exposed from the nickel oxide film, and the second region of the nickel electrode is covered with the nickel oxide film.
The method for manufacturing a semiconductor device according to claim 1, wherein the first region is smaller than the second region. The method for manufacturing a semiconductor device according to claim 2, wherein in the step of forming the electroless gold plating film, nickel is eluted from the first region of the nickel electrode and nickel is not eluted from the nickel oxide film. Nickel electrode and
A nickel oxide film provided on the nickel electrode so as to expose a part of the nickel electrode,
A semiconductor device including an electroless gold plating film provided on the nickel oxide film. The nickel electrode includes a first region exposed from the nickel oxide film and a second region covered with the nickel oxide film.
The semiconductor device according to claim 4, wherein the first region is smaller than the second region. With metal electrodes
Further provided with a protective film provided on the metal electrode,
The nickel electrode is provided on the metal electrode, and the nickel electrode is provided on the metal electrode.
The semiconductor device according to claim 5, wherein the protective film is arranged between the first region and the second region. A main conversion circuit having the semiconductor device according to any one of claims 4 to 6 and converting and outputting input power.
A control circuit that outputs a control signal that controls the main conversion circuit to the main conversion circuit, and a control circuit that outputs the control signal to the main conversion circuit.
Power conversion device equipped with.

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