CN116886779A - SENT protocol decoding detection circuit - Google Patents
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- CN116886779A CN116886779A CN202310971279.7A CN202310971279A CN116886779A CN 116886779 A CN116886779 A CN 116886779A CN 202310971279 A CN202310971279 A CN 202310971279A CN 116886779 A CN116886779 A CN 116886779A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/03—Protocol definition or specification
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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Abstract
The invention discloses a SENT protocol decoding detection circuit, and relates to the field of decoding; the SENT protocol decoding detection circuit includes: the data decoding circuit is used for generating SENT decoding data according to SENT frame format information and the filtered SENT serial data and transmitting the SENT decoding data to the data checking circuit and an external system provided with a receiving host; the data checking circuit is used for generating error monitoring information according to the SENT decoding data and the filtered SENT serial data and transmitting the error monitoring information to an external system provided with a receiving host. The SENT protocol decoding detection circuit is integrated between the transmitting chip and the interface chip of the receiving host, and can decode the data before the data enters the receiving host, so that the limitation that the data can only depend on the receiving host for decoding detection is avoided, and the data is decoded and detected by the SENT protocol decoding detection circuit before entering the receiving host, so that the operation complexity of the receiving host is reduced.
Description
Technical Field
The invention relates to the field of decoding, in particular to a SENT protocol decoding detection circuit.
Background
The single wire transmission protocol (Single Edge Nibble Transmission, send) is a low cost single wire, unidirectional, point-to-point data transmission protocol specified by the american society of automotive engineers and is widely used for information transmission from automotive sensors, electronic control units. As a unidirectional transmission protocol, the send data transmission module of the chip cannot identify errors of transmitted data in time, which can lead to a series of potential safety hazards. And the current widely used SENT protocol is a unidirectional transmission protocol, and decoding and checking of correctness of the transmitted data can only be realized by a receiving host by using a relevant decoding and checking tool, so that the decoding and checking of the transmitted data have limitations.
The decoding of the transmitted data and the verification of its correctness can only be achieved by the receiving host using the relevant decoding verification tool, which results in the complexity of the decoding operation of the receiving host.
Disclosure of Invention
The invention aims to provide a SENT protocol decoding detection circuit, which solves the limitation that a receiving host machine is required to be relied on for decoding detection in the prior art by designing the SENT protocol decoding detection circuit.
In order to achieve the above object, the present invention provides the following solutions:
a send protocol decode detection circuit integrated in an interface chip or a transmit chip of a receiving host, the send protocol decode detection circuit comprising:
a data decoding circuit for:
generating SENT decoding data according to SENT frame format information and the filtered SENT serial data based on the SENT decoding clock and the start signal;
transmitting the SENT decoding data to a data checking circuit and an external system provided with a receiving host;
a data verification circuit for:
generating error monitoring information according to the SENT decoding data and the filtered SENT serial data based on the SENT frame format information, the SENT decoding clock and the start signal;
and transmitting the error detection information to an external system provided with a receiving host.
Optionally, the send protocol decoding detection circuit further includes:
a data synchronization and filtering circuit for:
carrying out synchronous processing on the SENT serial data to obtain synchronous SENT serial data;
filtering the synchronized SENT serial data to obtain filtered SENT serial data;
and transmitting the filtered SENT serial data to the data decoding circuit and the data checking circuit.
Optionally, the send protocol decoding detection circuit further includes:
start signal generation logic to:
generating the start signal according to the filtered SENT serial data;
transmitting the start signal to the data decoding circuit and the data verification circuit.
Optionally, the data decoding circuit specifically includes:
the counter is used for decoding the filtered SENT serial data based on the SENT decoding clock and the starting signal to obtain decoded data; the decoding data comprises a status nibble, a data nibble and a cyclic redundancy check nibble;
frame structure judgment logic for determining subsequent pulses according to the synchronization pulse and the SENT frame format information; the synchronous pulse is obtained by identification according to the high level pulse length of the detected decoding data;
count value-data conversion logic for generating SENT decoded data from the decoded data and subsequent pulses;
and the internal register is used for registering the SENT decoding data and transmitting the SENT decoding data to the data checking circuit and the external system provided with the receiving host.
Optionally, the data verification circuit includes:
the serial data level detection logic is used for detecting whether the duration time of the high level and the low level of the filtered SENT serial data is abnormal or not, and obtaining a detection result;
if the detection result is negative, the filtered SENT serial data is characterized to have no error;
if the detection result is yes, representing that the filtered SENT serial data has errors, generating a first error reporting signal, and transmitting the first error reporting signal to an error state register;
the state nibble data extraction logic is used for generating channel information according to the SENT decoding data and respectively transmitting the channel information to the cyclic redundancy check calculation module and the cyclic redundancy check result comparison module; the channel message comprises fast channel information and slow channel information;
the cyclic redundancy check calculation module is used for calculating according to the channel information to obtain a first calculation result, and transmitting the first calculation result to the cyclic redundancy check result comparison module;
the cyclic redundancy check result comparison module is used for comparing whether the first calculation result is consistent with the slow channel message or not to obtain a comparison result;
if the comparison result is yes, representing that the SENT decoding data has no error;
if the comparison result is negative, representing that the SENT decoding data has errors, generating a second error reporting signal, and transmitting the second error reporting signal to the error state register;
the error status register is used for storing the second error reporting signal and the first error reporting result as the error monitoring information and transmitting the error monitoring information to an external system provided with a receiving host.
Optionally, the slow channel information includes a cyclic redundancy check value and slow channel data to be checked.
Optionally, the fast channel information includes a cyclic redundancy check value and fast channel data to be checked.
Optionally, the anomaly includes the low-level duration of the filtered SENT serial data not coinciding with the low-level duration threshold and the high-level duration of the filtered SENT serial data not being within the high-level duration normal threshold.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the SENT protocol decoding detection circuit provided by the invention can be integrated between the transmitting chip and the interface chip of the receiving host, and can decode data before the data enter the receiving host, so that the limitation that the data can only be decoded and detected by the receiving host is avoided, and the decoding and detection are carried out by the SENT protocol decoding detection circuit before the data enter the receiving host, so that the operation complexity of the receiving host is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a SENT protocol decoding detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data decoding circuit according to an embodiment of the present invention;
FIG. 3 is a basic SENT frame structure diagram in accordance with an embodiment of the invention;
FIG. 4 is a schematic diagram of a data verification circuit according to an embodiment of the invention.
Symbol description:
301. a synchronization pulse; 302. status nibbles; 303. a data nibble; 304. cyclic redundancy check nibbles.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a SENT protocol decoding detection circuit, which solves the limitation that a receiving host machine is required to be relied on for decoding detection in the prior art by designing the SENT protocol decoding detection circuit.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 1, in the present invention, an external clock is first input and converted into a send decoding clock for internal decoding detection by a corresponding module, and in the block diagram, a data decoding circuit, a data checking circuit, a data synchronization and filtering circuit and a start signal generating logic all operate under the send decoding clock. The input SENT serial data is synchronously processed by a data synchronization and filtering circuit by using a SENT decoding clock, and is filtered. The start signal is then generated from the filtered SENT serial data, and the SENT input bus is always pulled high when no input is present, so that when a falling edge occurs, the start signal generation logic will detect it and generate a start signal to turn on the data decoding circuitry and the data verification circuitry. The data checking circuit detects the SENT decoding data and the filtered SENT serial data at the same time. Finally, the SENT protocol decoding detection circuit outputs the decoded data and error detection information (if an error is detected). It should be noted that the circuit designed according to the present invention needs to know that the current send data frame structure is as shown in fig. 3 and 2, and the circuit has different detection functions under different frame structures.
As shown in fig. 1, a send protocol decoding detection circuit of the present invention is integrated in an interface chip or a transmitting chip of a receiving host, and the send protocol decoding detection circuit includes:
the data decoding circuit is used for generating SENT decoding data according to SENT frame format information and the filtered SENT serial data based on the SENT decoding clock and the starting signal, and transmitting the SENT decoding data to the data checking circuit and an external system provided with a receiving host.
The data checking circuit is used for generating error monitoring information according to SENT decoding data and the filtered SENT serial data based on SENT frame format information, SENT decoding clock and a start signal and transmitting the error monitoring information to an external system provided with a receiving host.
As a specific embodiment, the send protocol decoding detection circuit further includes:
the data synchronization and filtering circuit is used for carrying out synchronization processing on the SENT serial data to obtain synchronized SENT serial data; filtering the synchronized SENT serial data to obtain filtered SENT serial data; and transmitting the filtered SENT serial data to a data decoding circuit and a data checking circuit.
As a specific embodiment, the send protocol decoding detection circuit further includes:
the start signal generation logic is used for generating a start signal according to the filtered SENT serial data; and transmits a start signal to the data decoding circuit and the data verification circuit.
As shown in fig. 2, as a specific embodiment, the data decoding circuit specifically includes:
the counter is used for decoding the filtered SENT serial data based on the SENT decoding clock and the starting signal to obtain decoded data; the decoded data includes a status nibble 302, a data nibble 303, and a cyclic redundancy check nibble 304.
Frame structure judgment logic for determining a subsequent pulse based on the synchronization pulse 301 and the send frame format information; the synchronization pulse 301 is identified based on detecting the high level pulse length of the decoded data.
Count-to-data conversion logic for generating SENT decoded data from the decoded data and subsequent pulses.
And the internal register is used for registering the SENT decoding data and transmitting the SENT decoding data to the data checking circuit and an external system provided with a receiving host.
In a specific application, the decoding scheme of the data decoding circuit is designed based on the SENT protocol, and according to the standard SENT protocol, as shown in FIG. 3, the first pulse of the SENT data input of each frame is a synchronization pulse 301, and the length between the rising edge of the synchronization pulse 301 and the rising edge of the status nibble 302 is fixed to 56 clocks ticks. Therefore, the sync pulse 301 will be identified by detecting the high level pulse length and the subsequent pulse meaning will be determined in sequence based on the sync pulse 301 and the send frame format information setting. The decoding of the status nibble 302, the data nibble 303 and the cyclic redundancy check nibble 304 is implemented based on a counter, wherein a counter is used in the module to record the length (the number of ticks) of each nibble and obtain the representative data of each nibble through a count value-data conversion logic, so as to generate SENT decoded data, wherein the count value-data conversion logic is determined according to the SENT protocol, i.e. the number of ticks from the rising edge of each nibble pulse to the rising edge of the next nibble pulse minus the fixed number of ticks can obtain nibble data, and the obtained data can be temporarily stored in an internal register. The counter here is reusable, saving hardware resources. Each data obtained by decoding is sent to a data checking circuit and an external system provided with a receiving host.
As shown in fig. 4, as a specific embodiment, the data verification circuit includes:
and the serial data level detection logic is used for detecting whether the duration time of the high level and the low level of the filtered SENT serial data is abnormal or not, and obtaining a detection result.
If the detection result is negative, the filtered SENT serial data is characterized to have no error.
If the detection result is yes, representing that the filtered SENT serial data has errors, generating a first error reporting signal, and transmitting the first error reporting signal to an error state register.
The state nibble data extraction logic is used for generating channel information according to the SENT decoding data and respectively transmitting the channel information to the cyclic redundancy check calculation module and the cyclic redundancy check result comparison module; the channel message includes fast channel information and slow channel information.
The cyclic redundancy check calculation module is used for calculating according to the channel information to obtain a first calculation result, and transmitting the first calculation result to the cyclic redundancy check result comparison module.
And the cyclic redundancy check result comparison module is used for comparing whether the first calculation result is consistent with the slow channel message or not to obtain a comparison result.
If the comparison result is yes, the SENT decoding data is characterized to have no error.
If the comparison result is negative, representing that the SENT decoding data has errors, generating a second error reporting signal, and transmitting the second error reporting signal to an error state register.
The error status register is used for storing the second error reporting signal and the first error reporting result as error monitoring information and transmitting the error monitoring information to an external system provided with a receiving host.
In a specific application, the serial data level detection logic directly detects the high-low level duration of the filtered SENT serial data, if the level duration is abnormal, the error is reported, the abnormality includes that the low level duration is inconsistent with the setting, and the high level duration is not in a normal range (the upper limit and the lower limit of the high level length of the half byte are set according to the frame structure).
For SENT decoding data verification, firstly, the decoded state nibble data is extracted by the state nibble data extraction logic to be a complete slow channel message, the slow channel message comprises a cyclic redundancy check value and slow channel data to be verified, a cyclic redundancy check calculation module calculates after the extraction is completed, a calculated result is compared with the cyclic redundancy check value obtained by decoding through a cyclic redundancy check result comparison module, and if the calculated result is inconsistent, the state nibble data is considered to be wrong. The send fast channel message also performs cyclic redundancy check detection, the data nibbles of each frame are calculated by the cyclic redundancy check calculation module, the result is compared with the cyclic redundancy check nibble 304 in fig. 3, and if the result is inconsistent, the data nibbles of the frame are considered to be wrong. Finally, all error information is temporarily stored in an internal error state register for being read by an external circuit. Therefore, the external system can determine how to process according to the error information obtained at present in time, if the SENT protocol decoding detection circuit is integrated in the sending chip, the error can be identified at the first time and combined with other processing modules to process the error without waiting for the judgment of an external host, and the efficiency of data transmission and the safety of the chip are effectively improved.
As a specific embodiment, the slow channel information includes a cyclic redundancy check value and slow channel data to be checked.
As a specific embodiment, the fast channel information includes a cyclic redundancy check value and fast channel data to be checked.
As a specific example, anomalies include a low-level duration of the filtered SENT serial data not coinciding with a low-level duration threshold and a high-level duration of the filtered SENT serial data not being within a high-level duration normal threshold.
The invention can be integrated in the sending chip as a sub-module to give the sending chip the capability of timely acquiring error information, can be combined with the assistance of other modules, greatly improves the safety of the sending chip, and the decoding function not only supports data self-checking, but also can enable the chip to have the function of bidirectional communication, and can be connected with a SENT protocol decoding detection circuit through GPIO (general purpose input/output) to give the chip the function of realizing SENT bidirectional communication if necessary. The data checking circuit greatly improves the coverage of data error detection through various detection schemes including CRC check judgment, serial input level judgment and the like, is more reliable compared with single loop-back detection, and the obtained different error information is also beneficial to flexible processing of the chip. Meanwhile, the invention can be integrated in the host computer at the receiving end to serve as a first verification threshold, so that the host computer can be allowed to carry out decoding detection again without carrying out decoding detection, the dependence on verification tools and software is reduced, the data can be decoded before entering the receiving host computer, the limitation that the data can only depend on the receiving host computer to carry out decoding detection is avoided, and the decoding detection is carried out on the data through a SENT protocol decoding detection circuit before entering the receiving host computer, so that the operation complexity of the receiving host computer is reduced. The circuit designed according to the invention can be integrated as a sub-module in a transmitting chip to realize real-time data self-checking. Meanwhile, the circuit designed by the invention can be integrated into the interface chip of the receiving host as an independent module, can replace the host to decode information and detect correctness, is beneficial to reducing the complexity of the operation of the host and improves the security level.
The invention has two application modes, namely, the invention is integrated into a SENT sending chip or a related interface chip of a receiving host to realize the data decoding and checking function.
If integrated into a transmitting chip, a circuit engineer can use the circuit designed according to the invention as a sub-module of the transmitting module, input SENT configuration information, a system clock and external SENT serial data in the transmitting module into a SENT protocol decoding detection circuit, and can also add control signals such as check enabling and the like according to the requirement. After that, the send protocol decoding detection circuit will detect the data by itself (if enabled) and output the decoded data (if only the detection function is needed, the data output can be internally masked). The SENT protocol decoding detection circuit requires additional error state read logic to determine how to handle different errors, and whether an interrupt needs to be generated. The SENT input end externally connected with the SENT protocol decoding detection circuit can be directly connected with the output of the sending module, can also be connected with a SENT data interface on the top layer of the sending chip to form loop back, and can also select whether the input end loops back data or SENT data fed by external IO in a mux mode according to the requirement.
If the interface chip is integrated to the receiving host, the circuit engineer can directly connect the circuit designed according to the invention as a digital peripheral module to IO input, the SENT protocol decoding detection circuit also needs to determine the frame structure information of the current SENT input, so the frame structure information can be input into the module by setting SFR, the decoded data can be directly stored into memories such as FIFO or RAM for reading, and the error state value can also be read out by a register.
For convenience in use, the flag bits of internal decoding completion, error detection and the like can be used as a module to output signals for generating interrupt and the like for the chip to judge reading or processing time.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (8)
1. A send protocol decoding detection circuit, wherein the send protocol decoding detection circuit is integrated in an interface chip or a transmitting chip of a receiving host, the send protocol decoding detection circuit comprising:
a data decoding circuit for:
generating SENT decoding data according to SENT frame format information and the filtered SENT serial data based on the SENT decoding clock and the start signal;
transmitting the SENT decoding data to a data checking circuit and an external system provided with a receiving host;
a data verification circuit for:
generating error monitoring information according to the SENT decoding data and the filtered SENT serial data based on the SENT frame format information, the SENT decoding clock and the start signal;
and transmitting the error detection information to an external system provided with a receiving host.
2. The send protocol decoding detection circuit of claim 1, further comprising:
a data synchronization and filtering circuit for:
carrying out synchronous processing on the SENT serial data to obtain synchronous SENT serial data;
filtering the synchronized SENT serial data to obtain filtered SENT serial data;
and transmitting the filtered SENT serial data to the data decoding circuit and the data checking circuit.
3. The send protocol decoding detection circuit of claim 2, further comprising:
start signal generation logic to:
generating the start signal according to the filtered SENT serial data;
transmitting the start signal to the data decoding circuit and the data verification circuit.
4. The send protocol decoding detection circuit of claim 1, wherein the data decoding circuit specifically comprises:
the counter is used for decoding the filtered SENT serial data based on the SENT decoding clock and the starting signal to obtain decoded data; the decoding data comprises a status nibble, a data nibble and a cyclic redundancy check nibble;
frame structure judgment logic for determining subsequent pulses according to the synchronization pulse and the SENT frame format information; the synchronous pulse is obtained by identification according to the high level pulse length of the detected decoding data;
count value-data conversion logic for generating SENT decoded data from the decoded data and subsequent pulses;
and the internal register is used for registering the SENT decoding data and transmitting the SENT decoding data to the data checking circuit and an external system provided with a receiving host.
5. The send protocol decoding detection circuit of claim 1, wherein the data verification circuit comprises:
the serial data level detection logic is used for detecting whether the duration time of the high level and the low level of the filtered SENT serial data is abnormal or not, and obtaining a detection result;
if the detection result is negative, the filtered SENT serial data is characterized to have no error;
if the detection result is yes, representing that the filtered SENT serial data has errors, generating a first error reporting signal, and transmitting the first error reporting signal to an error state register;
the state nibble data extraction logic is used for generating channel information according to the SENT decoding data and respectively transmitting the channel information to the cyclic redundancy check calculation module and the cyclic redundancy check result comparison module; the channel message comprises fast channel information and slow channel information;
the cyclic redundancy check calculation module is used for calculating according to the channel information to obtain a first calculation result, and transmitting the first calculation result to the cyclic redundancy check result comparison module;
the cyclic redundancy check result comparison module is used for comparing whether the first calculation result is consistent with the slow channel message or not to obtain a comparison result;
if the comparison result is yes, representing that the SENT decoding data has no error;
if the comparison result is negative, representing that the SENT decoding data has errors, generating a second error reporting signal, and transmitting the second error reporting signal to the error state register;
the error status register is used for storing the second error reporting signal and the first error reporting result as the error monitoring information and transmitting the error monitoring information to an external system provided with a receiving host.
6. The send protocol decoding detection circuit of claim 5, wherein the slow channel information comprises a cyclic redundancy check value and slow channel data to be checked.
7. The send protocol decoding detection circuit of claim 5, wherein the fast channel information comprises a cyclic redundancy check value and fast channel data to be checked.
8. The send protocol decode detection circuit of claim 5, wherein the anomaly comprises a low-level duration of the filtered send serial data not coinciding with a low-level duration threshold and a high-level duration of the filtered send serial data not being within a high-level duration normal threshold.
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| CN202310971279.7A CN116886779A (en) | 2023-08-03 | 2023-08-03 | SENT protocol decoding detection circuit |
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