CN116886229A - Bus clock synchronization method and device - Google Patents
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Abstract
A bus clock synchronization method and device includes: taking a local clock signal of a master node as a clock source of a network topological structure, and carrying out time service on each level of nodes of the network topological structure according to the local clock signal of the previous level of nodes; calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations; after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet. The embodiment of the application can eliminate clock frequency difference and transmission delay among different nodes, synchronize clocks of a plurality of nodes in the networking, ensure consistency and reliability of communication and improve the utilization rate of data transmission bandwidth.
Description
Technical Field
The present disclosure relates to communication technology, and more particularly, to a method and apparatus for synchronizing bus clocks.
Background
In automation and manufacturing technology, serial buses are used more and more frequently, which, when applied in the field of aerospace, require high bandwidth, high certainty and high reliability of data transmission,
however, some bus protocols have improved certainty and reliability, but do not solve the problem of clock synchronization of multiple nodes in the network, which affects consistency and reliability of communication, and further limits the utilization of data transmission bandwidth.
Disclosure of Invention
The application provides a bus clock synchronization method and a bus clock synchronization device, which can synchronize clocks of a plurality of nodes in a network, ensure consistency and reliability of communication and improve the utilization rate of data transmission bandwidth.
In one aspect, the present application provides a bus clock synchronization method applied to a network topology structure in which a plurality of nodes are connected by a bus, where the plurality of nodes include: a master node and a plurality of child nodes, the method comprising:
taking a local clock signal of a master node as a clock source of the network topology structure, and carrying out time service on each stage of nodes of the network topology structure according to the local clock signal of the previous stage of nodes;
calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations;
after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet.
In another aspect, the present application provides a bus clock synchronizing device, including: a memory and a processor, the memory for storing an executable program;
the processor is used for reading and executing the executable program to realize the bus clock synchronization method.
Compared with the related art, the method comprises the steps that the local clock signal of the master node is used as a clock source of the network topology structure, and each stage of node of the network topology structure is subjected to time service according to the local clock signal of the previous stage of node; calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations; after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet. Clock frequency difference and transmission delay between different nodes can be eliminated, so that clocks of a plurality of nodes in the network are synchronized, the consistency and reliability of communication are ensured, and the utilization rate of data transmission bandwidth is greatly improved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.
Fig. 1 is a schematic flow chart of a bus clock synchronization method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a 1394 bus topology according to an embodiment of the present application;
FIG. 3 is a schematic diagram of data skew time of each node in a 1394 bus according to an embodiment of the present application;
fig. 4 is a schematic diagram of a clock topology structure corresponding to a 1394 bus topology structure according to an embodiment of the present application;
fig. 5 is a schematic diagram of transmission delay in a 1394 bus according to an embodiment of the present application.
Detailed Description
The present application has been described in terms of several embodiments, but the description is illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present application may also be combined with any conventional features or elements to form a unique inventive arrangement as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. It is therefore to be understood that any of the features shown and/or discussed in the present application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
The embodiment of the application provides a bus clock synchronization method which is applied to a network topology structure for connecting a plurality of nodes by buses, wherein the nodes comprise: a master node and a plurality of child nodes, as shown in fig. 1, the method comprising:
step 101, taking a local clock signal of a master node as a clock source of the network topology structure, and carrying out time service on each level of nodes of the network topology structure according to the local clock signal of the previous level of nodes;
step 102, calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations;
step 103, after the master node sends out the STOF packet, each child node performs data transmission according to the preset data transmission offset and the corresponding transmission delay of the received STOF packet.
The bus may be, for example, a 1394 bus. When the bus is a 1394 bus, the master Node refers to a Control Computer (CC) Node, and the child Node refers to a Remote Node (RN) Node. The 1394 bus topology may include a CC node and a plurality of RN nodes as shown in fig. 2.
IEEE 1394 is a high-speed serial bus, and the institute of electrical and electronics engineers (Institute of Electrical and Electronics Engineers, IEEE) formally promulgated the first IEEE 1394 bus standard in 1995. The standard defines data transmission protocols, connection systems, etc. and has the advantage of enabling higher performance to be achieved at lower cost, and later the institute of automotive engineers (Society of Automotive Engineers, SAE) has constrained and defined portions of the IEEE 1394 bus standard to begin its application in the aerospace field. The aerospace field requires high bandwidth, high certainty and high reliability of data transmission, and although the SAE AS5643 protocol is proposed to improve certainty and reliability, the problem of clock synchronization of a plurality of nodes in a network is not solved, so that consistency and reliability of communication are affected, and further bandwidth utilization rate of transmitted data is limited.
Each node in the 1394 bus has a time window for transmitting data, which is uniformly controlled by the CC node, the CC node periodically transmits a StarT Of Frame (stop) packet, the period time is set, each RN node can receive the stop packet, the RN starts to count after receiving the stop packet, and starts to transmit data after reaching the offset time for transmitting data, as shown in fig. 3. As can be seen from fig. 2, the times when the STOF packets sent by the CC nodes reach each RN node are inconsistent, so there is a transmission delay, and the clocks between each node also have a frequency difference, which results in a larger fault-tolerant space for the timing, and two factors of the clock frequency difference and the transmission delay limit the effective transmission bandwidth of the 1394 bus.
According to the bus clock synchronization method provided by the embodiment of the application, the local clock signal of the master node is used as the clock source of the network topology structure, and each stage of node of the network topology structure is subjected to time service according to the local clock signal of the previous stage of node; calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations; after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet. Clock frequency difference and transmission delay between different nodes can be eliminated, so that clocks of a plurality of nodes in the network are synchronized, the consistency and reliability of communication are ensured, and the utilization rate of data transmission bandwidth is greatly improved.
In an exemplary embodiment, a phase-locked loop is disposed in each sub-node, and the step of timing the sub-node according to the local clock signal of the previous node includes:
firstly, receiving a clock synchronization signal from a source node; the source node is a superior node connected with the current node, the source node clock synchronous signal is a signal with a frequency which is obtained based on a local clock signal of the source node and is a target frequency, and the frequency of the local clock signal of the source node is a preset frequency;
secondly, acquiring a clock synchronization signal of the source node at the preset frequency by using a phase-locked loop arranged in the current node;
and thirdly, adjusting the frequency of the acquired clock synchronous signal to a preset frequency, and taking the clock synchronous signal subjected to frequency adjustment as the local clock signal of the current node.
In an exemplary embodiment, after the clock synchronization signal subjected to the frequency adjustment process is used as the local clock signal of the current node, the method further includes:
and acquiring the local clock signal of the current node with a target frequency, taking the acquired local clock signal as a clock synchronous signal of the current node, and transmitting the clock synchronous signal of the current node to a next-stage node connected with the current node.
For example, fig. 4 is a schematic diagram of a clock topology corresponding to fig. 2, and as shown in fig. 4, a reference CM is a master clock, a reference CS is a slave clock, CC nodes are used as clock sources of the entire network topology, each RN node is a slave clock, and is also a master clock of a next-stage RN, and is synchronized downward layer by layer with CC nodes as sources.
In an illustrative example, the preset frequency is N times the target frequency; wherein N is an integer greater than 1.
Illustratively, integer multiples may make the frequency sampling process easier. The specific value of N can be 5, so that the cost caused by the frequency sampling process is considered, and the accuracy of clock synchronization is also considered. When n=5, each node uses a reference clock of 125M as a local clock signal, transmits a clock synchronization signal of 25M, and the slave receives the clock synchronization signal of 25M through the phase-locked loop and multiplies the frequency again, thereby synchronizing with the master.
In an exemplary embodiment, the calculating the transmission delay between all node pairs of the network topology using clock synchronization packets includes:
from top to bottom of the network topology, each node in each level of nodes is used as a current node, and the following operations are executed:
firstly, respectively acquiring first time when a current node sends a clock synchronization data packet, second time when an object node receives the clock synchronization data packet from the current node, third time when the object node sends a clock synchronization data reply packet to the current node, and fourth time when the current node receives the clock synchronization data reply packet from the object node; the object node is a next-stage node connected with the current node;
and secondly, calculating the transmission delay between the node pair formed by the current node and the object node according to the first time, the second time, the third time and the fourth time.
In an exemplary embodiment, the calculating a transmission delay between the current node and the node pair formed by the object node according to the first time, the second time, the third time, and the fourth time includes:
the transmission delay between the node pair formed by the current node and the object node is obtained through the following calculation expression:
transmission delay= (second time-first time + fourth time-third time)/2.
And after the clocks of the nodes are synchronized, measuring the propagation delay of the path. Fig. 5 is a schematic diagram of a transmission delay provided by an embodiment of the present application, as shown in fig. 5, assuming that a time difference t_offset between a master clock of a current node and a slave clock of an object node is equal to a path transmission delay D between the current node and the object node, then:
t1+D＝t2+T_Offset；
t3+D＝t4-T_Offset；
D＝(t2-t1+t4-t3)/2
t1 is a first time when a current node sends a clock synchronization data packet, and t2 is a second time when an object node receives the clock synchronization data packet from the current node; t3 is the third time when the target node sends the clock synchronization data reply packet to the current node, and t4 is the fourth time when the current node receives the clock synchronization data reply packet from the target node.
From the above formula, it can be known that the time difference t_offset between two clocks is negligible, the time synchronization is not affected, only the transmission delay D is concerned, the delay D is recorded by the node where each slave clock is located, and the delay D is compensated in the transmission data Offset timing after the stop is received.
In an exemplary embodiment, the obtaining the transmission delay of the stop packet received by all the child nodes according to the transmission delay between all the node pairs includes:
starting from a first level of sub-node in the network topology structure to step downwards, respectively taking each sub-node in each level of sub-node as a current sub-node, and executing the following operations:
firstly, all intermediate sub-nodes sequentially passing from the main node to the current sub-node are obtained, and an intermediate sub-node set is obtained;
secondly, taking the main node as a source node, taking the first intermediate child node in the intermediate child node set as a target node, and performing the following time delay acquisition operation: acquiring transmission delay between node pairs formed by the source node and the target node from the transmission delay between all node pairs, taking the target node as a new source node, taking the next intermediate child node in the intermediate node set as a new target node, continuing to execute the delay acquisition operation until the new target node is the last intermediate child node in the intermediate child node set, and acquiring the transmission delay from the new target node to the current node from the transmission delay between all node pairs;
and finally, acquiring the transmission delay of the STOF packet received by the current child node according to all the acquired transmission delays.
In an exemplary embodiment, each of the child nodes performs data transmission according to its preset data transmission offset and its corresponding transmission delay of the received STOF packet, including:
each child node determines the actual data transmission offset according to the preset data transmission offset and the corresponding transmission delay of the received STOF packet, and performs data transmission according to the determined actual data transmission offset.
In an exemplary embodiment, each of the child nodes determines an actual data transmission offset according to a preset data transmission offset and a corresponding transmission delay of the received STOF packet, and includes:
each child node determines the actual offset of data transmission based on the calculation expression by:
actual offset = self-preset data transmission offset-transmission delay of self-corresponding received STOF packet.
The embodiment of the application also provides a bus clock synchronization method, which is illustrated by the network topology structure of fig. 2, and comprises the following steps:
firstly, clock frequency offset elimination is carried out, the synchronous topology is as shown in fig. 4, the RN1 and the RN2 acquire clock signals from the CC nodes to carry out synchronization, then the clock signals are used as a main clock to carry out time service on the next stage, the RN1 is used for carrying out time service on the RN3, the RN2 is used for carrying out time service on the RN4 and the RN5, and finally the RN3 is used for carrying out time service on the RN6, so that the clock synchronization of the whole topology is completed.
And secondly, carrying out transmission delay solution, wherein the STOF period is one second. The RN node sequentially transmits data according to RN 1-RN 6, and the transmission time is 20ms. After path transmission delay measurement, the transmission delays of CC to RN1 and RN2 are respectively 1ms and 2ms, the transmission delay of RN1 to RN3 is 1ms, the transmission delay of RN3 to RN6 is 1ms, the transmission delay of RN2 to RN4 is 2ms, and the transmission delay of RN2 to RN5 is 1ms; starting from the STOF emission time point, the time offsets for RN1 to RN6 to receive STOF are 1ms, 2ms, 4ms, 3ms, and 3ms, respectively. Assuming that the RN1 sets the offset to 5ms, after synchronization, the RN1 starts to transmit data with a timing offset of 4 ms; similarly, the offset is set to 25ms by the RN2, and the RN2 starts to transmit data with a timing offset of 23ms after synchronization.
The embodiment of the application also provides a bus clock synchronization device, which comprises: a memory and a processor, the memory for storing an executable program;
the processor is configured to read and execute the executable program to implement the bus clock synchronization method described in any of the foregoing embodiments.
The bus clock synchronization method device provided by the embodiment of the application takes the local clock signal of the master node as the clock source of the network topology structure, and time service is carried out on each stage of nodes of the network topology structure according to the local clock signal of the previous stage of nodes; calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations; after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet. Clock frequency difference and transmission delay between different nodes can be eliminated, so that clocks of a plurality of nodes in the network are synchronized, the consistency and reliability of communication are ensured, and the utilization rate of data transmission bandwidth is greatly improved.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (10)
1. A bus clock synchronization method, applied to a network topology structure in which a plurality of nodes are connected by a bus, the plurality of nodes comprising: a master node and a plurality of child nodes, the method comprising:
taking a local clock signal of a master node as a clock source of the network topology structure, and carrying out time service on each stage of nodes of the network topology structure according to the local clock signal of the previous stage of nodes;
calculating the transmission delay between all node pairs of the network topology structure by using the clock synchronous data packet, and acquiring the transmission delay of the STOF packet received by all sub-nodes according to the transmission delay between all node pairs; the node is formed by two nodes with upper and lower connection relations;
after the master node sends out the STOF packet, each child node sends out data according to the preset data sending offset and the corresponding transmission delay of the received STOF packet.
2. The method according to claim 1, wherein a phase-locked loop is provided in each child node, and the time service is performed according to the local clock signal of the previous node, including:
receiving a clock synchronization signal from a source node; the source node is a superior node connected with the current node, the source node clock synchronous signal is a signal with a frequency which is obtained based on a local clock signal of the source node and is a target frequency, and the frequency of the local clock signal of the source node is a preset frequency;
acquiring a clock synchronization signal of the source node at the preset frequency by using a phase-locked loop arranged in the current node;
and adjusting the frequency of the acquired clock synchronous signal to a preset frequency, and taking the clock synchronous signal subjected to frequency adjustment processing as a local clock signal of the current node.
3. The method according to claim 2, wherein after using the clock synchronization signal subjected to the frequency adjustment process as the local clock signal of the current node, further comprising:
and acquiring the local clock signal of the current node with a target frequency, taking the acquired local clock signal as a clock synchronous signal of the current node, and transmitting the clock synchronous signal of the current node to a next-stage node connected with the current node.
4. A method according to claim 2 or 3, wherein the preset frequency is N times the target frequency; wherein N is an integer greater than 1.
5. The method of claim 1, wherein said calculating transmission delays between all node pairs of the network topology using clock synchronization packets comprises:
from top to bottom of the network topology, each node in each level of nodes is used as a current node, and the following operations are executed:
respectively obtaining first time when a current node sends a clock synchronization data packet, second time when an object node receives the clock synchronization data packet from the current node, third time when the object node sends a clock synchronization data reply packet to the current node, and fourth time when the current node receives the clock synchronization data reply packet from the object node; the object node is a next-stage node connected with the current node;
and calculating the transmission delay between the node pair formed by the current node and the object node according to the first time, the second time, the third time and the fourth time.
6. The method of claim 5, wherein said calculating a transmission delay between a node pair formed by the current node and the object node based on the first time, the second time, the third time, and the fourth time comprises:
the transmission delay between the node pair formed by the current node and the object node is obtained through the following calculation expression:
transmission delay= (second time-first time + fourth time-third time)/2.
7. The method of claim 5, wherein the obtaining the transmission delay of the stop packet received by all the child nodes according to the transmission delay between all the node pairs comprises:
starting from a first level of sub-node in the network topology structure to step downwards, respectively taking each sub-node in each level of sub-node as a current sub-node, and executing the following operations:
obtaining all intermediate sub-nodes sequentially passing from the main node to the current sub-node to obtain an intermediate sub-node set;
taking the main node as a source node, taking the first intermediate child node in the intermediate child node set as a target node, and performing the following time delay acquisition operation: acquiring transmission delay between node pairs formed by the source node and the target node from the transmission delay between all node pairs, taking the target node as a new source node, taking the next intermediate child node in the intermediate node set as a new target node, continuing to execute the delay acquisition operation until the new target node is the last intermediate child node in the intermediate child node set, and acquiring the transmission delay from the new target node to the current node from the transmission delay between all node pairs;
and acquiring the transmission delay of the STOF packet received by the current child node according to all the acquired transmission delays.
8. The method of claim 1, wherein each child node performs data transmission according to its own preset data transmission offset and its own corresponding transmission delay of the received STOF packet, comprising:
each child node determines the actual data transmission offset according to the preset data transmission offset and the corresponding transmission delay of the received STOF packet, and performs data transmission according to the determined actual data transmission offset.
9. The method of claim 8, wherein each of the child nodes determines the actual data transmission offset according to the preset data transmission offset and the corresponding transmission delay of the received STOF packet, comprising:
each child node determines the actual offset of data transmission based on the calculation expression by:
actual offset = self-preset data transmission offset-transmission delay of self-corresponding received STOF packet.
10. A bus clock synchronization device, characterized by a memory and a processor, the memory for storing an executable program;
the processor is configured to read and execute the executable program to implement the bus clock synchronization method according to any one of claims 1-9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117478561A (en) * | 2023-11-08 | 2024-01-30 | 上海勃傲自动化系统有限公司 | Ethernet industrial bus time delay analysis method and system |
| CN118138186A (en) * | 2024-05-08 | 2024-06-04 | 山东大学 | Slave node synchronizing method and system for mixed topology industrial bus system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117478561A (en) * | 2023-11-08 | 2024-01-30 | 上海勃傲自动化系统有限公司 | Ethernet industrial bus time delay analysis method and system |
| CN117478561B (en) * | 2023-11-08 | 2024-05-14 | 上海勃傲自动化系统有限公司 | Ethernet industrial bus time delay analysis method and system |
| CN118138186A (en) * | 2024-05-08 | 2024-06-04 | 山东大学 | Slave node synchronizing method and system for mixed topology industrial bus system |
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