CN116863854A

CN116863854A - Display panel and display device

Info

Publication number: CN116863854A
Application number: CN202310908758.4A
Authority: CN
Inventors: 高娅娜
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2023-07-24
Filing date: 2023-07-24
Publication date: 2023-10-10

Abstract

The invention relates to the technical field of display and discloses a display panel and a display device, wherein the display panel comprises a first display mode, and the first display mode displays a first picture; the display panel further comprises a second display mode, the second display mode displays a second picture, the second display mode comprises a first display stage and a second display stage, the refresh frequency of the display panel is F1 in the first display stage, and the refresh frequency of the display panel is F2 in the second display stage, wherein F1 is more than F2; the display panel is switched from the first display mode to the second display mode through the first display stage. The invention improves the technical problem of abnormal display image frames in the prior art.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.

Background

The electronic product can adopt different refresh rates for display in different application scenes, for example, in a video mode or a game mode, a driving mode with higher refresh rate can be adopted to drive and display dynamic pictures so as to ensure the fluency of the display pictures. For example, when some slow lens images or static images are displayed, a driving mode with a lower refresh rate can be used to drive the display of the slow lens images or static images so as to reduce power consumption.

However, the conventional display panel has a problem of abnormal display.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device to improve the technical problem of abnormal display of an image in the prior art.

The invention provides a display panel, which comprises a first display mode, wherein the first display mode displays a first picture; the display panel further comprises a second display mode, the second display mode displays a second picture, the second display mode comprises a first display stage and a second display stage, the refresh frequency of the display panel is F1 in the first display stage, and the refresh frequency of the display panel is F2 in the second display stage, wherein F1 is more than F2; the display panel is switched from the first display mode to the second display mode through the first display stage.

The invention provides a display panel, which comprises a pixel circuit and a light-emitting element electrically connected with the pixel circuit, wherein the pixel circuit comprises a driving transistor, a data writing module and a bias compensation module, the first end of the data writing module is connected with a data voltage end, the second end of the data writing module is electrically connected with a first pole of the driving transistor, the first end of the bias compensation module is connected with a bias compensation voltage end, and the second end of the bias compensation module is electrically connected with the first pole of the driving transistor; in the time of displaying a frame of display picture of the display panel, the working process of the pixel circuit comprises a reset phase and a data writing phase; in the data writing stage, the data writing module is conducted, and the data voltage end writes a data voltage signal into a first pole of the driving transistor; in a reset stage, the bias compensation module is conducted, and a bias compensation voltage end writes a bias compensation voltage signal into a first pole of the driving transistor; the working process of the pixel circuit further comprises a second bias phase in which the bias compensation module is conducted, and the bias compensation voltage end writes a bias compensation voltage signal into the first electrode of the driving transistor; the display panel comprises a first display mode, wherein the first display mode displays a first picture, and when the first display mode is adopted, the refresh frequency of the display panel is F3; the display panel also comprises a second display mode, the second display mode displays a second picture, and when the second display mode is adopted, the refresh frequency of the display panel is F4, and F3 is more than F4; when the display panel is switched from the first display mode to the second display mode, a reset stage is arranged before a data writing stage in the first display mode; a reset phase is arranged before the data writing phase in the first frame display picture time of the second display mode; and a reset phase is arranged before the data writing phase in the second frame display picture time of the second display mode, and a second bias phase is arranged between the data writing phase and the holding phase.

Based on the same thought, the invention also provides a display device which comprises the display panel provided by the invention.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

the display panel comprises a first display mode and a second display mode, wherein the display panel displays a first picture in the first display mode, and displays a second picture in the second display mode. The second display mode comprises a first display stage and a second display stage, wherein the refresh frequency of the display panel is F1 in the first display stage, and the refresh frequency of the display panel is F2 and F1 is more than F2 in the second display stage. I.e. the refresh frequency of the display panel is lower in the second display phase. When the display panel is switched from the first display mode to the second display stage, the first display stage is inserted between the first display mode and the second display stage, namely, the display panel is switched from the first display mode to the second display stage through the first display stage. When the refresh frequency of the display panel is higher in the first display mode, a first display stage is inserted between the first display mode and the second display stage, and when the refresh frequency of the display panel is higher in the first display stage, the first display stage can play a role in transition, so that the display panel is prevented from being directly switched from the high-frequency data refresh rate to the low-frequency data refresh rate, the screen flickering phenomenon is effectively improved, and the visual experience is improved. When the refresh frequency of the display panel is lower in the first display mode, a first display stage is inserted between the first display mode and the second display stage, and when the refresh frequency of the display panel is higher in the first display stage, the first display stage can play a role in transition, so that the display panel is prevented from directly switching high-order pictures and low-order pictures at a low refresh rate, the screen smear phenomenon is effectively improved, and the visual experience is improved.

Of course, it is not necessary for any one product to practice the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a driving method of a display panel according to the present invention;

FIG. 2 is a partial cross-sectional view of a display panel according to the present invention;

FIG. 3 is a schematic circuit diagram of a pixel circuit according to the present invention;

FIG. 4 is a timing diagram of a pixel circuit according to the present invention;

FIG. 5 is another driving timing diagram of a pixel circuit according to the present invention;

FIG. 6 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 7 is a further drive timing diagram of a pixel circuit according to the present invention;

FIG. 8 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 9 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 10 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 11 is a schematic circuit diagram of another pixel circuit according to the present invention;

FIG. 12 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 13 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 14 is a further drive timing diagram of a pixel circuit provided by the present invention;

fig. 15 is a further driving timing diagram of the pixel circuit provided by the present invention;

fig. 16 is a schematic plan view of a display device according to the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Based on the description of the background technology of the present application, in the inventive creation process of the present application, the inventor found that when a display panel adopting an organic self-luminous technology is directly switched from a high refresh rate to a low refresh rate, there is a problem that the brightness of a first frame with a low refresh rate is abnormal, that is, a screen flicker phenomenon occurs, which affects visual experience, and in particular: when the display panel is switched from the driving mode with the high frequency data refresh rate to the driving mode with the low frequency data refresh rate, the number of the holding frames is zero or the number of the holding frames is small in one data refresh period because the display panel is driven and displayed by adopting the driving mode with the high frequency data refresh rate, and the grid electrode of the driving transistor holds the input of the data signal, that is, the grid electrode potential of the driving transistor is refreshed more frequently, so that the driving transistor is biased mainly based on the data voltage signal. When the display panel adopts a driving mode of low-frequency data refresh rate to drive display, the number of the holding frames relatively becomes more in one data refresh period, and the grid potential of the driving transistor is kept unchanged for a long time in one data refresh period, so that the driving transistor is mainly biased based on a bias compensation voltage signal. When the display panel is switched from the driving mode with the high frequency data refresh rate to the driving mode with the low frequency data refresh rate, the problem of abnormal brightness occurs, that is, a screen flickering phenomenon occurs, which affects the visual experience.

In the inventive creation process of the present application, the inventor also found that when the display panel adopting the organic self-luminous technology directly performs high-low order picture switching at a low refresh rate, there is a problem that the brightness of the first frame or the first few frames of the switching picture is abnormal, that is, a screen smear phenomenon occurs, which affects the visual experience, and in particular: when the display panel is in low refresh rate, the gate potential of the driving transistor is kept unchanged for a long time, so that the device characteristic of the driving transistor is offset, and when the display panel is in low refresh rate and directly performs high-low order picture switching, the problem of abnormal brightness can occur due to the change of the device characteristic of the driving transistor, that is, a screen smear phenomenon can occur, and visual experience is affected. Specifically, when the low-gray-scale picture is switched to the high-gray-scale picture, the first frame or the first few frames of the high-gray-scale picture have low brightness; when the high gray scale picture is switched to the low gray scale picture, the first frame or the first few frames of the low gray scale picture have higher brightness.

Based on the above study, the application provides a display panel and a display device, which effectively improve the display effect. The display panel with the technical effects provided by the application is described in detail as follows:

Fig. 1 is a schematic diagram of a driving manner of a display panel according to the present invention, referring to fig. 1, the present embodiment provides a display panel, which includes a first display mode T1, where the first display mode T1 displays a first screen;

the display panel further comprises a second display mode T2, the second display mode T2 displays a second picture, the second display mode T2 comprises a first display stage T21 and a second display stage T22, the refresh frequency of the display panel is F1 when in the first display stage T21, and the refresh frequency of the display panel is F2 when in the second display stage T22, and F1 is more than F2;

the display panel is switched from the first display mode T1 to the second display stage T22 through the first display stage T21.

Specifically, the display panel includes a first display mode T1 and a second display mode T2, where the display panel displays a first screen in the first display mode T1 and displays a second screen in the second display mode T2. The second display mode T2 includes a first display stage T21 and a second display stage T22, where the refresh frequency of the display panel is F1 during the first display stage T21, and the refresh frequency of the display panel is F2 during the second display stage T22, where F1 > F2. I.e. the refresh frequency of the display panel is lower in the second display stage T22. When the display panel is switched from the first display mode T1 to the second display stage T22, the first display stage T21 is interposed between the first display mode T1 and the second display stage T22, i.e., the display panel is switched from the first display mode T1 to the second display stage T22 through the first display stage T21.

When the refresh frequency of the display panel is higher in the first display mode T1, a first display stage T21 is inserted between the first display mode T1 and the second display stage T22, and when the display panel is in the first display stage T21, the refresh frequency of the display panel is higher, the first display stage T21 can play a role in transition, the display panel is prevented from being directly switched from the high-frequency data refresh rate to the low-frequency data refresh rate, the screen flickering phenomenon is effectively improved, and the visual experience is improved.

When the refresh frequency of the display panel is lower in the first display mode T1, a first display stage T21 is inserted between the first display mode T1 and the second display stage T22, and when the first display stage T21 is used, the refresh frequency of the display panel is higher, the first display stage T21 can play a role in transition, the display panel is prevented from being directly switched between a high-order picture and a low-order picture at a low refresh rate, the screen smear phenomenon is effectively improved, and the visual experience is improved.

It should be noted that, in this embodiment, the first display stage T21 is exemplarily shown to be inserted between the first display mode T1 and the second display stage T22, and in other embodiments of the present invention, more display stages may be inserted between the first display mode T1 and the second display stage T22, and the refresh frequency of the display panel is greater than the refresh frequency of the display panel when the second display stage T22 is gradually reduced, which is not described herein.

Fig. 2 is a partial cross-sectional view of a display panel according to the present invention, fig. 3 is a circuit schematic of a pixel circuit according to the present invention, fig. 4 is a driving timing diagram of the pixel circuit according to the present invention, and referring to fig. 2 to 4, in some alternative embodiments, the display panel includes a pixel circuit 10 and a light emitting element 20 electrically connected thereto, the pixel circuit 10 includes a driving transistor M1 and a data writing module 11, the driving transistor M1 provides a driving current for the light emitting element 20, a first end of the data writing module 11 is connected to a data voltage terminal Vdata, and a second end of the data writing module 11 is electrically connected to a first electrode of the driving transistor M1;

in the time of one frame of display picture of the display panel, the working process of the pixel circuit comprises a data writing-in stage t1 and a holding stage t2, and the holding stage t2 comprises a first bias stage t21;

in the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first pole of the driving transistor M1;

in the first bias phase t21, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1.

Specifically, the display panel includes a substrate 30, an array layer 40 and a display layer 50 disposed on one side of the substrate 30, wherein the array layer 40 includes a plurality of pixel circuits 10, and the display layer 50 includes a plurality of light emitting elements 20. Specifically, the light emitting element 20 may include an organic light emitting diode, or the light emitting element 20 may include an inorganic light emitting diode. The light emitting element 20 includes a first electrode, a light emitting layer, and a second electrode that are stacked. In one embodiment, the first electrode is an anode and the second electrode is a cathode. Of course, in other embodiments of the present invention, the display panel may further include other structures, and for example, a side of the display layer 50 away from the substrate 30 may be provided with an encapsulation layer, where the encapsulation layer is used for encapsulating and protecting the light emitting element 20. Or when the display panel also has a touch function, the display panel also comprises a touch layer. The display panel of the present embodiment includes, but is not limited to, the above-described structure, and the present embodiment is not particularly limited herein, and may be understood with reference to the structure of the display panel in the related art.

The pixel circuit 10 is electrically connected to the light emitting element 20, and the pixel circuit 10 is configured to drive the light emitting element 20 electrically connected thereto to emit light. Specifically, the pixel circuit 10 supplies a driving current to the light emitting element 20 electrically connected thereto, and the light emitting element 20 displays a certain luminance according to the magnitude of the driving current.

The pixel circuit 10 includes a driving transistor M1 and a data writing module 11, the driving transistor M1 provides a driving current for the light emitting element 20, a first terminal of the data writing module 11 is connected to the data voltage terminal Vdata, and a second terminal of the data writing module 11 is electrically connected to a first pole of the driving transistor M1. Specifically, in a frame of display time of the display panel, the working process of the pixel circuit includes a data writing stage t1 and a holding stage t2, and the holding stage t2 includes a first bias stage t21.

In the data writing stage t1, the data writing module 11 is turned on, the data voltage terminal Vdata writes the data voltage signal V1 to the first pole of the driving transistor M1, and the driving transistor M1 can form the driving current based on the data voltage signal V1.

In the first bias stage t21, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1, so that the driving transistor M1 can be biased with a high voltage, thereby avoiding the characteristic offset phenomenon of the driving transistor M1 caused by that the driving transistor M1 does not write data for a long time in the holding stage t2, so that the electrical property of the driving transistor M1 is recovered, and the driving effect of the driving module 31 is improved.

It should be noted that, in fig. 4, the driving transistor M1 is illustratively shown as a PMOS driving transistor, and in other embodiments of the present invention, the driving transistor M1 may also be an NMOS driving transistor, which is not described herein again.

Optionally, with continued reference to fig. 4 and 5, the pixel circuit further includes a first light emitting control module 12, a second light emitting control module 13, a threshold compensation module 14, a first reset module 15, and a second reset module 16.

The control end of the first light emitting control module 12 is electrically connected to the light emitting control signal end Emit, the first end of the first light emitting control module 12 is electrically connected to the first power signal end PVDD, the second end of the first light emitting control module 12 is electrically connected to the first pole of the driving transistor M1, and the first light emitting control module 12 is configured to provide the first power signal PVDD to the first pole of the driving transistor M1.

The control end of the second light-emitting control module 13 is electrically connected with the light-emitting control signal end Emit, the first end of the second light-emitting control module 13 is electrically connected with the second electrode of the driving transistor M1, the second end of the second light-emitting control module 13 is electrically connected with the anode of the light-emitting element 20, and the second light-emitting control module 13 is used for controlling the driving current generated by the driving transistor M1 to be transmitted to the light-emitting element 20.

The threshold compensation module 14 is used for compensating the threshold voltage of the driving transistor M1, the first reset module 15 is used for providing a first reset signal to the gate of the driving transistor M1, and the second reset module 16 is used for providing a second reset signal to the anode of the light emitting element 20.

The control terminal of the data writing module 11 is electrically connected to the first scan signal terminal SP. The control terminal of the threshold compensation module 14 is electrically connected to the second scan signal terminal S2, the first terminal of the threshold compensation module 14 is electrically connected to the second pole of the driving transistor M1, and the second terminal of the threshold compensation module 14 is electrically connected to the gate of the driving transistor M1. The cathode of the light emitting element 20 is electrically connected to the second power signal terminal PVEE. The control end of the first reset module 15 is electrically connected to the third scan signal end S1, the first end of the first reset module 15 is electrically connected to the reset signal end Vref, and the second end of the first reset module 15 is electrically connected to the gate of the driving transistor M1. The control terminal of the second reset module 16 is electrically connected to the first scan signal terminal SP, the first terminal of the second reset module 16 is electrically connected to the reset signal terminal Vref, and the second terminal of the second reset module 16 is electrically connected to the anode of the light emitting element 20.

It should be noted that, in the embodiment of the present invention, specific structures of the reset module, the data writing module, the threshold compensation module, and the light emitting control module are not limited in particular, and each module of the pixel circuit may be designed according to actual needs on the premise that the bias compensation function of the threshold voltage of the driving transistor can be implemented. For easy understanding, specific structures of the reset module, the data writing module, the threshold compensation module, and the light emission control module are exemplified below in the embodiments of the present invention, where each module may optionally include a thin film transistor. With continued reference to fig. 4, a circuit configuration of 7T1C for the pixel circuit in the display panel is exemplarily shown in fig. 4. Of course, in other embodiments of the present invention, the pixel circuit may have other circuit structures, and the disclosure is not described herein.

FIG. 5 is a schematic diagram of another driving timing diagram of the pixel circuit according to the present invention, referring to FIGS. 1-3 and 5, in some alternative embodiments, in the second display stage T22, in the data writing stage T1, the voltage value of the data voltage signal is V11;

in the first frame display picture time of the second display stage T22, in the first bias stage T21, the voltage value of the bias compensation voltage signal is V21;

in the second frame display time of the second display stage T22, in the first bias stage T21, the voltage value of the bias compensation voltage signal is V22;

v21 is between V11 and V22.

Specifically, the second display mode T2 includes a first display stage T21 and a second display stage T22, where the refresh frequency of the display panel is F1 during the first display stage T21, and the refresh frequency of the display panel is F2 during the second display stage T22, where F1 > F2. I.e. the refresh frequency of the display panel is lower in the second display stage T22. When the display panel is switched from the first display mode T1 to the second display stage T22, the first display stage T21 is interposed between the first display mode T1 and the second display stage T22, i.e., the display panel is switched from the first display mode T1 to the second display stage T22 through the first display stage T21.

The refresh frequency of the display panel in the second display stage T22 is smaller than that in the first display stage T21, so that the duration of holding the frame T2 in the one-frame display frame time of the second display stage T22 is longer than that of holding the frame T2 in the one-frame display frame time of the first display stage T21, that is, the duration of holding the frame T2 in the one-frame display frame time of the second display stage T22 is longer, and correspondingly, the number of the first bias stages T21 is larger in the one-frame display frame time of the second display stage T22, so that the bias effects on the driving transistor M1 in the first display stage T21 and the second display stage T22 are different, and the problem of abnormal brightness occurs when the display panel is switched from the first display stage T21 to the second display stage T22, that is, a screen flicker phenomenon occurs, and visual experience is affected.

In the second display stage T22, in the data writing stage T1, the voltage value of the data voltage signal is V11, in the second frame display frame time of the second display stage T22, in the first bias stage T21, the voltage value of the bias compensation voltage signal is V22, in the first frame display frame time of the second display stage T22, in the first bias stage T21, the voltage value of the bias compensation voltage signal is V21, and V21 is between V11 and V22, so that the bias effect on the driving transistor M1 in the first frame display frame time of the second display stage T22 is between the bias effect on the driving transistor M1 in the first display stage T21 and the bias effect on the driving transistor M1 in the second frame display frame time of the second display stage T22, that is, the first frame display frame of the second display stage T22 plays a transitional role, and the problem of abnormal brightness phenomenon occurring when the display panel is switched from the first display stage T21 to the second display stage T22 is effectively relieved, that is effectively the screen flicker is effectively improved.

Similarly, when the refresh frequency of the display panel is higher in the first display mode T1 and the refresh frequency of the display panel is greater than the refresh frequency of the display panel in the first display stage T21 in the first display mode T1, a similar transition design may be made in the first frame display of the first display stage T21, that is, the voltage value of the bias compensation voltage signal in the first bias stage T21 is between the voltage value of the data voltage signal in the first display mode T1 and the data writing stage T1 and the voltage value of the bias compensation voltage signal in the first bias stage T21 in the first frame display of the first display stage T21.

Similarly, the voltage value of the offset compensation voltage signal may be set to be gradually changed during the second frame display frame time of the second display stage T22 and during the first offset stage T21, between the voltage value of the offset compensation voltage signal during the first offset stage T21 and the voltage value of the offset compensation voltage signal during the third frame display frame time of the second display stage T22 and during the first offset stage T21, that is, during the display frame time of the second display stage T22, during the first offset stage T21, and the invention will not be described herein.

FIG. 6 is a schematic diagram of a driving timing diagram of a pixel circuit according to the present invention, referring to FIGS. 1-3 and 6, in some alternative embodiments, in a first display mode T1, a voltage value of a data voltage signal is V12 in a data writing stage T1;

in the second display mode T2, in the data writing stage T1, the voltage value of the data voltage signal is V13;

in the first frame display time of the first display stage T21, in the first offset stage T21, the voltage value of the offset compensation voltage signal T21 is V31;

in the second frame display time of the first display stage T22, in the first bias stage T21, the voltage value of the bias compensation voltage signal T21 is V32;

wherein V12 > V13, and V31 > V32.

Specifically, in the first display mode T1, the voltage value of the data voltage signal is V12 in the data writing stage T1, and in the second display mode T2, the voltage value of the data voltage signal is V13, V12 > V13 in the data writing stage T1, that is, in the first display mode T1, the display panel displays a high gray-scale screen, and in the second display mode T2, the display panel displays a low gray-scale screen.

In the prior art, when the display panel is switched from a high-gray-scale picture to a low-gray-scale picture, the brightness is higher in the first frame or the first few frames of the display of the low-gray-scale picture.

In the present application, in the first frame display period of the first display period T21, the voltage value of the offset compensation voltage signal T21 is V31 in the first offset period T21, and in the second frame display period of the first display period T22, the voltage value of the offset compensation voltage signal T21 is V32 in the first offset period T21, V31 > V32. That is, in the first frame display time of the first display stage T21, in the first offset stage T21, the voltage value of the offset compensation voltage signal T21 is higher, so that the brightness of the first frame display screen of the display panel in the first display stage T21 can be reduced, the display tailing phenomenon is effectively improved, and the visual experience is improved.

Similarly, fig. 7 is a further driving timing diagram of the pixel circuit according to the present application, and referring to fig. 1-3 and fig. 7, V12 < V13, and V31 < V32.

In the first display mode T1, the voltage value of the data voltage signal is V12 in the data writing stage T1, and in the second display mode T2, the voltage value of the data voltage signal is V13, V12 < V13 in the data writing stage T1, that is, in the first display mode T1, the display panel displays a low gray-scale screen, and in the second display mode T2, the display panel displays a high gray-scale screen.

In the prior art, when the display panel is switched from a low-gray-scale picture to a high-gray-scale picture, the brightness is lower in the first frame or the first few frames of the low-gray-scale picture.

In the application, in the first frame display picture time of the first display stage T21, the voltage value of the bias compensation voltage signal T21 is V31 in the first bias stage T21, and in the second frame display picture time of the first display stage T22, the voltage value of the bias compensation voltage signal T21 is V32 in the first bias stage T21, and V31 is less than V32. That is, in the first frame display time of the first display stage T21, in the first offset stage T21, the voltage value of the offset compensation voltage signal T21 is lower, so that the brightness of the first frame display screen of the display panel in the first display stage T21 can be improved, the display tailing phenomenon is effectively improved, and the visual experience is improved.

FIG. 8 is a timing diagram of still another driving method of the pixel circuit according to the present application, referring to FIGS. 1-3 and 8, in some alternative embodiments, in the first display mode T1, the voltage value of the data voltage signal is V12 during the data writing phase T1;

In the first frame display picture time of the first display stage T21, the duration of the first bias stage T21 is h1;

in the second frame display picture time of the first display stage T21, the duration of the first bias stage T21 is h2;

wherein V12 is more than V13, and h1 is more than h2,

In the application, in the first frame display picture time of the first display stage T21, the duration of the first offset stage T21 is h1, and in the second frame display picture time of the first display stage T21, the duration of the first offset stage T21 is h2, wherein h1 is more than h2. Namely, the duration of the first offset stage T21 is increased in the first frame display frame time of the first display stage T21, so that the brightness of the first frame display frame of the display panel in the first display stage T21 can be reduced, the display tailing phenomenon is effectively improved, and the visual experience is improved.

Similarly, fig. 9 is a further driving timing diagram of the pixel circuit according to the present application, and referring to fig. 1-3 and fig. 9, V12 < V13, and h1 < h2.

In the application, in the first frame display picture time of the first display stage T21, the duration of the first offset stage T21 is h1, and in the second frame display picture time of the first display stage T21, the duration of the first offset stage T21 is h2, wherein h1 is less than h2. Namely, in the first frame display picture time of the first display stage T21, the duration of the first offset stage T21 is reduced, so that the brightness of the first frame display picture of the display panel in the first display stage T21 can be increased, the display tailing phenomenon is effectively improved, and the visual experience is improved.

Fig. 10 is a further driving timing diagram of the pixel circuit according to the present invention, referring to fig. 1-3 and fig. 10, in some alternative embodiments, the operation of the pixel circuit 10 further includes a reset phase t3 during which the data writing module 11 is turned on and the data voltage terminal Vdata writes the data voltage signal V1 to the first pole of the driving transistor M1 during a frame of display time of the display panel;

in the first frame display period of the first display period T21, a reset period T3 is set before the data writing period T1.

Specifically, in the first frame display period of the first display period T21, the reset period T3 is set before the data writing period T1, so that the driving transistor M1 can be reset once, thereby reducing the influence of the first image on the second image in the first display period T21 in the first display mode T1, and being beneficial to improving the display tailing phenomenon when the first display mode T1 is switched to the first display period T21.

Fig. 11 is a circuit schematic of another pixel circuit provided by the present invention, fig. 12 is a further driving timing diagram of the pixel circuit provided by the present invention, and referring to fig. 2, 11 and 12, in some alternative embodiments, the display panel includes a pixel circuit 10 and a light emitting element 20 electrically connected thereto, the pixel circuit 10 includes a driving transistor M1, a data writing module 11 and a bias compensation module 17, a first end of the data writing module 11 is connected to a data voltage terminal Vdata, a second end of the data writing module 11 is electrically connected to a first pole of the driving transistor M1, a first end of the bias compensation module 17 is connected to a bias compensation voltage terminal DVH, and a second end of the bias compensation module 17 is electrically connected to a first pole of the driving transistor M1;

In a frame of display time of the display panel, the working process of the pixel circuit 10 comprises a data writing stage t1 and a holding stage t2, wherein the holding stage t2 comprises a first bias stage t21;

in the first bias phase t21, the bias compensation module 17 is turned on and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1.

Specifically, the display panel includes a pixel circuit 10 and a light emitting element 20 electrically connected thereto, the pixel circuit 10 is electrically connected to the light emitting element 20, and the pixel circuit 10 is configured to drive the light emitting element 20 electrically connected thereto to emit light. Specifically, the pixel circuit 10 supplies a driving current to the light emitting element 20 electrically connected thereto, and the light emitting element 20 displays a certain luminance according to the magnitude of the driving current.

The pixel circuit 10 includes a driving transistor M1, a data writing module 11 and a bias compensation module 17, wherein a first end of the data writing module 11 is connected to the data voltage terminal Vdata, a second end of the data writing module 11 is electrically connected to the first pole of the driving transistor M1, a first end of the bias compensation module 17 is connected to the bias compensation voltage terminal DVH, and a second end of the bias compensation module 17 is electrically connected to the first pole of the driving transistor M1. Specifically, during a frame of display time of the display panel, the working process of the pixel circuit 10 includes a data writing stage t1 and a holding stage t2, and the holding stage t2 includes a first bias stage t21.

In the first bias stage t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 into the first pole of the driving transistor M1, so that the driving transistor M1 can be biased with a high voltage, thereby avoiding the characteristic offset phenomenon of the driving transistor M1 caused by that the driving transistor M1 does not write data for a long time in the holding stage t2, so that the electrical property of the driving transistor M1 is recovered, and the driving effect of the driving module 31 is improved.

Meanwhile, since the data writing module 11 is turned on during the data writing phase t1, the data voltage terminal Vdata writes the data voltage signal V1 to the first pole of the driving transistor M1, and the bias compensation module 17 is turned on during the first bias phase t21, the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1. Therefore, when the display panel is driven to display by adopting a high-frequency data refresh rate driving mode or a low-frequency data refresh rate driving mode, the bias compensation voltage signal V2 is written into the first pole of the driving transistor M1 based on the bias compensation voltage end DVH, so that the screen flickering phenomenon when the display panel is switched from the high-frequency data refresh rate to the low-frequency data refresh rate is effectively improved, and the visual experience is improved.

It should be noted that, in fig. 11, the driving transistor M1 is illustratively shown as a PMOS driving transistor, and in other embodiments of the present invention, the driving transistor M1 may also be an NMOS driving transistor, which is not described herein again.

Optionally, with continued reference to fig. 11 and 12, the pixel circuit further includes a first light emission control module 12, a second light emission control module 13, a threshold compensation module 14, a first reset module 15, and a second reset module 16.

It should be noted that, in the embodiment of the present invention, specific structures of the reset module, the data writing module, the threshold compensation module, and the light emitting control module are not limited in particular, and each module of the pixel circuit may be designed according to actual needs on the premise that the bias compensation function of the threshold voltage of the driving transistor can be implemented. For easy understanding, specific structures of the reset module, the data writing module, the threshold compensation module, and the light emission control module are exemplified below in the embodiments of the present invention, where each module may optionally include a thin film transistor. With continued reference to fig. 11, a circuit configuration of 8T1C for the pixel circuit in the display panel is exemplarily shown in fig. 11. Of course, in other embodiments of the present invention, the pixel circuit may have other circuit structures, and the disclosure is not described herein.

Fig. 13 is a further driving timing diagram of the pixel circuit according to the present invention, referring to fig. 1, 2, 11 and 13, in some alternative embodiments, during a frame of display time of the display panel, the operation process of the pixel circuit further includes a reset phase t3, in which the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1;

in the first display mode T1, the refresh frequency of the display panel is F3, and F3 is less than F2;

in the first display stage T21, a reset stage T3 is provided before the data writing stage T1;

in the time of displaying a frame of a part of the display panel, the working process of the pixel circuit 10 further comprises a second bias phase t4, and in the second bias phase t4, the bias compensation module 17 is conducted, and the bias compensation voltage terminal DVH writes a bias compensation voltage signal V2 into the first pole of the driving transistor M1;

in the second display stage T22, a reset stage T3 is provided before the data writing stage, and a second bias stage T4 is provided between the data writing stage T1 and the holding stage T2.

Specifically, during a frame of display time of the display panel, the working process of the pixel circuit further includes a reset stage t3, in the reset stage t3, the bias compensation module 17 is turned on, the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 into the first pole of the driving transistor M1, so that the driving transistor M1 can be reset once, and a tailing phenomenon during switching of the display panel picture can be reduced.

In the first display mode T1, the refresh frequency of the display panel is F3, in the first display stage T21, the refresh frequency of the display panel is F1, and in the second display stage T22, the refresh frequency of the display panel is F2, F3 < F2, and F1 > F2. That is, the refresh frequency of the display panel is low in the first display mode T1 and the second display stage T22, and the refresh frequency of the display panel is high in the first display stage T21.

In the prior art, when the display panel adopts a driving mode of high-frequency data refresh rate to drive display, the number of the holding frames is zero or the number of the holding frames is small in one data refresh period, and the gate of the driving transistor holds the input of the data signal, that is, the gate potential of the driving transistor is refreshed more frequently. When the display panel is driven to display by adopting a driving mode with a low frequency data refresh rate, the number of the holding frames becomes relatively large in one data refresh period, and the gate potential of the driving transistor remains unchanged for a long time in one data refresh period. In contrast, in the display panel, the driving transistor may be operated in an unsaturated state during the light emitting period, and for the PMOS type driving transistor, there may be a case where the gate potential is higher than the drain potential when the driving transistor is turned on; for an NMOS drive transistor, there may be a case where the gate potential is lower than the drain potential when the drive transistor is turned on; this leads to the polarization of ions in the driving transistor and thus the formation of a built-in electric field in the driving transistor, which leads to a constant shift in the threshold voltage of the driving transistor. When the display panel is driven to display by adopting the driving mode with the low-frequency data refresh rate, the problem of abnormal brightness can occur, that is, the phenomenon of screen flickering can occur, and the visual experience is affected.

In the present application, since the refresh frequency of the display panel is higher in the first display stage T21, the second bias stage T4 may not be set in the operation of the pixel circuit during one frame of display frame time of the display panel in the first display stage T21. Because the refresh frequency of the display panel is lower in the second display mode T1 and the second display stage T22, in the first display mode T1 and the second display stage T22, a second bias stage T4 is arranged between the data writing stage T1 and the holding stage T2 in one frame of display frame time of the display panel, in the second bias stage T4, the bias compensation module 17 is turned on, the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1, and the high-voltage bias can be performed on the driving transistor M1, so that the characteristic offset phenomenon of the driving transistor M1 caused by the fact that the driving transistor M1 does not write data for a long time in the first display mode T1 and the second display stage T22 is avoided, the electrical property of the driving transistor M1 is recovered, the driving effect of the driving module 31 is improved, the screen flicker phenomenon of the display panel in the first display mode T1 and the second display stage T22 is effectively improved, and the visual experience is effectively improved.

Fig. 14 is a further driving timing diagram of a pixel circuit according to the present invention, referring to fig. 2, 11 and 14, the present embodiment provides a display panel, the display panel includes a pixel circuit 10 and a light emitting element 20 electrically connected thereto, the pixel circuit 10 includes a driving transistor M1, a data writing module 11 and a bias compensation module 17, a first end of the data writing module 11 is connected to a data voltage terminal Vdata, a second end of the data writing module 11 is electrically connected to a first pole of the driving transistor M1, a first end of the bias compensation module 17 is connected to a bias compensation voltage terminal DVH, and a second end of the bias compensation module 17 is electrically connected to a first pole of the driving transistor M1;

in the period of one frame of display picture of the display panel, the working process of the pixel circuit 10 comprises a reset phase t3 and a data writing phase t1;

in the reset phase t3, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1;

The display panel comprises a first display mode T1, wherein the first display mode T1 displays a first picture, and the refresh frequency of the display panel is F3 when the first display mode T1 is adopted;

the display panel also comprises a second display mode T2, wherein the second display mode T2 displays a second picture, and when the second display mode T2 is adopted, the refresh frequency of the display panel is F4, and F3 is more than F4;

when the display panel is switched from the first display mode T1 to the second display mode T2, a reset phase T3 is arranged before a data writing phase T1 in the first display mode T1;

a reset phase T3 is arranged before the data writing phase T1 in the first frame display picture time of the second display mode T2;

in the second frame display time of the second display mode T2, a reset phase T3 is provided before the data writing phase T1, and a second bias phase T4 is provided between the data writing phase T1 and the holding phase T2.

In the period of one frame of display picture of the display panel, the working process of the pixel circuit further comprises a reset stage t3, in the reset stage t3, the bias compensation module 17 is conducted, the bias compensation voltage end DVH writes the bias compensation voltage signal V2 into the first pole of the driving transistor M1, the driving transistor M1 can be reset once, and the tailing phenomenon during the picture switching of the display panel can be reduced. In the first display mode T1 and the second display mode T2, the reset stage T3 is disposed before the data writing stage T1, so that the driving transistor M1 can be reset once, and the tailing phenomenon during switching of the display panel images can be reduced.

The display panel comprises a first display mode T1, wherein the first display mode T1 displays a first picture, the refresh frequency of the display panel is F3 when the first display mode T1 is adopted, the display panel also comprises a second display mode T2, the second display mode T2 displays a second picture, and the refresh frequency of the display panel is F4 when the second display mode T2 is adopted, and F3 is more than F4. That is, the refresh frequency of the display panel is high in the first display mode T1, and the refresh frequency of the display panel is low in the second display mode T2.

Since the refresh frequency of the display panel is higher in the first display mode T1, the second bias stage T4 does not need to be set in the first display mode T1. And because the setting of the second bias stage t4 and the setting of the reset stage t3 have the offset effect, that is, the setting of the second bias stage t4 affects the reset effect of the reset stage t3 on the driving transistor M1. Therefore, in the first display mode T1, the second offset stage T4 is not arranged, so that the reset stage T3 is beneficial to eliminating the influence on the previous display picture, and the tailing phenomenon during the picture switching of the display panel can be reduced.

When the display panel is switched from the first display mode T1 to the second display mode T2, that is, when the display panel is switched from the high-frequency data refresh rate to the low-frequency data refresh rate, the reset stage T3 is set before the data writing stage T1 in the first frame display frame time of the second display mode T2, so that the driving transistor M1 can be reset once, and the tailing phenomenon during the display panel frame switching can be reduced. And the second offset stage T4 is not arranged between the data writing stage T1 and the holding stage T2, so that the influence on the previous display picture caused by the reset stage T3 is eliminated, namely, the influence on the display picture of the second display mode T2 is effectively eliminated when the first frame of the display picture of the second display mode T2 is displayed, and the tailing phenomenon when the display panel picture is switched can be reduced.

In the second frame display time of the second display mode T2, a reset stage T3 is arranged before the data writing stage T1, a second bias stage T4 is arranged between the data writing stage T1 and the holding stage T2, the bias compensation module 17 is turned on in the second bias stage T4, the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 into the first pole of the driving transistor M1, and high-voltage bias can be performed on the driving transistor M1, so that the characteristic offset phenomenon of the driving transistor M1 caused by that the driving transistor M1 does not write data for a long time in the second display mode T2 is avoided, the electrical property of the driving transistor M1 is recovered, the driving effect of the driving module 31 is improved, the screen flicker phenomenon of the display panel in the second display mode T1 is effectively improved, and the visual experience is effectively improved. Meanwhile, since the display images are the same in the second display mode T2, the tailing phenomenon does not exist in the second frame display image and the subsequent frame display images of the second display mode T2, and thus the second offset stage T4 can be set in the second frame display image time of the second display mode T2.

It should be noted that, in this embodiment, only the reset phase T3 is set before the data writing phase T1 in the second frame display frame time of the second display mode T2, and the second bias phase T4 is set between the data writing phase T1 and the holding phase T2, and in other embodiments of the present invention, in the third frame and the subsequent frame display frame time of the second display mode T2, the timing setting of this embodiment in the second frame display frame time of the second display mode T2 may be referred to, which is not repeated herein.

Fig. 15 is a further driving timing diagram of a pixel circuit according to the present invention, and referring to fig. 2, 11 and 15, in some alternative embodiments, during a first frame display period of a second display period T2, a voltage value of the bias compensation voltage signal is V41;

in the second frame display picture time of the second display stage T2, the voltage value of the bias compensation voltage signal is V42;

V42＞V41。

specifically, when the display panel is switched from the first display mode T1 to the second display mode T2, that is, when the display panel is switched from the high frequency data refresh rate to the low frequency data refresh rate, the reset stage T3 is provided before the data writing stage T1 in the first frame display frame time of the second display mode T2, so that the driving transistor M1 can be reset once, and the tailing phenomenon during the frame switching of the display panel can be reduced. The setting of the first offset stage T21 affects the reset stage T3 to eliminate the influence on the previous display screen, so that the voltage value of the offset compensation voltage signal is reduced when the first frame of the second display mode T2 displays the screen, the influence of the display screen of the first display mode T1 on the display screen of the second display mode T2 can be effectively eliminated, and the tailing phenomenon when the display panel screen is switched can be reduced.

In the second frame display time of the second display mode T2, the second bias stage T4 between the data writing stage T1 and the holding stage T2 can bias the driving transistor M1 with a high voltage, so as to avoid the characteristic offset phenomenon of the driving transistor M1 caused by that the driving transistor M1 does not write data for a long time in the second display mode T2, and enable the electrical property of the driving transistor M1 to be recovered, improve the driving effect of the driving module 31, effectively improve the screen flicker phenomenon of the display panel in the second display mode T2, and effectively improve the visual experience. In the second frame display picture time of the second display mode T2, the voltage value of the bias compensation voltage signal is improved, the bias effect on the driving transistor M1 in the first bias stage T21 and the second bias stage T4 can be improved, the screen flicker phenomenon of the display panel in the second display mode T2 is further improved, and the visual experience is effectively improved.

It should be noted that, in this embodiment, only the voltage value of the offset compensation voltage signal in the second frame display frame time of the second display mode T2 is shown to be greater than the voltage value of the offset compensation voltage signal in the first frame display frame time of the second display mode T2, in other embodiments of the present invention, the voltage value of the offset compensation voltage signal in the third frame and subsequent frame display frame time of the second display mode T2 may be the same as the voltage value of the offset compensation voltage signal in the second frame display frame time of the second display mode T2, and the voltage value of the offset compensation voltage signal in the third frame and subsequent frame display frame time of the second display mode T2 may also be set according to the bias effect that is actually required.

In some alternative embodiments, please refer to fig. 16, fig. 16 is a schematic plan view of a display device provided by the present invention, and a display device 1000 provided by the present embodiment includes a display panel 100 provided by the above-mentioned embodiments of the present invention. The embodiment of fig. 16 is only an example of a mobile phone, and the display device 1000 is described, and it is to be understood that the display device 1000 provided in the embodiment of the present invention may be any other display device 1000 having a display function, such as a computer, a television, a vehicle-mounted display device, etc., which is not particularly limited in this respect. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and the specific description of the display panel 100 in the above embodiments may be referred to in the embodiments, and the description of the embodiment is omitted herein.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, which is characterized in that,

the display panel comprises a first display mode, and the first display mode displays a first picture;

the display panel further comprises a second display mode, the second display mode displays a second picture, the second display mode comprises a first display stage and a second display stage, the refresh frequency of the display panel is F1 in the first display stage, and the refresh frequency of the display panel is F2 in the second display stage, and F1 is more than F2;

the display panel is switched from the first display mode to the second display stage through the first display stage.

2. The display panel of claim 1, wherein the display panel comprises,

the display panel comprises a pixel circuit and a light-emitting element electrically connected with the pixel circuit, the pixel circuit comprises a driving transistor and a data writing module, the driving transistor supplies driving current for the light-emitting element, a first end of the data writing module is connected with a data voltage end, and a second end of the data writing module is electrically connected with a first pole of the driving transistor;

In the time of one frame of display picture of the display panel, the working process of the pixel circuit comprises a data writing-in stage and a holding stage, and the holding stage comprises a first bias stage;

in the data writing stage, the data writing module is conducted, and the data voltage end writes a data voltage signal to the first pole of the driving transistor;

in the first bias stage, the data writing module is conducted, and the data voltage end writes a bias compensation voltage signal to the first pole of the driving transistor.

3. The display panel of claim 2, wherein the display panel comprises,

in the second display stage, in the data writing stage, the voltage value of the data voltage signal is V11;

in the first frame display picture time of the second display stage, in the first bias stage, the voltage value of the bias compensation voltage signal is V21;

in the second frame display picture time of the second display stage, in the first bias stage, the voltage value of the bias compensation voltage signal is V22;

v21 is between V11 and V22.

4. The display panel of claim 2, wherein the display panel comprises,

in the first display mode, in the data writing stage, the voltage value of the data voltage signal is V12;

In the second display mode, in the data writing stage, the voltage value of the data voltage signal is V13;

in the first frame display picture time of the first display stage, in the first bias stage, the voltage value of the bias compensation voltage signal is V31;

in the second frame display picture time of the first display stage, in the first bias stage, the voltage value of the bias compensation voltage signal is V32;

wherein V12 > V13 and V31 > V32, or V12 < V13 and V31 < V32.

5. The display panel of claim 2, wherein the display panel comprises,

in the first frame display picture time of the first display stage, the duration of the first bias stage is h1;

in the second frame display picture time of the first display stage, the duration of the first bias stage is h2;

wherein V12 > V13 and h1 > h2, or V12 < V13 and h1 < h2.

6. The display panel of claim 2, wherein the display panel comprises,

in the period of one frame of display picture of the display panel, the working process of the pixel circuit further comprises a reset stage, wherein in the reset stage, the data writing module is conducted, and the data voltage end writes the bias compensation voltage signal into the first pole of the driving transistor;

and setting the reset stage before the data writing stage in the first frame display picture time of the first display stage.

7. The display panel of claim 1, wherein the display panel comprises,

the display panel comprises a pixel circuit and a light-emitting element electrically connected with the pixel circuit, wherein the pixel circuit comprises a driving transistor, a data writing module and a bias compensation module, a first end of the data writing module is connected with a data voltage end, a second end of the data writing module is electrically connected with a first pole of the driving transistor, a first end of the bias compensation module is connected with a bias compensation voltage end, and a second end of the bias compensation module is electrically connected with the first pole of the driving transistor;

in the first bias stage, the bias compensation module is turned on, and the bias compensation voltage terminal writes a bias compensation voltage signal to the first pole of the driving transistor.

8. The display panel of claim 7, wherein the display panel comprises,

in the period of one frame of display picture of the display panel, the working process of the pixel circuit further comprises a reset phase, wherein in the reset phase, the bias compensation module is conducted, and the bias compensation voltage end writes the bias compensation voltage signal into the first pole of the driving transistor;

in the first display mode, the refresh frequency of the display panel is F3, and F3 is less than F2;

the reset phase is arranged before the data writing phase in the first display phase;

the working process of the pixel circuit further comprises a second bias phase, wherein in the second bias phase, the bias compensation module is conducted, and the bias compensation voltage end writes the bias compensation voltage signal into the first pole of the driving transistor;

The reset phase is arranged before the data writing phase in the second display phase, and the second bias phase is arranged between the data writing phase and the holding phase.

9. A display panel, which is characterized in that,

in the time of one frame of display picture of the display panel, the working process of the pixel circuit comprises a reset phase and a data writing phase;

in the reset stage, the bias compensation module is conducted, and the bias compensation voltage end writes a bias compensation voltage signal into the first pole of the driving transistor;

the display panel comprises a first display mode, wherein a first picture is displayed in the first display mode, and the refresh frequency of the display panel is F3 in the first display mode;

the display panel further comprises a second display mode, wherein the second display mode displays a second picture, and when the second display mode is adopted, the refresh frequency of the display panel is F4, and F3 is more than F4;

when the display panel is switched from the first display mode to the second display mode, the reset phase is arranged before the data writing phase in the first display mode;

the reset phase is arranged before the data writing phase in the first frame display picture time of the second display mode;

and in the second frame display picture time of the second display mode, the reset stage is arranged before the data writing stage, and the second bias stage is arranged between the data writing stage and the holding stage.

10. The display panel of claim 9, wherein the display panel comprises,

in the first frame display picture time of the second display stage, the voltage value of the bias compensation voltage signal is V41;

in the second frame display picture time of the second display stage, the voltage value of the bias compensation voltage signal is V42;

V42＞V41。

11. a display device, characterized in that the display device comprises a display panel according to any one of claims 1-10.