CN116860301A - FPGA configuration method and device of chip tester - Google Patents

Abstract

The application discloses an FPGA configuration method of a chip tester, an FPGA configuration system of the chip tester, an FPGA configuration device of the chip tester and electronic equipment, belonging to the technical field of semiconductors, wherein the FPGA configuration method of the chip tester comprises the following steps: storing a plurality of program configuration data into different areas of the nonvolatile memory respectively; acquiring a hot start command and a hot start address; and resetting the FPGA based on the hot start command and loading program configuration data from a hot start address of the nonvolatile memory to complete FPGA configuration. According to the method, by loading the program configuration data through hot start, the problem that the time for downloading the program codes again each time when the FPGA is configured through power failure restarting can be avoided, the corresponding program configuration data is loaded from the nonvolatile memory based on the hot start address, the transmission quantity of the data is reduced, and the saving of system resources is facilitated.

Description

FPGA configuration method and device of chip tester

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to an FPGA configuration method of a chip tester, an FPGA configuration system of the chip tester, an FPGA configuration device of the chip tester and electronic equipment.

Background

The field programmable gate array (Field Programmable Gate Array, abbreviated as FPGA) is a product of further development on the basis of programmable devices such as PAL (programmable array logic), GAL (general array logic) and the like, the programmable logic device is a hardware carrier for realizing specific functions and technical indexes of an electronic application system by EDA technology, and the FPGA is one of main devices for realizing the path, and has the characteristics of direct user-oriented, extremely high flexibility and universality, convenient use, quick realization and the like.

Currently, the reconfiguration of the FPGA is to directly configure codes into the FPGA through an upper computer, so that the codes need to be retransmitted once each time. The chip tester needs to use the calibration code of the first program before starting to work, and then configures the code of the FPGA into the functional code of the second program, and the existing FPGA reconfiguration method wastes a lot of time and easily damages the calibrated chip data.

Disclosure of Invention

The application aims to provide an FPGA configuration method and an FPGA configuration system of a chip tester, an FPGA configuration device and electronic equipment of the chip tester, so as to solve the problem that the FPGA configuration of the traditional chip tester damages calibrated chip data.

According to a first aspect of an embodiment of the present application, there is provided an FPGA configuration method of a chip tester, which may include:

storing a plurality of program configuration data into different areas of the nonvolatile memory respectively;

acquiring a hot start command and a hot start address;

and resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete FPGA configuration.

In some optional embodiments of the application, acquiring the warm boot command and the warm boot address further comprises:

acquiring update data of the plurality of program configuration data by broadcasting;

and loading the update data to a corresponding area of the nonvolatile memory.

In some optional embodiments of the application, before loading the update data into the corresponding area of the nonvolatile memory, the method further comprises:

and checking whether the updating data has transmission errors or not based on the cyclic redundancy check code in the updating data, if so, generating an error report and re-acquiring the updating data.

In some optional embodiments of the application, the plurality of program configuration data includes calibration configuration data and functional configuration data, and storing the plurality of program configuration data in different areas of the non-volatile memory respectively comprises:

storing the calibration configuration data in a first address of a non-volatile memory;

and storing the function configuration data into a second address of the nonvolatile memory.

In some alternative embodiments of the present application, the first address is 0.

In some optional embodiments of the present application, before acquiring the warm boot command and the warm boot address, the method further comprises:

performing external chip data calibration based on the calibration configuration data;

wherein the hot start address is the second address.

In some optional embodiments of the application, when the program to be configured is a calibration program, the hot start address is the first address;

and when the program to be configured is a functional program, the hot start address is the second address.

In some alternative embodiments of the present application, obtaining a warm boot command and a warm boot address includes:

acquiring a hot start enabling command and the hot start address;

invoking the warm boot command encapsulated within the FPGA based on the warm boot enable command.

In some optional embodiments of the application, obtaining a warm boot enable command and the warm boot address comprises:

the lower computer is in communication connection with the upper computer to acquire a hot start enabling command and the hot start address sent by the upper computer;

the lower computer transmits the hot start enabling command and the hot start address to a communication board card;

and the communication board card sends the hot start enabling command and the hot start address to a service board where the FPGA is located.

According to a second aspect of the embodiment of the application, an FPGA configuration system of a chip tester is provided, which comprises an upper computer, a lower computer, a communication board card and a service board;

the service board comprises a nonvolatile memory, and different areas of the nonvolatile memory respectively store a plurality of program configuration data;

the upper computer is used for generating a hot start enabling command and a hot start address and sending the hot start enabling command and the hot start address to one or more lower computers through a network port;

the lower computer is used for issuing the hot start enabling command and the hot start address to one or more communication boards through a PCIE bus;

the communication board card is used for issuing the hot start enabling command and the hot start address to one or more service boards;

the service board is used for calling the hot start command packaged in the FPGA based on the hot start enabling command, resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete FPGA configuration.

In some optional embodiments of the present application, the upper computer is further configured to load update data of the plurality of program configuration data to the service board through broadcasting;

the service board is further configured to load the update data into a corresponding area of the nonvolatile memory.

According to a third aspect of the embodiment of the present application, there is provided an FPGA configuration apparatus of a chip tester, including:

the storage module is used for storing the program configuration data into different areas of the nonvolatile memory respectively;

the acquisition module is used for acquiring a hot start command and a hot start address;

and the configuration module is used for resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete the FPGA configuration.

According to a fourth aspect of embodiments of the present application, there is provided an electronic device, which may include:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to execute instructions to implement the FPGA configuration method of the chip tester as described in any of the embodiments of the first aspect.

The technical scheme of the application has the following beneficial technical effects:

according to the FPGA configuration method of the chip tester, provided by the embodiment of the application, the program configuration data is loaded through the hot start, so that the problem that the program code is downloaded again each time when the FPGA is configured through power failure restarting can be avoided, the corresponding program configuration data is loaded from the nonvolatile memory based on the hot start address, the transmission quantity of the data is reduced, and the system resource is saved.

Drawings

FIG. 1 is a flow chart of an FPGA configuration method of a chip tester according to an exemplary embodiment of the application;

FIG. 2 is a flow chart of an FPGA configuration method of a chip tester according to another exemplary embodiment of the application;

FIG. 3 is a flow chart of an FPGA configuration method of a chip tester according to another exemplary embodiment of the application;

fig. 4 is a flowchart of step S101 in an exemplary embodiment of the present application;

FIG. 5 is a flow chart of an FPGA configuration method of a chip tester according to still another exemplary embodiment of the application;

FIG. 6 is a flow chart of step S102 in an exemplary embodiment of the application;

fig. 7 is a flowchart of step S1021 in another exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of an FPGA configuration system of a chip tester in an exemplary embodiment of the application;

FIG. 9 is a schematic diagram of an FPGA configuration device of a chip tester in an exemplary embodiment of the application;

fig. 10 is a schematic diagram of an electronic device according to an exemplary embodiment of the present application.

Fig. 11 is a schematic diagram of a hardware structure of an electronic device in an exemplary embodiment of the application.

Detailed Description

The objects, technical solutions and advantages of the present application will become more apparent by the following detailed description of the present application with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the application. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present application.

A layer structure schematic diagram according to an embodiment of the present application is shown in the drawings. The figures are not drawn to scale, wherein certain details may be exaggerated and some details may be omitted for clarity. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.

According to the research, in the field of storage device testers, a service board card needs to use a set of codes to perform data calibration and initialization configuration operation on some external chips before working, but normal function codes do not contain the functions of a calibration part, so that the configuration of FPGA codes needs to be completed under the condition that the board card is not powered down. In the field of storage device testers, the calibration codes and the function codes of the service board card are two fixed codes, and because the FPGA resource is wasted when the two codes are combined into one set of codes, the cost is increased, so that the cost can be reduced when the two sets of codes are used in a time-sharing manner. In the field of memory device testers, if a service board card finishes the burning of calibration codes and function codes in an on-line JTAG loading mode, a machine can take a great deal of time for a lot of service boards to finish the burning of the boards one by one, each service board card needs one minute to finish, so hundreds of service boards need several hours to finish the burning of the codes, the same long time is required for switching the calibration codes into the function codes, and each board card must be ensured to be successful once. In the field of storage equipment testers, after the calibration of a service board card is completed, the FPGA calibration code needs to be switched into an FPGA functional code in a mode that the board card is not powered down. In order to solve the problems that the storage device tester is easy to destroy calibrated chip data and cause system resource waste during FPGA reconfiguration, the application provides an FPGA configuration method of the chip tester, an FPGA configuration system of the chip tester, an FPGA configuration device of the chip tester and electronic equipment.

The FPGA configuration method, the data transmitting device, the electronic device and the storage medium of the chip tester provided by the embodiment of the application are described in detail below through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

As shown in fig. 1, in a first aspect of the embodiment of the present application, there is provided an FPGA configuration method of a chip tester, where the method may include:

step S101: storing a plurality of program configuration data into different areas of the nonvolatile memory respectively;

step S102: acquiring a hot start command and a hot start address;

step S103: and resetting the FPGA based on the hot start command and loading program configuration data from a hot start address of the nonvolatile memory to complete FPGA configuration.

The method of the embodiment can be used for a memory chip tester, in the method, a plurality of program configuration data are respectively used for realizing different functions, no intersection exists between the functions, and each program configuration data can independently run. According to the FPGA configuration method of the chip tester, the programs corresponding to the functions without intersection are separated, so that independent updating of different functions can be realized, more functions are realized by fewer FPGAs, the operation resources of a system can be saved, long time is not required for downloading program codes each time when the FPGAs are configured, and the calibrated chip data can be prevented from being damaged in a mode of restarting the configuration FPGA codes by using the hot start loading program configuration data.

For a clearer description, the following description will be given for the above steps, respectively:

first, in step S101, a plurality of program configuration data are stored in different areas of the nonvolatile memory, respectively.

In this step, the number of program configuration data may be two, which are respectively a configuration bit stream of the calibration code and a configuration bit stream of the function code of the FPGA. When the FPGA codes need to be reconfigured, the communication system of the whole machine system can be shared, the configuration bit stream of the calibration codes and the configuration bit stream of the function codes of the FPGA can be sent to the nonvolatile memory of the same service board through the communication system of the whole machine, and the two configuration bit stream data are stored in different areas of the nonvolatile memory through configuring different addresses. One of the program configuration data may be stored at the 0 address, in this embodiment the calibration code is stored at the 0 address of the non-volatile memory, the function code is stored in a further free area of the non-volatile memory and the first address of the calibration code is recorded for subsequent loading of the program configuration data by the corresponding address.

Step S102 follows: a warm boot command and a warm boot address are obtained.

In this step, the hot start command and the hot start address may be obtained by the upper computer. In some embodiments, the hot start enabling command and the hot start address can be acquired through the upper computer, and then the hot start enabling command encapsulated in the FPGA is called through the hot start enabling command. When the memory chip tester needs to switch programs, a hot start command and a hot start address can be issued to a lower computer through a network port by the upper computer, the lower computer transmits the hot start command and the hot start address to a communication board card through a PCIE bus, and the communication board card issues the hot start command and the hot start address to all corresponding service board cards in parallel through inter-board communication of 10Gbase Ethernet standard.

Finally, step S103: and resetting the FPGA based on the hot start command and loading program configuration data from a hot start address of the nonvolatile memory to complete FPGA configuration.

The step is to execute the hot start based on the hot start command acquired in the step S102, replace the default loading address with the hot start address based on the hot start address acquired in the step S102, and load the program configuration data stored in the step S101, so that the FPGA reconfigures codes, and the program switching is realized under the condition that the FPGA is not required to be powered down. For the service board packaged hot start operation, the hot start command needs to be executed through an internal special interface ICAPE in the Xilinx FPGA, and because the IPROG reset command is fixed, in the embodiment, when the application program in the FPGA is reset, the hot start command is packaged in the FPGA for simplifying the operation, and the upper computer only needs to issue one hot start enabling command and one hot start address, so that data transmission errors are reduced, and data transmission time is saved.

As shown in fig. 2, in some embodiments, before the hot start command and the hot start address are acquired in step S102, the FPGA configuration method of the chip tester may further include:

step S104: acquiring update data of a plurality of program configuration data by broadcasting;

step S105: the update data is loaded into a corresponding region of the non-volatile memory.

In this embodiment, when there are multiple service boards and FPGA codes need to be updated, the upper computer loads the update data to each service board in a broadcast manner, and then the service boards load the update data to their respective nonvolatile memories, so that it is possible to configure multiple service boards at a time, and greatly save the time for upgrading the program.

As shown in fig. 3, in some embodiments, before loading the update data into the corresponding area of the nonvolatile memory in step S105, the method further includes:

step S106: and checking whether the updating data has transmission errors or not based on the cyclic redundancy check code in the updating data, if so, generating an error report and re-acquiring the updating data.

In this embodiment, in order to ensure that no error code occurs in the transmission of the update data of each service board card, a crc (cyclic redundancy check) code (Cyclic Redundancy Check) is added to the update data for verification, when the lower computer detects a data error, an error status is reported to the upper computer, and when the upper computer detects the error, the update data is retransmitted until the configuration data is completely correct, thereby achieving the purpose of correctly updating a plurality of service boards.

As shown in fig. 4, in some embodiments, step S101 includes:

step S1011: storing the calibration configuration data in a first address of the non-volatile memory;

step S1012: the functional configuration data is stored in a second address of the non-volatile memory.

In this embodiment, the plurality of program configuration data includes calibration configuration data and function configuration data, the calibration configuration data is stored at a first address of the nonvolatile memory, and the function configuration data is stored at a second address of the nonvolatile memory and recorded so that the program configuration data is subsequently loaded through the corresponding address. In this embodiment, the first address may be 0. When the FPGA configuration is carried out, when the program to be configured is a calibration program, the hot start address is the first address, so that calibration configuration data stored in the first address can be loaded, and the configuration of the calibration program is realized. When the program to be configured is a functional program, the hot start address is a second address, so that the functional configuration data stored in the second address can be loaded to realize the configuration of the functional program.

As shown in fig. 5, in some embodiments, before acquiring the warm boot command and the warm boot address in step S102, the method further includes:

step S107: external chip data calibration is performed based on the calibration configuration data.

In this embodiment, the hot start address is the second address, before the FPGA is reconfigured, the external chip data is calibrated based on the calibration configuration data stored in the first address, then the second address is acquired through the upper computer, and the functional configuration data stored in the second address is loaded, so that the FPGA configuration can be completed without power failure, the program code does not need to be downloaded again each time when the FPGA is configured, and damage to the calibrated external chip data is avoided to a certain extent.

As shown in fig. 6, in some embodiments, step S102 includes:

step S1021: acquiring a hot start enabling command and a hot start address;

step S1022: the hot start command encapsulated within the FPGA is invoked based on the hot start enable command.

In this embodiment, the hot start command is encapsulated in the FPGA, and the hot start enable command and the hot start address are sent only through the upper computer, which is conducive to reducing the transmission amount of data, saving system resources, where the data amount of the hot start enable command is far smaller than that of the hot start command, so that the probability of data transmission errors in the communication process can be reduced, and the communication time can be reduced, so that hot switching of a program can be realized faster and more stably.

As shown in fig. 7, in some embodiments, step S1021 includes:

step S10211: the lower computer is in communication connection with the upper computer to acquire a hot start enabling command and a hot start address sent by the upper computer;

step S10212: the lower computer transmits a hot start enabling command and a hot start address to the communication board card;

step S10213: and the communication board card sends the hot start enabling command and the hot start address to a service board where the FPGA is located.

In this embodiment, when the memory chip tester needs to switch the program, the heat-generating start enable command and the heat-generating start address may be issued to the lower computer through the network port by the upper computer, the lower computer transmits the heat-generating start enable command and the heat-generating start address to the communication board card through the PCIE bus, and the communication board card issues the heat-generating start enable command and the heat-generating start address to all corresponding service boards in parallel through inter-board communication according to the 10Gbase ethernet specification. The service card invokes a warm boot command encapsulated within the FPGA based on the warm boot enable command. According to the FPGA configuration method of the chip tester, provided by the embodiment, the hot start enabling command and the hot start address can be simultaneously sent to the plurality of lower computers through the upper computer, and synchronous updating of the plurality of lower computers can be achieved. The lower computer can send the hot start enabling command and the hot start address to the plurality of service boards simultaneously through the communication board, synchronous updating of the plurality of service boards can be achieved, the method is particularly suitable for a chip testing machine comprising the plurality of service boards, and compared with the method for completing board card burning one by one in the related technology, the FPGA configuration method of the chip testing machine provided by the embodiment can greatly improve updating efficiency of the service boards.

As shown in fig. 8, in a second aspect of the embodiment of the present application, an FPGA configuration system of a chip tester is provided, where the system may include an upper computer, a lower computer, a communication board card, and a service board;

the service board comprises a nonvolatile memory, and different areas of the nonvolatile memory respectively store a plurality of program configuration data;

the upper computer is used for generating a hot start enabling command and a hot start address and sending the hot start enabling command and the hot start address to one or more lower computers through a network port;

the lower computer is used for issuing a hot start enabling command and a hot start address to one or more communication boards through the PCIE bus;

the communication board card is used for issuing a hot start enabling command and a hot start address to one or more service boards;

the service board is used for calling a hot start command packaged in the FPGA based on the hot start enabling command, resetting the FPGA based on the hot start command and loading program configuration data from a hot start address of the nonvolatile memory to complete FPGA configuration.

According to the FPGA configuration system of the chip tester, provided by the embodiment, the hot start enabling command and the hot start address are sent to the plurality of service boards through the upper computer, so that the simultaneous configuration of the plurality of service boards can be realized, the time for FPGA configuration is greatly saved, the transmission quantity of data is reduced by sending the hot start enabling command to replace the hot start command, the probability of data transmission errors is reduced, and the FPGA configuration efficiency is further improved.

In some embodiments, the upper computer is further configured to load update data of the plurality of program configuration data to the service board by broadcasting; the service board is also used to load update data into a corresponding region of the non-volatile memory. The FPGA configuration system of the chip tester provided by the embodiment sends the update data to a plurality of service boards through the upper computer, can update the program configuration data while realizing the plurality of service boards, greatly improves the update efficiency of the program configuration data,

as shown in fig. 9, in a third aspect of the embodiment of the present application, there is provided an FPGA configuration device of a chip tester, which may include:

a storage module 11 for storing a plurality of program configuration data into different areas of the nonvolatile memory, respectively;

an acquiring module 12, configured to acquire a warm start command and a warm start address;

and the configuration module 13 is used for resetting the FPGA based on the hot start command and loading program configuration data from a hot start address of the nonvolatile memory to complete FPGA configuration.

Optionally, as shown in fig. 10, the embodiment of the present application further provides an electronic device 1100, including a processor 1101, a memory 1102, and a program or an instruction stored in the memory 1102 and capable of running on the processor 1101, where the program or the instruction implements each process of the FPGA configuration method embodiment of the chip tester when executed by the processor 1101, and the process can achieve the same technical effect, so that repetition is avoided and redundant description is omitted herein.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Fig. 11 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 1200 includes, but is not limited to: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

Those skilled in the art will appreciate that the electronic device 1200 may also include a power source (e.g., a battery) for powering the various components, which may be logically connected to the processor 1210 by a power management system, such as to perform functions such as managing charging, discharging, and power consumption by the power management system. The electronic device structure shown in fig. 11 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than illustrated, or may combine some components, or may be arranged in different components, which are not described in detail herein.

It should be appreciated that in embodiments of the present application, the input unit 1204 may include a graphics processor (Graphics Processing Unit, GPU) 12041 and a microphone 12042, the graphics processor 12041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 1206 may include a display panel 12061, and the display panel 12061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 1207 includes a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include two parts, a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein. Memory 1209 may be used to store software programs as well as various data including, but not limited to, application programs and an operating system. Processor 1210 may integrate an application processor that primarily processes operating systems, user interfaces, applications, etc., with a modem processor that primarily processes wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 1210.

The embodiment of the application also provides a readable storage medium, wherein the readable storage medium stores a program or an instruction, and the program or the instruction realizes each process of the FPGA configuration method embodiment of the chip tester when being executed by a processor, and can achieve the same technical effect, so that repetition is avoided and redundant description is omitted.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

The embodiment of the application further provides a chip, the chip comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions, the processes of the FPGA configuration method embodiment of the chip tester can be realized, the same technical effects can be achieved, and the repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (13)

1. An FPGA configuration method of a chip tester, comprising:

storing a plurality of program configuration data into different areas of the nonvolatile memory respectively;

acquiring a hot start command and a hot start address;

and resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete FPGA configuration.

2. The FPGA configuration method of a chip tester according to claim 1, further comprising, before acquiring the hot start command and the hot start address:

acquiring update data of the plurality of program configuration data by broadcasting;

and loading the update data to a corresponding area of the nonvolatile memory.

3. The FPGA configuration method of a chip tester according to claim 2, further comprising, before loading the update data into the corresponding area of the nonvolatile memory:

and checking whether the updating data has transmission errors or not based on the cyclic redundancy check code in the updating data, if so, generating an error report and re-acquiring the updating data.

4. The FPGA configuration method of a chip tester according to claim 1, wherein the plurality of program configuration data includes calibration configuration data and functional configuration data, and storing the plurality of program configuration data in different areas of the nonvolatile memory, respectively, includes:

storing the calibration configuration data in a first address of a non-volatile memory;

and storing the function configuration data into a second address of the nonvolatile memory.

5. The FPGA configuration method of a chip tester according to claim 4, wherein the first address is 0.

6. The FPGA configuration method of a chip tester according to claim 5, further comprising, before acquiring the hot start command and the hot start address:

performing external chip data calibration based on the calibration configuration data;

wherein the hot start address is the second address.

7. The FPGA configuration method of a chip tester according to claim 4, wherein the hot start address is the first address when the program to be configured is a calibration program;

and when the program to be configured is a functional program, the hot start address is the second address.

8. The FPGA configuration method of a chip tester according to any one of claims 1 to 7, wherein obtaining a warm boot command and a warm boot address includes:

acquiring a hot start enabling command and the hot start address;

invoking the warm boot command encapsulated within the FPGA based on the warm boot enable command.

9. The FPGA configuration method of a chip tester according to claim 8, wherein obtaining a warm boot enable command and the warm boot address comprises:

the lower computer is in communication connection with the upper computer to acquire a hot start enabling command and the hot start address sent by the upper computer;

the lower computer transmits the hot start enabling command and the hot start address to a communication board card;

and the communication board card sends the hot start enabling command and the hot start address to a service board where the FPGA is located.

10. The FPGA configuration system of the chip tester is characterized by comprising an upper computer, a lower computer, a communication board card and a service board;

the service board comprises a nonvolatile memory, and different areas of the nonvolatile memory respectively store a plurality of program configuration data;

the upper computer is used for generating a hot start enabling command and a hot start address and sending the hot start enabling command and the hot start address to one or more lower computers through a network port;

the lower computer is used for issuing the hot start enabling command and the hot start address to one or more communication boards through a PCIE bus;

the communication board card is used for issuing the hot start enabling command and the hot start address to one or more service boards;

the service board is used for calling the hot start command packaged in the FPGA based on the hot start enabling command, resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete FPGA configuration.

11. The FPGA configuration system of a chip tester according to claim 10, wherein the host computer is further configured to load update data of the plurality of program configuration data to the service board by broadcasting;

the service board is further configured to load the update data into a corresponding area of the nonvolatile memory.

12. An FPGA configuration device of a chip tester, comprising:

the storage module is used for storing the program configuration data into different areas of the nonvolatile memory respectively;

the acquisition module is used for acquiring a hot start command and a hot start address;

and the configuration module is used for resetting the FPGA based on the hot start command and loading the program configuration data from the hot start address of the nonvolatile memory to complete the FPGA configuration.

13. An electronic device, comprising: a processor, a memory and a program or instruction stored on the memory and executable on the processor, which when executed by the processor implements a method of FPGA configuration of a chip tester as claimed in any of claims 1 to 9.