CN116860202A - Data processing method, processor and storage medium - Google Patents
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Abstract
The embodiment of the application discloses a data processing method, a processor and a storage medium. According to the scheme, floating point data or fixed point data which needs to be subjected to a preset algorithm can be converted into posit format data, the posit format data is subjected to division operation through the preset algorithm to obtain an operation result in posit format, and the operation result in posit format is converted into target floating point data or target fixed point data. According to the embodiment, the compatible division operation instruction can be integrated in the PIC single chip microcomputer, so that more complex data conversion and corresponding calculation can be realized, and the calculation efficiency is greatly improved.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a data processing method, a processor, and a storage medium.
Background
RISC (Reduced Instruction Set Computer ) is characterized by controlling the operation of the whole processor by microcode (microcode) stored in a read-only memory, while PIC singlechip (Peripheral Interface Controller) based on RISC architecture is an Integrated Circuit (IC) for controlling peripheral devices. From practical point of view, PIC attach importance to the performance-to-price ratio of the product, so most PIC singlechips do not contain complex arithmetic units. Therefore, a controller based on logic operation or simple arithmetic operation is generally implemented using a PIC single-chip microcomputer.
In some industrial control fields, a certain complex arithmetic operation is usually required according to an input signal to achieve the purpose of precise control. For example, a voltage compensation link is introduced into a motor control system, and bus voltage ripple can be reduced by rapidly compensating the voltage.
However, the conventional PIC unit machine is used to realize motor control, and since the existing PIC unit machine does not include a division operation unit, when calculating the compensation voltage, only multiplication, addition and shift operations can be used to realize division operation, and hundreds of instructions are usually required to be executed to complete the corresponding division operation, so that the motor control system cannot meet the requirement of the motor control system on real-time performance, and the calculation efficiency is low.
Disclosure of Invention
The embodiment of the application provides a data processing method, a processor and a storage medium, which are used for realizing more complex data conversion and corresponding calculation by integrating compatible division operation instructions in a PIC (peripheral interface controller) singlechip, thereby greatly improving the calculation efficiency.
The embodiment of the application provides a data processing method, which comprises the following steps:
converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
dividing the posit format data by a preset algorithm to obtain a posit format operation result;
and converting the operation result in the posit format into target floating point data or target fixed point data.
The embodiment of the application also provides a processor, which comprises:
the address taking unit is used for taking the value of the register as the address of the processor and acquiring an instruction from the instruction cache;
the decoding unit is used for decoding the instruction and determining a source operand of the instruction according to the decoding value;
the execution unit is used for executing corresponding calculation according to the type of the instruction, an integrated division unit is integrated in the execution unit, and the division unit is used for performing division operation;
the access unit is used for accessing the data cache to obtain an operation result;
and the submitting unit is used for writing the operation result into a general register.
The embodiment of the application also provides a storage medium which stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor to execute any data processing method provided by the embodiment of the application.
According to the data processing scheme provided by the embodiment of the application, floating point data or fixed point data which needs to be subjected to a preset algorithm can be converted into posit format data, the posit format data is subjected to division operation through the preset algorithm to obtain an operation result in the posit format, and the operation result in the posit format is converted into target floating point data or target fixed point data. According to the embodiment, the compatible division operation instruction can be integrated in the PIC single chip microcomputer, so that more complex data conversion and corresponding calculation can be realized, and the calculation efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first flow chart of a data processing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a processor according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a division unit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the application may have the same meaning or may have different meanings, the particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily occurring in sequence, but may be performed alternately or alternately with other steps or at least a portion of the other steps or stages.
It should be noted that, in this document, step numbers such as 101 and 102 are used for the purpose of more clearly and briefly describing the corresponding contents, and not to constitute a substantial limitation on the sequence, and those skilled in the art may execute 102 first and then execute 101 when they are implemented, which is within the scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The embodiment of the application provides a data processing method, and an execution main body of the data processing method can be a clock frequency dividing circuit provided by the embodiment of the application or an electronic device integrated with the clock frequency dividing circuit, wherein the clock frequency dividing circuit can be realized in a hardware mode.
As shown in fig. 1, fig. 1 is a schematic flow chart of a data processing method according to an embodiment of the present application, where a specific flow of the data processing method may be as follows:
101. and converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data.
The data processing method provided in this embodiment may be run in a PDPU (Posit Division Processing Unit, posit format lightweight division arithmetic unit) unit in the CPU, where the PDPU performs division operation on data read out from the general register set according to an operation specified by an operation code. It is therefore also necessary to convert the read floating point data or fixed point data into posit format data before division is performed.
Wherein the posit format consists of mandatory sign bits(s), one or more region bits (r), a plurality of optional exponent bits (e) and a plurality of optional fraction bits (f). A posit numerical system is defined by 2 variables: n and es, where n represents the number of bits used in total, es represents the number of exponent bits that can be used most, and the position data format is of complete structure position < n, es >, as follows
One post format data p is:
where k represents the same number of bits in the region bits, es represents the number of exponent bits, and e represents an unsigned integer of the exponent bits.
In the data storage in the embodiment of the application, the main difference between the floating point number and the fixed point number is the setting of the position of the decimal point. The storage of fixed point decimal points in a computer is fixed, e.g. 23.125 is converted into binary, respectively by integer parts: 10111. fractional part: 001, in an 8-bit computer, 10111001, the decimal point defaults to the fifth bit. Floating point numbers represent larger values in the count method, e.g., 152.1875 converted to binary 10011000.0011, which in turn may be represented as 1.00110000011 ×2 7 Each of which includes a digit(s), an exponent (e), and a mantissa (m), is generally denoted as 000000000111000 … 00010110010001 in a 64-bit computer.
In one embodiment, the step of converting the floating point data into the posit format data may include extracting sign bits, exponents, and mantissas of the floating point data, respectively, using the sign bits as sign bits of the posit format data, converting the exponents into control bits of the posit format data through a predetermined encoder, and converting the mantissas into exponent bits and fraction bits of the posit format data through a right shifter.
Correspondingly, the step of converting the fixed-point data into the posit-format data may include extracting an integer and a fraction in the fixed-point data, respectively, converting the integer into a exponent of the posit-format data, and converting the fraction into a control bit and a fraction of the posit-format data.
102. And dividing the posit format data by a preset algorithm to obtain the operation result of the posit format.
Specifically, division operation is performed on the input position format data, and sign bits do not participate in operation. Assuming that the position format data a and b are provided, dividing the data a and b, wherein a is a dividend, b is a divisor, if a-b is a positive number, the quotient is 1, otherwise, the quotient is 0; then shifting the remainder and the quotient one bit to the left, subtracting a, and if the remainder is a negative number, the quotient is 0, otherwise, the quotient is 1; repeating the above steps until the remainder of the n+1th step is negative, and adding the absolute value of b to the remainder to obtain the correct remainder of the n+1th step.
103. And converting the operation result in the posit format into target floating point data or target fixed point data.
In one embodiment, after the operation is completed, the operation result may be converted back to the original data format. Specifically, the position format data is converted into floating point or fixed point data, the sign bit(s), the control bit region bits (r), the exponent bit (e) and the decimal bit (f) of the position data can be stored in different modules respectively, the sign bit(s) of the position format data corresponds to a floating point number sign bit, an exponent and a mantissa of the floating point number are obtained through 16-BIT REGMIE ENCODE, and the sign bit, the exponent and the mantissa are combined to obtain the final floating point number. The fixed point number only needs to convert the exponent bit into integer bit, the region bits and decimal bit (f) into decimal, and the conversion flow is the same as the floating point number.
In one embodiment, after the target floating point data or the target fixed point data is obtained, the target floating point data or the target fixed point data can be further used in subsequent calculation, such as calculating a compensation voltage in a system based on the target floating point data or the target fixed point data. Wherein, the system can be a motor system, in particular, in the running process of the motor, the bus current is increased, so that the power supply voltage is rapidly reduced, and the actual working V is realized d And V q The resulting bus voltage is different from the actual power supply bus voltage, and in order to reduce and eliminate errors in the bus voltage, when the PDPU unit is not employed, it is required to calculate by the following formula:
wherein U is d Is the equivalent voltage value of the motor on the d axis under the rotating coordinate system, U q Is the equivalent voltage value of the motor on the q axis under the rotating coordinate system, R is the equivalent resistance value of the motor under the rotating coordinate system, i d Is the equivalent current value of the motor on the d axis under the rotating coordinate system,and->Is the flux linkage component of the motor on the d-axis and the q-axis in the rotating coordinate system, ω is the angular velocity of the motor, +.>Is to->And (5) conducting derivation. By the method provided by the embodiment of the application, the circuit compensation precision requirement can be realized by adopting a "posit" format lightweight division arithmetic unit (PDPU). In vector control for Permanent Magnet Synchronous Motor (PMSM), voltage value U on d-axis d And for a voltage value U on the q-axis q The formula of (2) is as follows:
therefore, the PDPU unit is adopted to directly operate division in the formula, multiplication, addition and shift operations are not needed, so that the bus voltage of the motor system has instantaneity, voltage errors caused by too long operation time are reduced or eliminated, and the requirement of circuit voltage compensation precision is met.
In this way, the data processing method provided by the embodiment of the application can convert floating point data or fixed point data which needs to be subjected to a preset algorithm into posit format data, divide the posit format data by the preset algorithm to obtain a posit format operation result, and convert the posit format operation result into target floating point data or target fixed point data. According to the embodiment, the compatible division operation instruction can be integrated in the PIC single chip microcomputer, so that more complex data conversion and corresponding calculation can be realized, and the calculation efficiency is greatly improved.
In order to implement the above method, the embodiment of the present application further provides a processor, where the processor may be specifically integrated in a terminal device, such as a terminal, a tablet computer, or other devices.
For example, as shown in fig. 2, a schematic structure of a processor according to an embodiment of the present application is shown. The processor may include:
an address Fetch unit (Fetch) for taking the value of the register as the address of the processor and fetching the instruction from the instruction cache;
a Decode unit (Decode) to Decode the instruction and to determine a source operand of the instruction based on the decoded value;
an execution unit (execution) comprising a logic unit ALU for performing the corresponding calculations according to the type of instruction. In addition, the execution unit is integrated with an integrated division unit (PDPU) which is used for performing division operation;
a Memory unit (Memory) for accessing the data cache to obtain the operation result;
a commit unit (Commint) for writing the result of the operation into a general purpose register.
In the embodiment of the application, a five-stage pipeline structure is adopted by a central processing unit, and a lightweight division unit PDPU capable of supporting a posit format is added in an instruction execution stage for completing the lightweight division calculation of 16bits or 8 bits. The PDPU unit can be used for accelerating division operation in the system calculation process by adding a configuration instruction for the PDPU unit and a configuration algorithm thereof in a software compiling library.
With further continued reference to FIG. 3, the division unit (PDPU) may include
The first data conversion unit is used for converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
the division operation unit is used for carrying out division operation on the posit format data through a preset algorithm to obtain an operation result of the posit format;
and the second data conversion unit is used for converting the operation result in the posit format into target floating point data or target fixed point data.
In an embodiment, the division Unit may further include a Control Unit (Control Unit), where the Control Unit is respectively connected to the first data conversion Unit, the division Unit, and the second data conversion Unit. The control unit selects an operation data stream according to the executed division instruction and controls an operation mode of the posit-based lightweight division carrying out unit. The first data conversion unit may include fp32_p8, fp32_p16, FIX16_p16 and FIX16_p16 for completing floating point or fixed point data to posit format data conversion. The second data conversion unit may include p8_fp32, p16_fp32, p8_fix8, and p16_fix16 for completing the posit format data to floating point or fixed point data conversion. The division unit may be a div_p module.
Specifically, fp32_P8, F32_P16, FIX16_P16 and FIX16_P16 are data that convert floating point or fixed point data into posit format data. And respectively storing sign bits, indexes and mantissas of floating points into different modules, wherein the sign bits correspond to sign bits(s) of the posit format data, the index part obtains region bits of the posit format data through a 16-BIT POSITREGIME ENCODE module, the mantissa part obtains index bits (e) and decimal bits (f) of the posit format data through a RIGHT SHIFTER module, and finally, the final posit format data is obtained through a multiplexing module according to a posit data structure. The fixed point number only needs to convert an integer into a exponent bit, and the decimal point is converted into a region bits and a decimal bit (f), and the conversion flow is the same as that of the floating point number.
P8_fp32, p16_fp32, p8_fix8 and p16_fix16 are bits of symbols(s) of "posit" data, regions bits (r), exponent bits (e) and decimal bits (f) are stored in different modules, respectively, the bits(s) of posit format data are corresponding to floating point number bits, the exponent and mantissa of the floating point number are obtained by 16-BIT REGMIE ENCODE, and the sign bits, exponent and mantissa are combined to obtain the final floating point number. The fixed point number only needs to convert the exponent bit into integer bit, the region bits and decimal bit (f) into decimal, and the conversion flow is the same as the floating point number.
Further, the div_p module performs division operation on the input posit format data, and sign bits do not participate in the operation. Assuming that there are posit format data a and b, division operation is performed on a and b, a is a dividend, b is a divisor, subtraction operation of a and b exists in the operation, complement of a and b is required, addition operation is performed on the complement of a and b, if the difference is positive, the quotient is 1, otherwise, 0, the remainder and the quotient are moved one bit to the left, then the divisor is subtracted, when the remainder is negative, the quotient is 0, otherwise, 1, the operation is repeated, when the remainder of the n+1th step is negative, correct remainder of the n+1th step is required to be obtained by adding the absolute value of b, and the final result needs to pay attention to the remainder and the dividend to be the same as the number.
The technical scheme can finally complete the division operation function on the PIC chip with low cost, wherein the calculation delay can be reduced to 1/10 of the original PIC chip aiming at the operations requiring division operation such as voltage compensation and the like, and the operation precision can be improved by 50%.
In this way, the processor provided by the application can convert floating point data or fixed point data which needs to be subjected to a preset algorithm into position format data, divide the position format data by the preset algorithm to obtain a position format operation result, and convert the position format operation result into target floating point data or target fixed point data. According to the embodiment, the compatible division operation instruction can be integrated in the PIC single chip microcomputer, so that more complex data conversion and corresponding calculation can be realized, and the calculation efficiency is greatly improved.
Embodiments of the present application also provide a terminal, as shown in fig. 4, which may include a Radio Frequency (RF) circuit 601, a memory 602 including one or more computer readable storage media, an input unit 603, a display unit 604, a sensor 605, an audio circuit 606, a wireless fidelity (WiFi, wireless Fidelity) module 607, a processor 608 including one or more processing cores, and a power supply 609. It will be appreciated by those skilled in the art that the terminal structure shown in fig. 4 is not limiting of the terminal and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. Wherein:
the RF circuit 601 may be used for receiving and transmitting signals during a message or a call, and in particular, after receiving downlink information of a base station, the downlink information is processed by one or more processors 608; in addition, data relating to uplink is transmitted to the base station.
The memory 602 may be used to store software programs and modules, and the processor 608 may execute various functional applications and information processing by executing the software programs and modules stored in the memory 602. Accordingly, the memory 602 may also include a memory controller to provide access to the memory 602 by the processor 608 and the input unit 603.
The input unit 603 may be used to receive input numeric or character information and to generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control.
The display unit 604 may be used to display information input by a user or information provided to the user and various graphical user interfaces of the terminal, which may be composed of graphics, text, icons, video and any combination thereof.
The terminal may also include at least one sensor 605, such as a light sensor, a motion sensor, and other sensors.
The audio circuit 606 may transmit the received electrical signal converted from audio data to a speaker, which may be converted to a sound signal for output.
The WiFi belongs to a short-distance wireless transmission technology, and the terminal can help the user to send and receive e-mail, browse web pages, access streaming media and the like through the WiFi module 607, so that wireless broadband internet access is provided for the user. Although fig. 4 shows a WiFi module 607, it is understood that it does not belong to the essential constitution of the terminal, and can be omitted entirely as required within the scope of not changing the essence of the application.
The processor 608 is a control center of the terminal, and connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or executing software programs and/or modules stored in the memory 602, and calling data stored in the memory 602, thereby performing overall monitoring of the terminal. Optionally, the processor 608 may include one or more processing cores.
The terminal also includes a power supply 609 (e.g., a battery) for powering the various components, which may be logically connected to the processor 608 via a power management system so as to provide for managing charging, discharging, and power consumption by the power management system.
Specifically, in this embodiment, the processor 608 in the terminal loads executable files corresponding to the processes of one or more application programs into the memory 602 according to the following instructions, and the processor 608 executes the application programs stored in the memory 602, so as to implement various functions:
converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
dividing the posit format data by a preset algorithm to obtain a posit format operation result;
and converting the operation result in the posit format into target floating point data or target fixed point data.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the portions of a certain embodiment that are not described in detail may be referred to the above detailed description of the data processing method, which is not repeated herein.
As can be seen from the above, the terminal according to the embodiment of the present application may convert floating point data or fixed point data that needs to be subjected to a preset algorithm into posit format data, divide the posit format data by the preset algorithm to obtain a posit format operation result, and convert the posit format operation result into target floating point data or target fixed point data. According to the embodiment, the compatible division operation instruction can be integrated in the PIC single chip microcomputer, so that more complex data conversion and corresponding calculation can be realized, and the calculation efficiency is greatly improved.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.
To this end, an embodiment of the present application provides a storage medium having stored therein a plurality of instructions capable of being loaded by a processor to perform steps in any of the data processing methods provided by the embodiments of the present application. For example, the instructions may perform the steps of:
converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
dividing the posit format data by a preset algorithm to obtain a posit format operation result;
and converting the operation result in the posit format into target floating point data or target fixed point data.
The specific implementation of each operation above may be referred to the previous embodiments, and will not be described herein.
Wherein the storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.
The instructions stored in the storage medium may perform steps in any data processing method provided by the embodiments of the present application, so that the beneficial effects that any data processing method provided by the embodiments of the present application can be achieved, which are detailed in the previous embodiments and are not described herein.
The foregoing has described in detail a data processing method, a processor and a storage medium according to embodiments of the present application, and specific examples have been applied to illustrate the principles and embodiments of the present application, where the foregoing examples are only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (10)
1. A method of data processing, comprising:
converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
dividing the posit format data by a preset algorithm to obtain a posit format operation result;
and converting the operation result in the posit format into target floating point data or target fixed point data.
2. The data processing method of claim 1, wherein the step of converting floating point data into posit format data comprises:
extracting sign bits, exponents and mantissas in the floating point data respectively;
and taking the sign bit as the sign bit of the position format data, converting the exponent into a control bit of the position format data through a preset encoder, and converting the mantissa into the exponent bit and the decimal bit of the position format data through a right shifter.
3. The data processing method of claim 1, wherein the step of converting the fixed point data into posit format data comprises:
respectively extracting integers and decimal places in the fixed point data;
converting the integer into the exponent bit of the position format data, and converting the fraction into the control bit and the fraction bit of the position format data.
4. The method of claim 1, wherein dividing the posit format data by a preset algorithm to obtain a posit format operation result comprises:
dividing data a and b in a posit format, wherein a is a dividend, b is a divisor, if a-b is a positive number, the quotient is 1, otherwise, the quotient is 0;
shifting the remainder and the quotient one bit to the left, subtracting a, and if the remainder is a negative number, the quotient is 0, otherwise, the quotient is 1;
repeating the above steps until the remainder of the n+1th step is negative, and adding the absolute value of b to the remainder to obtain the correct remainder of the n+1th step.
5. The data processing method of claim 1, wherein the method further comprises:
calculating a compensation voltage in the system based on the target floating point data or the target fixed point data, wherein when calculating the compensation voltage in the system, the following formula is used:
wherein U is d Is the equivalent voltage value of the motor on the d axis under the rotating coordinate system, R is the equivalent resistance value of the motor under the rotating coordinate system, i d Is the equivalent current value of the motor on the d axis under the rotating coordinate system,and->Is the flux linkage component of the motor on the d-axis and the q-axis in the rotating coordinate system, ω is the angular velocity of the motor, +.>Is to->And (5) conducting derivation.
6. A processor, comprising:
the address taking unit is used for taking the value of the register as the address of the processor and acquiring an instruction from the instruction cache;
the decoding unit is used for decoding the instruction and determining a source operand of the instruction according to the decoding value;
the execution unit is used for executing corresponding calculation according to the type of the instruction, an integrated division unit is integrated in the execution unit, and the division unit is used for performing division operation;
the access unit is used for accessing the data cache to obtain an operation result;
and the submitting unit is used for writing the operation result into a general register.
7. The processor of claim 6, wherein the division unit comprises
The first data conversion unit is used for converting floating point data or fixed point data which need to be subjected to a preset algorithm into position format data;
the division operation unit is used for carrying out division operation on the posit format data through a preset algorithm to obtain an operation result of the posit format;
and the second data conversion unit is used for converting the operation result in the posit format into target floating point data or target fixed point data.
8. The processor of claim 6, wherein,
the division unit is configured according to a configuration instruction and a configuration algorithm by adding the configuration instruction and the configuration algorithm in a software compiling library in advance.
9. The processor of claim 8, wherein the configuration instructions comprise:
fcvt.s.p8 for converting single-precision floating point data into 8bits Posit data;
fcvt.p8.s for converting 8bits Posit data into single precision floating point numbers;
fcvt.s.p16 for converting single precision floating point data into 16bits Posit data;
fcvt.p16.s for converting 16bits Posit data into single precision floating point data;
FXCVT.H.P8 for converting fixed point data into 8bits Posit data;
fxcvt.p8.h for converting 8bits Posit data into fixed point data;
FXCVT.W.P16 for converting fixed point data into 16bits of Posit data;
fxcvt.p16.w for converting 16bits Posit into data fixed point data;
p16.div for 16bits Posit data division operations;
and P8.DIV, which is used for 8bits Posit data division operation.
10. A storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the data processing method of any one of claims 1 to 5.
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