CN106997284B - Method and device for realizing floating point operation - Google Patents
Method and device for realizing floating point operation Download PDFInfo
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- CN106997284B CN106997284B CN201710161711.0A CN201710161711A CN106997284B CN 106997284 B CN106997284 B CN 106997284B CN 201710161711 A CN201710161711 A CN 201710161711A CN 106997284 B CN106997284 B CN 106997284B
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Abstract
The invention provides a method and a device for realizing floating-point operation. The method comprises the following steps: receiving a floating-point operation instruction, wherein the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates the precision of a processing result of the floating-point operation; performing cyclic floating-point operation processing on the source operand corresponding to the source operand information according to the operation precision requirement information until the floating-point operation processing result meets the precision; and acquiring a floating point operation processing result according to an intermediate floating point value obtained by floating point operation processing in each circulation before the precision requirement is met. The method for realizing the floating-point operation can execute any number of cycles, save execution time and reduce power consumption.
Description
Technical Field
The present invention relates to the field of floating point operations, and in particular, to a method and an apparatus for implementing a floating point operation.
Background
As the demand of users increases, the requirements of the users on the performance of the computer are higher and higher, and the performance of the floating point operation is used as a basic module for processing data of the computer and determines the performance of the computer.
The existing floating-point division operation, floating-point evolution operation, fixed-point division operation and fixed-point remainder operation usually adopt a redundant number iterative algorithm (SRT algorithm). However, floating point numbers or floating point numbers converted from fixed point operands basically adopt single-precision and double-precision formats specified in IEEE754-2008, and therefore, when the SRT algorithm is used for calculation, only a fixed number of cycles can be performed. For example, with the base 2 SRT algorithm, each time a 2-bit quotient digit is calculated, single-precision floating-point operations typically require 12 iterations to calculate a 24-bit significand, while double-precision floating-point operations typically require 20 iterations to calculate a 53-bit significand.
When the precision requirement of a user on data is low, the existing SRT algorithm consumes a long time when executing division operation every time, a part of results which are not needed by the user are calculated, and the performance of the whole application is reduced. Therefore, the existing SRT algorithm can only execute a fixed number of cycles, resulting in poor computational flexibility, increased execution time, increased power consumption, and resource waste.
Disclosure of Invention
The invention provides a method and a device for realizing floating point operation, which are used for solving the problems of increased execution time, increased power consumption and resource waste caused by the fact that only fixed times of circulation can be executed in the conventional floating point operation.
One aspect of the present invention provides a method for implementing floating point operation, including:
receiving a floating-point operation instruction, wherein the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates the precision of a processing result of the floating-point operation;
performing cyclic floating-point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until the floating-point operation processing result meets the precision;
and acquiring a floating point operation processing result according to a middle floating point value obtained by the floating point operation processing in each circulation before the requirement of the precision is met.
The method for implementing a floating-point operation as described above, where performing a circular floating-point operation on a source operand corresponding to the source operand information according to the operation precision requirement information until a result of the floating-point operation processing satisfies the precision, includes:
according to the floating-point operation instruction, setting the cycle number to be 0, performing floating-point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder, adding 1 to the cycle number to obtain a new cycle number, and judging whether the new cycle number is consistent with the operation precision requirement information;
if not, the floating point operation processing is carried out on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, the cycle number is added by 1 again to obtain a new cycle number, whether the new cycle number is consistent with the operation precision requirement information or not is judged again, and if not, the step is repeatedly executed on the new intermediate remainder until the new cycle number is consistent with the operation precision requirement information.
In the method for implementing floating point operation as described above, the operation precision requirement information includes a preset floating point operation processing result precision value; the determining whether the new cycle number is consistent with the operation precision requirement information includes:
acquiring a preset cycle number according to the precision value of the preset floating point operation processing result, and judging whether the new cycle number is consistent with the preset cycle number or not; alternatively, the first and second electrodes may be,
the operation precision requirement information comprises preset cycle times; the determining whether the new cycle number is consistent with the operation precision requirement information includes:
and judging whether the new cycle times are consistent with the preset cycle times or not.
The method for implementing floating-point operation as described above, after receiving the floating-point operation instruction, the method further comprising:
and acquiring the precision of a floating point operation processing result as the operation precision requirement information according to the source operand information.
As described above, in the method for implementing a floating-point operation, the floating-point operation instruction indicates that the source operand information is specifically: address information indicating a first register storing the source operand; after the receiving the floating-point operation instruction, the method further comprises:
and reading a first register according to address information of the first register which is indicated by the floating point operation instruction and used for storing the source operand, and acquiring the source operand.
In the method for implementing floating-point operation as described above, if the floating-point operation instruction further indicates that the floating-point operation processing is division, the source operand includes a divisor and a dividend; the performing the floating-point operation on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder includes:
performing the floating point operation processing on the intermediate remainder and the divisor to obtain a new intermediate quotient and a new intermediate remainder;
if the floating-point operation instruction also indicates that the floating-point operation processing is square, the source operand includes a number of squares, and the intermediate quotient is a square root of the middle.
The method for implementing a floating-point operation as described above, where the obtaining a floating-point operation processing result according to an intermediate floating-point value obtained by processing the floating-point operation in each cycle before the requirement of precision is met, includes:
and normalizing according to the intermediate quotient obtained by the floating-point operation processing in each cycle before the requirement of the precision is met to obtain the floating-point operation processing result.
In the method for implementing a floating-point operation as described above, the floating-point operation instruction further indicates address information of a second register storing the intermediate quotient;
the method further comprises the following steps: storing the intermediate quotient obtained after each floating point operation processing in the second register;
correspondingly, the obtaining a floating-point operation processing result according to an intermediate floating-point value obtained by the floating-point operation processing in each cycle before the requirement of the precision is met includes:
and reading the second register to obtain the floating-point operation processing result.
Another aspect of the present invention is to provide an apparatus for implementing a floating point operation, which is used to execute the method for implementing a floating point operation in the foregoing embodiments, and has the same technical features and technical effects, which are not described herein again.
The invention provides a device for realizing floating-point operation, which comprises: the device comprises a receiving module, a circulating floating point operation processing module and an output module;
the receiving module is configured to receive a floating-point operation instruction, where the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates precision of a floating-point operation processing result;
the cyclic floating-point operation processing module is configured to perform cyclic floating-point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until the floating-point operation processing result meets the precision;
and the output module is used for acquiring a floating point operation processing result according to an intermediate floating point value obtained by the floating point operation processing in each circulation before the requirement of the precision is met.
The apparatus for implementing floating point operation as described above, the circular floating point operation processing module includes: the device comprises an input unit, a cycle control unit and a floating point operation processing unit;
the input unit is used for receiving a source operand corresponding to the source operand information and sending the source operand to the floating-point operation processing unit;
the cycle control unit is used for receiving the operation precision requirement information, setting the cycle number to be 0 and sending a first operation signal to the floating-point operation processing unit; the operation precision requirement information indicates the precision of a floating point operation processing result;
the floating-point operation processing unit is used for performing floating-point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder when receiving the first operation signal, sending a completion signal to the cycle control unit, sending the intermediate quotient to the output module, and sending the intermediate remainder to the input unit;
the cycle control unit is further used for adding 1 to the cycle times to obtain new cycle times when the completion signal is received, and judging whether the new cycle times are consistent with the operation precision requirement information or not; if the output signals are consistent with the preset output signals, sending an end signal to the output module; if the two signals are not consistent, a second operation signal is sent to the floating-point operation processing unit;
the input unit is further used for sending the intermediate remainder to the floating-point operation processing unit when receiving the intermediate remainder;
the floating-point operation processing unit is further configured to, when receiving the second operation signal, perform floating-point operation processing on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send the completion signal to the cycle control unit, send the new intermediate quotient to the output module, and send the new intermediate remainder to the input unit.
The apparatus for implementing floating point operation as described above, where the operation precision requirement information includes a preset floating point operation processing result precision value; the loop control unit is specifically configured to,
acquiring a preset cycle number according to the precision value of the preset floating point operation processing result, and judging whether the new cycle number is consistent with the preset cycle number or not; and/or the like, and/or,
the operation precision requirement information comprises preset cycle times; the loop control unit is specifically configured to,
and judging whether the new cycle times are consistent with the preset cycle times or not.
The apparatus for implementing floating-point operation as described above, the circular floating-point operation processing module is specifically configured to,
and acquiring the precision of a floating point operation processing result as the operation precision requirement information according to the source operand information.
In the apparatus for implementing floating-point operation described above, the floating-point operation instruction indicates that the source operand information is specifically: address information indicating a first register storing the source operand; the cyclic floating-point operation processing module is specifically configured to,
and reading a first register according to address information of the first register which is indicated by the floating point operation instruction and used for storing the source operand, and acquiring the source operand.
In the apparatus for implementing floating-point operation as described above, if the floating-point operation instruction further indicates that the floating-point operation processing is division, the source operand includes a divisor and a dividend;
correspondingly, the input unit is further configured to send the intermediate remainder and the source operand to the floating-point operation processing unit when receiving the intermediate remainder;
the floating-point operation processing unit is further configured to, when receiving the second operation signal, perform floating-point operation processing on the source operand and the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send the completion signal to the loop control unit, send the new intermediate quotient to the output module, and send the new intermediate remainder to the input unit;
if the floating-point operation instruction also indicates that the floating-point operation processing is square, the source operand includes a number of squares, and the intermediate quotient is a square root of the middle.
The apparatus for implementing floating-point operation as described above, the output module is specifically configured to,
and when an end signal is received, normalizing all the received intermediate quotients to obtain the floating point operation processing result.
The apparatus for implementing a floating-point operation as described above, the floating-point operation instruction further indicating address information of a second register storing the intermediate quotient;
the output module is specifically configured to store the received intermediate quotient in the second register; and when an end signal is received, reading the second register to obtain the floating-point operation processing result.
Another aspect of the present invention provides a processor including the apparatus for performing floating point operations as described above.
According to the method and the device for realizing the floating point operation, the operation precision requirement information is added, whether the precision of the floating point operation processing result meets the precision indicated in the operation precision requirement information is judged firstly in the process of circulating the floating point operation processing, and the circulation is stopped under the condition that the precision meets the requirement, so that the floating point operation method can execute the circulation for any number of times, the execution time is saved, and the power consumption is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a flowchart illustrating a first embodiment of a method for performing floating-point operations according to the present invention;
FIG. 2 is a schematic diagram illustrating a first embodiment of an apparatus for performing floating-point operations according to the present invention;
FIG. 3 is a schematic structural diagram of a second apparatus for implementing floating-point operation according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart illustrating a first method for implementing a floating-point operation according to an embodiment of the present invention, and as shown in fig. 1, an embodiment of the present invention provides a method for implementing a floating-point operation, where an execution main body of the method is a device for implementing a floating-point operation, and the device may be implemented by software or hardware, which is not limited in the present invention. The method comprises the following steps:
s101, receiving a floating-point operation instruction, wherein the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates the precision of a floating-point operation processing result;
s102, performing circulating floating point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until a floating point operation processing result meets the precision;
s103, acquiring a floating point operation processing result according to a middle floating point value obtained by floating point operation processing in each circulation before the requirement of precision is met.
As will be appreciated by those skilled in the art, a floating-point operation instruction is used to instruct a floating-point operation to be performed to obtain a floating-point operation result. The process of floating-point operation processing includes cyclic floating-point operation processing, that is, a plurality of floating-point operation processing constitutes floating-point operation processing. The number of times of execution of the floating-point operation processing depends on the precision of the result of the floating-point operation processing indicated by the floating-point operation instruction.
The floating-point arithmetic processing can be a floating-point division operation or a floating-point evolution operation, and can also extend the floating-point division operation to a fixed-point division operation and a fixed-point remainder operation by adding a preprocessing module and a post-processing module in the device for realizing the floating-point arithmetic operation. For example, for fixed-point division operation, an input fixed-point divisor and dividend may be converted into a floating-point number by a preprocessing module, and then the floating-point operation is performed by using the method for implementing floating-point operation provided in the embodiment of the present invention. The following embodiments of the present invention are described in the context of floating point operations.
Specifically, in S101, a floating-point operation instruction is received, where the floating-point operation instruction indicates source operand information indicating a source operand to be subjected to a floating-point operation. Illustratively, when the floating-point operation is a division operation, the source operands include a divisor and a dividend. Optionally, the source operands further comprise a cardinality of the SRT algorithm. Illustratively, when the floating-point operation is an open-square operation, the source operands include an open-square number. The floating-point operation instruction further indicates operation precision requirement information indicating precision of a result processed by the floating-point operation. The accuracy can be set by the user as desired.
Optionally, after S101, a source operand detecting step is further included, configured to detect whether the source operand is legal. Illustratively, when the floating-point operation is a division operation, the divisor in the source operand cannot be 0. And suspending floating point operations and issuing warning information when illegal source operands are detected. For example, the operation result may be directly output when the source operand is detected to be a certain number. For example, when the dividend is 0, the floating point operation result is directly output as 0.
Specifically, in S102, the cyclic floating-point operation processing is performed on the source operand corresponding to the source operand information until the floating-point operation processing result satisfies the precision.
Illustratively, the processing of the circular floating-point operation specifically includes:
s1021, according to the floating point operation instruction, setting the cycle number to be 0, performing floating point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder, adding 1 to the cycle number to obtain a new cycle number, and judging whether the new cycle number is consistent with the operation precision requirement information or not; if not, go to S1022; if yes, executing S103;
and S1022, performing floating point operation on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, adding 1 to the cycle number again to obtain a new cycle number, judging whether the new cycle number is consistent with the operation precision requirement information again, and if not, repeating the step on the new intermediate remainder until the new cycle number is consistent with the operation precision requirement information.
Specifically, when a floating-point operation instruction is received, the counter is first set to 0, and the count of the counter is the number of cycles. And then, carrying out floating point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder, and adding 1 to the cycle number to obtain a new cycle number. And judging whether the new cycle number is consistent with the operation precision requirement information or not.
And when the new cycle number is inconsistent with the operation precision requirement information, indicating that the precision of the floating-point operation processing result does not meet the requirement desired by the user, performing floating-point operation processing on the intermediate remainder and the source operand again to obtain a new intermediate quotient and a new intermediate remainder. And adding 1 to the cycle number again to obtain a new cycle number, and judging whether the new cycle number is consistent with the operation precision requirement information again. When the new cycle number is not consistent with the operation precision requirement information, the step is repeatedly executed for the new intermediate remainder until the new cycle number is consistent with the operation precision requirement information.
And when the new cycle number is consistent with the operation precision requirement information, the precision of the floating point operation processing result is shown to meet the requirement desired by the user. At this time, the cyclic floating-point operation processing may be stopped, and the floating-point operation processing result may be obtained from the intermediate quotient obtained at each cycle.
Specifically, in S103, when the floating point operation processing result satisfies the precision, the loop is stopped, and the floating point operation processing result is obtained according to an intermediate floating point value, such as an intermediate quotient, obtained by processing each floating point operation.
It should be noted that the intermediate floating-point value obtained by the floating-point operation processing in each cycle before the requirement of precision is satisfied in S103 includes both the intermediate floating-point value obtained by the floating-point operation processing in each cycle before and the intermediate floating-point value obtained by the floating-point operation processing in this time. That is, when the number of cycles is consistent with the operation precision requirement information, the intermediate floating point value obtained in the last cycle is also included.
According to the method for realizing the floating point operation, the operation precision requirement information is added, whether the precision of the floating point operation processing result meets the precision indicated in the operation precision requirement information is judged firstly in the process of circulating the floating point operation processing, and the circulation is stopped under the condition that the precision is met, so that the floating point operation method can execute the circulation for any number of times, the execution time is saved, and the power consumption is reduced.
Optionally, based on the embodiment shown in fig. 1, specific contents of the operation accuracy requirement information are described in detail. The operation precision requirement information can be exemplarily implemented in the following three possible implementations:
a first possible implementation:
the operation precision requirement information comprises a preset floating point operation processing result precision value; at this time, judging whether the new cycle number is consistent with the operation precision requirement information specifically includes:
and acquiring a preset cycle number according to the precision value of the preset floating point operation processing result, and judging whether the new cycle number is consistent with the preset cycle number.
For example, when the operation precision requirement information includes a preset floating point operation processing result precision value, a preset cycle number needs to be obtained according to the preset floating point operation processing result precision value. After the preset number of cycles is acquired, it is possible to compare whether the number of cycles obtained after each cycle reaches the preset number of cycles.
A second possible implementation:
the operation accuracy requirement information may directly include the preset number of cycles. At this time, judging whether the new cycle number is consistent with the operation precision requirement information specifically includes:
and judging whether the new cycle times are consistent with the preset cycle times or not.
A third possible implementation:
and acquiring the precision of the floating point operation processing result as operation precision requirement information according to the source operand information.
For example, after receiving the floating-point operation instruction, the precision of the floating-point operation processing result may be obtained according to the source operand corresponding to the source operand information indicated by the floating-point operation instruction. For example, the precision of the source operand is obtained, and the precision of the source operand is used as the precision of the floating point operation processing result, that is, the precision indicated by the operation precision requirement information.
For example, when the source operand is received, the preset loop number may be obtained directly according to the source operand. The manner of obtaining the preset cycle number is specifically as follows:
assuming that the dividend in the source operand is A, the divisor is B, A and B are both m-bit unsigned numbers, m is a positive integer greater than 1, and A is divided by B to obtain an unsigned number. Assuming that a is 00 … 01 …, the number of leading 0 s of a (0 before the first appearing 1 is leading 0) is recorded as za; b is 000 … 01 … and zb is the number of leader 0 s of B.
Then according to
Obtaining a preset cycle number, wherein 1.a is multiplied by 2m-za-1Is a scientific notation of A, 1.b × 2m-zb-1Is the scientific notation of B.
(1) When za > zb, the result is definitely 0, and thus it can be known that the preset number of cycles is 0.
(2) When za ═ zb, if a > ═ b, the preset cycle number is 1; if a < b, the preset number of cycles is 0.
(3) When za<zb, if a>B, the resulting quotient is zb-za +1, so the predetermined number of cycles is
Secondly; if a is<b, the obtained quotient is zb-za bit, and the preset cycle number is
Next, the process is carried out. Wherein the content of the first and second substances,
means to obtain the smallest integer greater than or equal to x.
Exemplarily, when the floating-point operation method provided by the embodiment of the present invention is applied to perform a floating-point operation:
single precision division floating point arithmetic cycle when the quotient determined from the source operands is greater than a predetermined value (i.e., the quotient is a normalized floating point number)
Double-precision division floating-point operation cycle
And (ii) where r is the cardinality of the SRT algorithm.
When the quotient determined from the source operand is less than a predetermined number (i.e., the quotient is a denormalized floating point number), it is assumed that the calculated quotient is 1.c × 2expWhere c is the fractional part of the quotient, the exponent offset bias is 1023 for floating point numbers in double precision format and 127 for floating point numbers in single precision format, and to convert the result of the floating point operation directly to a non-normalized floating point number gridDue to 1. c.times.2exp＝1.c×2exp+bias-1×2-bias+1And exp<Bias +1, so 1.c needs to be shifted to the right by | exp + bias-1| bits. The number of quotient significands in the result is therefore: the double precision is 53- | exp + bias-1| bits, and the single precision is 24- | exp + bias-1| bits. Thus the preset number of cycles for double precision is
Next, the process is carried out. The preset cycle number is as follows when the single precision is
Further, in any of the above embodiments, the floating-point operation instruction indicates that the source operand information is: address information indicating a first register storing a source operand; after receiving the floating-point operation instruction, the method further comprises:
and reading the first register according to the address information of the first register for storing the source operand indicated by the floating point operation instruction, and acquiring the source operand.
For example, the source operand information indicated in the instruction of the floating-point operation is a storage address of the source operand, that is, address information of a first register storing the source operand. Thereby reducing the length of floating-point operation instructions.
Optionally, if the floating-point operation instruction further indicates that the floating-point operation is processed as division, the source operands include a divisor and a dividend. And carrying out floating point operation processing on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, wherein the floating point operation processing comprises the following steps:
and carrying out floating point operation processing on the intermediate remainder and the divisor to obtain a new intermediate quotient and a new intermediate remainder.
When division floating-point operation is carried out, when division is carried out in the first cycle, the intermediate quotient and the intermediate remainder are obtained according to source operation, and in each cycle, a new intermediate quotient and a new intermediate remainder are obtained according to the divisor and the intermediate remainder.
Optionally, if the floating-point operation instruction further indicates that the floating-point operation processing is square, the source operand includes a square root and the intermediate quotient is the intermediate square root.
Optionally, on the basis of any of the above embodiments, obtaining a floating-point operation processing result according to an intermediate floating-point value obtained by processing a floating-point operation in each cycle before meeting a precision requirement includes:
and normalizing according to the intermediate quotient obtained by the floating point operation processing in each cycle before the precision requirement is met to obtain a floating point operation processing result.
Illustratively, the floating-point operation processing result is obtained by performing normalization processing according to the intermediate quotient obtained by processing each cycle of the floating-point operation. All the intermediate quotients are arranged from front to back, and then symbol information, exponent information and the like are combined to obtain a floating point operation processing result.
Optionally, in combination with the foregoing embodiment, the floating-point operation instruction further indicates address information of a second register storing the intermediate quotient; the method for implementing the floating-point operation further comprises the following steps: storing the intermediate quotient obtained after each floating point operation in a second register;
correspondingly, obtaining a floating-point operation processing result according to an intermediate floating-point value obtained by floating-point operation processing in each cycle before the requirement of precision is met, including:
and reading the second register to obtain a floating-point operation processing result.
For example, the floating-point operation instruction may also indicate address information of a second register storing the intermediate quotient. When the intermediate quotient is obtained in each cycle, the intermediate quotient is stored in the second register, so that the floating point operation processing result can be directly read from the second register after the cycle is finished. The number of bits of the second register can be determined according to the operation precision requirement information.
In another aspect, the present invention provides an apparatus for implementing a floating-point operation, which is used to execute the method for implementing a floating-point operation in the foregoing embodiments, and has the same technical features and technical effects.
FIG. 2 is a schematic structural diagram of a first embodiment of an apparatus for implementing floating-point operation according to the present invention. As shown in fig. 2, the floating-point operator includes: a receiving module 201, a cyclic floating point operation processing module 202 and an output module 203;
the receiving module 201 is configured to receive a floating-point operation instruction, where the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates precision of a floating-point operation processing result;
the circular floating-point operation processing module 202 is configured to perform circular floating-point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until a floating-point operation processing result meets precision;
and the output module 203 is configured to obtain a floating point operation processing result according to an intermediate floating point value obtained by processing the floating point operation in each cycle before the precision requirement is met.
Optionally, on the basis of the embodiment shown in fig. 2, fig. 3 is a schematic structural diagram of a second embodiment of the apparatus for implementing floating-point operation provided by the present invention. As shown in fig. 3, the cyclic floating point operation processing module 202 includes: an input unit 2021, a cycle control unit 2022, and a floating-point arithmetic operation processing unit 2023;
the input unit 2021 is configured to receive a source operand corresponding to the source operand information, and send the source operand to the floating-point operation processing unit;
the cycle control unit 2022 is configured to receive the operation precision requirement information, set the cycle number to 0, and send a first operation signal to the floating point operation processing unit; the operation precision requirement information indicates the precision of the floating point operation processing result;
the floating-point operation processing unit 2023 is configured to, when receiving the first operation signal, perform floating-point operation on the source operand to obtain an intermediate quotient and an intermediate remainder, send a completion signal to the loop control unit 2022, send the intermediate quotient to the output module 203, and send the intermediate remainder to the input unit 2021;
the cycle control unit 2022 is further configured to, when receiving the completion signal, add 1 to the cycle count to obtain a new cycle count, and determine whether the new cycle count is consistent with the operation accuracy requirement information; if the two signals are consistent, an end signal is sent to the output module 203; if not, a second operation signal is sent to the floating-point operation processing unit 2023;
the input unit 2021 is further configured to, when receiving the intermediate remainder, send the intermediate remainder to the floating-point operation processing unit 2023;
the floating-point operation processing unit 2023 is further configured to, when receiving the second operation signal, perform floating-point operation on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send a completion signal to the loop control unit 2022, send the new intermediate quotient to the output module 203, and send the new intermediate remainder to the input unit 2021.
After the loop control unit 2022 sends the end signal to the output module 203, the floating-point operation processing is ended this time, and the loop control unit 2022 does not send the second operation signal to the floating-point operation processing unit 2023 any more.
Optionally, the operation precision requirement information includes a preset floating point operation processing result precision value; the loop control unit 2022 is used in particular for,
acquiring a preset cycle number according to the precision value of the preset floating point operation processing result, and judging whether the new cycle number is consistent with the preset cycle number or not; and/or the like, and/or,
the operation precision requirement information comprises a preset cycle number; the loop control unit 2022 is used in particular for,
and judging whether the new cycle times are consistent with the preset cycle times or not.
Optionally, the circular floating-point operation processing module 202 is specifically configured to,
and acquiring the precision of the floating point operation processing result as operation precision requirement information according to the source operand information.
Optionally, the floating-point operation instruction indicates that the source operand information is specifically: address information indicating a first register storing a source operand; the circular floating-point operation processing module 202 is specifically configured to,
and reading the first register according to the address information of the first register for storing the source operand indicated by the floating point operation instruction, and acquiring the source operand.
Optionally, if the floating-point operation instruction further indicates that the floating-point operation processing is division, the source operand includes a divisor and a dividend;
correspondingly, the input unit 2021 is further configured to, when receiving the intermediate remainder, send the intermediate remainder and the source operand to the floating-point operation processing unit 2023;
the floating-point operation processing unit 2023 is further configured to, when receiving the second operation signal, perform floating-point operation on the source operand and the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send a completion signal to the loop control unit 2022, send the new intermediate quotient to the output module 203, and send the new intermediate remainder to the input unit 2021;
if the floating-point operation instruction also indicates that the floating-point operation processing is an open party, the source operand includes an open party number and the intermediate quotient is an intermediate square root.
Optionally, the output module 203 is specifically configured to,
and when the ending signal is received, normalizing all the received intermediate quotients to obtain a floating point operation processing result.
Optionally, the floating-point operation instruction further indicates address information of a second register storing the intermediate quotient;
the output module is specifically used for storing the received intermediate quotient in the second register; and when receiving the end signal, reading the second register to obtain the floating point operation processing result.
Another aspect of the invention provides a processor including an apparatus for performing floating point operations as shown in FIG. 2 or FIG. 3.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1.A method for performing floating point operations, comprising:
receiving a floating-point operation instruction, wherein the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates the precision of a processing result of the floating-point operation; the source operand information is address information of a first register for storing the source operand;
reading the first register according to the address information of the first register to obtain the source operand;
performing cyclic floating-point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until the floating-point operation processing result meets the precision;
acquiring a floating point operation processing result according to a middle floating point value obtained by the floating point operation processing in each circulation before the requirement of the precision is met; the operation precision requirement information comprises a preset cycle number, the source operands comprise dividends and divisors, and the method further comprises the following steps:
acquiring the preset cycle times according to the number of leading 0 s in the dividend and the number of leading 0 s in the divisor;
the obtaining the preset cycle number according to the number of leading 0 s in the dividend and the number of leading 0 s in the divisor includes:
wherein A is dividend in the source operand, B is divisor in the source operand, A and B are unsigned numbers with m bits, m is positive integer greater than 1, 1.a x 2m-za-1Is a binary representation of A, 1.b × 2m-zb-1In a binary representation of B, za is the number of leading 0 s in the dividend, and zb is the number of leading 0 s in the divisor;
when za is greater than zb, the preset cycle number is 0;
when za ═ zb, if a > ═ b, the preset cycle number is 1; if a is less than b, the preset cycle number is 0;
when za<zb, if a>B, the preset cycle number is
Secondly; if a is<b, the preset cycle number is
Secondly; wherein the content of the first and second substances,
the minimum integer greater than or equal to x is obtained, and r is the base number of the redundancy iteration algorithm.
2. The method according to claim 1, wherein performing a circular floating-point operation on a source operand corresponding to the source operand information according to the operation precision requirement information until a result of the floating-point operation processing satisfies the precision comprises:
according to the floating-point operation instruction, setting the cycle number to be 0, performing floating-point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder, adding 1 to the cycle number to obtain a new cycle number, and judging whether the new cycle number is consistent with the operation precision requirement information;
if not, the floating point operation processing is carried out on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, the cycle number is added by 1 again to obtain a new cycle number, whether the new cycle number is consistent with the operation precision requirement information or not is judged again, and if not, the step is repeatedly executed on the new intermediate remainder until the new cycle number is consistent with the operation precision requirement information.
3. The method of claim 2,
the operation precision requirement information comprises preset cycle times; the determining whether the new cycle number is consistent with the operation precision requirement information includes:
and judging whether the new cycle times are consistent with the preset cycle times or not.
4. The method of claim 1, wherein after said receiving a floating-point operation instruction, the method further comprises:
and acquiring the precision of a floating point operation processing result as the operation precision requirement information according to the source operand information.
5. The method of claim 2 or 3, wherein if the floating-point operation instruction further indicates that the floating-point operation processing is division, the source operands comprise a divisor and a dividend; the performing the floating-point operation on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder includes:
performing the floating point operation processing on the intermediate remainder and the divisor to obtain a new intermediate quotient and a new intermediate remainder;
if the floating-point operation instruction also indicates that the floating-point operation processing is square, the source operand includes a number of squares, and the intermediate quotient is a square root of the middle.
6. The method according to claim 2 or 3, wherein the obtaining of the floating-point operation processing result according to the intermediate floating-point value obtained by the floating-point operation processing in each cycle before the requirement of precision is met comprises:
and normalizing according to the intermediate quotient obtained by the floating-point operation processing in each cycle before the requirement of the precision is met to obtain the floating-point operation processing result.
7. The method of claim 2 or 3, wherein the floating-point operation instruction further indicates address information of a second register storing the intermediate quotient;
the method further comprises the following steps: storing the intermediate quotient obtained after each floating point operation processing in the second register;
correspondingly, the obtaining a floating-point operation processing result according to an intermediate floating-point value obtained by the floating-point operation processing in each cycle before the requirement of the precision is met includes:
and reading the second register to obtain the floating-point operation processing result.
8. An apparatus for performing floating point arithmetic operations, comprising: the device comprises a receiving module, a circulating floating point operation processing module and an output module;
the receiving module is configured to receive a floating-point operation instruction, where the floating-point operation instruction indicates source operand information and operation precision requirement information, and the operation precision requirement information indicates precision of a floating-point operation processing result; the source operand information is address information of a first register for storing the source operand;
reading the first register according to the address information of the first register to obtain the source operand;
the cyclic floating-point operation processing module is configured to perform cyclic floating-point operation processing on a source operand corresponding to the source operand information according to the operation precision requirement information until the floating-point operation processing result meets the precision;
the output module is used for acquiring a floating point operation processing result according to an intermediate floating point value obtained by the floating point operation processing in each circulation before the requirement of the precision is met;
the operation precision requirement information comprises preset cycle times, the source operand comprises a dividend and a divisor, and the cycle floating point operation processing module is further configured to:
acquiring the preset cycle times according to the number of leading 0 s in the dividend and the number of leading 0 s in the divisor;
the obtaining the preset cycle number according to the number of leading 0 s in the dividend and the number of leading 0 s in the divisor includes:
wherein A is dividend in the source operand, B is divisor in the source operand, A and B are unsigned numbers with m bits, m is positive integer greater than 1, 1.a x 2m-za-1Is a binary representation of A, 1.b × 2m-zb-1In a binary representation of B, za is the number of leading 0 s in the dividend, and zb is the number of leading 0 s in the divisor;
when za is greater than zb, the preset cycle number is 0;
when za ═ zb, if a > ═ b, the preset cycle number is 1; if a is less than b, the preset cycle number is 0;
when za<zb, if a>B, the preset cycle number is
Secondly; if a is<b, the preset cycle number is
Secondly; wherein the content of the first and second substances,
the minimum integer greater than or equal to x is obtained, and r is the base number of the redundancy iteration algorithm.
9. The apparatus of claim 8, wherein the circular floating-point operation processing module comprises: the device comprises an input unit, a cycle control unit and a floating point operation processing unit;
the input unit is used for receiving a source operand corresponding to the source operand information and sending the source operand to the floating-point operation processing unit;
the cycle control unit is used for receiving the operation precision requirement information, setting the cycle number to be 0 and sending a first operation signal to the floating-point operation processing unit; the operation precision requirement information indicates the precision of a floating point operation processing result;
the floating-point operation processing unit is used for performing floating-point operation processing on the source operand to obtain an intermediate quotient and an intermediate remainder when receiving the first operation signal, sending a completion signal to the cycle control unit, sending the intermediate quotient to the output module, and sending the intermediate remainder to the input unit;
the cycle control unit is further used for adding 1 to the cycle times to obtain new cycle times when the completion signal is received, and judging whether the new cycle times are consistent with the operation precision requirement information or not; if the output signals are consistent with the preset output signals, sending an end signal to the output module; if the two signals are not consistent, a second operation signal is sent to the floating-point operation processing unit;
the input unit is further used for sending the intermediate remainder to the floating-point operation processing unit when receiving the intermediate remainder;
the floating-point operation processing unit is further configured to, when receiving the second operation signal, perform floating-point operation processing on the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send the completion signal to the cycle control unit, send the new intermediate quotient to the output module, and send the new intermediate remainder to the input unit.
10. The apparatus of claim 9,
the operation precision requirement information comprises preset cycle times; the loop control unit is specifically configured to,
and judging whether the new cycle times are consistent with the preset cycle times or not.
11. The apparatus of claim 8, wherein the round floating point operation processing module is specifically configured to,
and acquiring the precision of a floating point operation processing result as the operation precision requirement information according to the source operand information.
12. The apparatus of claim 9 or 10, wherein the source operands comprise a divisor and a dividend if the floating-point operation instruction further indicates that the floating-point operation is to be processed as a division;
correspondingly, the input unit is further configured to send the intermediate remainder and the source operand to the floating-point operation processing unit when receiving the intermediate remainder;
the floating-point operation processing unit is further configured to, when receiving the second operation signal, perform floating-point operation processing on the source operand and the intermediate remainder to obtain a new intermediate quotient and a new intermediate remainder, send the completion signal to the loop control unit, send the new intermediate quotient to the output module, and send the new intermediate remainder to the input unit;
if the floating-point operation instruction also indicates that the floating-point operation processing is square, the source operand includes a number of squares, and the intermediate quotient is a square root of the middle.
13. The apparatus according to claim 9 or 10, characterized in that the output module is specifically configured to,
and when an end signal is received, normalizing all the received intermediate quotients to obtain the floating point operation processing result.
14. The apparatus of claim 9 or 10, wherein the floating point operation instruction further indicates address information of a second register storing the intermediate quotient;
the output module is specifically configured to store the received intermediate quotient in the second register; and when an end signal is received, reading the second register to obtain the floating-point operation processing result.
15. A processor including apparatus for performing floating point arithmetic operations as claimed in any one of claims 8 to 14.
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| US7085940B2 (en) * | 2002-05-09 | 2006-08-01 | International Business Machines Corporation | Floating point unit power reduction via inhibiting register file write during tight loop execution |
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