CN116846398A - Signal processing system, chip and electronic equipment - Google Patents
Signal processing system, chip and electronic equipment Download PDFInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
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Abstract
The embodiment of the application provides a signal processing system, a chip and electronic equipment. The method comprises the following steps: the system comprises a clock module and a conversion link, wherein the conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected, and the clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to a system clock; the control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate; the digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is a target sampling rate; the digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal. The area of the generated chip is reduced, and the production cost of the chip is reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a signal processing system, a chip and electronic equipment.
Background
When using an electronic device with audio functionality, an audio digital signal may be converted to an analog signal by a signal processing system.
In the related art, an audio signal may be processed as follows: the signal processing system comprises a clock module, a digital filter, a digital processing module and an analog processing module. The clock module provides working clocks for the digital filter, the digital processing module and the analog processing module. The digital filter performs up-sampling processing on the input first signal to obtain a second signal. The digital processing module and the analog processing module perform digital-to-analog conversion processing and noise reduction processing on the second signal to obtain a target signal. In the above process, if the input first signal sampling rates are different, different links are required to perform up-sampling processing, digital-to-analog conversion processing and noise reduction processing on the input first signal, so as to obtain the target signal. That is, a plurality of links including a digital filter, a digital processing module and an analog processing module are required to be arranged in the chip, the area of the generated chip is large, and the production cost of the chip is high.
Disclosure of Invention
The embodiment of the application provides a signal processing system, a chip and electronic equipment, which are used for solving the problem of higher production cost of the chip.
In a first aspect, an embodiment of the present application provides a signal processing system, including: the conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected, wherein,
the clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to a system clock;
the control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate;
the digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is a target sampling rate;
the digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal.
In one possible implementation, the clock module is specifically configured to:
performing frequency division processing on the system clock to obtain a first working clock corresponding to the control module, a second working clock of the digital filter, a third working clock corresponding to the digital processing module and a fourth working clock corresponding to the analog processing module;
providing the first operating clock to the control module, the second operating clock to the digital filter, the third operating clock to the digital processing module, and the fourth operating clock to the analog processing module.
In one possible implementation, the signal processing system further comprises a first clock gate, a second clock gate, a third clock gate, and a fourth clock gate connected in sequence, wherein,
the first clock gating is respectively connected with the output end of the clock module and the control module;
the second clock gating is respectively connected with the output end of the clock module and the digital filter;
the third clock gating is respectively connected with the output end of the clock module and the digital processing module;
the fourth clock gate is connected with the output end of the clock module and the analog processing module respectively.
In one possible implementation, the control module is specifically configured to:
determining a current sampling rate of the first signal;
if the current sampling rate is greater than the preset sampling rate, determining the first signal as the second signal;
and if the current sampling rate is smaller than the preset sampling rate, converting the sampling rate of the first signal into the preset sampling rate to obtain the second signal.
In one possible implementation, the digital filter includes at least one fixed filter unit, M selectable filter units including a filter unit and a selector, M being an integer greater than or equal to 0, wherein,
the at least one fixed filtering unit and the at least one selectable filtering unit are sequentially connected;
the selector is used for controlling the corresponding filtering unit to execute the up-sampling process or not.
In one possible implementation, the digital filter is specifically configured to:
determining a target filtering unit in the at least one selectable filtering unit according to the sampling rate of the second signal;
setting a selector corresponding to the target filtering unit to a preset state, so as to perform up-sampling processing on the second signal through the at least one fixed filtering unit and the target filtering unit, and obtain the third signal.
In one possible implementation, the digital filter is specifically configured to:
determining a target filtering unit in the at least one selectable filtering unit according to the sampling rate of the second signal;
setting a selector corresponding to the target filtering unit to a preset state, so as to perform up-sampling processing on the second signal through the at least one fixed filtering unit and the target filtering unit, and obtain the third signal.
In one possible implementation, the analog processing module includes at least a digital-to-analog converter and a low-pass filter; the simulation processing module is specifically configured to:
performing digital-to-analog conversion processing on the fourth signal through the digital-to-analog converter to obtain a fifth signal;
and carrying out noise reduction processing on the fifth signal to obtain the target signal.
In one possible implementation, the clock module, the control module, the digital filter and the digital processing module are located on a first chip, and the analog processing module is located on a second chip; the signal processing system further comprises a first data interface and a second data interface, wherein,
the first data interface is positioned on the first chip, and the second data interface is positioned on the second chip;
the digital processing module and the analog processing module are connected through the first data interface and the second data interface.
In one possible implementation, the clock module, the control module, the digital filter, the digital processing module, and the analog processing module are located on a first chip.
In a second aspect, an embodiment of the present application provides a chip, where the signal processing system according to any one of the first aspect is provided.
In a third aspect, an embodiment of the present application provides a chip module, including the chip described in the second aspect.
In a fourth aspect, an embodiment of the present application provides an electronic device, including the chip set forth in the second aspect, or the chip module set forth in the third aspect.
The signal processing system, the chip and the electronic equipment provided by the embodiment of the application comprise a clock module and a conversion link. The conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected. The clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to the system clock. The control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate. The digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is the target sampling rate. The digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal. In the above process, due to the control module, the first signals with different sampling rates can be subjected to sampling rate conversion processing to obtain the second signal, and the sampling rate of the second signal is greater than or equal to the preset sampling rate. Only one conversion link is needed to process the first signals with different sampling rates, so that the area of a generated chip is reduced, and the production cost of the chip is reduced.
Drawings
Fig. 1 is a schematic diagram of an application scenario provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a signal processing system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another signal processing system according to an embodiment of the present application;
fig. 4A is a schematic structural diagram of a conversion link according to an embodiment of the present application;
fig. 4B is a schematic structural diagram of another conversion link according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a digital filter according to an embodiment of the present application;
fig. 6 is a schematic diagram of a signal processing process performed by the digital filter according to the embodiment of the present application;
fig. 7A is a schematic structural diagram of a signal processing system disposed in a chip according to an embodiment of the present application;
fig. 7B is a schematic structural diagram of another signal processing system disposed in a chip according to an embodiment of the present application;
fig. 8 is a flow chart of a design method of a signal processing system according to an embodiment of the present application;
fig. 9 is a schematic diagram of a process of obtaining a system clock used by a clock module according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In order to facilitate understanding, an application scenario to which the embodiment of the present application is applicable is described below with reference to fig. 1.
Fig. 1 is a schematic diagram of an application scenario provided in an embodiment of the present application. Referring to fig. 1, an electronic device 101 is included, and the electronic device may be a mobile phone, a tablet computer, a computer, or other devices with audio functions. The electronic device 101 is provided with a chip for processing audio, and a signal processing system is provided in the chip. The signal processing system is used to process the audio signal of the electronic device 101.
In the related art, an audio signal may be processed as follows: the signal processing system comprises a clock module, a digital filter, a digital processing module and an analog processing module. The clock module provides working clocks for the digital filter, the digital processing module and the analog processing module. The signal processing system determines a current sampling rate of the first signal. And selecting a corresponding link to process the first signal according to the current sampling rate. For any one link, the link includes a digital filter, a digital processing module, and an analog processing module. The digital filter performs up-sampling processing on the input first signal to obtain a second signal, wherein the sampling rate of the second signal is the target sampling rate. The digital processing module and the analog processing module perform digital-to-analog conversion processing and noise reduction processing on the second signal to obtain a target signal. In the above process, if the sampling rates of the first signals are different, a plurality of links including the digital filter, the digital processing module and the analog processing module need to be set in the chip, and the generated chip area is larger, resulting in higher production cost of the chip.
In the embodiment of the application, a control module is arranged in a signal processing system. The signal processing system includes a clock module and a conversion link. The conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected. The clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to the system clock. The control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate. The digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is the target sampling rate. The digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal. In the above process, due to the control module, the first signals with different sampling rates can be subjected to sampling rate conversion processing to obtain the second signal, and the sampling rate of the second signal is greater than or equal to the preset sampling rate. Only one conversion link is needed to process the first signals with different sampling rates, so that the area of a generated chip is reduced, and the production cost of the chip is reduced.
The method according to the present application will be described below by way of specific examples. It should be noted that the following embodiments may exist alone or in combination with each other, and for the same or similar content, the description will not be repeated in different embodiments.
Fig. 2 is a schematic structural diagram of a signal processing system according to an embodiment of the present application. The signal processing system is arranged in the chip. Referring to fig. 2, the signal processing system 20 may include: a clock module 21 and a conversion link 22, the conversion link comprising a control module 30, a digital filter 31, a digital processing module 32 and an analog processing module 33 connected in sequence, wherein,
the clock module 21 is configured to provide an operating clock to the control module 30, the digital filter 31, the digital processing module 32, and the analog processing module 33 according to a system clock. The control module 30 is configured to perform sampling rate conversion processing on the first signal to obtain a second signal, where a sampling rate of the second signal is greater than or equal to a preset sampling rate. The digital filter 31 is configured to perform up-sampling processing on the second signal to obtain a third signal, where the sampling rate of the third signal is the target sampling rate. The digital processing module 32 and the analog processing module 33 are configured to perform noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal.
The clock module 21 is specifically configured to: the system clock is subjected to frequency division processing, so as to obtain a first working clock corresponding to the control module 30, a second working clock corresponding to the digital filter 31, a third working clock corresponding to the digital processing module 32, and a fourth working clock corresponding to the analog processing module 33. The first operating clock is provided to the control module 30, the second operating clock is provided to the digital filter 31, the third operating clock is provided to the digital processing module 32, and the fourth operating clock is provided to the analog processing module 33.
The frequency of the system clock is an integer multiple of the audio sampling rate. The system clock may be divided by an integer or fractional frequency division module of the clock module 21 to provide corresponding operating clocks to the control module 30, the digital filter 31, the digital processing module 32, and the analog processing module 33.
For example, the frequency of the system clock is 294.912MHz. The frequency division processing is performed on the system clock, so that the working clock frequency of each module in the conversion link 22 can be specifically shown in table 1:
TABLE 1
| Working clock | Frequency of |
| First working clock | 2.048MHz |
| Second working clock | 3.072MHz |
| Third working clock | 12.288MHz |
| Fourth working clock | 6.144MHz |
The signal processing system 20 further comprises a first clock gate 23, a second clock gate 24, a third clock gate 25 and a fourth clock gate 26, which are connected in sequence. Next, a signal processing system for setting registers will be described with reference to fig. 3. Fig. 3 is a schematic structural diagram of another signal processing system according to an embodiment of the present application. Referring to fig. 3, a signal processing system 20 is included. Wherein,,
the first clock gate 23 is connected to the output of the clock module 21 and to the control module 30, respectively. The second clock gate 24 is connected to the output of the clock module 21 and to the digital filter 31, respectively. The third clock gate 25 is connected to the output of the clock module 21 and to the digital processing module 32, respectively. The fourth clock gate 26 is connected to the output of the clock module 21 and to the analog processing module 33, respectively.
The control module 30, the digital filter 31, the digital processing module 32 and the analog processing module 33 may be controlled by configuring 4 clock-gated registers to provide corresponding operating clocks. When the signal processing system 20 is not in use, the 4 clock-gated registers are configured to not provide corresponding operating clocks to the control module 30, the digital filter 31, the digital processing module 32, and the analog processing module 33. Thereby shutting down the signal processing system 20 and saving power consumption.
The control module 30 is specifically configured to: a current sample rate of the first signal is determined. And if the current sampling rate is greater than the preset sampling rate, determining the first signal as the second signal. If the current sampling rate is smaller than the preset sampling rate, the sampling rate of the first signal is converted into the preset sampling rate, and a second signal is obtained.
The preset sampling rate may be equal to or greater than a maximum value of the current sampling rates of the plurality of first signals.
Alternatively, the control module 30 may be configured with a pass-through function. If the current sampling rate of the first signal is greater than or equal to the preset sampling rate, the transparent transmission of the control module 30 may be started, so that the sampling rate of the second signal output by the control module 30 is the current sampling rate of the first signal.
Next, the structure of the conversion link 22 will be described with reference to fig. 4A to 4B. Fig. 4A is a schematic structural diagram of a conversion link according to an embodiment of the present application. The sampling rates of the first signal are determined to be 8KHz, 16KHz, 32KHz and 44.1KHz, respectively. At this time, the conversion link 22 includes 4 sub-conversion links, which are a first sub-conversion link, a second sub-conversion link, a third sub-conversion link, and a fourth sub-conversion link, respectively. The first sub-conversion link is used for processing a first signal with a sampling rate of 8KHz. The second sub-conversion link is used for processing the first signal with the sampling rate of 16 KHz. The third sub-conversion link is used for processing the first signal with the sampling rate of 32 KHz. The fourth sub-conversion link is used for processing the first signal with the sampling rate of 44.1KHz. In this way, the area and cost of the chip are increased, increasing the complexity of the control of the signal processing system 20.
Fig. 4B is a schematic structural diagram of another conversion link according to an embodiment of the present application. The preset sampling rate of the control module 30 is set to 48KHz. The first signal of the different sampling rate combination is converted into the audio signal with the same sampling rate through the conversion sampling function. At this time, one conversion link 22 can process the first signals of different sampling rates, reducing the chip cost and the complexity of the control of the signal processing system 20. The control module 30 may also be configured with a pass-through function. If the sampling rate of the first signal is greater than 48KHz, the control module 30 may turn on the transparent transmission function so that the sampling rate of the second signal output by the control module 30 is the same as the sampling rate of the first signal.
For example, assume that the sampling rate of the first signal is 96KHz. At this time, the control module 30 may turn on the transparent transmission function, so that the sampling rate of the second signal output by the control module 30 is 96KHz.
Next, the structure of the digital filter 31 will be described with reference to fig. 5. Fig. 5 is a schematic structural diagram of a digital filter according to an embodiment of the present application. Referring to fig. 5, the digital filter 31 includes at least one fixed filtering unit 40, M selectable filtering units 41, the selectable filtering units 41 including a filtering unit 50 and a selector 51, M being an integer greater than or equal to 0, wherein,
at least one fixed filtering unit 40 and at least one optional filtering unit 41 are connected in sequence. The selector 51 is used to control the corresponding filter unit 50 to perform the up-sampling process or not.
The digital filter 31 is specifically configured to: a target filter unit is determined among the at least one selectable filter unit based on the sampling rate of the second signal. And setting a selector corresponding to the target filtering unit to be in a preset state so as to perform up-sampling processing on the second signal through at least one fixed filtering unit and the target filtering unit to obtain a third signal.
The preset state may be to turn on the pass-through function or not turn on the pass-through function. I.e. the filtering unit 50 performs the up-sampling process or does not perform the up-sampling process. If the target filtering unit starts the transparent transmission function, the signal sampling rate of the input target filtering unit is the same as the signal sampling rate of the output target filtering unit.
Preferably, during actual use, it may be determined that the fixed filtering unit 40 is disposed at the head and tail of the digital filter. The method of setting the combination of the other filter units is the same as the above method.
Next, a procedure of performing signal processing on the digital filter 31 will be described with reference to fig. 6. Fig. 6 is a schematic diagram of a signal processing process performed by the digital filter according to the embodiment of the present application. Referring to fig. 6, the digital filter 31 includes 2 fixed filter units 40, 2 selectable filter units 41, and the selectable filter units 40 include a filter unit 50 and a selector 51. Wherein 2 optional filter units 41 and 2 fixed filter units 40 are connected in sequence. The up-sampling times of the 2 optional filter units 41 and the first fixed filter unit 40 are 2 times and the up-sampling times of the second fixed filter unit 40 are 8 times. The target sample rate of the third signal output by the digital filter 31 is 3.072MHz.
If the sampling rate of the second signal is 48KHz, the selector 51 of the 2 selectable filter units 41 is set to a power-off state, i.e., the corresponding filter unit 50 is controlled to perform the up-sampling process. At this time, the second signal is subjected to 64-fold up-sampling processing by the digital filter, and a third signal is obtained. The sample rate of the third signal is the target sample rate of 3.072MHz.
If the sampling rate of the second signal is 96KHz, the selector 51 of the first selectable filter unit 41 is set to an on-pass function state, i.e., the corresponding filter unit 50 is controlled not to perform the up-sampling process. The selector 51 of the second selectable filter unit 41 is set to a power-on state, i.e., the corresponding filter unit 50 is controlled to perform the up-sampling process. At this time, the second signal is subjected to 32-fold up-sampling processing by the digital filter, and a third signal is obtained. The sample rate of the third signal is the target sample rate of 3.072MHz.
If the sampling rate of the second signal is 192KHz, the selector 51 of the 2 selectable filter units 41 is set to an on-pass function state, i.e., the corresponding filter unit 50 is controlled not to perform the up-sampling process. At this time, the second signal is subjected to 16-fold up-sampling processing by the digital filter, and a third signal is obtained. The sample rate of the third signal is the target sample rate of 3.072MHz.
The digital processing module 31 comprises a digital modulator. The digital processing module 31 is specifically configured to: modulating the third signal to obtain a fourth signal
The analog processing module 32 includes at least a digital-to-analog converter and a low pass filter. The analog processing module 32 is specifically configured to: and D/A conversion processing is carried out on the fourth signal through a D/A converter, so as to obtain a fifth signal. And carrying out noise reduction processing on the fifth signal to obtain a target signal.
Next, a structure in which the signal processing system 20 is provided in the chip will be described with reference to fig. 7A to 7B.
Fig. 7A is a schematic structural diagram of a signal processing system disposed in a chip according to an embodiment of the present application. Referring to fig. 7A, a first chip 701 and a second chip 702 are included. The clock module 21, the control module 30, the digital filter 31 and the digital processing module 32 are located on the first chip 701. The analog processing module 33 is located on the second chip 702. The signal processing system 20 further comprises a first data interface 34 and a second data interface 35, wherein,
the first data interface 34 is located on a first chip 701 and the second data interface 35 is located on a second chip 702. The digital processing module 32 and the analog processing module 33 are connected by a first data interface 34 and a second data interface 35.
The combination of the first chip 701 and the second chip 702 includes, but is not limited to, a system on a chip and a power management chip, a micro control unit chip and a power management chip, a dedicated chip and a power management chip, or other chip combinations, etc.
Fig. 7B is a schematic diagram of another structure of a signal processing system disposed in a chip according to an embodiment of the present application. Referring to fig. 7B, a first chip 701 is included. The clock module 21, the control module 30, the digital filter 31, the digital processing module 32 and the analog processing module 33 are located on the first chip 701.
The signal processing system provided by the embodiment of the application comprises a clock module and a conversion link. The conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected. The clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to the system clock. The control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate. The digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is the target sampling rate. The digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal. In the above process, due to the control module, the first signals with different sampling rates can be subjected to sampling rate conversion processing to obtain the second signal, and the sampling rate of the second signal is greater than or equal to the preset sampling rate. Only one conversion link is needed to process the first signals with different sampling rates, so that the area of a generated chip is reduced, and the production cost of the chip is reduced.
On the basis of any of the above embodiments, a method of designing a signal processing system will be described below with reference to fig. 8.
Fig. 8 is a flow chart of a design method of a signal processing system according to an embodiment of the present application. Referring to fig. 8, the method includes:
s801, determining a system clock used by a clock module.
The system clock used by the clock module may multiplex an existing clock in the electronic device. The frequency of the existing clock is an integer multiple of the common audio sampling rate. The existing clock may be an existing clock of an audio domain or an existing clock of other domains.
Next, a process of multiplexing the system clocks used by the clock module will be described with reference to fig. 9. Fig. 9 is a schematic diagram of a process of obtaining a system clock used by a clock module according to an embodiment of the present application. Referring to fig. 9, a system 901 and a signal processing system 902 are included. The system 901 and the signal processing system 902 are provided in the same electronic device. After determining to use the existing clock a of the electronic device, a communication link may be established between clock a and signal processing system 902 such that the system clock used by signal processing system 902 clock module is clock a.
After determining the system clock used by the clock module, the system clock may be frequency divided such that the clock module provides corresponding operating clocks to the control module, digital filter, digital processing module, and analog processing module. The frequency of the corresponding operating clock may be determined based on the timing requirements and computational complexity of the control module, digital filter, digital processing module, and analog processing module.
Alternatively, the control module, digital filter, digital processing module and analog processing module may be designed to multiplex the same operating clock drive. At this time, the data among the modules are synchronously transferred, and the whole system is stable in terms of time sequence, transmission delay matching, device performance matching and the like.
S802, determining a preset sampling rate of the control module, and testing the control module to obtain a first signal-to-noise ratio and first total harmonic distortion plus noise.
The preset sampling rate may be determined according to the sampling rates of a plurality of signals to be processed by the signal processing system. The preset sampling rate may be equal to or greater than a maximum value of sampling rates of the plurality of signals to be processed, and the preset sampling rate is an integer.
For example, the sample rates of the plurality of signals to be processed of the signal processing system are determined to be 8KHz, 16KHz, 32KHz and 44.1KHz, respectively. At this time, the preset sampling rate may be determined to be 48KHz.
Optionally, if the signal processing system needs to process a signal greater than a preset sampling rate, the control module may set a transparent function.
After determining the preset sampling rate, the control module can be tested to obtain a first signal-to-noise ratio and first total harmonic distortion plus noise corresponding to the control module.
S803, the number and types of fixed filtering units, optional filtering units of the digital filter are determined.
The number of fixed filter units, optional filter units of the digital filter may be determined based on a target sample rate and a preset sample rate of the digital filter output signal.
The number of fixed filter units, the number of optional filter units, and the up-sampling multiple of each filter unit may be determined by the following equation 1:
wherein OSR is the oversampling rate; m is M i Representing the multiple of the i-th stage up-sampling filtering and P representing the number of filtering units.
The ratio of the target sampling rate to the preset sampling rate may be determined as the oversampling rate.
The number combination of the at least one fixed filter unit, the optional filter unit, can be determined according to equation 1. The target number and type combination of the fixed filter unit and the selectable filter unit with the minimum cost on the premise of all the required functions being supported according to the realization cost of each combination and high sampling rate support and the algorithm evaluation.
S804, testing the digital filter to obtain a second signal-to-noise ratio and second total harmonic distortion plus noise.
After the target number and type combination of the fixed filtering units and the selectable filtering units is determined, the digital filter is tested, and a second signal-to-noise ratio and a second total harmonic distortion plus noise corresponding to the digital filter are obtained.
S805, determining a first design parameter of the digital processing module, and testing the digital processing module to obtain a third signal-to-noise ratio and third total harmonic distortion plus noise.
The digital processing module comprises a digital modulator and a dynamic element matcher. The first design parameter of the target digital modulator can be obtained according to the key design parameters of the digital modulator such as the target signal bandwidth, the oversampling rate, the quantization bit number and the like.
Alternatively, the structure of the digital modulator may be a cascade integration feedback structure, a cascade integration feedforward structure, a cascade integration resonator structure, or the like.
After the first design parameters of the target digital modulator are determined, testing is conducted on the digital processing, and a third signal-to-noise ratio and third total harmonic distortion plus noise corresponding to the digital processing are obtained.
S806, determining a second design parameter of the analog processing module, and testing the analog processing module to obtain a fourth signal-to-noise ratio and fourth total harmonic distortion plus noise.
The analog processing includes a digital-to-analog converter, a low-pass filter, and the like.
After the second design parameters of the analog processing module are determined, the analog processing module is tested, and a fourth signal-to-noise ratio and a fourth total harmonic distortion plus noise corresponding to the analog processing module are obtained.
S807, determining a design signal-to-noise ratio according to the first signal-to-noise ratio, the second signal-to-noise ratio, the third signal-to-noise ratio and the fourth signal-to-noise ratio.
The design signal-to-noise ratio can be determined by the following equation 2:
wherein D is SNR Designing a signal-to-noise ratio for the design; SNR of 1 Is a first signal to noise ratio; SNR of 2 Is a second signal to noise ratio; SNR of 3 Is a third signal to noise ratio; SNR of 4 And is the fourth signal to noise ratio.
S808, determining the design total harmonic distortion noise according to the first total harmonic distortion noise adding, the second total harmonic distortion noise adding, the third total harmonic distortion noise adding and the fourth total harmonic distortion noise adding.
The total harmonic distortion plus noise can be determined by the following equation 3:
wherein D is THDN Adding noise for designing total harmonic distortion; THDN 1 Adding noise to the first total harmonic distortion; THDN 2 Adding noise to the second total harmonic distortion; THDN 3 Adding noise to the third total harmonic distortion; THDN 4 And adding noise to the fourth total harmonic distortion.
S809, when the design signal-to-noise ratio and the design total harmonic distortion plus noise of the signal processing system meet preset conditions, determining the parameters of each module of the signal processing system as target parameters.
The preset condition may be determined by the following equation 4:
wherein SNR is aim Is the target signal to noise ratio; THDN aim And adding noise to the target total harmonic distortion.
The design method of the signal processing system provided by the embodiment of the application determines the system clock used by the clock module. And determining a preset sampling rate of the control module, and testing the control module to obtain a first signal-to-noise ratio and first total harmonic distortion plus noise. And testing the digital filter to obtain a second signal-to-noise ratio and second total harmonic distortion plus noise. And testing the digital filter to obtain a second signal-to-noise ratio and second total harmonic distortion plus noise. And determining a first design parameter of the digital processing module, and testing the digital processing module to obtain a third signal-to-noise ratio and third total harmonic distortion plus noise. And determining a second design parameter of the analog processing module, and testing the analog processing module to obtain a fourth signal-to-noise ratio and fourth total harmonic distortion plus noise. And determining a design signal-to-noise ratio according to the first signal-to-noise ratio, the second signal-to-noise ratio, the third signal-to-noise ratio and the fourth signal-to-noise ratio. And determining the design total harmonic distortion noise according to the first total harmonic distortion noise adding, the second total harmonic distortion noise adding, the third total harmonic distortion noise adding and the fourth total harmonic distortion noise adding. When the design signal-to-noise ratio and the design total harmonic distortion plus noise of the signal processing system meet preset conditions, determining the parameters of each module of the signal processing system as target parameters. In the above process, the signal processing system may multiplex clocks existing in the electronic device, and may process signals of different sampling rates with one conversion link. The condition that a plurality of conversion links process signals with corresponding sampling rates or cannot process signals with high sampling rates is avoided, the cost of a chip is reduced, and the flexibility of a signal processing system in processing signals is improved.
The embodiment of the application also provides a chip comprising the signal processing system.
The embodiment of the application also provides a chip module which comprises the chip.
The embodiment of the application also provides electronic equipment comprising the chip or the chip module. The electronic device may be a mobile phone, a tablet computer, a computer, or other devices with audio functions.
The electronic device provided by the embodiment of the application can execute the technical scheme shown in the embodiment of the method, and the implementation principle and the beneficial effects are similar, and are not repeated here.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.
In the present disclosure, the term "include" and variations thereof may refer to non-limiting inclusion; the term "or" and variations thereof may refer to "and/or". The terms "first," "second," and the like, herein, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. In the present application, "a plurality of" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Claims (13)
1. A signal processing system, comprising: the conversion link comprises a control module, a digital filter, a digital processing module and an analog processing module which are sequentially connected, wherein,
the clock module is used for providing working clocks for the control module, the digital filter, the digital processing module and the analog processing module according to a system clock;
the control module is used for carrying out sampling rate conversion processing on the first signal to obtain a second signal, and the sampling rate of the second signal is greater than or equal to a preset sampling rate;
the digital filter is used for carrying out up-sampling processing on the second signal to obtain a third signal, and the sampling rate of the third signal is a target sampling rate;
the digital processing module and the analog processing module are used for carrying out noise reduction processing and digital-to-analog conversion processing on the third signal to obtain a target signal.
2. The system according to claim 1, wherein the clock module is specifically configured to:
performing frequency division processing on the system clock to obtain a first working clock corresponding to the control module, a second working clock of the digital filter, a third working clock corresponding to the digital processing module and a fourth working clock corresponding to the analog processing module;
providing the first operating clock to the control module, the second operating clock to the digital filter, the third operating clock to the digital processing module, and the fourth operating clock to the analog processing module.
3. The system of claim 2, wherein the signal processing system further comprises a first clock gate, a second clock gate, a third clock gate, and a fourth clock gate connected in sequence, wherein,
the first clock gating is respectively connected with the output end of the clock module and the control module;
the second clock gating is respectively connected with the output end of the clock module and the digital filter;
the third clock gating is respectively connected with the output end of the clock module and the digital processing module;
the fourth clock gate is connected with the output end of the clock module and the analog processing module respectively.
4. A system according to any one of claims 1-3, characterized in that the control module is specifically adapted to:
determining a current sampling rate of the first signal;
if the current sampling rate is greater than the preset sampling rate, determining the first signal as the second signal;
and if the current sampling rate is smaller than the preset sampling rate, converting the sampling rate of the first signal into the preset sampling rate to obtain the second signal.
5. The system of any of claims 1-4, wherein the digital filter comprises at least one fixed filter unit, M selectable filter units, the selectable filter units comprising a filter unit and a selector, the M being an integer greater than or equal to 0, wherein,
the at least one fixed filtering unit and the at least one selectable filtering unit are sequentially connected;
the selector is used for controlling the corresponding filtering unit to execute the up-sampling process or not.
6. The system of claim 5, wherein the digital filter is specifically configured to:
determining a target filtering unit in the at least one selectable filtering unit according to the sampling rate of the second signal;
setting a selector corresponding to the target filtering unit to a preset state, so as to perform up-sampling processing on the second signal through the at least one fixed filtering unit and the target filtering unit, and obtain the third signal.
7. The system of any of claims 1-6, wherein the digital processing module comprises at least a digital modulator; the digital processing module is specifically configured to:
and modulating the third signal to obtain a fourth signal.
8. The system according to any of claims 1-7, wherein the analog processing module comprises at least a digital-to-analog converter and a low pass filter; the simulation processing module is specifically configured to:
performing digital-to-analog conversion processing on the fourth signal through the digital-to-analog converter to obtain a fifth signal;
and carrying out noise reduction processing on the fifth signal to obtain the target signal.
9. The system of any of claims 1-8, wherein the clock module, the control module, the digital filter, and the digital processing module are located on a first chip, and the analog processing module is located on a second chip; the signal processing system further comprises a first data interface and a second data interface, wherein,
the first data interface is positioned on the first chip, and the second data interface is positioned on the second chip;
the digital processing module and the analog processing module are connected through the first data interface and the second data interface.
10. The system of any of claims 1-8, wherein the clock module, the control module, the digital filter, the digital processing module, and the analog processing module are located on a first chip.
11. A chip comprising the signal processing system of any one of claims 1-9.
12. A chip module comprising the chip of claim 11.
13. An electronic device comprising the chip of claim 11 or the chip module of claim 12.
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