KR20020064523A - Analog-digital converter for converting multi-channel input signal - Google Patents

Abstract

PURPOSE: An analog-digital converter converting multi channel input signals is provided, which reduces fabrication costs as inputting multi channel analog signals. CONSTITUTION: According to the analog-digital converter(201) inputting multi channel analog signals, a clock generation part(211) inputs a system clock and generates a sampling clock signal and a main clock signal. An initialization signal generation part(221) inputs the sampling clock signal and generates an initialization signal. A channel selection signal generation part(231) inputs the sampling clock signal and generates a channel selection signal. A multiplexer(241) inputs the initialization signal and multi channel analog signals, and initializes an output signal in response to the initialization signal, and selects one of the multi channel analog signals in response to the channel selection signal. A converter part(251) initializes an internal feedback circuit in response to the initialization signal, and converts an analog signal being output from the multiplexer into a digital signal by being synchronized to the system clock signal and the main clock signal. And a register(261) stores the digital signal, and outputs an effective digital signal by being synchronized to the sampling clock signal.

Description

Analog-to-digital converter for converting multi-channel input signal

The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter for inputting multichannel analog signals.

1 is a block diagram of a conventional oversampling sigma-delta analog-to-digital converter. Referring to FIG. 1, a conventional oversampling sigma-delta analog-to-digital converter includes an analog modulator 111, a first digital decimation filter 121, and a second digital decimation filter 131. do.

The analog modulator 111 oversamples the analog signal AN1 input from the outside, modulates it, and outputs a 1-bit pulse density modulation (PDM) signal. A PDM signal is a signal that represents the amplitude of a signal as a small density of pulses. The first digital decimation filter 121 receives the output of the analog modulator 111 and down-samples while removing noise outside the signal band. The second digital decimation filter 131 down-samples and removes noise outside the signal band included in the signal output from the first digital decimation filter 121 and outputs it. The first digital decimation filter 121 has the same function as the second digital decimation filter 131.

In this way, two digital decimation filters are used to eliminate noise in stages, thereby reducing the burden on hardware than using one. However, if the input channel is not one but plural, analog to digital converters should exist as many as the number of input channels. Therefore, when the analog signal is a multi-channel input, the manufacturing cost of the analog-to-digital converter is high.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an analog-digital converter in which a manufacturing cost is reduced while inputting a multi-channel analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional oversampling sigma-delta analog-to-digital converter.

2 is a block diagram of an analog-to-digital converter according to the present invention.

3 is a timing diagram of the signals shown in FIG. 2.

4A to 4D are diagrams showing the results of simulating signals input and output to the analog-digital converter shown in FIG.

The present invention to achieve the above technical problem,

An analog-to-digital converter for inputting multi-channel analog signals, comprising: a clock generator for inputting a system clock and generating a sampling clock signal and a main clock signal; An initialization signal generator configured to input the sampling clock signal and generate an initialization signal; A channel selection signal generator for inputting the sampling clock signal and generating a channel selection signal; A multiplexer for inputting the initialization signal, the channel selection signal, and the multichannel analog signals, initializing an output signal in response to the initialization signal, and selecting and outputting one of the multichannel analog signals in response to the channel selection signal; A converter configured to initialize an internal feedback circuit in response to the initialization signal, and convert an analog signal output from the multiplexer into a digital signal in synchronization with the system clock signal and the main clock signal; And a register for inputting and storing the digital signal and outputting a valid digital signal in synchronization with the sampling clock signal.

Preferably, the conversion unit converts the input analog signal into the digital signal using a sigma-delta method.

Preferably, the main clock signal is a signal having a frequency obtained by multiplying the sampling clock signal by a group delay occurring in the converter.

Preferably, the initialization signal is generated at the end of operation of one of the multi-channel analog signals input to the multiplexer to completely remove the one analog signal from the multiplexer.

Preferably, the conversion unit further inputs the initialization signal to remove the analog signal from which the processing is completed whenever the processing of one of the plurality of analog signals is completed.

According to the present invention, since the multi-channel input signal is processed by the conversion unit of one channel, the manufacturing cost is reduced.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram of an analog-to-digital converter according to the present invention. Referring to FIG. 2, the analog-to-digital converter 201 includes a clock generator 211, an initialization signal generator 221, a channel select signal generator 231, a multiplexer 241, and a converter 251. ) And a register 251.

The clock generator 211 receives a system clock signal ECL and generates a sampling clock signal SCL and a main clock signal MCL. The main clock signal MCL has a frequency obtained by multiplying the group delay generated by the converter 251 and the sampling clock signal SCL. As such, the frequency of the main clock signal MCL is higher than the group delay generated by the converter 251 so that the frequency of the digital signal OUT output from the converter 251 is operated above the group delay. A valid output can be achieved by synchronizing with the sampling clock signal in the register 251.

The initialization signal generator 221 inputs the sampling clock signal SCL and generates an initialization signal INI. The initialization signal generator 221 generates the initialization signal INI by delaying the sampling clock signal SCL for a predetermined time or synchronizing with the system clock signal ECL.

The channel select signal generator 231 inputs the sampling clock signal SCL and generates the channel select signal SC. The channel select signal SC is generated as many as the number of analog signals input to the multiplexer 241. For example, if there are three analog signals input to the multiplexer 241, the channel select signal generator 231 generates three channel select signals.

The multiplexer 241 receives the initialization signal INI, the channel select signal SC, and the multichannel analog signals IN1 to INn, and the multichannel analog signals IN1 to INn in response to the channel select signal SC. Select one signal SC-1 and output it. For example, when the first to third analog signals IN1 to IN3 are input to the multiplexer 241, the first to third channel select signals SC1 to SCn are input to the multiplexer 241, and the multiplexer ( 241 outputs a first analog signal IN1 while the first channel select signal SC1 is enabled at a logic high, and the second channel select signal SC2 is at a logic high. Outputs the second analog signal IN2 and outputs the third analog signal IN3 while the third channel select signal SC3 is logic high. In this case, each time the output of the analog signal is completed, the multiplexer 241 completely removes the analog signal from which the output is completed using the initialization signal INI. For example, when the output of the first analog signal IN1 is completed, since the multiplexer 241 is initialized by the initialization signal INI, the first analog signal IN1 is completely removed, and the output of the second analog signal IN2 is Upon completion, the multiplexer 241 is initialized by the initialization signal INI so that the second analog signal IN2 is completely removed.

The converter 251 inputs the initialization signal INI, the system clock signal ECL, the main clock signal MCL, and the output signal SC-1 of the multiplexer 241. The converter 251 oversamples the analog signals output from the multiplexer 241 in synchronization with the system clock signal ECL and the main clock signal MCL to convert the digital signals into digital signals. The initialization signal INI input to the converting unit 251 is configured to generate an internal feedback circuit generated by the oversampling when the conversion is completed through oversampling of one analog signal among a plurality of analog signals input from the multiplexer 241. Remove the accumulated value. Therefore, since the accumulated value of the internal feedback circuit is removed through the initialization signal INI after the conversion through oversampling of the converter 251, the analog signals do not affect each other and noise is reduced.

The converter 251 converts the input analog signal SC-1 into the digital signal OUT using the sigma-delta method. That is, the converter 251 is a conventional oversampling sigma-delta analog-to-digital converter, that is, an analog modulator (111 in FIG. 1) for inputting the output signal SC-1 of the multiplexer 241, and the output of the analog modulator. A first digital decimation filter (121 of FIG. 1) for inputting the second digital decimation filter 131 for inputting an output of the first digital decimation filter and outputting a digital signal OUT.

The register 261 inputs and stores the digital signals output from the converter 251 and synchronizes with the sampling clock signal (SCL) so that each time a group delay is completed from the converter 251 and valid data comes in, the corresponding digital signal is input. Sample is output.

As such, noise is reduced by using the initialization signal INI so that analog signals output from the multiplexer 241 are not mutually affected. In addition, the converter 251 operates in synchronization with the main clock signal MCL higher than the group delay, and operates the signal Fs_OUT output from the register 261 in synchronization with the sampling clock signal SCL to operate the analog-digital device. The transducer 201 gets a stable output. The analog-to-digital converter 201 of the present invention has a simple structure and can convert multi-channel analog signals into digital signals using only one channel converter, thereby reducing the manufacturing cost of the analog-to-digital converter 201.

3 is a timing diagram of the signals shown in FIG. 2. FIG. 3 exemplifies three analog signals input to the multiplexer 241 of FIG. 2. Referring to FIG. 3, the frequency of the main clock signal MCL is lower than the system clock signal ECL, and the frequency of the sampling clock signal SCL is lower than the main clock signal MCL. The initialization signal INI is enabled at logic high when the sampling clock signal SCL is enabled at logic high and when the sampling clock signal SCL is disabled at logic low. Disabled to logic low. The channel selection signals SC1 to SC3 are enabled to be logic high when the sampling clock signal SCL is generated, and are disabled to logic low when the initialization signal INI is generated. Whenever the channel select signals SC1 to SC3 are enabled, a corresponding one of the analog signals IN1 to IN3 is output from the multiplexer 241 of FIG. 2.

The initialization signal INI is enabled whenever an analog signal is output from the multiplexer 241 of FIG. 2 to remove noise caused by the analog signal in which the output is completed. That is, the initialization signal INI initializes the multiplexer 241 of FIG. 2 whenever an analog signal is output from the multiplexer 241 of FIG. 2. In addition, the initialization signal INI converts the output of the multiplexer 241 into a digital signal by the converter 251 and then removes the accumulated value of the internal feedback circuit, thereby affecting the noise of the previous multiplexer output on the output of the new multiplexer. Eliminate The initialization section t1 of the initialization signal INI may be adjusted.

4A to 4D illustrate simulation results of signals input and output to the analog-to-digital converter 201 shown in FIG. 2.

FIG. 4A illustrates three analog signals, ie, first to third analog signals IN1 to IN3, input to the multiplexer 241 of FIG. 2. The first analog signal IN1 is 24 [Hz], the second analog signal IN2 is 48 [Hz] which is twice the first analog signal IN1, and the third analog signal IN3 is the second analog signal IN2. 96 [㎐], which is twice as large as.

FIG. 4B shows a state in which the signals IN1 to IN3 shown in FIG. 4A are sampled to a valid output after being converted through the converter 251 of FIG. 2 and output to the register 261 of FIG. As shown in FIG. 4B, it can be seen that the three signals are output without affecting each other.

FIG. 4C illustrates a result of artificially sampling and dividing the three signals illustrated in FIG. 4B into a channel selection signal in a simulation environment. As such, it can be seen that the three signals Fs_OUT1 to Fs_OUT3 are normally converted without noise.

FIG. 4D is an enlarged view of the relationship between the output of the register 261 and the initialization signal INI shown in FIG. 2. As shown in FIG. 4D, three signals are normally output for each channel by initializing noise of an internal circuit by a previous signal before a new signal is converted.

As described with reference to FIGS. 4B to 4D, even when the analog-to-digital converter 201 inputs the multi-channel analog signals IN1 to INn, the output signals do not interfere with each other, so noise is reduced and conversion characteristics are improved.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the analog-to-digital converter 201 of the present invention has a simple structure and converts the multi-channel analog signals IN1 to INn into digital signals using a converter of one channel. Therefore, manufacturing cost is reduced. In addition, since the analog-to-digital converter 201 of the present invention uses the initialization signal INI, noise is reduced.

Claims (5)

An analog-to-digital converter for inputting multichannel analog signals, A clock generator for inputting a system clock and generating a sampling clock signal and a main clock signal; An initialization signal generator configured to input the sampling clock signal and generate an initialization signal; A channel selection signal generator for inputting the sampling clock signal and generating a channel selection signal; A multiplexer for inputting a vaporization signal, a channel selection signal, and a multichannel analog signal, initializing an output signal in response to the initialization signal, and selecting and outputting one of the multichannel analog signals in response to the channel selection signal; A converter configured to initialize an internal feedback circuit in response to the initialization signal, and convert an analog signal output from the multiplexer into a digital signal in synchronization with the system clock signal and the main clock signal; And And a register for inputting and storing the digital signal and outputting a valid digital signal in synchronization with the sampling clock signal. The analog-to-digital converter of claim 1, wherein the converter converts the input analog signal into the digital signal using a sigma-delta method. The analog-to-digital converter of claim 1, wherein the main clock signal is a signal having a frequency obtained by multiplying the sampling clock signal by a group delay occurring in the converter. The method of claim 1, wherein the initialization signal is generated at the end of the operation of the analog signal of one of the multi-channel analog signals input to the multiplexer to completely remove the one analog signal from the multiplexer Analog-to-digital converter. 2. The analog of claim 1, wherein the converter further inputs the initialization signal to remove noise caused by the analog signal in which the processing is completed whenever the analog signal of one of a plurality of analog signals is completed. -Digital converter.