CN116845694A

CN116845694A - Flow-control balance VCSEL chip and preparation method thereof

Info

Publication number: CN116845694A
Application number: CN202210289537.9A
Authority: CN
Inventors: 郭铭浩; 周圣凯; 赖威廷; 王立; 李念宜
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2023-10-03

Abstract

A flow control balanced VCSEL chip and a method for manufacturing the same are disclosed, wherein the flow control balanced VCSEL chip comprises a light emitting region and a resistor structure formed in the light emitting region. The light emitting region comprises a plurality of VCSEL light emitting points, and the flow control balance type VCSEL chip can adjust the light emitting intensity of the VCSEL light emitting points of different parts by controlling the current passing through the VCSEL light emitting points of each part in the light emitting region so as to improve the overall light emitting uniformity.

Description

Flow-control balance VCSEL chip and preparation method thereof

Technical Field

The application relates to the field of semiconductor lasers, in particular to a flow control balanced VCSEL chip and a preparation method thereof.

Background

A VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. The VCSEL chip has the characteristics of small temperature drift, low threshold value, high optical fiber coupling efficiency, easy integration and encapsulation and the like, and is widely applied to the fields of intelligent transportation, health care, biological detection, military security and the like.

In the practical industry, a plurality of light emitting points formed by a plurality of VCSEL lasers are typically arranged on a VCSEL chip, so as to meet requirements on light intensity, partition lighting, sensing accuracy and the like of a light source in different application scenarios. However, when the light emitting points are more and the light emitting power is larger, the problem of uneven heat dissipation of the VCSEL chip is easy to occur, resulting in uneven light emitting intensity of different areas of the VCSEL chip.

Specifically, the luminous intensity of the luminous point is affected by temperature, and the higher the temperature, the lower the luminous intensity within a certain temperature variation range. The luminous points of the partial areas of the VCSEL chip are concentrated, heat is easily accumulated with the duration of the operating time, the temperature is high, and the luminous intensity is relatively low. The luminous points of other areas of the VCSEL chip are scattered, the heat dissipation space is large, the temperature is low in the working state, and the luminous intensity is relatively high. In this way, the VCSEL chip in which the plurality of light emitting points are arranged is liable to have a problem that the light emitting intensities of the light emitting points are not uniform, so that the light emitting intensities of the VCSEL chip are not uniform.

Therefore, a new VCSEL chip design is needed to improve the emission uniformity of the VCSEL chip.

Disclosure of Invention

The application provides a flow control balanced VCSEL chip and a preparation method thereof, wherein the flow control balanced VCSEL chip can improve the overall luminous uniformity by reducing the luminous intensity of a VCSEL luminous point with higher luminous intensity in a luminous area.

Another advantage of the present application is to provide a flow-controlling balanced VCSEL chip and a method of fabricating the same, in which the flow-controlling balanced VCSEL chip is capable of improving the overall light emission uniformity by adjusting the light emission intensities of the VCSEL light emitting points of different portions by controlling the current passing through the VCSEL light emitting points of the respective portions in the light emitting region thereof.

Still another advantage of the present application is to provide a flow-controlling balanced VCSEL chip and a method for fabricating the same, in which the flow-controlling balanced VCSEL chip is configured with a resistor structure having a specific pattern for the light emitting region, so as to compensate for a difference in light emitting intensity between a light emitting point having a low light emitting intensity and a light emitting point having a high light emitting intensity, which is less advantageous in heat dissipation, and to improve light emitting uniformity between the light emitting points of the VCSELs.

It is yet another advantage of the present application to provide a flow-controlled balanced VCSEL chip and a method of fabricating the same, in which the resistance of the resistive structure is controllable, and the current through the VCSEL emission point of each section in the emission region can be controllably adjusted.

Still another advantage of the present application is to provide a flow-controlling balanced VCSEL chip and a method for fabricating the same, in which the flow-controlling balanced VCSEL chip improves light emission uniformity of the VCSEL chip by reducing light emission intensity of a VCSEL light emission point having a higher light emission intensity in a light emission region thereof, and the overall difficulty of improving a VCSEL chip light emission uniformity scheme can be reduced.

Still another advantage of the present application is to provide a flow-controlling balanced VCSEL chip and a method for fabricating the same, in which the flow-controlling balanced VCSEL chip is capable of improving light-emitting uniformity of the flow-controlling balanced VCSEL chip without changing a relative positional relationship of light-emitting points of the individual VCSELs.

The application has the advantages that the application provides the flow control balanced VCSEL chip and the preparation method thereof, wherein the resistance structure can be formed by changing or adding one procedure on the basis of the traditional VCSEL chip preparation process, so that the luminous uniformity of the finally formed VCSEL chip can be improved by simply adjusting the traditional preparation process, the original VCSEL chip production line and production equipment can be reserved for preparing the flow control balanced VCSEL chip, the production line transformation cost of the flow control balanced VCSEL chip is effectively reduced, and the preparation cost is further reduced.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided a flow-controlling balanced VCSEL chip, comprising:

a light emitting region including a plurality of VCSEL light emitting points, wherein the plurality of VCSEL light emitting points includes a first partial light emitting point adjacent to an outer periphery of the light emitting region and a second partial light emitting point other than the first partial light emitting point; and

the resistance structure formed in the light-emitting area comprises a first resistance unit formed at the first part light-emitting point, wherein the resistance value of the first part light-emitting point formed with the first resistance unit is larger than that of the first part light-emitting point not formed with the first resistance unit.

In the current-controlled balanced VCSEL chip according to the present application, the resistive structure is formed in the light emitting region by means of ion implantation.

In the flow control balanced VCSEL chip according to the present application, the resistive structure forms the first resistive element by implanting a first ion body to a VCSEL emission point of the first partial emission points.

In the flow control balanced VCSEL chip according to the present application, the first resistive unit extends downward from an upper surface of at least one of the VCSEL emission points in the first partial emission points.

In the flow control balanced VCSEL chip according to the present application, each VCSEL emission point includes, from bottom to top, a negative electrode, a substrate layer, an N-DBR layer, an active region, a confinement layer having a confinement hole, a P-DBR layer, and a positive electrode, wherein an upper surface of the P-DBR layer forms an upper surface of the VCSEL emission point, and the first resistive unit extends downward from an upper surface of the P-DBR layer of at least one of the VCSEL emission points in the first partial emission point.

In the current control balance type VCSEL chip according to the present application, the current control balance type VCSEL chip further includes a second resistive element formed at the second partial light emitting point, wherein a resistance value of the second partial light emitting point at which the second resistive element is formed is greater than a resistance value of the second partial light emitting point at which the second resistive element is not formed, and a blocking effect of the first resistive element on a current passing through the first partial light emitting point is greater than a blocking effect of the second resistive element on a current passing through the second partial light emitting point, in such a manner that light emission uniformity of the current control balance type VCSEL chip is improved.

In the current control balanced VCSEL chip according to the present application, the first resistance unit includes a plurality of first resistance sections formed at a plurality of VCSEL emission points among the first partial emission points, the second resistance unit includes a plurality of second resistance sections formed at a plurality of VCSEL emission points among the second partial emission points, and an average level of resistance values of the plurality of first resistance sections is greater than an average level of resistance values of the plurality of second resistance sections.

In the flow control balanced VCSEL chip according to the present application, the width average level of the plurality of first resistive portions is greater than the width average level of the plurality of second resistive portions.

In the flow control balanced VCSEL chip according to the present application, the depth average level of the plurality of first resistive portions is greater than the depth average level of the plurality of second resistive portions.

In the flow control balanced VCSEL chip according to the present application, the resistor structure is formed by forming the plurality of first resistor portions by implanting first ions into a plurality of VCSEL light emitting points among the first partial light emitting points, and the resistor structure is formed by forming the plurality of second resistor portions by implanting second ions into a plurality of VCSEL light emitting points among the second partial light emitting points, wherein an implantation concentration average level of the first ions in their corresponding VCSEL light emitting points is greater than an implantation concentration average level of the second ions in their corresponding VCSEL light emitting points.

In the flow control balanced VCSEL chip according to the present application, the distribution density of the plurality of first resistive portions is greater than the distribution density of the plurality of second resistive portions.

In the flow control balanced VCSEL chip according to the present application, the resistance values of the plurality of first resistive portions gradually increase from the region of the light emitting region adjacent to the first partial light emitting point toward the outer periphery thereof.

In the flow control balanced VCSEL chip according to the present application, the resistance values of the plurality of second resistance parts gradually increase from the central region of the light emitting region toward the outer periphery thereof.

According to another aspect of the present application, the present application also provides a method for fabricating a VCSEL chip, comprising:

forming an epitaxial layer structure, wherein the epitaxial layer structure comprises from bottom to top: a substrate layer structure, an N-DBR layer structure, an active layer structure and a P-DBR layer structure;

forming a negative electrode and a plurality of positive electrodes electrically connected to the epitaxial structure;

removing at least a portion of the epitaxial layer structure to form a plurality of sub-structural units, each sub-structural unit comprising, from bottom to top: a negative electrode, a substrate layer, an N-DBR layer, an active region, a P-DBR layer, and a positive electrode;

processing the plurality of sub-structural units to form a confinement layer having a confinement hole above the active region, thereby forming a plurality of VCSEL emission points, wherein the plurality of VCSEL emission points include a first partial emission point adjacent to an outer periphery of an emission region formed by the plurality of VCSEL emission points and a second partial emission point other than the first partial emission point; the method comprises the steps of,

Implanting first ions into at least one VCSEL luminous point in the first partial luminous points in an ion implantation mode to form a first resistance unit, wherein the resistance value of the first partial luminous points formed with the first resistance unit is larger than that of the first partial luminous points not formed with the first resistance unit.

In the method for manufacturing a VCSEL chip according to the present application, the method for manufacturing a VCSEL chip further comprises: and implanting second ions into the second part luminous points in an ion implantation mode to form a second resistance unit, wherein the resistance value of the second part luminous points formed with the second resistance unit is larger than that of the second part luminous points not formed with the second resistance unit, and the blocking effect of the first resistance unit on the current passing through the first part luminous points is larger than that of the second resistance unit on the current passing through the second part luminous points.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, wherein:

fig. 1 illustrates a schematic diagram of the luminous intensity of each luminous point of a conventional VCSEL chip.

Fig. 2 illustrates a schematic structure of a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 3 illustrates a partial enlarged schematic view of the flow-controlling balanced VCSEL chip illustrated in fig. 2 according to an embodiment of the present application.

Fig. 4 illustrates a schematic structural diagram of a modified implementation of a flow-controlling balanced VCSEL chip according to an embodiment of the present application.

Fig. 5 illustrates a partial enlarged schematic diagram of a variant implementation of the flow-controlling balanced VCSEL chip illustrated in fig. 4 according to an embodiment of the present application.

Fig. 6 illustrates a partial enlarged schematic view of another variant implementation of a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 7 illustrates a partial enlarged schematic view of a further variant implementation of a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 8 illustrates a flow chart of a method of fabricating a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 9A illustrates one of the schematic diagrams of the fabrication process of a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 9B illustrates a second schematic diagram of a process for fabricating a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Fig. 9C illustrates a third schematic diagram of a process for fabricating a flow-controlled balanced VCSEL chip according to an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the application is provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application

As described above, a VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. The VCSEL chip has the characteristics of small temperature drift, low threshold value, high optical fiber coupling efficiency, easy integration and encapsulation and the like, and is widely applied to the fields of intelligent transportation, health care, biological detection, military security and the like.

The emitted light intensity unevenness of the VSCEL chip is generally expressed as: the light emission intensity of the peripheral portion adjacent to the outer periphery of the VCSEL chip in the light emission region is high compared with that of the portion in the peripheral portion, as shown in fig. 1. The main reason is that: the periphery of the VCSEL luminous point (namely, the luminous point of the outer layer) of the peripheral part is a non-luminous area, so that the heat dissipation space is large, and the heat dissipation of the luminous point of the outer layer is facilitated. And the metal layer extending outwards from the luminous point of the outer layer has stronger heat conductivity, so that the heat dissipation speed of the luminous point of the outer layer is further accelerated. The VCSEL luminous points of the parts in the peripheral part are concentrated, the heat dissipation space is limited, the luminous points of the outer layer are surrounded by the luminous points of the outer layer, the luminous points of the outer layer form a heat source, the outward diffusion of the heat of the VCSEL luminous points in the heat source is prevented, and the inward diffusion of the heat of the part of the luminous points of the outer layer is prevented, so that the heat at the VCSEL luminous points in the heat source is easy to accumulate, the heat dissipation performance is poor, and the luminous intensity is relatively low.

At present, the luminescence uniformity of the VCSEL chip is mainly improved by improving the luminescence intensity of the VCSEL luminescence point with lower luminescence intensity. Specifically, the problem of uneven light emission intensity is solved by improving the heat radiation performance of a portion of the light emission region where the heat radiation advantage is poor. For example, increasing the distance between the plurality of VCSEL emission points located in the middle of the emission region increases the heat dissipation performance of the middle structure of the emission region, thereby improving the heat dissipation uniformity of the VCSEL chip. However, an increase in the distance between the plurality of VCSEL emission points of the VCSEL emission region reduces the available space around the VCSEL emission region, resulting in a decrease in wiring flexibility and an increase in wiring difficulty. Also, the overall volume of the VCSEL chip may need to be increased, resulting in an increase in manufacturing costs. Further, increasing the distance between a portion of the plurality of VCSEL emission points will affect the distribution uniformity and distribution density between all of the plurality of VCSEL emission points. However, in some application scenarios where there is a specific requirement for the distribution position of the plurality of VCSEL emission points, increasing the distance between the plurality of VCSEL emission points located in the middle of the emission region conflicts with the specific requirement, for example, in some sensing scenarios, it is necessary to increase the density of the emission points in the middle of the emission region to increase the sensing accuracy.

The inventors of the present application have conducted the contrary, and proposed to improve the light emission uniformity of a VCSEL chip by reducing the light emission intensity of the VCSEL light emission point having a higher light emission intensity. And it should be understood that, when the light emission intensity of the VCSEL light emission point 11 is raised to a certain level, the light emission intensity is difficult to be further raised due to the heat dissipation performance, the self structural characteristics, the material characteristics and other factors of the area where the VCSEL light emission point 11 is located, and the difficulty of lowering the light emission intensity of the VCSEL light emission point 11 is relatively low compared with that of raising the light emission intensity of the VCSEL light emission point 11. Accordingly, the overall difficulty of the scheme of improving the light emission uniformity of the VCSEL chip can be reduced to some extent by improving the light emission uniformity of the VCSEL chip by reducing the light emission intensity of the VCSEL light emission point 11 having a higher light emission intensity in the light emission region 10.

Further, the luminous intensity of the VCSEL emission point is related not only to the heat dissipation performance of the place where it is located, but also to the magnitude of the current passing through the VCSEL emission point. The larger the current passing through the VCSEL emission point, the larger the emission intensity of the VCSEL emission point, and the smaller the current passing through the VCSEL emission point, the smaller the emission intensity of the VCSEL emission point. Accordingly, the light emission intensity of the VCSEL light emission points of different portions can be adjusted by controlling the current passing through the VCSEL light emission points of each portion in the light emission region of the VCSEL chip, so as to compensate for the light emission intensity difference between each VCSEL light emission point caused by the uneven heat dissipation, thereby improving the light emission uniformity of the VCSEL chip.

Based on this, according to one aspect of the application, the application proposes a controlled-flow type VCSEL chip comprising: a light emitting region and a resistive structure formed in the light emitting region. The light emitting region includes a plurality of VCSEL light emitting points, wherein the plurality of VCSEL light emitting points includes a first partial light emitting point adjacent to an outer periphery of the light emitting region and a second partial light emitting point other than the first partial light emitting point. The resistance structure comprises a first resistance unit formed at the first part luminous point, wherein the resistance value of the first part luminous point formed with the first resistance unit is larger than that of the first part luminous point not formed with the first resistance unit.

According to another aspect of the present application, the present application also provides a method for fabricating a VCSEL chip, comprising: forming an epitaxial layer structure, wherein the epitaxial layer structure comprises from bottom to top: a substrate layer structure, an N-DBR layer structure, an active layer structure and a P-DBR layer structure; forming a negative electrode and a plurality of positive electrodes electrically connected to the epitaxial structure; removing at least a portion of the epitaxial layer structure to form a plurality of sub-structural units, each sub-structural unit comprising, from bottom to top: a negative electrode, a substrate layer, an N-DBR layer, an active region, a P-DBR layer, and a positive electrode; processing the plurality of sub-structural units to form a confinement layer having a confinement hole above the active region, thereby forming a plurality of VCSEL emission points, wherein the plurality of VCSEL emission points include a first partial emission point adjacent to an outer periphery of an emission region formed by the plurality of VCSEL emission points and a second partial emission point other than the first partial emission point; and implanting first ions into at least one VCSEL luminous point in the first partial luminous points in an ion implantation mode to form a first resistance unit, wherein the resistance value of the first partial luminous points formed with the first resistance unit is larger than that of the first partial luminous points not formed with the first resistance unit.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Schematic flow control and leveling VCSEL chip

As shown in fig. 2 to 8, a flow control balanced VCSEL chip according to an embodiment of the present application is illustrated, wherein the flow control balanced VCSEL chip comprises a light emitting region 10 and a resistive structure 30 formed in the light emitting region 10. The light emitting region 10 includes a plurality of VCSEL light emitting points 11, the plurality of VCSEL light emitting points 11 including a first partial light emitting point 110 adjacent to an outer circumference of the light emitting region 10 and a second partial light emitting point 120 other than the first partial light emitting point 110, the resistive structure 30 having a specific structural pattern to compensate for a difference in light emitting intensity between the first partial light emitting point 110 and the second partial light emitting point 120 by regulating and controlling a current passing through the first partial light emitting point 110 and the second partial light emitting point 120, thereby improving light emitting uniformity of the plurality of VCSEL light emitting points 11.

Specifically, in the embodiment of the present application, each VCSEL emission point 11 includes a light emitting body and a positive electrode 60 and a negative electrode 70 electrically connected to the light emitting body. The light emitting body includes, from bottom to top, a substrate layer 112, an N-DBR layer 113, an active region 114, a confinement layer 115, and a P-DBR layer 116, an upper surface of the P-DBR layer 116 forming an upper surface of the VCSEL light emitting point 11.

The substrate layer 112 is made of any one selected from GaAs, gaN, and lnP, which allows laser light having a wavelength ranging from 300nm to 150mm to pass therethrough. Preferably, the substrate layer 112 is made of GaAs material, which may be undoped, may be N-type doped (e.g., si doped), or may be P-type doped (e.g., zn doped). The absorption loss of the substrate layer 112 made of GaAs material for a laser light of a specific wavelength (e.g., 980nm band laser light) is very small and even negligible (e.g., when the substrate layer 112 is made in an undoped condition, the absorption loss thereof can be ignored).

The N-DBR layer 113 is made of N-type doped Al with high aluminum content _x Ga _1-x As (x=1 to 0) and N-doped Al with low aluminum content _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. The P-DBR layer 116 is made of P-doped high aluminum content Al _x Ga _1-x As (x=1 to 0) and P-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. In some examples of the application, the N-DBR layer 113 and the P-DBR layer 116 may even be made of materials that do not include aluminum, i.e., aluminum. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser light emitted by the VCSEL emission point 11, and that the optical thickness of each alternating layer is equal to or approximately equal to 1/4 of the operating wavelength of the laser light.

The active region 114 is sandwiched between the N-DBR layer 113 and the P-DBR layer 116 to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth in the resonant cavity after being excited to form laser oscillation, thereby forming laser light. It will be appreciated by those skilled in the art that the direction of the laser light emission, for example, from the N-DBR layer 113 or from the P-DBR layer 116 can be selectively controlled by configuring and designing the N-DBR layer 113 and the P-DBR layer 116. Accordingly, the N-DBR layer 113 and the P-DBR layer 116 are configured such that, after the VCSEL light emitting point 11 is turned on, laser light generated by the active region 114 is reflected multiple times in a resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116 and then emitted from the P-DBR layer 116 or from the N-PDBR layer 113.

The positive electrode 60 and the negative electrode 70 are used to turn on the VCSEL emission point 11. When the N-DBR layer 113 and the P-DBR layer 116 are configured such that laser light generated by the active region 114 is emitted from the P-DBR layer 116 after being reflected multiple times within a resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116 after the VCSEL light emitting point 11 is turned on, the positive electrode 60 has a ring shape, and the positive electrode 60 has a light emitting hole 102 corresponding to the limiting hole 101.

During operation, an operating voltage/current is applied to the positive electrode 60 and the negative electrode 70 of the VCSEL emission point 11 to generate a current in the VCSEL emission point 11. After being turned on, the current is limited in flow direction by the limiting layer 115, which is finally introduced into the middle region of the VCSEL emission point 11, so that the middle region of the active region 114 generates laser light, and the plurality of VCSEL emission points 11 generate a large amount of heat during the lasing and lasing process. More specifically, in the embodiment of the present application, the confinement layer 115 has a confinement region formed around the confinement holes 101, the confinement region having a higher resistivity to confine carriers flowing into the middle region of the VCSEL emission point 11, and a lower refractive index of the confinement region to laterally confine photons, the carriers and optical lateral confinement increasing the density of carriers and photons within the active region 114, increasing the efficiency of light generation within the active region 114, and the confinement holes 101 defining the exit aperture of the VCSEL emission point 11.

In some embodiments of the present application, the confinement layer 115 is implemented as an oxidation confinement layer formed over the active region 114 by an oxidation process. In the embodiment of the present application, the oxidation limiting layer may be formed as a separate layer above the active region 114, or may be formed above the active region 114 by oxidizing at least a portion of the lower region of the P-DBR layer 116, which is not limited to the present application. In other embodiments of the present application, the confinement layer 115 is implemented in other forms, for example, as an ion confinement layer (not shown) formed over the active region 114 by an ion implantation process, which is not limited to the present application.

In the embodiment of the present application, an isolation structure 103 is disposed between every two VCSEL emission points 11 in the plurality of VCSEL emission points 11, and the isolation structure 103 extends downward from the upper surface of the VCSEL emission point 11 to below the active region 114, so as to achieve electrical isolation between the plurality of VCSEL emission points 11. In a specific example of the present application, the isolation structure 103 is implemented as an isolation trench recessed from the upper surface of the VCSEL emission point 11 down to below the active region 114. In another specific example of the present application, the isolation structure 103 includes not only an isolation trench recessed downward from the upper surface of the VCSEL emission point 11 to below the active region 114, but also a point isolation layer covering at least a portion of the upper surface of the VCSEL emission point 11 and at least a portion of the isolation trench. In yet another specific example of the present application, the isolation structure 103 is implemented as an ion implantation layer extending from the upper surface of the VCSEL emission point 11 down to below the active region 114.

In the embodiment of the present application, the plurality of VCSEL emission points 11 of the emission region 10 are distributed in the emission region 10 in an equidistant manner. In a variant embodiment of the application, the plurality of VCSEL emission points 11 may be distributed in other ways in the emission region 10, which is not limiting to the application.

The light emitting region 10 has a peripheral portion adjacent to an outer periphery thereof and an inner region portion formed within the peripheral portion, the first partial light emitting point 110 is formed at the peripheral portion of the light emitting region 10, and the second partial light emitting point 120 is formed at the inner region portion of the light emitting region 10. The flow-control balanced VCSEL chip further includes a peripheral region 20 surrounding the light-emitting region 10, the peripheral region 20 is a non-light-emitting region, and the first portion of light-emitting points 110 are close to the peripheral region 20.

It should be noted that the light emission intensity of the VCSEL light emission point 11 is affected by temperature, and the higher the temperature, the lower the light emission intensity within a certain temperature variation range. When the VCSEL emission point 11 is in an operating state, heat will be generated and accumulated continuously with the duration of the operating time, affecting the emission intensity of the VCSEL emission point 11.

The peripheral area 20 provides sufficient heat dissipation space for the first portion of the light-emitting points 110, and the metal layer extending outward from the first portion of the light-emitting points 110 has strong thermal conductivity, so that the heat dissipation speed of the first portion of the light-emitting points 110 is further increased, and the heat dissipation advantage of the area where the first portion of the light-emitting points 110 are located is relatively better, the working temperature is lower, and the light-emitting intensity is relatively higher.

The second part of the light-emitting points 120 are surrounded by the first part of the light-emitting points 110, when the light-emitting points are in a working state, not only is the heat dissipation space limited, and heat is easy to accumulate, but also part of the heat of the first part of the light-emitting points 110 is diffused to the area where the second part of the light-emitting points 120 are located, so that the heat accumulation of the area where the second part of the light-emitting points 120 are located is aggravated, the heat dissipation advantage of the area where the second part of the light-emitting points 120 are located is relatively poor, the working temperature is higher, and the light-emitting intensity is relatively low. In this way, the plurality of VCSEL emission points 11 of the emission region 10 is prone to the problem of uneven emission intensity.

For this reason, the inventors of the present application proposed to improve the light emission uniformity of the VCSEL chip by reducing the light emission intensity of the VCSEL light emission point 11 having a higher light emission intensity. And further, the luminous intensity of the VCSEL luminous point 11 is related not only to the heat dissipation performance of the place where it is located, but also to the magnitude of the current passing through the VCSEL luminous point 11. The luminous intensity of the VCSEL luminous points 11 of different parts can be adjusted by controlling the current passing through the VCSEL luminous points 11 of each part in the luminous region 10 of the current control balanced VCSEL chip, so as to compensate the luminous intensity difference between the luminous points with poor heat dissipation advantage and lower luminous intensity and the luminous points with better heat dissipation advantage and higher luminous intensity, thereby improving the luminous uniformity among the plurality of VCSEL luminous points 11.

In the embodiment of the present application, different resistor configurations are formed at the peripheral portion and the inner region portion of the light emitting region 10, respectively, so as to regulate and control the current passing through the first partial light emitting point 110 of the peripheral portion and the second partial light emitting point 120 of the inner region portion of the light emitting region 10, and improve the light emitting uniformity among the plurality of VCSEL light emitting points 11 of the light emitting region 10.

Specifically, a resistor unit may be formed only at the first partial light emitting point 110, as shown in fig. 2 and 3, to increase the resistance of the first partial light emitting point 110, reduce the current passing through the first partial light emitting point 110, maintain the original structure of the second partial light emitting point 120 and the current passing through the second partial light emitting point 120, and balance the light emitting intensity between the first partial light emitting point 110 and the second partial light emitting point 120 through such a resistance configuration mode, so as to improve the light emitting uniformity of the flow control balanced VCSEL chip.

Accordingly, in some embodiments of the present application, the resistor structure 30 includes only the first resistor unit 31 formed at the first partial light emitting point 110, wherein the resistance value of the first partial light emitting point 110 formed with the first resistor unit 31 is greater than the resistance value of the first partial light emitting point 110 not formed with the first resistor unit 31.

It should be understood that the resistor units may be formed at both the first partial light emitting point 110 and the second partial light emitting point 120, as shown in fig. 4 to 7, and the degree of decrease of the resistor unit formed at the first partial light emitting point 110 to the light emitting intensity of the first partial light emitting point 110 is greater than the degree of decrease of the resistor unit formed at the second partial light emitting point 120 to the light emitting intensity of the second partial light emitting point 120, so that the light emitting intensity between the first partial light emitting point 110 and the second partial light emitting point 120 is balanced by such a resistor configuration mode, so as to improve the light emitting uniformity of the flow control balanced VCSEL chip.

Accordingly, in some embodiments of the present application, the resistor structure 30 includes not only the first resistor unit 31 formed at the first partial light emitting point 110, but also the second resistor unit 32 formed at the second partial light emitting point 120. The second partial light emitting point 120, in which the second resistance unit 32 is formed, has a resistance value greater than that of the second partial light emitting point 120, in which the second resistance unit 32 is not formed, and the first resistance unit 31 has a greater blocking effect on the current passing through the first partial light emitting point 110 than the second resistance unit 32 has on the current passing through the second partial light emitting point 120, so that the first resistance unit 31 has a greater degree of decrease in the light emitting intensity of the first partial light emitting point 110 than the second resistance unit 32 has in the light emitting intensity of the second partial light emitting point 120.

The control experiments were performed on the current-controlled balanced VCSEL chip (i.e., experimental group) provided with the resistive structure 30 and the conventional VCSEL chip (i.e., control group) not provided with the resistive structure 30, and experimental data show that the overall luminous intensity uniformity of the current-controlled balanced VCSEL chip is improved by 3% -25% compared to the conventional chip not provided with the resistive structure 30, and the average value of the overall luminous intensity uniformity of the current-controlled balanced VCSEL chip is about 15%.

The uniformity of the VCSEL chip can be represented by the non-uniformity characterization value, wherein the higher the non-uniformity characterization value is, the lower the luminous intensity uniformity is, and the lower the non-uniformity characterization value is, the higher the luminous intensity uniformity is. The improvement amplitude of the overall luminous intensity uniformity of the flow control balanced VCSEL chip is as follows: the ratio of the absolute value of the difference between the non-uniformity characterization value of the conventional VCSEL chip and the non-uniformity characterization value of the control flow type VCSEL chip to the non-uniformity characterization value of the conventional VCSEL chip. In a specific example of the present application, the flow control balanced VCSEL chip of the experimental group has a non-uniformity characterization value of 11.17%, the conventional VCSEL chip of the control group has a non-uniformity characterization value of 14.29%, and the overall emission intensity uniformity of the flow control balanced VCSEL chip of the experimental group is improved by 21.83% compared to the control group.

It should be noted that, in the embodiment of the present application, the resistor structure 30 is formed in the light emitting region 10 by ion Implantation (IMP), which makes the structural style and resistance of the finally formed resistor structure 30 controllable, and the current passing through the VCSEL light emitting point 11 of each portion of the light emitting region 10 can be controllably adjusted according to a desired pattern. Accordingly, the resistive structure 30 forms the first resistive element 31 by implanting a first ion body 301 to the VCSEL emission point 11 in the first partial emission point 110, and the resistive structure 30 forms the second resistive element 32 by implanting a second ion body 302 to the VCSEL emission point 11 in the second partial emission point 120.

The first resistor unit 31 extends downward from the upper surface of at least one of the VCSEL emission points 11 in the first partial emission point 110, and the second resistor unit 32 extends downward from the upper surface of at least one of the VCSEL emission points 11 in the second partial emission point 120. The extension depths of the first and second resistive units 31 and 32 are not limited by the present application. In a specific example of the present application, the first resistor unit 31 extends downward from the upper surface of the P-DBR layer 116 of at least one of the VCSEL emission points 11 in the first partial emission point 110, and the second resistor unit 32 extends downward from the upper surface of the P-DBR layer 116 of at least one of the VCSEL emission points 11 in the second partial emission point 120.

Further, the first resistance unit 31 includes a plurality of first resistance portions 311 formed at the plurality of VCSEL emission points 11 in the first partial emission point 110, and the second resistance unit 32 includes a plurality of second resistance portions 321 formed at the plurality of VCSEL emission points 11 in the second partial emission point 120. The resistor structure 30 forms the plurality of first resistor portions 311 by implanting first ions 301 into the plurality of VCSEL emission points 11 in the first partial emission point 110 to form the first resistor unit 31, and the resistor structure 30 forms the plurality of second resistor portions 321 by implanting second ions 302 into the plurality of VCSEL emission points 11 in the second partial emission point 120 to form the second resistor unit 32.

As described above, the first partial light-emitting point 110 is formed at the peripheral portion of the light-emitting area 10, the second partial light-emitting point 120 is formed at the inner portion of the light-emitting area 10, and the heat dissipation advantage of the area where the first partial light-emitting point 110 is located is relatively better, and the heat dissipation advantage of the area where the second partial light-emitting point 120 is located is relatively worse. According to the distribution characteristics of the plurality of VCSEL emission points 11 and the heat dissipation characteristics of the area where the plurality of VCSEL emission points 11 are located, when the plurality of VCSEL emission points 11 are turned on and are in a working state, the heat dissipation advantage of the area where the plurality of VCSEL emission points 11 are located from the center of the emission area 10 to the outer periphery thereof is gradually increased, and the emission intensity is gradually increased.

The pattern of the resistive structure 30 may be designed according to the above characteristics to improve the light emission uniformity of the control flow type VCSEL chip. Preferably, the resistive structure 30 gradually increases the blocking effect of the current through the VCSEL emission point 11 from the center of the emission region 10 towards its outer periphery. Accordingly, the resistance values of the plurality of first resistance portions 311 gradually increase from the region of the light emitting region 10 adjacent to the first partial light emitting point 110 toward the outer peripheral edge thereof, and the resistance values of the plurality of second resistance portions 321 gradually increase from the central region of the light emitting region 10 toward the outer peripheral edge thereof, and the average resistance value level of the plurality of first resistance portions 311 is greater than the average resistance value level of the plurality of second resistance portions 321.

Specifically, the resistance values of the first resistive portion 311 and the second resistive portion 321 may be adjusted by adjusting the distribution density, the size arrangement, the formation manner, and the like of the first resistive portion 311 and the second resistive portion 321. Preferably, the distribution density of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 of the resistive structure 30 is gradually increased from the central region of the light emitting region 10 toward the outer periphery thereof, and/or the width is gradually increased, and/or the depth is gradually increased, and/or the ion implantation concentration is gradually increased.

Accordingly, in one specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321. Specifically, the average level of the distance between each adjacent two of the plurality of first resistive portions 311 is smaller than the average level of the distance between each adjacent two of the plurality of second resistive portions 321. The first resistor portions 311 and the second resistor portions 321 are arranged in a uniform size, and the first resistor portions 311 and the second resistor portions 321 have a uniform ion implantation concentration.

In another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the average width level of the plurality of first resistive portions 311 is greater than the average width level of the plurality of second resistive portions 321, the average depth level of the plurality of first resistive portions 311 is identical to the average depth level of the plurality of second resistive portions 321, and the average ion implantation concentrations of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are identical.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is identical to the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the ion implantation concentration average levels of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are identical.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is greater than the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the ion implantation concentration average levels of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are identical.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is greater than the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11, as shown in fig. 7.

In yet another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are configured to be uniform in size, and the average implantation concentration level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL light emitting point 11 is greater than the average implantation concentration level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL light emitting point 11.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is greater than the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 and the depth average level of the plurality of second resistive portions 321 are identical, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is greater than the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 and the width average level of the plurality of second resistive portions 321 are identical, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11.

In another specific example of the present application, the distribution of the plurality of first resistive portions 311 and the distribution density of the plurality of second resistive portions 321 are identical. Specifically, the average level of the distance between each adjacent two of the plurality of first resistive portions 311 coincides with the average level of the distance between each adjacent two of the plurality of second resistive portions 321. The average width level of the first resistor 311 is greater than the average width level of the second resistor 321, and as shown in fig. 5, the average depth level of the first resistor 311 is identical to the average depth level of the second resistor 321, and the average ion implantation concentration levels of the first resistor 311 and the second resistor 321 are identical.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is identical to the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the ion implantation concentration average levels of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are identical.

In still another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the average width level of the plurality of first resistive portions 311 is greater than the average width level of the plurality of second resistive portions 321, the average depth level of the plurality of first resistive portions 311 is greater than the average depth level of the plurality of second resistive portions 321, and the average ion implantation concentration levels of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 are identical as shown in fig. 6.

In yet another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is greater than the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11.

In yet another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the size configuration of the plurality of first resistive portions 311 and the plurality of second resistive portions 321 is identical, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL light emitting point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL light emitting point 11.

In yet another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is greater than the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is identical to the depth average level of the plurality of second resistive portions 321, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11.

In yet another specific example of the present application, the distribution density of the plurality of first resistive portions 311 is identical to the distribution density of the plurality of second resistive portions 321, the width average level of the plurality of first resistive portions 311 is identical to the width average level of the plurality of second resistive portions 321, the depth average level of the plurality of first resistive portions 311 is greater than the depth average level of the plurality of second resistive portions 321, and the implantation concentration average level of the first ion body 301 of the plurality of first resistive portions 311 in its corresponding VCSEL emission point 11 is greater than the implantation concentration average level of the second ion body 302 of the plurality of second resistive portions 321 in its corresponding VCSEL emission point 11.

In some embodiments of the present application, the resistance of the first resistor 311 and the resistance of the second resistor 321 may also be controlled by adjusting the type of ions (i.e., the first ion body 301) implanted at the VCSEL emission point 11 in the first partial emission point 110 and the type of ions (i.e., the second ion body 302) implanted at the VCSEL emission point 11 in the second partial emission point 120.

Here, the parameter average level (e.g., distance average level, width average level, depth average level, implantation concentration average level) may be obtained by calculating an average value, a weighted sum, or a variance value of the parameters.

In summary, the VCSEL chip according to the embodiment of the present application has been elucidated, which can adjust the light emission intensities of the VCSEL light emission points 11 of different parts by controlling the currents passing through the VCSEL light emission points 11 of the respective parts in the light emission region 10 thereof, so as to improve the light emission uniformity of the whole thereof.

Method for preparing schematic VCSEL chip

According to another aspect of the present application, there is also provided a method of fabricating a VCSEL chip for fabricating a flow-controlled balanced VCSEL chip as described above. Referring to fig. 8 to 9C of the drawings of the specification, a method of fabricating a flow-controlling balanced VCSEL chip according to an embodiment of the present application is illustrated. It should be noted that, in the embodiment of the present application, the preparation method of the VCSEL chip provided by the present application can form the resistor structure 30 only by changing or adding one process based on the conventional preparation process of the VCSEL chip, so that the light emitting uniformity of the finally formed VCSEL chip can be improved by simply adjusting the conventional preparation process of the VCSEL chip, and the original VCSEL chip production line and production equipment can be reserved for preparing the flow-control balanced VCSEL chip of the present application, so that the modification cost of the flow-control balanced VCSEL chip production line is effectively reduced, and the preparation cost is further reduced.

As shown in fig. 8, in an embodiment of the present application, the method for preparing the VCSEL chip includes: s110, forming an epitaxial layer structure, wherein the epitaxial layer structure comprises the following components from bottom to top: a substrate layer structure, an N-DBR layer structure, an active layer structure and a P-DBR layer structure; s120, forming a negative electrode and a plurality of positive electrodes electrically connected to the epitaxial structure; s130, removing at least one part of the epitaxial layer structure to form a plurality of sub-structure units, wherein each sub-structure unit comprises from bottom to top: a negative electrode, a substrate layer, an N-DBR layer, an active region, a P-DBR layer, and a positive electrode; s140, processing the plurality of sub-structural units to form a confinement layer having a confinement hole above the active region, thereby forming a plurality of VCSEL emission points, wherein the plurality of VCSEL emission points include a first partial emission point adjacent to an outer periphery of an emission region formed by the plurality of VCSEL emission points and a second partial emission point other than the first partial emission point; and S150, implanting first ions into at least one VCSEL luminous point in the first partial luminous points in an ion implantation mode to form a first resistance unit, wherein the resistance value of the first partial luminous points formed with the first resistance unit is larger than that of the first partial luminous points not formed with the first resistance unit.

Fig. 9A to 9C are schematic diagrams illustrating a process of fabricating the flow control balanced VCSEL chip according to an embodiment of the present application. As shown in fig. 9A, in step S110, an epitaxial layer structure 300 is formed. Specifically, a substrate layer structure 320 is formed through a semiconductor growth process, and then an N-DBR layer structure 330, an active layer structure 340, and a P-DBR layer structure 350 stacked on the substrate layer structure 320 are sequentially formed on the upper surface of the substrate layer structure 320.

In step S120, a negative electrode 70 and a plurality of positive electrodes 60 electrically connected to the epitaxial structure 300 are formed. Specifically, a P-type electrical contact layer structure is formed on the upper surface of the P-DBR layer structure 350 to form the plurality of positive electrodes 60, and an N-type electrical contact layer structure is formed on the lower surface of the substrate layer structure 320 opposite to the upper surface thereof to form the negative electrode 70. Further, the plurality of positive electrodes 60 and the negative electrode 70 may be formed through an electroplating process, or the plurality of positive electrodes 60 and the negative electrode 70 may be formed through other processes, which is not limited to the present application.

In one specific example of the present application, the flow-controlling balanced VCSEL chip is designed such that laser light exits the P-DBR layer 116 formed from at least a portion of the P-DBR layer structure 350 during subsequent fabrication. In this specific example, a plurality of positive electrodes 60 are formed at preset positions of the P-DBR layer structure 350, and the positive electrodes 60 are ring-shaped to define a plurality of light exit holes 102 allowing laser light to pass through.

As shown in fig. 9B, at least a portion of the epitaxial-layer structure 300 is removed in step S130 to form a plurality of sub-structure units 400. Specifically, at least a portion of the epitaxial layer structure 300 is removed by an etching process to form at least one isolation trench, thereby forming a plurality of sub-structure units 400, wherein the isolation trench forms an isolation structure 103 between the plurality of sub-structure units 400 to achieve electrical isolation between the plurality of sub-structure units 400. Each of the sub-structure units 400 includes, from bottom to top: a negative electrode 70, a substrate layer 112, an N-DBR layer 113, an active region 114, a P-DBR layer 116, and a positive electrode 60.

The specific depth of the isolation trench is not limited by the present application in this embodiment, and in one specific example of the present application, the isolation trench extends downward from the P-DBR layer structure 350 to below the first active layer structure 340. In one specific example of the present application, the isolation trench extends downward from the P-DBR layer structure 350 to the first N-DBR layer structure 330. In another specific example of the present application, the isolation trench extends downward from the P-DBR layer structure 350 to the substrate layer structure 320.

In a variant embodiment of the present application, the isolation structure 103 between the plurality of sub-structure units 400 may be formed by implanting ions into the epitaxial structure 300 to achieve electrical isolation between the plurality of sub-structure units 400.

In step S140, the plurality of sub-structure units 400 are processed to form a confinement layer 115 having a confinement hole 101 above the active region 114. Specifically, the confinement layer 115 may be formed by an oxidation process. First, in order to protect the positive electrode 60, a protective layer covering the positive electrode 60 is formed before oxidizing the plurality of sub-structural units 400; next, the plurality of sub-structure units 400 are oxidized, and after the sub-structure units 400 are oxidized, a portion of the P-DBR layer 116 is oxidized to form an oxidation limiting layer 115 having limiting holes 101 above the active region 114, the limiting holes 101 corresponding to the light emitting holes 102; then, the positive electrode 60 is exposed, and the positive electrode 60 may be exposed by removing at least a portion of the protective layer coated on the positive electrode 60. That is, step S140 includes: forming a protective layer covering the positive electrode 60; oxidizing the plurality of sub-structure units 400 to form an oxidation limiting layer 115 having limiting holes 101 over the active region 114; and exposing the plurality of positive electrodes 60.

It should be noted that the confinement layer 115 may be formed by other processes, for example, the ion confinement layer 115 above the active region 114 may be formed by an ion implantation process, which is not limited by the present application.

The plurality of sub-structure units 400 forming the confinement layer 115 form a plurality of VCSEL emission points 11, each of the VCSEL emission points 11 including, from bottom to top: a negative electrode 70, a substrate layer 112, an N-DBR layer 113, an active region 114, a confinement layer 115 having a confinement aperture 101 corresponding to the active region 114, a P-DBR layer 116, and a P-type electrical contact layer 117. The plurality of VCSEL emission points 11 includes a first partial emission point 110 adjacent to an outer periphery of the emission region 10 formed of the plurality of VCSEL emission points 11 and a second partial emission point 120 other than the first partial emission point 110.

When the VCSEL emission points 11 are turned on, heat in the area where the second partial emission point 120 is located is easily accumulated, and the operating temperature is higher and the emission intensity is lower than that of the first partial emission point 110. In some embodiments of the present application, the resistor unit is formed only at the first partial light emitting point 110, so as to reduce the current passing through the first partial light emitting point 110, reduce the light emitting intensity of the first partial light emitting point 110, and further improve the light emitting uniformity of the whole flow control type VCSEL chip.

Accordingly, as shown in fig. 9C, in step S150, the first ion body 301 is implanted into at least one VCSEL light emitting point 11 of the first partial light emitting points 110 by means of ion implantation, so as to form the first resistor unit 31, and the resistance value of the first partial light emitting point 110 formed with the first resistor unit 31 is greater than the resistance value of the first partial light emitting point 110 not formed with the first resistor unit 31.

In other embodiments of the present application, the resistor unit is formed not only at the first partial light emitting point 110 but also at the second partial light emitting point 120, and the degree of decrease of the resistor unit formed at the first partial light emitting point 110 to the light emitting intensity of the first partial light emitting point 110 is greater than the degree of decrease of the resistor unit formed at the second partial light emitting point 120 to the light emitting intensity of the second partial light emitting point 120, so that the light emitting intensity between the first partial light emitting point 110 and the second partial light emitting point 120 is balanced by such a resistor configuration mode, so as to improve the light emitting uniformity of the flow control balanced VCSEL chip.

Accordingly, the method for fabricating a VCSEL chip further includes step S160 of implanting a second ion body 302 to the second partial light emitting point 120 by ion implantation to form a second resistor unit 32, wherein a resistance value of the second partial light emitting point 120 formed with the second resistor unit 32 is greater than a resistance value of the second partial light emitting point 120 not formed with the second resistor unit 32, and a blocking effect of the first resistor unit 31 on a current passing through the first partial light emitting point 110 is greater than a blocking effect of the second resistor unit 32 on a current passing through the second partial light emitting point 120.

The resistance values of the first resistor 311 and the second resistor 321 can be adjusted by adjusting the distribution density, the size configuration, the formation mode, and the like of the first resistor 311 and the second resistor 321, so as to improve the light emission uniformity of the control flow type VCSEL chip. The specific structures of the first resistive portion 311 and the second resistive portion 321 are described in detail in the description of the first resistive portion 311 and the second resistive portion 321 of the flow control balanced VCSEL chip illustrated in fig. 1 to 7, and thus, repetitive descriptions thereof will be omitted.

In summary, the method for fabricating the VCSEL chip according to the embodiment of the present application is explained, which adjusts the light emission intensity of the VCSEL light emitting points 11 of different portions by controlling the current passing through the VCSEL light emitting points 11 of each portion in the light emitting region 10 thereof, so as to improve the overall light emission uniformity thereof.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

Claims

1. A controlled flow type VCSEL chip, comprising:

2. The flow-controlled balanced VCSEL chip of claim 1, wherein the resistive structure is formed in the light emitting region by ion implantation.

3. The controlled-flow distributed VCSEL chip of claim 2, wherein the resistive structure forms the first resistive element by implanting a first ion body into a VCSEL emission point in the first partial emission point.

4. A flow-controlled balanced VCSEL chip as claimed in claim 3, wherein the first resistive element extends downwards from an upper surface of at least one of the VCSEL emission points in the first section emission point.

5. The flow-controlled balanced VCSEL chip of claim 4, wherein each VCSEL emission point comprises, from bottom to top, a negative electrode, a substrate layer, an N-DBR layer, an active region, a confinement layer with a confinement aperture, a P-DBR layer, and a positive electrode, wherein an upper surface of the P-DBR layer forms an upper surface of the VCSEL emission point, the first resistive element extending downward from an upper surface of the P-DBR layer of at least one of the VCSEL emission points in the first section.

6. The flow-controlled balanced VCSEL chip of claim 1, further comprising a second resistive element formed at the second partial light emitting point, wherein the second partial light emitting point at which the second resistive element is formed has a resistance value greater than that of the second partial light emitting point at which the second resistive element is not formed, and the first resistive element has a greater blocking effect on a current passing through the first partial light emitting point than that of the second resistive element, in such a manner that the light emission uniformity of the flow-controlled balanced VCSEL chip is improved.

7. The flow-controlled balanced VCSEL chip of claim 6, wherein the first resistive unit comprises a plurality of first resistive sections formed at a plurality of VCSEL emission points in the first partial emission point, the second resistive unit comprises a plurality of second resistive sections formed at a plurality of VCSEL emission points in the second partial emission point, and an average level of resistance of the plurality of first resistive sections is greater than an average level of resistance of the plurality of second resistive sections.

8. The controlled-flow distributed VCSEL chip of claim 7, wherein the average level of the width of the first plurality of resistive segments is greater than the average level of the width of the second plurality of resistive segments.

9. The controlled-flow distributed VCSEL chip of claim 7, wherein the depth average level of the first plurality of resistive portions is greater than the depth average level of the second plurality of resistive portions.

10. The controlled-flow distributed VCSEL chip of claim 7, wherein the resistive structure forms the first resistive element by implanting first ions into a plurality of VCSEL emission points in the first portion emission point, and the resistive structure forms the second resistive element by implanting second ions into a plurality of VCSEL emission points in the second portion emission point, wherein an average level of implantation concentration of the first ions in their corresponding VCSEL emission points is greater than an average level of implantation concentration of the second ions in their corresponding VCSEL emission points.

11. The controlled-flow distributed VCSEL chip of claim 7, wherein the distribution density of the first plurality of resistive segments is greater than the distribution density of the second plurality of resistive segments.

12. A controlled-flow type VCSEL chip as claimed in claim 1 or 7, wherein the resistances of the plurality of first resistive portions gradually increase from a region of the light emitting region adjacent to the first partial light emitting point to an outer periphery thereof.

13. The controlled-flow distributed VCSEL chip of claim 7, wherein the resistances of the plurality of second resistive portions gradually increase from a central region of the light emitting region to an outer periphery thereof.

14. A method of fabricating a VCSEL chip, comprising:

15. The method of fabricating a VCSEL chip of claim 14, further comprising:

and implanting second ions into the second part luminous points in an ion implantation mode to form a second resistance unit, wherein the resistance value of the second part luminous points formed with the second resistance unit is larger than that of the second part luminous points not formed with the second resistance unit, and the blocking effect of the first resistance unit on the current passing through the first part luminous points is larger than that of the second resistance unit on the current passing through the second part luminous points.