CN116667136A

CN116667136A - VCSEL chip and preparation method thereof

Info

Publication number: CN116667136A
Application number: CN202210145862.8A
Authority: CN
Inventors: 王聖允; 王朝成; 田志偉; 李正潮; 王立; 李念宜
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2022-02-17
Filing date: 2022-02-17
Publication date: 2023-08-29

Abstract

The application discloses a VCSEL chip and a preparation method thereof, wherein the VCSEL chip comprises a light-emitting area and a heat sink structure formed in the light-emitting area. The light emitting region includes a plurality of VCSEL light emitting points, wherein the plurality of VCSEL light emitting points includes a second partial light emitting point adjacent to an outer periphery of the light emitting region and a first partial light emitting point other than the second partial light emitting point. The heat sink structure only corresponds to the first part of luminous points, and has a specific structural style so that the heat dissipation performance of the first part of luminous points is improved under the heat dissipation effect of the heat sink structure, and in such a way, the luminous uniformity of the plurality of VCSEL luminous points is improved.

Description

VCSEL chip and preparation method thereof

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to VCSEL chips and methods of fabricating the same.

Background

A VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. In recent years, VCSEL chips are widely used as projection light sources in the fields of intelligent transportation, health care, biological detection, military security, and the like.

In the practical industry, a plurality of light emitting points formed by a plurality of VCSEL lasers are typically arranged on a VCSEL chip, so as to meet requirements on light intensity, partition lighting, sensing accuracy and the like of a light source in different application scenarios. However, when the light emitting points are more and the light emitting power is larger, the problem of uneven heat dissipation of the VCSEL chip is easy to occur, resulting in uneven light emitting intensity of different areas of the VCSEL chip.

Specifically, the luminous intensity of the luminous point is affected by temperature, and the higher the temperature, the lower the luminous intensity within a certain temperature variation range. The luminous points of the partial areas of the VCSEL chip are concentrated, heat is easily accumulated with the duration of the operating time, the temperature is high, and the luminous intensity is relatively low. The luminous points of other areas of the VCSEL chip are scattered, the heat dissipation space is large, the temperature is low in the working state, and the luminous intensity is relatively high. In this way, the VCSEL chip in which the plurality of light emitting points are arranged is liable to have a problem that the light emitting intensities of the light emitting points are not uniform, so that the light emitting intensities of the VCSEL chip are not uniform.

Therefore, a new VCSEL chip design is needed to improve the emission uniformity of the VCSEL chip.

Disclosure of Invention

An advantage of the present application is to provide a VCSEL chip and a method of fabricating the same, in which the VCSEL chip can improve heat dissipation performance of a portion of a light emitting region by adding a heat dissipation structure to only the portion of the light emitting region where heat is easily accumulated, so as to improve light emission uniformity of the VCSEL chip.

Another advantage of the present application is to provide a VCSEL chip and a method for manufacturing the same, in which the VCSEL chip is configured with a heat sink structure having a specific pattern for a portion of the light emitting region having poor self-heat dissipation advantage, so that the heat sink structure not only can enhance the overall light emitting intensity of the portion to balance the light emitting intensity of the portion and a portion of the light emitting region having good self-heat dissipation advantage, but also can present a gradually increasing tendency of heat dissipation of the portion from a central region of the light emitting region to an outer periphery thereof to enhance the light emitting uniformity of the portion.

Still another advantage of the present application is to provide a VCSEL chip and a method of fabricating the same, in which the VCSEL chip can improve light emission uniformity of the VCSEL chip without changing a relative positional relationship of light emitting points of the respective VCSELs.

In one advantage of the present application, a VCSEL chip and a method for manufacturing the same are provided, wherein a conventional process for manufacturing the VCSEL chip is used in the manufacturing process of the VCSEL chip, so that an original VCSEL chip production line and production equipment can be reserved for manufacturing the VCSEL chip of the present application, and the production line modification cost of the VCSEL chip is effectively reduced, thereby reducing the manufacturing cost of the VCSEL chip.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided a VCSEL chip including:

a light emitting region including a plurality of VCSEL light emitting points, wherein the plurality of VCSEL light emitting points includes a second partial light emitting point adjacent to an outer periphery of the light emitting region and a first partial light emitting point other than the second partial light emitting point; and

and the heat sink structure is formed in the light-emitting area and corresponds to the first part of light-emitting points only, and has a specific structural style so that the heat dissipation performance of the first part of light-emitting points is improved under the heat dissipation effect of the heat sink structure.

In the VCSEL chip according to the present application, the heat sink structure comprises a plurality of heat sink points spaced from the center of the light emitting region toward the outer periphery thereof.

In the VCSEL chip according to the present application, an arrangement density of the plurality of heat sink points in a central region adjacent to and/or the light emitting region is greater than an arrangement density of the plurality of heat sink points in a central region distant from the light emitting region.

In the VCSEL chip according to the present application, a width dimension of a heat sink point of the plurality of heat sink points in a central region adjacent to and/or the light emitting region is equal to or larger than a width dimension of a heat sink point of the plurality of heat sink points in a central region distant from the light emitting region.

In the VCSEL chip according to the present application, a depth dimension of a heat sink point of the plurality of heat sink points in a central region adjacent to and/or the light emitting region is equal to or greater than a depth dimension of a heat sink point of the plurality of heat sink points in a central region distant from the light emitting region.

In the VCSEL chip according to the present application, a thermal conductivity coefficient of a heat sink point of the plurality of heat sink points that is adjacent to and/or in a central region of the light emitting region is greater than or equal to a thermal conductivity coefficient of a heat sink point of the plurality of heat sink points that is distant from the central region of the light emitting region.

In the VCSEL chip according to the present application, at least some of the plurality of heat sink points are annularly distributed to form at least one point-annular heat sink strip.

In the VCSEL chip according to the present application, wherein the at least one dot-loop heat sink strip includes a plurality of dot-loop heat sink strips, a distance between the plurality of dot-loop heat sink strips gradually increasing from a central region of the light emitting region toward an outer periphery thereof.

In the VCSEL chip according to the present application, the heat sink structure comprises at least two heat sink strips spaced from the center of the light emitting region to the outer periphery thereof.

In the VCSEL chip according to the present application, the distance between each two adjacent heat sink strips of the at least two heat sink strips gradually increases from the central region of the light emitting region toward the outer periphery thereof.

In the VCSEL chip according to the application, the individual heat sink strips of the at least two heat sink strips have the same dimensional configuration.

In the VCSEL chip according to the present application, a width dimension of the heat sink strip of the at least two heat sink strips adjacent to and/or located at the central region of the light emitting region is equal to or larger than a width dimension of the heat sink strip of the at least two heat sink strips remote from the central region of the light emitting region.

In the VCSEL chip according to the present application, a depth dimension of the heat sink strips of the at least two heat sink strips adjacent to and/or located in the central region of the light emitting region is equal to or larger than a depth dimension of the heat sink strips of the at least two heat sink strips remote from the central region of the light emitting region.

In the VCSEL chip according to the present application, the heat sink strips of the at least two heat sink strips adjacent to and/or located in the central region of the light emitting region have a heat conduction coefficient that is greater than or equal to the heat conduction coefficient of the heat sink strips of the at least two heat sink strips remote from the central region of the light emitting region.

In the VCSEL chip according to the present application, the distances between every two adjacent heat sink strips of the at least two heat sink strips are equal, the at least two heat sink strips having different dimensional configurations.

In the VCSEL chip according to the application, the width dimension of the heat sink strips of the at least two heat sink strips adjacent to and/or at the central region of the light emitting region is larger than the width dimension of the heat sink strips of the at least two heat sink strips remote from the central region of the light emitting region.

In the VCSEL chip according to the application, the depth dimension of the heat sink strips of the at least two heat sink strips adjacent to and/or at the central region of the light emitting region is greater than the depth dimension of the heat sink strips of the at least two heat sink strips remote from the central region of the light emitting region.

According to another aspect of the present application, there is provided a method of manufacturing a VCSEL chip, comprising:

forming an epitaxial layer structure, wherein the epitaxial layer structure comprises from bottom to top: a substrate layer structure, an N-type electrical contact layer structure, an N-DBR layer structure, an active layer structure, a P-DBR layer structure, and a P-type electrical contact layer structure;

forming a plurality of positive electrodes electrically connected to the P-type electrical contact layer structure;

removing at least a portion of the epitaxial layer structure to form a plurality of sub-structural units, each sub-structural unit comprising, from bottom to top: a substrate layer, an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer;

Processing the plurality of sub-structural units to form a confinement layer having a confinement hole above the active region, thereby forming a plurality of light emitting bodies, wherein the plurality of light emitting bodies includes a second partial light emitting body adjacent to an outer periphery of a light emitting region forming region formed by the plurality of light emitting bodies and a first partial light emitting body other than the second partial light emitting body;

removing at least a portion of the substrate layer to form at least one recess corresponding to only the first portion of the light-emitting body; and

and filling the at least one groove with a heat conducting material to form a heat sink structure.

Thinning the substrate layer; and

and removing at least one part of the thinned substrate layer of the first part of luminous body through an etching process to form at least one groove.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, wherein:

Fig. 1 illustrates a schematic partial structure of a VCSEL chip according to an embodiment of the present application.

Fig. 2 illustrates another partial schematic structure of a VCSEL chip according to an embodiment of the present application.

Fig. 3 illustrates a partial schematic structure of a variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 4 illustrates a schematic diagram of a heat sink structure distribution of a VCSEL chip according to an embodiment of the present application.

Fig. 5 illustrates a heat sink structure distribution diagram of a variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 6 illustrates a heat sink structure distribution diagram of another variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 7 illustrates a heat sink structure distribution diagram of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 8 illustrates a heat sink structure distribution diagram of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 9 illustrates a heat sink structure distribution diagram of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Figure 10 illustrates a heat sink structure distribution diagram of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Figure 11 illustrates a heat sink structure distribution schematic of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Figure 12 illustrates a heat sink structure distribution schematic of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 13 illustrates a heat sink structure distribution diagram of a further variant implementation of a VCSEL chip according to an embodiment of the present application.

Fig. 14 illustrates a flow diagram of a method of fabricating a VCSEL chip according to an embodiment of the present application.

Fig. 15A illustrates one of schematic diagrams of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Fig. 15B illustrates a second schematic diagram of a process for fabricating a VCSEL chip according to an embodiment of the present application.

Fig. 15C illustrates a third schematic diagram of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Fig. 16 illustrates a partial schematic diagram of an analog structure of a VCSEL chip according to an embodiment of the present application.

Fig. 17 illustrates a schematic diagram of a thermal performance test of a VCSEL chip according to an embodiment of the present application.

Fig. 18 illustrates an operating temperature schematic of the light emission point of a VCSEL chip according to an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the application is provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application

As described above, in the actual industry, a plurality of light emitting points formed by a plurality of VCSEL lasers are generally arranged on a VCSEL chip to satisfy requirements in terms of light intensity, area lighting, sensing accuracy, and the like of a light source in different application scenes. However, when the light emitting points are more and the light emitting power is larger, the problem of uneven heat dissipation of the VCSEL chip is easy to occur, resulting in uneven light emitting intensity of different areas of the VCSEL chip.

For example, in general, the light emitting points of the middle area of the VCSEL chip are concentrated, the outer layer of the VCSEL chip is further provided with a plurality of light emitting points, and the light emitting points of the outer layer form a heat source, which not only blocks outward diffusion of heat from the light emitting points of the middle area, but also blocks inward diffusion of heat from the light emitting points of the outer layer, so that the heat from the middle area is easily accumulated, the heat dissipation performance is poor, and the light emitting intensity is relatively low. The periphery of the luminous point (namely, the luminous point of the outer layer) of the VCSEL chip, which is close to the edge area of the VCSEL chip, is a non-luminous area, so that the heat dissipation space is large, and the heat dissipation of the luminous point of the outer layer is facilitated. And the metal layer extending outwards from the luminous point of the outer layer has stronger heat conductivity, so that the heat dissipation speed of the luminous point of the outer layer is further accelerated, and therefore, the heat dissipation performance of the VCSEL chip at the luminous point close to the edge area of the VCSEL chip is better, and the luminous intensity is relatively higher. Thus, the VCSEL chip is liable to have a problem that the luminous intensity of the middle luminous point and the luminous point of the outer layer are not uniform, so that the luminous intensity of the VCSEL chip is not uniform.

At present, the heat dissipation performance of the middle part of the light emitting area structure is improved mainly by increasing the distance between the light emitting points of the VCSELs positioned at the middle part of the light emitting area, so that the heat dissipation uniformity of the VCSEL chip is improved. However, the increase in the distance between the plurality of VCSEL emission points of the VCSEL emission region structure reduces the available space around the VCSEL emission region structure, resulting in a reduction in wiring flexibility and an increase in wiring difficulty. Also, the overall volume of the VCSEL chip may need to be increased, resulting in an increase in manufacturing costs. Further, increasing the distance between a portion of the plurality of VCSEL emission points will affect the distribution uniformity and distribution density between all of the plurality of VCSEL emission points. Moreover, in some application scenarios with specific requirements on the distribution positions of the plurality of VCSEL emission points, increasing the distance between the plurality of VCSEL emission points located in the middle of the emission region conflicts with the specific requirements, for example, in some sensing scenarios, the density of the emission points in the middle of the emission region needs to be increased to increase the sensing accuracy.

The inventor of the present application proposes that a heat dissipation structure may be added only to a portion of the light emitting region of the VCSEL chip where heat is easily accumulated to enhance heat dissipation performance of the portion of the light emitting region, so as to enhance overall light emission uniformity of the VCSEL chip. Specifically, a heat sink structure is formed at a part of the light-emitting area corresponding to a first part of light-emitting points with poor self heat radiation advantage, so that the heat radiation performance of the first part of light-emitting points is improved under the heat radiation effect of the heat sink structure, the light-emitting intensity of the first part of light-emitting points is close to the light-emitting intensity of a second part of light-emitting points with good self light radiation advantage in the light-emitting area, and the light-emitting uniformity of a plurality of VCSEL light-emitting points of the VCSEL chip is improved.

Based on this, the application proposes a VCSEL chip comprising: the light-emitting device comprises a light-emitting area and a heat sink structure formed in the light-emitting area. The light emitting region includes a plurality of VCSEL light emitting points, wherein the plurality of VCSEL light emitting points includes a second partial light emitting point adjacent to an outer periphery of the light emitting region and a first partial light emitting point other than the second partial light emitting point. The heat sink structure only corresponds to the first part of luminous points, and has a specific structural style so that the heat dissipation performance of the first part of luminous points is improved under the heat dissipation effect of the heat sink structure, and in such a way, the luminous uniformity of the plurality of VCSEL luminous points is improved.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Schematic VCSEL chip

As shown in fig. 1 to 13, a VCSEL chip according to an embodiment of the present application is illustrated, wherein the VCSEL chip includes a light emitting region 10 and a heat sink structure 20 formed at the light emitting region 10. The light emitting region 10 includes the plurality of VCSEL light emitting points 11 including a second partial light emitting point 120 adjacent to an outer periphery of the light emitting region 10 and a first partial light emitting point 110 other than the second partial light emitting point 120, and the heat sink structure 20 corresponds to only the first partial light emitting point 110 of the light emitting region 10, so that a heat dissipation performance of the first partial light emitting point 110 having poor self heat dissipation advantage is improved under a heat dissipation effect of the heat sink structure 20, and further, a light emission intensity of the first partial light emitting point 110 approaches a light emission intensity of the second partial light emitting point 120 having excellent self heat dissipation advantage, in such a manner that light emission uniformity of the plurality of VCSEL light emitting points 11 is improved.

Specifically, when the plurality of VCSEL emission points 11 are turned on and in an operating state, the closer the position of the VCSEL emission point 11 is to the outer periphery of the emission region 10, the better the self heat radiation advantage, and conversely, the closer the position of the VCSEL emission point 11 is to the center of the emission region 10, the worse the self heat radiation advantage. That is, the heat radiation advantage of the plurality of VCSEL light emitting points 11 themselves gradually increases from the center of the light emitting region 10 toward the outer periphery thereof, and the heat radiation advantage of the plurality of VCSEL light emitting points 11 themselves gradually decreases from the outer periphery of the light emitting region inward. The light emitting region 10 may be divided into an edge region portion and an inner region portion according to a distance from an outer circumference thereof and a heat dissipation difference of the VCSEL light emitting point 11 formed due to the distance of the outer circumference thereof.

For example, in the light emitting region 10 formed by the VCSEL array of 10×10, the outermost layer of VCSEL light emitting points 11 surrounding the outer periphery of the light emitting region 10 forms an annular edge region portion, the width of which is one tenth of the width of the entire light emitting region 10, and the total area accounts for 36% of the entire light emitting region 10. The portion formed in the edge region portion is an inner region portion of the light emitting region 10, and the total area occupies 64% of the entire light emitting region 10.

Accordingly, in the embodiment of the present application, the light emitting region 10 has an edge region portion adjacent to the outer periphery thereof and an inner region portion formed within the edge region. The first partial light emitting point 110 is formed at an inner region portion of the light emitting region 10. The light emission intensity of the VCSEL light emission point 11 is affected by temperature, and the higher the temperature, the lower the light emission intensity within a certain temperature variation range. When the VCSEL emission point 11 is in the operating state, heat will be generated and accumulated over the duration of the operating time.

The first part of the light-emitting points 110 are surrounded by the second part of the light-emitting points 120, when the light-emitting points are in a working state, not only is the heat dissipation space limited, and heat is easy to accumulate, but also part of the heat of the second part of the light-emitting points 120 diffuses to the area where the first part of the light-emitting points 110 are located, so that the heat accumulation of the area where the first part of the light-emitting points 110 is located is aggravated, the heat dissipation advantage of the first part of the light-emitting points 110 is relatively poor, the working temperature is high, and the light-emitting intensity is relatively low.

The periphery of the second part luminous point 120 is a non-luminous area of the VCSEL chip, the non-luminous area can provide enough heat dissipation space for the second part luminous point 120, and the metal layer extending outwards from the second part luminous point 120 has strong thermal conductivity, so that the heat dissipation speed of the second part luminous point 120 is further increased, the heat dissipation advantage of the second part luminous point 120 is relatively better, the working temperature is lower, and the luminous intensity is relatively higher. Thus, the plurality of VCSEL units of the light emitting region 10 is liable to have a problem of uneven light emission intensity.

In the embodiment of the present application, a heat dissipation structure is added only to the inner region portion of the light emitting region 10 where heat is easily accumulated, so as to improve the heat dissipation performance of the inner region portion of the light emitting region 10, so as to improve the light emission uniformity of the plurality of VCSEL light emitting points 11 of the VCSEL light emitting region 10. Further, in the embodiment of the present application, the heat sink structure 20 corresponds to only the first part of the light emitting points 110 of the inner area of the light emitting area 10, so that the heat dissipation performance of the first part of the light emitting points 110 with poor self heat dissipation advantage of the VCSEL chip is improved under the heat dissipation effect of the heat sink structure 20, so that the final heat dissipation performance of the area where the first part of the light emitting points 110 is located approaches to the final heat dissipation performance of the area where the second part of the light emitting points 120 is located, and further, the light emission intensity of the first part of the light emitting points 110 approaches to the light emission intensity of the second part of the light emitting points 120 with good self heat dissipation advantage, so as to improve the light emission uniformity of the plurality of VCSEL light emitting points 11.

More specifically, in the embodiment of the present application, each VCSEL emission point 11 includes a light emitting body and a positive electrode 60 and a negative electrode 70 electrically connected to the light emitting body. As shown in fig. 1 to 3, the light emitting body includes a substrate layer 111, an N-type electric contact layer 112, an N-DBR layer 113, an active region 114, a confinement layer 115, a P-DBR layer 116, and a P-type electric contact layer 117 from bottom to top.

The material of the substrate layer 111 is selected from any one of GaAs, gaN, and lnP, which allows laser light having a wavelength ranging from 300nm to 150mm to pass therethrough. Preferably, the substrate layer 111 is made of GaAs material, which may be undoped, may be N-type doped (e.g., si doped), or may be P-type doped (e.g., zn doped). The absorption loss of the substrate layer 111 made of GaAs material to a laser light of a specific wavelength (for example, a laser light of 980nm band) is very small and can be ignored (for example, when the substrate layer 111 is made in an undoped condition, the absorption loss thereof can be ignored).

The N-DBR layer 113 is made of N-type doped Al with high aluminum content _x Ga _1-x As (x=1 to 0) and N-doped Al with low aluminum content _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. The P-DBR layer 116 is made of P-doped high aluminum content Al _x Ga _1-x As (x=1 to 0) and P-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. In some examples of the application, the N-DBR layer 113 and the P-DBR layer 116 may even be made of materials that do not include aluminum, i.e., aluminum. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser light emitted by the VCSEL emission point 11, and that the optical thickness of each alternating layer is equal to or approximately equal to 1/4 of the operating wavelength of the laser light.

The active region 114 is sandwiched between the N-DBR layer 113 and the P-DBR layer 116 to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth in the resonant cavity after being excited to form laser oscillation, thereby forming laser light. It will be appreciated by those skilled in the art that the direction of the laser light emission, for example, from the N-DBR layer 113 or from the P-DBR layer 116 can be selectively controlled by configuring and designing the N-DBR layer 113 and the P-DBR layer 116. Accordingly, the N-DBR layer 113 and the P-DBR layer 116 are configured such that, after the VCSEL light emitting point 11 is turned on, laser light generated by the active region 114 is reflected multiple times in a resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116 and then exits the P-DBR layer 116, or exits the N-PDBR layer.

The positive electrode 60 and the negative electrode 70 are used to turn on the VCSEL emission point 11. When the N-DBR layer 113 and the P-DBR layer 116 are configured such that laser light generated by the active region 114 is emitted from the P-DBR layer 116 after being reflected multiple times within a resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116 after the VCSEL light emitting point 11 is turned on, the positive electrode 60 has a ring shape, and the positive electrode 60 has a light emitting hole 102 corresponding to the limiting hole 101.

During operation, an operating voltage/current is applied to the positive electrode 60 and the negative electrode 70 of the VCSEL light emitting point 11 to generate a current in the VCSEL light reflecting unit. After being turned on, the current is limited in flow direction by the limiting layer 115, which is finally introduced into the middle region of the VCSEL emission point 11, so that the middle region of the active region 114 generates laser light, and the plurality of VCSEL emission points 11 generate a large amount of heat during the lasing and lasing process. More specifically, in the embodiment of the present application, the confinement layer 115 has a confinement region formed around the confinement holes 101, the confinement region having a higher resistivity to confine carriers flowing into the middle region of the VCSEL emission point 11, and a lower refractive index of the confinement region to laterally confine photons, the carriers and optical lateral confinement increasing the density of carriers and photons within the active region 114, increasing the efficiency of light generation within the active region 114, and the confinement holes 101 defining the exit aperture of the VCSEL emission point 11.

In some embodiments of the present application, the confinement layer 115 is implemented as an oxidation confinement layer formed over the active region 114 by an oxidation process. In the embodiment of the present application, the oxidation limiting layer may be formed as a separate layer above the active region 114, or may be formed above the active region 114 by oxidizing at least a portion of the lower region of the P-DBR layer 116, which is not limited to the present application. In other embodiments of the present application, the confinement layer 115 is implemented in other forms, for example, as an ion confinement layer (not shown) formed over the active region 114 by an ion implantation process, which is not limited to the present application.

In the embodiment of the present application, an isolation structure 103 is disposed between every two VCSEL emission points 11 in the plurality of VCSEL emission points 11, and the isolation structure 103 extends downward from the upper surface of the VCSEL emission point 11 to below the active region 114, so as to achieve electrical isolation between the plurality of VCSEL emission points 11. In a specific example of the present application, the isolation structure 103 is implemented as an isolation trench recessed from the upper surface of the VCSEL emission point 11 down to below the active region 114. In another specific example of the present application, the isolation structure 103 is implemented as an ion implantation layer extending from the upper surface of the VCSEL emission point 11 down to below the active region 114.

In the embodiment of the present application, the plurality of VCSEL emission points 11 of the emission region 10 are distributed in the emission region 10 in an equidistant manner. In a variant embodiment of the application, the plurality of VCSEL emission points 11 may be distributed in other ways in the emission region 10, which is not limiting to the application.

As described above, in the embodiment of the present application, the heat dissipation advantage of the first portion of the light emitting points 110 is relatively poor, the working temperature is relatively high, and the light emitting intensity is relatively low, and the heat dissipation advantage of the second portion of the light emitting points 120 is relatively good, the working temperature is relatively low, and the light emitting intensity is relatively high. In this way, the plurality of VCSEL units of the light emitting region 10 is prone to the problem of uneven light emission intensity. In the embodiment of the present application, the heat sink structure 20 only corresponds to the first part of the light emitting points 110 of the light emitting area 10, so that the heat dissipation performance of the first part of the light emitting points 110 with poor self heat dissipation advantage of the VCSEL chip is improved under the heat dissipation effect of the heat sink structure 20, and in this way, the light emitting uniformity of the plurality of VCSEL light emitting points 11 is improved.

It should be noted that, in the embodiment of the present application, the heat sink structure 20 (heat dissipation structure) is configured for the first portion of the light emitting points 110 of the light emitting area 10, so that the light emitting uniformity of the whole VCSEL chip is improved, and the light emitting intensity of the whole VCSEL chip can be improved.

In the embodiment of the present application, the form of the heat sink structure 20 is not limited by the present application, for example, the heat sink structure 20 may be implemented as a non-continuously distributed heat sink points 21 in a dot shape, and may be implemented as a heat sink strip 22 having a continuous distribution characteristic. Accordingly, in some embodiments of the present application, the heat sink structure 20 includes at least one heat sink point 21 (as shown in fig. 4 and 7) corresponding to the first partial light emitting point 110. In other embodiments of the present application, the heat sink structure 20 includes at least one heat sink strip 22 (shown in fig. 8-13) corresponding to the first portion of the light emitting points 110. In still other embodiments of the present application, the heat sink structure 20 includes at least one heat sink point 21 and at least one heat sink strip 22 (as shown in fig. 5 and 6) corresponding to the first partial light emitting point 110.

In the embodiment of the present application, the shape of the cross section of the heat sink 21 is not limited to the present application, for example, in some embodiments of the present application, the shape of the cross section of the heat sink 21 is circular (as shown in fig. 4), and in other embodiments of the present application, the shape of the cross section of the heat sink 21 is quadrilateral (as shown in fig. 7).

In some embodiments of the application, the heat sink structure 20 comprises only one heat sink point 21 corresponding to the first partial light emitting point 110. The one heat sink point 21 may correspond to only a part of the first partial light emitting points 110 among the first partial light emitting points 110, or may correspond to all of the first partial light emitting points 110. Accordingly, the cross-sectional area of the one heat sink point 21 is not limited by the present application, and the cross-sectional area of the one heat sink point 21 may be approximately equal to the total cross-sectional area of all the first partial light emitting points 110 in the first partial light emitting points 110, or may be approximately equal to the total cross-sectional area of a part of the first partial light emitting points 110 in the first partial light emitting points 110, which is smaller than the total cross-sectional area of all the first partial light emitting points 110 in the first partial light emitting points 110.

As described above, when the plurality of VCSEL emission points 11 are turned on and in an operating state, the heat radiation advantage of the plurality of VCSEL emission points 11 themselves from the center of the emission region 10 to the outer periphery thereof is gradually increased, and the emission intensity is gradually increased. The inner region portion of the light emitting region 10 may be subdivided into a plurality of portions having different heat radiation advantages according to a difference in heat radiation of the VCSEL light emitting point 11 formed from a distance from an outer circumference thereof and a distance from the outer circumference thereof, and the plurality of first partial light emitting points may be subdivided into a plurality of partial light emitting points. The heat sink structure 20 may be patterned according to this feature to form different heat dissipation configurations at the VCSEL emission points of different regions of the inner region portion, as shown in fig. 16, to improve the emission uniformity of the plurality of first partial emission points.

A control experiment was performed on the light emitting region 10 (i.e., experimental group) of the VCSEL chip in which the heat sink structure 20 of a specific pattern was disposed in the inner region portion and the light emitting region (i.e., control group) of the VCSEL chip in which the heat sink structure 20 was not disposed, as shown in fig. 17 and 18, it was found that both exhibited a gradual decrease in junction temperature of the VCSEL light emitting point 11 with an increase in distance (center distance) from the center region of the light emitting region 10.

Further, the junction temperature of the VCSEL emission point 11 of the experimental group configured with the specific pattern of heat sink structure 20 is lower than that of the VCSEL emission point 11 of the control group, indicating that: the specific style of heat sink structure 20 improves the final heat dissipation performance of its corresponding VCSEL emission point 11.

Further, the smaller the distance (center distance) from the center region of the light emitting region 10, the larger the difference between the junction temperature of the VCSEL light emitting point 11 of the experimental group and the junction temperature of the VCSEL light emitting point 11 of the control group, indicating that: the smaller the distance from the central area of the light emitting area 10, the stronger the heat dissipation of the specific type heat sink structure 20 to the VCSEL light emitting point 11, the greater the improvement degree, so that the junction temperature difference of the VCSEL light emitting points 11 between different areas of the experimental group is reduced, which is beneficial to improving the light emitting uniformity of the plurality of VCSEL light emitting points 11, and the heat sink structure 20 improves the light emitting uniformity of the VCSEL chip by 3% to 7% in terms of quantification.

The heat sink structure 20 can improve the light emitting uniformity of the whole VCSEL chip and simultaneously improve the light emitting intensity of the whole VCSEL chip, and in quantization, the heat sink structure 20 improves the actual light emitting power of the VCSEL chip by about 0.4%.

Taking the above-mentioned light emitting region 10 formed by a VCSEL array of 10×10 as an example, a layer of VCSEL light emitting points 11 closest to the edge region in the inner region portion forms a first annular inner annular region, and the width is one tenth of the width of the entire light emitting region 10, and the total area accounts for 28% of the entire light emitting region 10. A layer of VCSEL light emitting points 11 adjacent to the first inner ring region forms a second inner ring region in the shape of a ring, having a width of one tenth of the width of the entire light emitting region 10, and a total area of 20% of the entire light emitting region 10. A layer of VCSEL light emitting points 11 adjacent to the second inner ring region forms a third inner ring region in the shape of a ring, having a width of one tenth of the width of the entire light emitting region 10, and a total area accounting for 12% of the entire light emitting region 10. The VCSEL emission point 11 formed in the third inner ring region forms a central region of the emission region 10, and the total area is 4% of the entire emission region 10.

The heat dissipation advantage of the VCSEL light emitting point 11 itself gradually decreases from the edge region portion of the light emitting region 10 to the third inner ring region, the second inner ring region, the first inner ring region, and the central region in order. Preferably, the heat dissipation of the heat sink structure 20 to the VCSEL emission points 11 is gradually increased to improve the emission uniformity of the plurality of VCSEL emission points 11. Specifically, it may be represented that the arrangement density of the heat sink structure 20 is gradually increased, and/or the width is gradually increased, and/or the depth is gradually increased, and/or the thermal conductivity is gradually increased from the edge region portion of the light emitting region 10 to the third inner ring region, the second inner ring region, the first inner ring region, and the central region.

Accordingly, in other embodiments of the present application, the heat sink structure 20 includes a plurality of heat sink points 21 spaced from the center of the light emitting area to the outer periphery thereof, and the structure and distribution of the plurality of heat sink points 21 may be designed according to the above-mentioned characteristics of the light emitting area 10. Specifically, the heat sink points 21 may be designed starting from the arrangement density, width dimension, depth dimension, and thermal conductivity. When the cross-section of the heat sink 21 is circular or elliptical, the width dimensions of the heat sink 22 and the heat sink 21 refer to the equivalent circular diameters of the heat sink 22 and the heat sink 21, respectively, and the equivalent circular diameter of one cross-section refers to the diameter of a circular cross-section having the same area as the cross-section.

In some embodiments of the present application, the arrangement density of the plurality of heat sink points 21 is greater in a central region adjacent to and/or the light emitting region 10 than the arrangement density of the plurality of heat sink points 21 in a central region remote from the light emitting region 10, as shown in fig. 4. The plurality of heat sink points 21 have the same size configuration, and the heat conduction coefficient of the heat sink points 21 in the center region adjacent to and/or the light emitting region 10 among the plurality of heat sink points 21 is greater than or equal to the heat conduction coefficient of the heat sink points 21 in the center region away from the light emitting region 10 among the plurality of heat sink points 21.

In some embodiments of the present application, the arrangement density of the plurality of heat sink points 21 is greater in a central region adjacent to and/or the light emitting region 10 than in a central region remote from the light emitting region 10. The plurality of heat sink points 21 have the same size configuration, and the heat conduction coefficient of the heat sink points 21 in the center region adjacent to and/or the light emitting region 10 among the plurality of heat sink points 21 is greater than or equal to the heat conduction coefficient of the heat sink points 21 in the center region away from the light emitting region 10 among the plurality of heat sink points 21.

In some embodiments of the present application, the arrangement density of the plurality of heat sink points 21 is greater in a central region adjacent to and/or the light emitting region 10 than in a central region remote from the light emitting region 10. The width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is equal to or greater than the width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10, and the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is equal to or greater than the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10. The heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are adjacent to and/or in the central region of the light emitting region 10 is greater in size than or equal to the heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are distant from the central region of the light emitting region 10.

In some embodiments of the present application, the arrangement density of the plurality of heat sink points 21 adjacent to and/or in the central region of the light emitting region 10 is consistent with the arrangement density of the plurality of heat sink points 21 away from the central region of the light emitting region 10, the plurality of heat sink points 21 and the plurality of heat sink points 21 having different dimensional configurations. The width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is larger than the width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10, and the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is larger than or equal to the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10. The heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are adjacent to and/or in the central region of the light emitting region 10 is greater in size than or equal to the heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are distant from the central region of the light emitting region 10.

In some embodiments of the present application, the arrangement density of the plurality of heat sink points 21 adjacent to and/or in the central region of the light emitting region 10 is consistent with the arrangement density of the plurality of heat sink points 21 away from the central region of the light emitting region 10, the plurality of heat sink points 21 and the plurality of heat sink points 21 having different dimensional configurations. The width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is greater than or equal to the width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10, and the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is greater than the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10. The heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are adjacent to and/or in the central region of the light emitting region 10 is greater in size than or equal to the heat transfer coefficient of the heat sink points 21 of the plurality of heat sink points 21 that are distant from the central region of the light emitting region 10.

In some embodiments of the application, the heat sink points 21 of the plurality of heat sink points 21 that are adjacent to and/or in the central region of the light emitting region 10 have a greater thermal conductivity size than the heat sink points 21 of the plurality of heat sink points 21 that are remote from the central region of the light emitting region 10. The arrangement density of the plurality of heat sink points 21 in the central region adjacent to and/or the light emitting region 10 is consistent with the arrangement density of the plurality of heat sink points 21 in the central region away from the light emitting region 10, or the arrangement density of the plurality of heat sink points 21 in the central region adjacent to and/or the light emitting region 10 is greater than the arrangement density of the plurality of heat sink points 21 in the central region away from the light emitting region 10. The width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is equal to or greater than the width dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10, and the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10 is equal to or greater than the depth dimension of the heat sink points 21 of the plurality of heat sink points 21 in the vicinity of and/or the central region of the light emitting region 10.

In the embodiment of the present application, the heat sink points 21 may be in a dot square ring shape (as shown in fig. 5 and 7), or a dot circular ring shape (as shown in fig. 4) may be disposed in the light emitting area 10, or may be in a dot line shape (as shown in fig. 6) from inside to outside, which is not limited by the present application.

In a specific example of the present application, at least some of the plurality of heat sink points 21 are annularly distributed to form at least one point annular heat sink strip. The at least one dot-loop heat sink strip includes a plurality of dot-loop heat sink strips, the distances between the plurality of dot-loop heat sink strips gradually increasing from the central region of the light emitting region 10 toward the outer periphery thereof.

As previously mentioned, the heat sink structure 20 may also be implemented as a band-shaped heat sink band 22 having a continuous distribution characteristic. Accordingly, in some implementations of the application, the heat sink structure 20 includes at least one heat sink strip 22 corresponding to the first partial light emitting point 110.

In the embodiment of the present application, the shape of the cross section of the heat sink strip 22 is not limited to the present application, for example, in some embodiments of the present application, the shape of the cross section of the heat sink strip 22 is circular (as shown in fig. 11), and in other embodiments of the present application, the shape of the cross section of the heat sink strip 22 is square (as shown in fig. 9). In still other embodiments of the present application, the heat sink strip 22 is strip-shaped in cross-section (as shown in fig. 12 and 13).

In some embodiments of the present application, the heat sink structure 20 includes only one heat sink strip 22 corresponding to the first partial light emitting point 110, as shown in fig. 8. The one heat sink strip 22 may correspond to only a part of the first partial light-emitting points 110, or may correspond to all of the first partial light-emitting points 110. Accordingly, the cross-sectional area of the one heat sink strip 22 is not limited by the present application, and the cross-sectional area of the one heat sink strip 22 may be approximately equal to the total cross-sectional area of all the first partial light emitting points 110 in the first partial light emitting points 110, or may be approximately equal to the total cross-sectional area of a part of the first partial light emitting points 110 in the first partial light emitting points 110, which is smaller than the total cross-sectional area of all the first partial light emitting points 110 in the first partial light emitting points 110.

In some embodiments of the present application, the heat sink structure 20 includes at least two heat sink strips 22 spaced from the center of the light emitting area 10 toward the outer periphery thereof. The structure and distribution of the at least two heat sink strips 22 may be designed according to the heat dissipation characteristics of the light emitting area 10. Specifically, the design may be initiated from the distance, width dimension, depth dimension, thermal conductivity between the heat sink strip 22 and the adjacent heat sink strip.

In some embodiments of the present application, the distance between each two adjacent heat sink strips 22 of the at least two heat sink strips 22 gradually increases from the central region of the light emitting region 10 toward the outer periphery thereof, as shown in fig. 9, 12 and 13. Each of the at least two heat sink strips 22 has the same dimensional configuration, and the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or at the central region of the light emitting region 10 has a heat conduction coefficient greater than or equal to the heat conduction coefficient of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region.

In some embodiments of the present application, the distance between each two adjacent heat sink strips 22 of the at least two heat sink strips 22 gradually increases from the central region of the light emitting region 10 toward the outer periphery thereof, and the width dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located at the central region of the light emitting region 10 is greater than or equal to the width dimension of the heat sink strip 22 of the at least two heat sink strips 22 distant from the central region of the light emitting region 10, as shown in fig. 3. The depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located in the central region of the light emitting region 10 is greater than or equal to the depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region 10, as shown in fig. 3. The heat sink strips 22 of the at least two heat sink strips 22 that are adjacent to and/or located in the central region of the light-emitting region 10 have a thermal conductivity that is greater than or equal to the thermal conductivity of the heat sink strips 22 of the at least two heat sink strips 22 that are remote from the central region of the light-emitting region.

In some embodiments of the present application, the distances between each two adjacent heat sink strips 22 of the at least two heat sink strips 22 are equal, the at least two heat sink strips 22 having different dimensional configurations. Specifically, a width dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located at a central region of the light emitting region 10 is greater than a width dimension of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region 10. The depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located in the central region of the light emitting region 10 is greater than or equal to the depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region 10. The heat sink strips 22 of the at least two heat sink strips 22 that are adjacent to and/or located in the central region of the light-emitting region 10 have a thermal conductivity that is greater than or equal to the thermal conductivity of the heat sink strips 22 of the at least two heat sink strips 22 that are remote from the central region of the light-emitting region.

In some embodiments of the present application, the distances between each two adjacent heat sink strips 22 of the at least two heat sink strips 22 are equal, the at least two heat sink strips 22 having different dimensional configurations. Specifically, the width dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located in the central region of the light emitting region 10 is greater than or equal to the width dimension of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region 10. The depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 adjacent to and/or located in the central region of the light emitting region 10 is greater than the depth dimension of the heat sink strip 22 of the at least two heat sink strips 22 remote from the central region of the light emitting region 10. The heat sink strips 22 of the at least two heat sink strips 22 that are adjacent to and/or located in the central region of the light-emitting region 10 have a thermal conductivity that is greater than or equal to the thermal conductivity of the heat sink strips 22 of the at least two heat sink strips 22 that are remote from the central region of the light-emitting region.

In the embodiment of the present application, the heat sink strip 22 may be square ring-shaped (as shown in fig. 9 and 10), or circular ring-shaped (as shown in fig. 11) may be disposed in the light emitting area 10, or may linearly extend from inside to outside (as shown in fig. 12 and 13), which is not limited by the present application. In one specific example of the application, the heat sink strip 22 extends radially outward from the inside (as shown in fig. 12).

In some embodiments of the present application, a part of the heat sink strips 22 is disposed in the light emitting region 10 in a square ring shape or a circular ring shape, and the other part of the heat sink strips 22 linearly extends from inside to outside to guide heat to be conducted outwards, as shown in fig. 10 and 11. The type and arrangement of the heat sink strips 22 may be selected to form a particular thermal conduction path, as appropriate, to direct heat away according to the desired thermal conduction path.

In some embodiments of the present application, the heat sink structure 20 is formed with both heat sink strips 22 and heat sink points 21. Accordingly, in some embodiments of the present application, the heat sink structure 20 includes a plurality of heat sink points 21 corresponding to the plurality of VCSEL emission points 11 in the first partial emission point 110 and at least one heat sink strip 22 extending outwardly from at least one heat sink point 21 of the plurality of heat sink points 21, the outwardly extending at least one heat sink strip 22 being capable of guiding heat outwardly. The arrangement of the heat sink points 21 and the heat sink strips 22 may be selected according to the actual situation to form a specific heat conduction path, and the heat is guided to be conducted out according to the expected heat conduction path.

It should be noted that, in the embodiment of the present application, the heat sink structure 20 is formed on the substrate layer 111 of at least some of the VCSEL emission points 11 in the plurality of VCSEL emission points 11. In some embodiments of the present application, the bottom surface of the heat sink structure 20 is flush with the bottom surface of the VCSEL light emitting point 11, as shown in fig. 1-3; in other embodiments of the present application, the bottom surface of the heat sink structure 20 protrudes from the bottom surface of the substrate layer 111; in still other embodiments of the present application, the bottom surface of the heat sink structure 20 is recessed inwardly relative to the bottom surface of the substrate layer 111, which is not limiting of the present application.

In the embodiment of the present application, the heat sink structure 20 is made of a material with good heat conduction performance (e.g., gold, silver, copper), which is favorable for heat dissipation of the VCSEL light emitting point 11, and can play a supporting role to a certain extent, so as to meet the requirements of the VCSEL chip on structural strength and structural stability.

In some embodiments of the present application, the heat sink structure 20 is made of an electrically and thermally conductive material, which not only accelerates heat dissipation, but also serves as the negative electrode 70 of the VCSEL emission point 11.

In summary, the VCSEL chip according to the embodiment of the present application has been elucidated, which can improve the heat dissipation performance of the portion of the light emitting region 10 by adding the heat dissipation structure only to the portion of the light emitting region 10 where heat is easily accumulated, so as to improve the light emission uniformity of the VCSEL chip.

Method for preparing schematic VCSEL chip

According to another aspect of the present application, there is also provided a method of manufacturing a VCSEL chip for manufacturing a VCSEL chip as described above. Referring to the drawings, a method of fabricating a VCSEL chip according to an embodiment of the present application is illustrated. It should be noted that, in the embodiment of the present application, the conventional VCSEL chip fabrication process is used in the VCSEL chip fabrication process, and the heat sink structure 30 is formed in the conventional VCSEL chip fabrication process, so that the VCSEL chip fabrication in the embodiment of the present application can be implemented. Therefore, the original VCSEL chip production line and production equipment can be reserved for preparing the VCSEL chip, the production line transformation cost of the VCSEL chip is effectively reduced, and the preparation cost is further reduced.

As shown in fig. 13, in some embodiments of the present application, the method for preparing the VCSEL chip includes: s110, forming an epitaxial layer structure, wherein the epitaxial layer structure comprises the following components from bottom to top: a substrate layer structure, an N-type electrical contact layer structure, an N-DBR layer structure, an active layer structure, a P-DBR layer structure, and a P-type electrical contact layer structure; s120, forming a plurality of positive electrodes electrically connected to the P-type electric contact layer structure; s130, removing at least one part of the epitaxial layer structure to form a plurality of sub-structure units, wherein each sub-structure unit comprises from bottom to top: a substrate layer, an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer; s140, processing the plurality of sub-structural units to form a confinement layer having a confinement hole above the active region, thereby forming a plurality of light emitting bodies, wherein the plurality of light emitting bodies includes a second portion light emitting body adjacent to an outer periphery of a light emitting region forming region formed by the plurality of light emitting bodies and a first portion light emitting body other than the second portion light emitting body; s150, removing at least one part of the substrate layer to form at least one groove corresponding to the first part of the luminous body only; and S160, filling heat conduction materials into the at least one groove to form a heat sink structure.

In step S110, an epitaxial layer structure 100 is formed. Specifically, the substrate layer structure 110 is formed through a semiconductor growth process, and then, the N-type electric contact layer structure 120, the N-DBR layer structure 130, the active layer structure 140, and the P-DBR layer structure 150, which are stacked on the substrate layer structure 110, are sequentially formed.

In step S120, a plurality of positive electrodes 60 electrically connected to the P-type electrical contact layer structure 360 are formed. Specifically, the plurality of positive electrodes 60 are formed through an electroplating process, and the plurality of positive electrodes 60 may be formed through other processes, which is not a limitation of the present application.

In one specific example of the present application, the VCSEL chip is designed to laser light exiting the P-DBR layer 116 formed from at least a portion of the P-DBR layer structure 150 during subsequent fabrication. In this specific example, a plurality of positive electrodes 60 are formed at preset positions of the P-type electrical contact layer structure 360, and the positive electrodes 60 are annular in shape to define a plurality of light emitting holes 102.

In step S130, at least a portion of the epitaxial-layer structure 100 is removed to form a plurality of sub-structure units 200 spaced apart from each other. Specifically, at least a portion of the epitaxial layer structure 100 is removed by an etching process to form at least one isolation trench, thereby forming a plurality of sub-structure units 200. Each of the sub-structural units 200 includes, from bottom to top: a substrate layer 111, an N-type electrical contact layer 112, an N-DBR layer 113, an active region 114, a P-DBR layer 116, and a P-type electrical contact layer 117.

The specific depth of the isolation trench is not limited by the present application in this embodiment, and in one specific example of the present application, the isolation trench extends downward from the P-DBR layer structure 150 to below the first active layer structure 140. In one specific example of the present application, the isolation trench extends downward from the P-DBR layer structure 150 to the first N-DBR layer structure 130. In another specific example of the present application, the isolation trench extends from the P-DBR layer structure 150 down to the N-type electrical contact layer structure 120.

In step S140, the plurality of sub-structure units 200 are processed to form a confinement layer 115 having a confinement hole 101 above the active region 114. Specifically, the confinement layer 115 may be formed by an oxidation process. First, in order to protect the positive electrode 60, a protective layer covering the positive electrode 60 is formed before oxidizing the plurality of sub-structural units 200; next, the plurality of sub-structure units 200 are oxidized, and after the sub-structure units 200 are oxidized, a portion of the P-DBR layer 116 is oxidized to form an oxidation limiting layer 115 having limiting holes 101 above the active region 114, the limiting holes 101 corresponding to the light emitting holes 102; then, the positive electrode 60 is exposed, and the positive electrode 60 may be exposed by removing at least a portion of the protective layer coated on the positive electrode 60. That is, step S140 includes: forming a protective layer covering the positive electrode 60; oxidizing the plurality of sub-structure units 200 to form an oxidation limiting layer 115 having limiting holes 101 over the active region 114; and exposing the plurality of positive electrodes 60.

It should be noted that the confinement layer 115 may be formed by other processes, for example, the ion confinement layer 115 above the active region 114 may be formed by an ion implantation process, which is not limited by the present application.

The plurality of sub-structural units 200 forming the confinement layer 115 form a plurality of light emitting bodies, each of which includes from bottom to top: a substrate layer 111, an N-type electrical contact layer 112, an N-DBR layer 113, an active region 114, a confinement layer 115 having a confinement aperture 101 corresponding to the active region 114, a P-DBR layer 116, and a P-type electrical contact layer 117. The plurality of light emitting bodies includes a second partial light emitting body adjacent to an outer periphery of a light emitting region forming region formed by the plurality of light emitting bodies and a first partial light emitting body other than the second partial light emitting body. In the subsequent manufacturing process, the first partial light emitting body, the positive electrode and the negative electrode corresponding thereto will form the first partial light emitting point 110, and the second partial light emitting body, the positive electrode and the negative electrode corresponding thereto will form the second partial light emitting point 120.

When the light-emitting bodies are conducted, compared with the second part light-emitting bodies, the heat in the area where the first part light-emitting bodies are located is easy to accumulate, the working temperature is high, and the light-emitting intensity is low. In the embodiment of the application, a heat dissipation structure (heat sink structure) is added for the first part of luminous points only, so that the luminous intensity of the subsequently formed first part of luminous points is improved, and the luminous uniformity of the whole VCSEL chip is improved. Specifically, at least one groove corresponding to only the first portion of the light emitting body is first formed in the substrate layer 111, and then a heat conductive material is filled in the at least one groove to form the heat sink structure.

In step S150, at least a portion of the substrate layer 111 is removed to form at least one recess 300 corresponding to only the first portion of the light emitting body. Specifically, at least a portion of the substrate layer 111 may be removed by an etching process to form at least one recess 300. In some embodiments of the present application, the substrate layer 111 is first thinned, and then at least a portion of the thinned substrate layer 111 of the first portion of the light emitting body is removed by an etching process to form the at least one recess 300.

In the embodiment of the present application, the specific shape of the groove 300 is not limited by the present application. In some embodiments of the present application, all of the at least one groove 300 has a strip shape. In other embodiments of the present application, all of the grooves 300 of the at least one groove 300 are punctiform. In still other embodiments of the present application, a portion of the at least one groove 300 is dotted, and a portion of the at least one groove 300 is band-shaped. In some embodiments of the application, the cross-section of the recess 300 is quadrilateral in shape. In other embodiments of the present application, the cross-section of the recess 300 is circular in shape. In still other embodiments of the present application, the recess 300 is elliptical in shape.

The substrate layer 111 has a first region 1110 corresponding to the first portion of the light emitting body and a second region 1120 corresponding to the second portion of the light emitting body, the second region 1120 being adjacent to an outer periphery of the substrate layer 111, the first region 1110 being formed within the second region 1120. The at least one recess 300 is formed in the first region 1110.

In some embodiments of the present application, the at least one groove 300 includes only one groove 300, and in other embodiments of the present application, the at least one groove 300 includes at least two grooves 300 spaced apart from each other.

In some embodiments of the present application, the distance between every two adjacent grooves 300 of the at least two grooves 300 gradually increases from the central region of the light emitting region toward the outer periphery thereof. In other embodiments of the present application, the distance between every two adjacent grooves 300 in the at least two grooves 300 is equal.

In some embodiments of the present application, each of the at least two grooves 300 has the same size configuration. In other embodiments of the present application, a width dimension of the groove 300 adjacent to and/or located in the central region of the first region 1110 of the at least two grooves 300 is greater than or equal to a width dimension of the groove 300 distant from the central region of the first region 1110 of the at least two grooves 300, and/or a depth dimension of the groove 300 adjacent to and/or located in the central region of the first region 1110 of the at least two grooves 300 is greater than or equal to a depth dimension of the groove 300 distant from the central region of the first region 1110 of the at least two grooves 300.

In step S160, the at least one groove 300 is filled with a heat conductive material to form the heat sink structure 20. Specifically, the heat conducting material may just fill the at least one groove 300, so that the bottom surface of the heat sink structure 20 is flush with the bottom surface of the substrate layer 111, and the heat conducting material may overflow the at least one groove 300, so that the bottom surface of the heat sink structure 20 protrudes from the bottom surface of the substrate layer 111, and the bottom surfaces of the heat sink structures 20 are in the same plane.

It should be noted that in the embodiment of the present application, the heat sink structure 20 is made of an electrically conductive and heat conductive material, which can be used for heat conduction, and can be used as the negative electrode 70 electrically connected to the light emitting body. The plurality of light emitting bodies, the plurality of positive electrodes 60, and the heat sink structure 20 form a plurality of VCSEL light emitting points 11, each light emitting point comprising a light emitting body and a positive electrode 60 and a negative electrode 70 electrically connected to the light emitting body. The plurality of VCSEL emission points 11 includes a second partial emission point 120 adjacent to the outer circumference of the emission region 10 and a first partial emission point 110 excluding the second partial emission point 120.

When the plurality of VCSEL emission points 11 are turned on, heat in the area where the first portion emission point 110 is located is easily accumulated, the temperature is higher, the emission intensity is relatively lower, and compared with the area where the second portion emission point 120 is located, the heat dissipation performance is better, the temperature is lower, the emission intensity is relatively higher, and the plurality of VCSEL emission points 11 are prone to have the problem of uneven emission intensity.

In this embodiment of the present application, the heat sink structure 20 has a specific structural style so that the heat dissipation performance of the first part of the light emitting points 110 is improved under the heat dissipation effect of the heat sink structure 20, and in this way, the light emitting uniformity of the plurality of VCSEL light emitting points 11 is improved. The specific structure of the heat sink structure 20 is described in detail in the description of the heat sink structure 20 of the VCSEL chip illustrated in fig. 1 to 9, and thus, repetitive description thereof will be omitted.

In summary, the method for fabricating the VCSEL chip according to the embodiment of the present application is explained, which balances the light emission intensities of the plurality of VCSEL light emission points 11 through the heat sink structure 20 formed only at the first partial light emission point 110 where heat is easily accumulated, so as to improve the light emission uniformity of the plurality of VCSEL light emission points 11.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

Claims

1. A VCSEL chip, comprising:

2. A VCSEL chip as claimed in claim 1, wherein the heat sink structure comprises a plurality of heat sink points spaced from the centre of the light emitting region towards its outer periphery.

3. A VCSEL chip as claimed in claim 2, wherein the arrangement density of the plurality of heat sink points in a central region adjacent to and/or remote from the light emitting region is greater than the arrangement density of the plurality of heat sink points in a central region remote from the light emitting region.

4. A VCSEL chip as claimed in claim 2, wherein the width dimension of a heat sink point of the plurality of heat sink points in a central region adjacent to and/or the light emitting region is greater than or equal to the width dimension of a heat sink point of the plurality of heat sink points in a central region remote from the light emitting region.

5. The VCSEL chip of claim 2, wherein a depth dimension of a heat sink point of the plurality of heat sink points in a central region adjacent to and/or the light emitting region is greater than or equal to a depth dimension of a heat sink point of the plurality of heat sink points in a central region remote from the light emitting region.

6. A VCSEL chip as claimed in claim 2, wherein the heat sink points of the plurality of heat sink points that are adjacent to and/or in the central region of the light emitting region have a thermal conductivity coefficient of greater than or equal to the thermal conductivity coefficient of the heat sink points of the plurality of heat sink points that are remote from the central region of the light emitting region.

7. The VCSEL chip of claim 2, wherein at least some of the plurality of heat sink points are annularly distributed to form at least one point-ring heat sink strip.

8. The VCSEL chip of claim 7, wherein at least some of the plurality of heat sink points are annularly distributed to form at least one point-ring heat sink strip.

9. The VCSEL chip of claim 8, wherein the at least one dot-loop heat sink strip comprises a plurality of dot-loop heat sink strips, the distance between the plurality of dot-loop heat sink strips increasing from a central region of the light emitting region to an outer periphery thereof.

10. A VCSEL chip as claimed in claim 1, wherein the heat sink structure comprises at least two heat sink strips spaced from the centre of the light emitting region towards its outer periphery.

11. A VCSEL chip as claimed in claim 10, wherein the distance between each two adjacent ones of the at least two heat sink strips increases progressively from the central region of the light emitting region to its outer periphery.

12. The VCSEL chip of claim 11, wherein each of the at least two heatsink strips has the same dimensional configuration.

13. The VCSEL chip of claim 10, wherein a width dimension of a heat sink strip of the at least two heat sink strips adjacent to and/or at a central region of the light emitting region is greater than or equal to a width dimension of a heat sink strip of the at least two heat sink strips remote from the central region of the light emitting region.

14. The VCSEL chip of claim 10, wherein a depth dimension of a heat sink strip of the at least two heat sink strips adjacent to and/or at a central region of the light emitting region is greater than or equal to a depth dimension of a heat sink strip of the at least two heat sink strips remote from the central region of the light emitting region.

15. The VCSEL chip of claim 10, wherein a thermal conductivity of a heat sink strip of the at least two heat sink strips adjacent to and/or at a central region of the light emitting region is greater than or equal to a thermal conductivity of a heat sink strip of the at least two heat sink strips remote from the central region of the light emitting region.

16. The VCSEL chip of claim 10, wherein the distance between each two adjacent ones of the at least two heat sink strips is equal, the at least two heat sink strips having different dimensional configurations.

17. The VCSEL chip of claim 16, wherein a width dimension of a heat sink strip of the at least two heat sink strips adjacent to and/or at a center region of the light emitting region is greater than a width dimension of a heat sink strip of the at least two heat sink strips remote from the center region of the light emitting region.

18. The VCSEL chip of claim 16, wherein a depth dimension of a heat sink strip in the at least two heat sink strips adjacent to and/or at a central region of the light emitting region is greater than a depth dimension of a heat sink strip in the at least two heat sink strips away from the central region of the light emitting region.

19. A method of fabricating a VCSEL chip, comprising:

20. The method of fabricating a VCSEL chip as claimed in claim 19, wherein removing at least a portion of the substrate layer to form at least one recess corresponding to only the first portion of the light emitting body comprises:

Thinning the substrate layer; and