CN116844970A - High-layer-number, high-yield and high-density fan-out packaging method and structure thereof - Google Patents

High-layer-number, high-yield and high-density fan-out packaging method and structure thereof Download PDF

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Publication number
CN116844970A
CN116844970A CN202310827331.1A CN202310827331A CN116844970A CN 116844970 A CN116844970 A CN 116844970A CN 202310827331 A CN202310827331 A CN 202310827331A CN 116844970 A CN116844970 A CN 116844970A
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Prior art keywords
layer
wiring
yield
thickness
fan
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张政楷
戴飞虎
王成迁
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CETC 58 Research Institute
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CETC 58 Research Institute
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Priority to CN202310827331.1A priority Critical patent/CN116844970A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods

Abstract

The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out packaging method with high layer number, high yield and high density and a structure thereof. Comprising the following steps: glass wafers were used as slides; coating photolytic temporary bonding glue on a wafer by a spin coating mode, curing, and then preparing a metal protection layer on the cured temporary bonding glue; back-attaching a polyimide film; completing a rewiring process on the metal protection layer; after the wiring layer and the passivation layer are finished, a plurality of chips are flipped at the corresponding Pad, and underfill is performed after the flip is finished to ensure the reliability of the package; flip chip and underfilling are carried out, and then plastic packaging is carried out by using resin materials; removing the polyimide film; removing the glass wafer by using a laser de-bonding process to carbonize the bonding adhesive; the residual temporary bonding glue is further removed using a cleaning solution. The invention has the advantages of high yield and simple process, and the prepared multilayer high-density packaging structure has high reliability and excellent integration level.

Description

High-layer-number, high-yield and high-density fan-out packaging method and structure thereof
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out packaging method with high layer number, high yield and high density and a structure thereof.
Background
With the continuous development of multi-chip integration technology, the packaging process has become an important fulcrum in the semiconductor industry, and advanced high-density Fan-Out technology plays a more important role therein. The fan-out packaging technology is mainly divided into the following three types: chip-first/face-down (chip-first/face-up), chip-first/face-up (chip-last), and chip-last (also referred to as RDL-first). The former two chip-first processes require wiring on the fan-out surface, while the RDL first process is flip-chip after wiring on the wafer or panel (carrier) is completed, which has more excellent wiring capability and higher package yield. The RDL-first process has significant advantages if the package manufacturer is to make a more sophisticated fan-out package. Since NEC Electronics Corporation (now Renesas Electronics Corporation) developed the RDL-first process, this technology has evolved rapidly and has found a great deal of application. For example SWIFT developed by Amkor corporation in 2015 and 2017 TM (silicon wafer integrated fan-out technology silicon wafer Integrated Fan-out technology) and SLIM TM (Silicon-Less Integrated Module Silicon-free integrated circuit module). However, most RDL-first packages currently only achieve 6 layers and less of wiring due to warpage, and cannot meet the wiring requirements of some high performance processors and have low yield.
Fan-out packaging is accomplished in the prior art by either a separate RDL-first process or a resin-based fan-out process. However, the warpage problem in the packaging process causes that the number of wiring layers is difficult to exceed 6 layers, the yield is low, and with the continuous increase of the current signal density, the single fan-out packaging process cannot meet the requirement of the number of wiring layers.
Disclosure of Invention
The invention aims to provide a high-layer-number, high-yield and high-density fan-out packaging method and structure.
In order to solve the technical problems, the invention provides a fan-out packaging method with high layer number, high yield and high density, which comprises the following steps:
step S1: glass wafers were used as slides;
step S2: coating photolysis temporary bonding glue on a slide glass in a spin coating mode, solidifying, and then protecting the front temporary bonding glue by using a metal protection layer;
step S3: bonding a polyimide film on the back of the slide glass;
step S4: finishing the rewiring process;
step S5: completing multi-chip flip-chip and underfilling;
step S6: plastic packaging is carried out by using resin materials;
step S7: removing the polyimide film;
step S8: using a laser de-bonding process to carbonize the bonding glue and remove the slide;
step S9: further removing the residual temporary bonding glue by using a cleaning liquid;
step S10: removing the metal protective layer by using etching liquid;
step S11: and finishing the second round of rewiring process and ball implantation on the plastic packaged wafer.
Preferably, the thickness of the glass wafer is 400-1200 μm, and the size is 8 inches or 12 inches.
Preferably, the glue coating thickness of the temporary bonding glue is 0.1-2 mu m, the curing temperature after glue coating is 300-400 ℃, the curing time is 0.5-3 h, the material of the metal protection layer is Cu, ti, au or Ag, and the thickness of the metal protection layer is 0.1-0.3 mu m.
Preferably, the thickness of the back-bonded polyimide film is 10 to 100 μm.
Preferably, the thickness of the passivation layer in the rewiring process on the glass wafer is 2-10 mu m, the thickness of the wiring layer is 1-8 mu m, and the number of the wiring layers is 3-7.
Preferably, when the re-wiring process is completed on the plastic packaged wafer, the thickness of the wiring layer is 1-8 mu m, the thickness of the passivation layer is 2-10 mu m, the diameter of the bump is 60-1000 mu m, and the number of the wiring layers is 1-6.
Preferably, ultra-high layer number wiring is realized by combining the RDL-first process and the resin-based fan-out process.
Preferably, the RDL-first process is completed by using a slide, 3-7 layers of wiring are realized, and 1-6 layers of wiring are completed by a resin-based fan-out process after the slide is removed.
The invention also provides the following technical scheme: the fan-out packaging structure with high layer number, high yield and high density is manufactured by adopting the fan-out packaging method with high layer number, high yield and high density.
Compared with the prior art, the invention has the following beneficial effects:
the invention can obviously relieve the warpage problem by combining the RDL-first technology with the resin-based fan-out technology and the back-attached polyimide film, thereby realizing ultra-high layer number wiring and meeting the current multi-chip heterogeneous integration requirement. The specific principle is as follows: when the glass wafer is used as a carrier for wiring, the warping degree increases along with the increase of the number of layers, after the glass carrier is removed by plastic packaging, the wafer is turned over to continue wiring, at the moment, the warping degree of the plastic packaging wafer is reduced and is negative compared with that before the plastic packaging wafer is turned over, the wiring is continuously completed, and along with the further increase of the number of wiring layers, the warping degree is changed from negative to positive and gradually increases. The method can realize higher wiring layer number, and the yield is higher than that of the traditional method due to smaller warpage in the process, so that the method is more suitable for fan-out packaging of the current ultra-high density and high price chip.
Drawings
FIG. 1 is a schematic representation of a glass slide in the method of the present invention.
FIG. 2 is a schematic illustration of the application of temporary bonding glue and a metal protective layer in the method of the present invention.
FIG. 3 is a schematic illustration of the method of the present invention after bonding a polyimide film to the back side of a glass slide.
Fig. 4 is a schematic diagram of the completion of wiring layers and passivation layers in the method of the present invention.
Fig. 5 is a schematic diagram of the flip-chip assembly performed by the method of the present invention.
Fig. 6 is a schematic diagram of the method of the present invention for completing the molding.
FIG. 7 is a schematic diagram of the removal of polyimide film in the process of the present invention.
FIG. 8 is a schematic representation of the removal of a glass slide in the method of the present invention.
FIG. 9 is a schematic illustration of the removal of residual temporary bonding glue in the method of the present invention.
FIG. 10 is a schematic diagram of the method of removing the metal passivation layer according to the present invention.
FIG. 11 is a schematic diagram of a second multilayer wiring and ball placement in the method of the present invention.
FIG. 12 is a graph showing the relationship between the total wiring layer number M and warpage in examples 1-2 and comparative examples 3-4 of the present invention; wherein the abscissa is M (X) to represent the total number of layers, and the ordinate is Microns to represent warpage.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
A fan-out packaging method with high layer number, high yield and high density comprises the following steps:
(1) Using glass wafer 101 as a carrier sheet, the glass wafer has a thickness of 400-1200 μm and a size of 8 inches or 12 inches, as shown in fig. 1;
(2) Coating photolysis temporary bonding glue 102 on the wafer in the step (1) in a spin coating mode, wherein the glue coating thickness is 0.1-2 mu m, curing after the glue coating is finished, the curing temperature is 300-400 ℃, the curing time is 30 min-3 h, and protecting the front temporary bonding glue by using a metal protection layer 103 to prevent water corrosion of the temporary bonding glue in a wet process, as shown in fig. 2;
(3) Bonding a polyimide film 104 on the back surface of the glass carrier sheet, in this way, the warpage problem in the subsequent multilayer wiring is alleviated, as shown in fig. 3;
(4) Completing a rewiring process on the glass wafer in the step (3), wherein the thickness of the passivation layer 105 is 2-10 mu m, the thickness of the wiring layer 106 is 1-8 mu m, and the number of wiring layers is 3-7, as shown in fig. 4;
(5) After the wiring layer and the passivation layer are completed, a plurality of chips 107 are flipped at the corresponding Pad, and underfill is performed after the flip-chip is completed to ensure package reliability, as shown in fig. 5.
(6) After the flip-chip and underfill of step (5) are completed, the resin material 108 is used for plastic packaging, as shown in fig. 6.
(7) The polyimide film 104 is removed after step (6), as shown in fig. 7.
(8) The glass wafer 101 is removed using a laser de-bonding process, carbon bond paste 102, as shown in fig. 8.
(9) The remaining temporary bonding glue 102 is further removed after step (8) using a cleaning solution, as shown in fig. 9.
(10) The metal protective layer 103 is removed using an etching liquid after step (9), as shown in fig. 10.
(11) After step (10), the re-wiring process is completed on the plastic package wafer, the thickness of the wiring layer 109 is 1-8 μm, the thickness of the passivation layer 110 is 2-10 μm, the diameter of the bump 111 is 60-1000 μm, and the number of wiring layers is 1-5, as shown in fig. 8.
Example 1:
a fan-out packaging method with high layer number, high yield and high density comprises the following specific steps:
(1) After the metal protection layer is completed, the rewiring process is completed on the glass wafer, the thickness of the passivation layer 105 is 7 μm, the thickness of the wiring layer 106 is 5 μm, the number of wiring layers is 6, and the change condition of the warping degree is shown in fig. 12.
(2) After the wiring layer and the passivation layer are completed, a plurality of chips 107 are flipped at the corresponding Pad, and underfill is performed after the flip-chip is completed to ensure package reliability, as shown in fig. 5.
(3) After the flip-chip and underfill of step (2) are completed, the resin material 108 is used for plastic packaging, as shown in fig. 6.
(4) After plastic encapsulation, the polyimide film 104 is removed, as shown in fig. 7.
(5) The glass wafer 101 is removed using a laser de-bonding process, such as the carbon bond paste, as shown in fig. 8.
(6) The remaining temporary bonding glue 102 is further removed after step (5) using a cleaning solution, as shown in fig. 9.
(7) After step (6), the metal protection layer is etched using an etching solution, as shown in fig. 9.
(8) After the step (7), the re-wiring process is completed on the plastic package wafer, the thickness of the wiring layer 109 is 5 μm, the thickness of the passivation layer 110 is 7 μm, the diameter of the bump 111 is 200 μm, the number of wiring layers is 6, and the change condition of the warpage is shown in fig. 12.
From fig. 12, it can be seen that after the glass carrier is removed, the plastic package wafer is turned over, at this time, the warpage is obviously reduced and becomes negative, so that subsequent more layers of wiring can be realized, and the final package wiring layer can reach 12 layers, which is suitable for the fan-out packaging condition of the current ultra-high density and high price chip.
Example 2:
this embodiment differs from embodiment 1 in that:
(1) After the metal protection layer is completed, the rewiring process is completed on the glass wafer, the thickness of the passivation layer 105 is 10 μm, the thickness of the wiring layer 106 is 5 μm, the number of wiring layers is 5, and the change condition of the warping degree is shown in fig. 12.
(2) After the step (7), the re-wiring process is completed on the plastic package wafer, the thickness of the wiring layer 109 is 5 μm, the thickness of the passivation layer 110 is 10 μm, the diameter of the bump 111 is 200 μm, the number of wiring layers is 5, and the change condition of the warpage is shown in fig. 12.
As can be seen from fig. 12, when the plastic package wafer is flipped over after the glass carrier is removed, the warpage is significantly reduced and becomes negative, so that the subsequent more layers of wiring can be realized, and the final package wiring layer is 10 layers, mainly because the passivation layer thickness in example 2 is greater than that in example 1, and the warpage is more serious. The results of example 2 demonstrate that this approach is applicable to different wiring layers and passivation layer thickness.
Comparative example 3:
this comparative example 1 is different from example 1 in that:
(1) The solution uses a single resin-based fan-out process, the passivation layer 105 has a thickness of 7 μm, the wiring layer 106 has a thickness of 5 μm, the number of wiring layers is 7, and subsequent wiring cannot be performed due to excessive warpage, and the warpage change condition is shown in fig. 12.
It can be seen from fig. 12 that the warpage of the single resin-based fan-out process increases more rapidly with the number of wiring layers, and a higher number of wiring processes cannot be realized.
Comparative example 4:
this comparative example 2 is different from example 1 in that:
(1) In this scheme, a single RDL-first fan-out process is used, the passivation layer 105 has a thickness of 7 μm, the wiring layer 106 has a thickness of 5 μm, the number of wiring layers is 7, and subsequent wiring cannot be performed due to excessive warpage, and the warpage change situation is shown in fig. 12.
It can be seen from fig. 12 that the warpage of the single RDL-first fan-out process increases more slowly with the number of wiring layers, but a higher number of wiring layers cannot be achieved due to the larger glass slide and narrower hardness process window.
In examples 1-2 and comparative examples 3-4, the glass wafer thickness was 1000 μm, the wafer size was 12 inches, the temporary bond paste thickness was 0.5 μm, the metal protective layer was Ti (0.3 μm) or Cu (0.3 μm), the curing temperature was 350 ℃, the curing time was 2 hours, and the back-applied polyimide film thickness was 20 μm.
In summary, in combination with the data comparison between the comparative example and the embodiment, in the high-layer, high-yield and high-density fan-out packaging method and the structure thereof, the ultra-high density multi-layer wiring is realized by combining the RDL-first technology with the resin-based fan-out technology, meanwhile, the polyimide film is pasted on the front and back of the first round of wiring, the warping problem caused by the passivation layer is relieved by the shrinkage characteristic of the polyimide film in the thermal process, the wiring layer number can reach 12 layers, the chip packaging technology far exceeding the current common use is achieved, and the metal protection layer is additionally introduced in the technological process, so that the yield is improved, and meanwhile, the method has the advantages of simple technology and low requirements on equipment.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (9)

1. The fan-out packaging method with high layer number, high yield and high density is characterized by comprising the following steps:
step S1: glass wafers were used as slides;
step S2: coating photolysis temporary bonding glue on a slide glass in a spin coating mode, solidifying, and then protecting the front temporary bonding glue by using a metal protection layer;
step S3: bonding a polyimide film on the back of the slide glass;
step S4: finishing the rewiring process;
step S5: completing multi-chip flip-chip and underfilling;
step S6: plastic packaging is carried out by using resin materials;
step S7: removing the polyimide film;
step S8: using a laser de-bonding process to carbonize the bonding glue and remove the slide;
step S9: further removing the residual temporary bonding glue by using a cleaning liquid;
step S10: removing the metal protective layer by using etching liquid;
step S11: and finishing the second round of rewiring process and ball implantation on the plastic packaged wafer.
2. The high layer, high yield, high density fan out package method of claim 1, wherein the glass wafer has a thickness of 400-1200 μm and a dimension of 8 inches or 12 inches.
3. The method of high layer number, high yield and high density fan-out package according to claim 1, wherein the glue coating thickness of the temporary bonding glue is 0.1-2 μm, the curing temperature after glue coating is 300-400 ℃, the curing time is 0.5-3 h, the metal protection layer is made of Cu, ti, au or Ag, and the thickness of the metal protection layer is 0.1-0.3 μm.
4. The high layer, high yield, high density fan out package method of claim 1, wherein said back side bonded polyimide film has a thickness of 10 to 100 μm.
5. The high-layer, high-yield and high-density fan-out packaging method according to claim 1, wherein the passivation layer thickness in the rewiring process on the glass wafer is 2-10 μm, the wiring layer thickness is 1-8 μm, and the wiring layer number is 3-7.
6. The method of claim 1, wherein the thickness of the wiring layer is 1-8 μm, the thickness of the passivation layer is 2-10 μm, the diameter of the bump is 60-1000 μm, and the number of wiring layers is 1-6 when the re-wiring process is completed on the plastic packaged wafer.
7. The high layer, high yield, high density fan out package method of claim 1 wherein ultra high layer routing is achieved by combining an RDL-first process with a resin based fan out process.
8. The high layer, high yield, high density fan out package method of claim 7 wherein said RDL-first process is accomplished using a carrier to achieve 3-7 layers of wiring and said resin based fan out process is performed after removing said carrier to achieve 1-6 layers of wiring.
9. The high-layer, high-yield and high-density fan-out packaging structure is characterized in that the high-layer, high-yield and high-density fan-out packaging structure is manufactured by adopting the high-layer, high-yield and high-density fan-out packaging method according to any one of claims 1-8.
CN202310827331.1A 2023-07-07 2023-07-07 High-layer-number, high-yield and high-density fan-out packaging method and structure thereof Pending CN116844970A (en)

Priority Applications (1)

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CN202310827331.1A CN116844970A (en) 2023-07-07 2023-07-07 High-layer-number, high-yield and high-density fan-out packaging method and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310827331.1A CN116844970A (en) 2023-07-07 2023-07-07 High-layer-number, high-yield and high-density fan-out packaging method and structure thereof

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CN116844970A true CN116844970A (en) 2023-10-03

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