CN116844948A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN116844948A CN116844948A CN202311116859.4A CN202311116859A CN116844948A CN 116844948 A CN116844948 A CN 116844948A CN 202311116859 A CN202311116859 A CN 202311116859A CN 116844948 A CN116844948 A CN 116844948A
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- 238000000034 method Methods 0.000 title claims abstract description 106
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000005530 etching Methods 0.000 claims abstract description 144
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 88
- 229920005591 polysilicon Polymers 0.000 claims abstract description 88
- 150000004767 nitrides Chemical class 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 16
- 230000000149 penetrating effect Effects 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 229
- 239000011247 coating layer Substances 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 15
- 230000009286 beneficial effect Effects 0.000 abstract description 5
- 239000006117 anti-reflective coating Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and sequentially forming a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflection coating and a patterned photoresist layer on the substrate; executing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer to form a first opening in the second oxide layer; executing a second etching process to etch the second polysilicon layer to form a second opening in the second polysilicon layer; executing a third etching process to etch the nitride layer and the first oxide layer to form a third opening penetrating through the nitride layer and the first oxide layer; and performing a fourth etching process to etch the first polysilicon layer and the substrate to form a fourth opening extending through the first polysilicon layer and into the substrate. The invention can reduce the preparation cost, save the preparation time and is more beneficial to the transfer of the graph.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
In the manufacturing process of the semiconductor device, a stacked layer is formed on a substrate, and then pattern transfer is performed in one step. The stacked layer generally comprises at least two oxide layers, at least two nitride layers, an organic material layer (or an amorphous carbon layer), an anti-reflection coating and a patterned photoresist layer, and then pattern transfer is performed step by step; because the number of layers of the stacked layers is large, the preparation cost is increased, and simultaneously, the etching step required by pattern transfer is increased, so that the preparation time is increased, the pattern transfer is difficult to control, and the electrical performance of the device is difficult to ensure.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which reduces the preparation cost, saves the preparation time, is more beneficial to pattern transfer and ensures the electrical property of the device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, and sequentially forming a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflection coating and a patterned photoresist layer on the substrate;
performing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer by taking the patterned photoresist layer as a mask to form a first opening in the second oxide layer;
performing a second etching process to etch the second polysilicon layer downwards along the first opening so as to form a second opening in the second polysilicon layer;
performing a third etching process to etch the nitride layer and the first oxide layer downwards along the second opening so as to form a third opening penetrating through the nitride layer and the first oxide layer; the method comprises the steps of,
and performing a fourth etching process to etch the first polysilicon layer and the substrate downwards along the third opening so as to form a fourth opening penetrating the first polysilicon layer and extending into the substrate, wherein the rest of the first polysilicon layer is used as a grid electrode.
Optionally, the thickness of the first polysilicon layer is 600 to 1000 angstroms, the thickness of the first oxide layer is 20 to 60 angstroms, the thickness of the nitride layer is 300 to 400 angstroms, the thickness of the second polysilicon layer is 1000 to 1200 angstroms, the thickness of the second oxide layer is 90 to 150 angstroms, and the thickness of the anti-reflection coating is 180 to 250 angstroms.
Optionally, the etching gas of the first etching process comprises CF 4 And O 2 The etching selection ratio of the second oxide layer to the anti-reflection layer is 3:1-6:1.
Optionally, the patterned photoresist layer and the anti-reflective coating layer are removed simultaneously when the first etching process is performed.
Optionally, the etching gas of the second etching process comprises CL 2 And C x F y The etching selection ratio of the second polysilicon layer to the second oxide layer is 4.5:1-8:1.
Optionally, the second oxide layer is removed simultaneously when the second etching process is performed.
Optionally, the third etching process includes a first etching process and a second etching process that are sequentially performed, where the first etching process etches the nitride layer downward along the second opening, and the second etching process etches the first oxide layer downward along the second opening.
Optionally, the etching gas of the first etching process comprises CHF 3 、CH 2 F 2 And O 2 The etching gas of the second etching process comprises CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching selection ratio of the nitride layer to the second polysilicon layer is 7:1-10:1, and the etching selection ratio of the first oxide layer to the nitride layer is 3:1-6:1.
Optionally, the etching gas of the fourth etching process comprises CL 2 And C x F y The etching selection ratio of the first polysilicon layer to the first oxide layer is 4.5:1-8:1.
Optionally, removing the second polysilicon layer simultaneously when the fourth etching process is performed; and removing the first oxide layer and the nitride layer after the fourth etching process is executed.
In the method for manufacturing the semiconductor device, a substrate is provided, and a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflection coating and a graphical photoresist layer are sequentially formed on the substrate; performing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer by taking the patterned photoresist layer as a mask to form a first opening in the second oxide layer; performing a second etching process to etch the second polysilicon layer down the first opening to form a second opening in the second polysilicon layer; executing a third etching process, and etching the nitride layer and the first oxide layer downwards along the second opening to form a third opening penetrating through the nitride layer and the first oxide layer; and performing a fourth etching process to etch the first polysilicon layer and the substrate downwards along the third opening to form a fourth opening penetrating the first polysilicon layer and extending into the substrate, and the remaining first polysilicon layer serving as a gate. The invention uses the second polysilicon layer as the mask, wherein the rest first polysilicon layer is used as the grid, the unexpected technical effect of the invention is that the number of layers of the mask is reduced, the preparation cost is reduced, and the preparation time is saved; and the second polysilicon layer is easier to improve the etching selection ratio, is more beneficial to pattern transfer, meets the design requirement of the device, and ensures the electrical property of the device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a substrate is provided.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after a first etching process is performed.
Fig. 4 is a schematic cross-sectional view of a semiconductor device after removing a second oxide layer in a second etching process according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a second etching process is performed.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a first etching process of a third etching process is performed.
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a second etching process of a third etching process is performed.
Fig. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a fourth etching process is performed.
Fig. 9 is a schematic cross-sectional view of a semiconductor device after removing a first oxide layer and a nitride layer on a first polysilicon layer according to an embodiment of the present invention.
Wherein, the reference numerals are as follows:
10-a substrate; 11-trench isolation structures; 21-a first polysilicon layer; 22-a second polysilicon layer; 31-a first oxide layer; 32-a second oxide layer; 40-nitriding layer; 50-an anti-reflective coating; 60-patterning the photoresist layer; 71-a first opening; 72-a second opening; 73-a third opening; 74-fourth opening.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", "a third" may include one or at least two such features, either explicitly or implicitly. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. Referring to fig. 1, the present invention provides a method for manufacturing a semiconductor device, including:
step S1: providing a substrate, and sequentially forming a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflection coating and a patterned photoresist layer on the substrate;
step S2: performing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer by taking the patterned photoresist layer as a mask to form a first opening in the second oxide layer;
step S3: performing a second etching process to etch the second polysilicon layer down the first opening to form a second opening in the second polysilicon layer;
step S4: executing a third etching process, and etching the nitride layer and the first oxide layer downwards along the second opening to form a third opening penetrating through the nitride layer and the first oxide layer;
step S5: and performing a fourth etching process to etch the first polysilicon layer and the substrate downwards along the third opening so as to form a fourth opening penetrating the first polysilicon layer and extending into the substrate, and taking the rest of the first polysilicon layer as a grid electrode.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a substrate is provided. Fig. 3 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a first etching process is performed. Fig. 4 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after removing the second oxide layer in the second etching process. Fig. 5 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after performing a second etching process. Fig. 6 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a first etching process of a third etching process is performed. Fig. 7 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a second etching process of a third etching process is performed. Fig. 8 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a fourth etching process is performed. Fig. 9 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after removing the first oxide layer and the nitride layer on the first polysilicon layer. The following describes the method for manufacturing the semiconductor device according to this embodiment in detail with reference to fig. 2 to 9.
Referring to fig. 2, step S1 is performed: a substrate 10 is provided, the substrate 10 comprising a semiconductor material such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon germanium substrate, a fully depleted silicon on insulator substrate, a trench isolation structure 11, an active region and a well region (not shown) are formed in the substrate 10. A first polysilicon layer 21, a first oxide layer 31, a nitride layer 40, a second polysilicon layer 22, a second oxide layer 32, an anti-reflective coating layer 50, and a patterned photoresist layer 60 are sequentially formed on the substrate 10. In this embodiment, the thickness of the first polysilicon layer 21 is preferably 600 to 1000 angstroms, for example 800 angstroms; the thickness of the first oxide layer 31 is preferably 20 to 60 angstroms, for example 37 angstroms; the thickness of the nitride layer 40 is preferably 300 to 400 angstroms, for example 350 angstroms; the thickness of the second polysilicon layer 22 is preferably 1000 to 1200 angstroms, for example 1100 angstroms; the thickness of the second oxide layer 32 is preferably 90 to 150, for example 120; the thickness of the anti-reflective coating 50 is preferably 180 to 250, for example 220; the preferred thicknesses of the first polysilicon layer 21, the first oxide layer 31, the nitride layer 40, the second polysilicon layer 22, the second oxide layer 32, the anti-reflective coating layer 50 and the patterned photoresist layer 60 are not limited to the above thickness ranges. In this embodiment, the second polysilicon layer 22 is used as a mask, so that the number of layers of the mask can be reduced, which is beneficial to reducing the preparation cost and saving the preparation time; and the etching selection ratio can be improved, the transfer of patterns is facilitated, the design requirement of a device is met, and the electrical property of the device is ensured.
With continued reference to fig. 2 and 3, step S2 is performed: performing a first etching process, and sequentially etching the anti-reflection coating 50 and the second oxide layer 32 by using the patterned photoresist layer 60 as a mask to form a first opening 71 in the second oxide layer 32, wherein the first opening 71 exposes the second polysilicon layer 22; during the first etching process, the patterned photoresist layer 60 and the anti-reflective coating layer 50 are simultaneously removed due to etching loss. In the present embodiment, the etching gas of the first etching process includes CF 4 And O 2 Second oxide layer 32 andthe etching selectivity of the anti-reflection layer 50 is preferably 3:1 to 6:1, and is not limited to the etching gas and the etching selectivity.
With continued reference to fig. 3, 4 and 5, step S3 is performed: performing a second etching process to etch the second polysilicon layer 22 downward along the first opening 71, wherein the second oxide layer 32 is simultaneously removed when the second etching process is performed to etch the second polysilicon layer 22, and a second opening 72 is formed in the second polysilicon layer 22, wherein the second opening 72 does not penetrate through the second polysilicon layer 22; the second etching process continues by etching the second polysilicon layer 22 down along the second opening 72 such that the second opening 72 extends to the surface of the nitride layer 40 to form the second opening 72 in the second polysilicon layer 22, which loses a portion of the thickness of the second polysilicon layer 22. In the present embodiment, the etching gas of the second etching process includes CL 2 And C x F y Wherein x is an integer greater than or equal to 1 and y is an integer greater than or equal to 4, e.g. C x F y May be CF 4 、C 2 F 4 The etching selectivity ratio of the second polysilicon layer 22 to the second oxide layer 32 is preferably 4.5:1 to 8:1, and is not limited to the etching gas and the etching selectivity ratio.
With continued reference to fig. 5, 6 and 7, step S4 is performed: performing a third etching process to etch the nitride layer 40 and the first oxide layer 31 downward along the second opening 72, wherein the third etching process includes a first etching process and a second etching process performed sequentially, the first etching process etching the nitride layer 40 downward along the second opening 72 to form a third opening 73 penetrating the nitride layer 40; the second etching process etches the first oxide layer 31 down the second opening 72 so that the third opening 73 extends to the surface of the first polysilicon layer 21 to form the third opening 73 penetrating the nitride layer 40 and the first oxide layer 31, and a part of the thickness of the second polysilicon layer 22 is lost in the process. In the present embodiment, the etching gas for the first etching process includes CHF 3 、CH 2 F 2 And O 2 The etching gas of the second etching process comprises CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching selectivity ratio of the nitride layer 40 to the second polysilicon layer 22 is preferably 7:1-10:1, and the first oxide layer 31 to the nitride layer 4The etching selection ratio of 0 is preferably 3:1 to 6:1, and is not limited to the etching gas and the etching selection ratio.
With continued reference to fig. 7 and 8, step S5 is performed: performing a fourth etching process to etch the first polysilicon layer 21 and the substrate 10 down the third opening 73 to form a fourth opening 74 extending through the first polysilicon layer 21 and into the substrate 10; when the fourth etching process is performed to etch the first polysilicon layer 21 and the substrate 10, the second polysilicon layer 22 is simultaneously removed, and a portion of the thickness of the nitride layer 40 is lost. In the present embodiment, the etching gas of the fourth etching process includes CL 2 And C x F y Wherein x is an integer greater than or equal to 1 and y is an integer greater than or equal to 4, e.g. C x F y May be CF 4 、C 2 F 4 The etching selectivity ratio of the first polysilicon layer 21 to the first oxide layer 31 is preferably 4.5:1 to 8:1, and is not limited to the etching gas and the etching selectivity ratio.
Referring to fig. 9, further, after the fourth etching process is performed, the first oxide layer 31 and the nitride layer 40 are removed, and the remaining first polysilicon layer 21 is used as the gate of the semiconductor device, so that the process of preparing the gate can be saved.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, a substrate is provided, and a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflective coating layer and a patterned photoresist layer are sequentially formed on the substrate; performing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer by taking the patterned photoresist layer as a mask to form a first opening in the second oxide layer; performing a second etching process to etch the second polysilicon layer down the first opening to form a second opening in the second polysilicon layer; executing a third etching process, and etching the nitride layer and the first oxide layer downwards along the second opening to form a third opening penetrating through the nitride layer and the first oxide layer; and performing a fourth etching process to etch the first polysilicon layer and the substrate downwards along the third opening to form a fourth opening penetrating the first polysilicon layer and extending into the substrate, and the remaining first polysilicon layer serving as a gate. The invention uses the second polysilicon layer as the mask, wherein the rest first polysilicon layer is used as the grid, the unexpected technical effect of the invention is that the number of layers of the mask is reduced, the preparation cost is reduced, and the preparation time is saved; and the second polysilicon layer is easier to improve the etching selection ratio, is more beneficial to pattern transfer, meets the design requirement of the device, and ensures the electrical property of the device.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and sequentially forming a first polysilicon layer, a first oxide layer, a nitride layer, a second polysilicon layer, a second oxide layer, an anti-reflection coating and a patterned photoresist layer on the substrate;
performing a first etching process, and sequentially etching the anti-reflection coating and the second oxide layer by taking the patterned photoresist layer as a mask to form a first opening in the second oxide layer;
performing a second etching process to etch the second polysilicon layer downwards along the first opening so as to form a second opening in the second polysilicon layer;
performing a third etching process to etch the nitride layer and the first oxide layer downwards along the second opening so as to form a third opening penetrating through the nitride layer and the first oxide layer; the method comprises the steps of,
and performing a fourth etching process to etch the first polysilicon layer and the substrate downwards along the third opening so as to form a fourth opening penetrating the first polysilicon layer and extending into the substrate, wherein the rest of the first polysilicon layer is used as a grid electrode.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the first polysilicon layer is 600 to 1000 angstroms, the thickness of the first oxide layer is 20 to 60 angstroms, the thickness of the nitride layer is 300 to 400 angstroms, the thickness of the second polysilicon layer is 1000 to 1200 angstroms, the thickness of the second oxide layer is 90 to 150 angstroms, and the thickness of the anti-reflection coating is 180 to 250 angstroms.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas of the first etching process includes CF 4 And O 2 The etching selection ratio of the second oxide layer to the anti-reflection coating is 3:1-6:1.
4. The method of manufacturing a semiconductor device according to claim 1 or 3, wherein the patterned photoresist layer and the anti-reflection coating layer are simultaneously removed while the first etching process is performed.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas of the second etching process includes CL 2 And C x F y The etching selection ratio of the second polysilicon layer to the second oxide layer is 4.5:1-8:1.
6. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the second oxide layer is removed simultaneously when the second etching process is performed.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the third etching process includes a first etching process and a second etching process that are sequentially performed, the first etching process etching the nitride layer downward along the second opening, the second etching process etching the first oxide layer downward along the second opening.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the etching gas of the first etching process includes CHF 3 、CH 2 F 2 And O 2 The etching gas of the second etching process comprises CF 4 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching selection ratio of the nitride layer to the second polysilicon layer is 7:1-10:1, and the etching selection ratio of the first oxide layer to the nitride layer is 3:1-6:1.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the etching gas of the fourth etching process includes CL 2 And C x F y The etching selection ratio of the first polysilicon layer to the first oxide layer is 4.5:1-8:1.
10. The method for manufacturing a semiconductor device according to claim 1 or 9, wherein the second polysilicon layer is removed simultaneously when the fourth etching process is performed; and removing the first oxide layer and the nitride layer after the fourth etching process is executed.
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