CN116844623A

CN116844623A - Control method, semiconductor memory and electronic equipment

Info

Publication number: CN116844623A
Application number: CN202210498332.1A
Authority: CN
Inventors: 严允柱; 王琳; 张志强; 龚园媛
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-03-25
Filing date: 2022-05-09
Publication date: 2023-10-03
Anticipated expiration: 2042-05-09

Abstract

The embodiment of the disclosure provides a control method, a semiconductor memory and an electronic device, which allow a first mode register and a second mode register related to a data pin to directly define the impedance of the data mask pin when the semiconductor memory is in a preset test mode, and do not need to increase the definition of an output driving state and a related control circuit for the preset test mode for the data mask pin, so that the adaptation of the preset test mode and the data mask pin is ensured, the impedance of the data mask pin can be tested in the preset test mode, and circuit processing errors are avoided.

Description

Control method, semiconductor memory and electronic equipment

Cross Reference to Related Applications

The present disclosure claims priority from chinese patent office, application number 202210307454.8, application name "a control method, semiconductor memory and electronic device," filed 25 at 2022, 03, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a control method, a semiconductor memory, and an electronic device.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and there are at least a data pin and a data mask pin. The data pin has dual functions of data writing and data reading, and the data mask pin is used for receiving an input mask signal of writing data and is used for shielding unnecessary input data during writing operation and only supports the data writing function. In release 5 memory standards (or referred to as DDR 5), some test patterns require testing of the impedance of the data mask pin or the data pin.

Disclosure of Invention

The present disclosure provides a control method, a semiconductor memory, and an electronic device, which define a control method for a data mask pin in a preset test mode, and avoid a circuit processing error.

In a first aspect, embodiments of the present disclosure provide a control method applied to a semiconductor memory including a data mask pin for receiving an input mask signal for writing data; the method comprises the following steps:

when the semiconductor memory is in a preset test mode, if the data mask pin is selected as a test object, controlling the impedance of the data mask pin to be a first impedance parameter through a first mode register; or if the data mask pin is not the test object, controlling the impedance of the data mask pin to be a second impedance parameter through a second mode register;

The semiconductor memory further comprises at least one data pin, the data pin is used for receiving or outputting data, the first mode register is used for indicating that the impedance of the at least one data pin in an output driving state is a first impedance parameter, and the second mode register is used for indicating that the impedance of the at least one data pin in a termination state is a second impedance parameter.

In a second aspect, embodiments of the present disclosure provide a semiconductor memory including a first mode register, a second mode register, a data mask pin, and a first driving circuit, the first driving circuit being connected to the first mode register, the second mode register, and the data mask pin, respectively; wherein, the liquid crystal display device comprises a liquid crystal display device,

a data mask pin configured to receive an input mask signal of write data;

the first driving circuit is configured to control the impedance of the data mask pin to be a first impedance parameter according to the first mode register if the data mask pin is selected as a test object when the semiconductor memory is in a preset test mode; or alternatively, the process may be performed,

if the data mask pin is not the test object, controlling the impedance of the data mask pin to be a second impedance parameter according to the second mode register;

In a third aspect, embodiments of the present disclosure provide an electronic device comprising a semiconductor memory as described in the second aspect.

The embodiment of the disclosure provides a control method, a semiconductor memory and an electronic device, when the semiconductor memory is in a preset test mode, a first mode register and a second mode register which are related to a data pin are allowed to directly define the impedance of the data mask pin DM, the definition of an output driving state and a related control circuit are not required to be increased for the preset test mode for the data mask pin DM, the adaptation of the preset test mode and the data mask pin is ensured, the impedance of the data mask pin can be tested in the preset test mode, and circuit processing errors are avoided.

Drawings

Fig. 1 is a schematic flow chart of a control method according to an embodiment of the disclosure;

FIG. 2 is a flow chart of another control method according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present disclosure;

fig. 4A is a schematic diagram of a partial structure of a semiconductor memory according to an embodiment of the disclosure;

fig. 4B is a schematic diagram of a partial structure of a semiconductor memory according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a first decoding module according to an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of a first driving circuit according to an embodiment of the disclosure;

fig. 7 is a detailed schematic diagram of a first driving circuit according to an embodiment of the disclosure;

fig. 8 is a detailed schematic diagram of a second driving circuit according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a second driving circuit according to an embodiment of the disclosure;

fig. 10 is a detailed schematic diagram of a second driving circuit according to an embodiment of the disclosure;

fig. 11 is a detailed schematic diagram of a second driving circuit according to an embodiment of the disclosure;

fig. 12 is a schematic diagram of a composition structure of an electronic device according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first/second/third" in relation to embodiments of the present disclosure is used merely to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if permitted, to enable embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described herein.

The following is a description of terms and relationships related to embodiments of the present disclosure:

dynamic random access memory (Dynamic Random Access Memory, DRAM)

Synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM)

Double Data Rate memory (Double Data Rate SDRAM, DDR)

DDR5 th generation standard (DDR 5 Specification, DDR5 SPEC)

Data Pin (DQ Pin, DQ)

Data Mask Pin (Data Mask Pin, DM)

Post-package output drive test mode (Package Output Driver Test Mode, PODTM)

Mode Register (Mode Register, MR)

Operation code (Opera, OP)

DDR5 SPEC defines a new test mode, called PODTM, for enabling the Output Driver of one data pin DQ or data mask pin DM after chip packaging, while the other data pin DQ or data mask pin DM is in a terminated state, by the host, to test whether the pull-up impedance of the enabled data pin DQ or data mask pin DM in the Output Driver state meets the expectations. However, since the output driving state of the data mask pin DM is not defined originally, the pod mode cannot be adapted to the data mask pin DM, which easily causes a circuit processing error.

Based on this, the embodiment of the disclosure provides a control method, when the semiconductor memory is in a preset test mode, the first mode register and the second mode register related to the data pin DQ are allowed to directly define the impedance of the data mask pin DM, and the definition of the output driving state and the related control circuit are not required to be added for the preset test mode for the data mask pin DM, so that the adaptation of the preset test mode and the data mask pin DM is ensured, the impedance of the data mask pin can be tested in the preset test mode, and the circuit processing error is avoided.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 1, a schematic flow chart of a control method provided by an embodiment of the present disclosure is shown. As shown in fig. 1, the method may include:

s101: when the semiconductor memory is in a preset test mode, if the data mask pin is selected as a test object, controlling the impedance of the data mask pin to be a first impedance parameter through a first mode register; or if the data mask pin is not the test object, controlling the impedance of the data mask pin to be a second impedance parameter through the second mode register.

It should be noted that the control method provided by the embodiment of the present disclosure is applied to a semiconductor memory. The semiconductor memory includes a data mask pin DM and at least one data pin DQ. The data pin DQ is used for receiving or outputting data, has a Write (Write) function or a Read (Read) function, and has a termination state and an output driving state; the data mask pin DM is used to receive an input mask signal of Write data, has only a Write function, and has a termination state.

In the embodiment of the present disclosure, the preset test mode refers to a pod mode introduced in DDR5 for testing the impedance of the data mask pin or the at least one data pin after packaging. More specifically, the pod mode allows the host to test the pull-up impedance of the data mask pin DM or the data pin DQ.

When the data mask pin DM is selected as a test object in the pod mode, the first mode register is allowed to control the impedance of the data mask pin DM to a first impedance parameter. Here, since the first mode register is used to indicate a Pull-up (Pull-up) impedance of the data pin DQ in an output driving state, the host is enabled to test the Pull-up impedance of the data mask pin DM in relation to the output driving without defining the output driving state of the data mask pin DM.

When the data mask pin DM is not the test object in pod, the second mode register is allowed to control the impedance of the data mask pin DM to a second impedance parameter. Here, since the second mode register is used to indicate the impedance in the finalized state, it is possible to avoid the data mask pin DM from affecting the test result of the selected test object.

In this way, when the semiconductor memory is in the preset test mode, the first mode register and the second mode register are allowed to directly define the impedance of the data mask pin DM, and the definition of the output driving state and the related control circuit are not required to be increased for the preset test mode for the data mask pin DM, so that the adaptation of the preset test mode and the data mask pin DM is ensured, the impedance of the data mask pin can be tested in the preset test mode, and the circuit processing error is avoided.

In some embodiments, the method further comprises:

when the semiconductor memory is in a preset test mode, if the data pin is selected as a test object, controlling the impedance of the data pin to be a first impedance parameter through a first mode register; or if the data pin is not the test object, controlling the impedance of the data pin to be a second impedance parameter through the second mode register.

Thus, when the data pin DQ is selected as a test object in the PODTM mode, controlling the pull-up output driving impedance of the data pin DQ through the first mode register, thereby obtaining a test result of the data pin DQ; when the data pin DQ is not used as a test object in the PODTM mode, the data pin DQ is controlled to be in a termination state through the second mode register, so that the data pin DQ is prevented from influencing the test result of the selected test object.

In some embodiments, determining, by the third mode register, that the semiconductor memory enters a preset test mode and selecting a test object; alternatively, it is determined that the semiconductor memory does not enter the preset test mode through the third mode register.

It should be appreciated that each mode register has a respective plurality of opcode bits to provide a corresponding control function. In the embodiment of the present disclosure, the operation code related to the embodiment of the present disclosure in the first mode register is referred to as a first operation code, the operation code related to the embodiment of the present disclosure in the second mode register is referred to as a second operation code, and the operation code related to the embodiment of the present disclosure in the third mode register is referred to as a third operation code.

That is, in the embodiment of the present disclosure, it is determined whether the semiconductor memory enters the pod mode by the third operation code in the third mode register, and a test object is selected from the data mask pin DM and the at least one data pin DQ in the case of entering the pod mode; then, the impedance of the selected test object is controlled to be a first impedance parameter (essentially, pull-up output driving impedance) through a first operation code in the first mode register, and the impedance of the unselected pins is controlled to be a second impedance parameter (essentially, termination impedance) through a second operation code in the second mode register, so that an impedance test result of the test object is obtained. The definition of the output driving state and the related control circuit are not required to be added for the preset test mode for the data mask pin DM, so that the adaptation of the preset test mode and the data mask pin DM is ensured, the impedance of the data mask pin can be tested in the preset test mode, and the circuit processing error is avoided.

In some embodiments, the standard number of the first mode register is 5, and the first operation code refers to the 2 nd to 1 st operation codes stored in the first mode register, denoted as MR5 OP [2:1]; the standard number of the second mode register is 34, and the second operation code refers to the 2 nd bit to 0 th bit operation codes stored in the second mode register and is expressed as MR34 OP [2:0]; the standard number of the third mode register is 61, and the third operation code refers to the 4 th bit to 0 th bit operation codes stored in the third mode register, and is denoted by MR61 OP [4:0]. Here, the standard number refers to a mode register number in DDR 5.

The third opcode MR61 OP [4:0], the first opcode MR5OP [2:1] and the second opcode MR34 OP [2:0] are described in detail below with reference to tables 1-3, respectively.

As shown in Table 1, MR61 OP [4:0] is used to determine whether to enter PODTM (Package Output Driver Test Mode) mode and to determine the pin selected. It should be understood that the number of data mask pins DM and data pins DQ is different for semiconductor memories of different bits. For a 4-bit (X4) memory, there are 1 low bit data mask pin (denoted DML) and 4 low bit data pins DQ (respectively referred to as DQL 0-DQL 3); for an 8-bit (X8) memory, there are 1 low data mask pin (denoted DML) and 8 low data pins DQ (respectively referred to as DQL 0-DQL 7); for a 16-bit (X16) memory, there are 1 low data mask pin (denoted DML), 1 high data mask pin (denoted DMU), 8 low data pins DQ (respectively referred to as DQL 0-DQL 8), and 8 high data pins DQ (respectively referred to as DQU-DQU).

If MR61 OP [4:0]]＝00000 _B Indicating that the semiconductor memory is not in the pod mode; if MR61 OP [4:0]]The value of (2) is calculated by dividing 00000 in Table 1 _B Other combinations thanIn the form, the semiconductor memory is illustrated in the pod mode. Specifically, if MR61 OP [4:0] ]＝00001 _B The test object is illustrated as the low data mask pins DML if MR61 OP [4:0]＝00010 _B The test object is illustrated as a high data mask pin DMU (valid only for 16-bit memory). If MR61 OP [4:0 ]]＝10000 _B The test object is bit data pin DQL0 at 0, and other references will be understood, and explanation will not be made.

TABLE 1

As shown in Table 2, MR5 OP [2:1] is used to determine the Pull-up output drive impedance (Pull-up Output Driver Impedance) of the data pins DQ, so the impedance of the selected pins is controlled to be the first impedance parameter by MR5 OP [2:1] in PODTM mode.

If MR5 OP [2:1]]＝00 _B Indicating that the pull-up input drive impedance should be RZQ/7, 34 ohms; if MR5 OP [2:1]]＝01 _B Indicating that the pull-up input drive impedance should be RZQ/6, i.e., 40 ohms; if MR5 OP [2:1]]＝10 _B The pull-up input drive impedance should be RZQ/5, i.e., 48 ohms, here RZQ is the standard resistance 240 ohms.

TABLE 2

As shown in Table 3, MR34 OP [2:0] is used to determine the termination impedance (RTT_PARK) of the data pins DQ or the data mask pins DM, so the impedance of the unselected pins is controlled to be the second impedance parameter by MR34 OP [2:0] in PODTM mode.

If MR5 OP [2:0]]＝001 _B Indicating that the termination impedance is RZQ, 240 ohms; if it is MR5OP[2:0]The termination impedance is described as RZQ/2, i.e. 120 ohms, for example, =010B, and others are not explained one by one with reference to understanding.

TABLE 3 Table 3

In addition, the unexplained portions of tables 1 to 3 can be understood with reference to DDR5 SPEC.

From the above, when the DRAM is in the pod mode, the Host (Host) is allowed to independently turn on the output driving circuit of a single pin in the DRAM, while controlling other pins to be in a termination state, thereby performing a characteristic test on the packaged DRAM. To turn on PODTM mode, the host sets MR61:OP [4:0 ]]To select either the data mask pin DM or the data pin DQ as the target test object, the host also sets MR5 OP [2:1 ] by setting]＝00 _B The pull-up impedance value of the output driving circuit of the control target test object is 34 ohms, while the impedance state of the rest of the data mask pins DM or the data pins DQ in the DRAM is controlled by MR34 OP [2:0 ]]Is defined as rtt_park. Note whether the data mask pin DM is enabled by MR5 OP [5 ]]And (5) defining. In addition, if the data mask pin DM is selected as the target test object in PODTM mode, the DRAM should be according to MR5 OP [ 2:1:]the impedance of the data mask pin DM is set.

To implement the above mechanism, the following exemplary provides a specific signal processing method.

As shown in fig. 2, in some embodiments, in a case where it is determined that the semiconductor memory enters the preset test mode, the method further includes:

s201: the method includes the steps of acquiring a first operation code in a first mode register, a second operation code in a second mode register and a third operation code in a third mode register.

S202: decoding the third operation code to obtain a first test mark signal; the first test flag signal indicates whether the data mask pin is a test object.

S203: one of the first operation code and the second operation code is selected to control the impedance of the data mask pin according to the first test flag signal.

In some embodiments, in the case where it is determined that the semiconductor memory enters the preset test mode, after step S201, the method further includes:

s204: decoding the third operation code to obtain at least one second test mark signal; wherein a second test flag signal indicates whether a data pin is a test object.

S205: and selecting one of the first operation code and the second operation code to control the impedance of the corresponding data pin according to the second test mark signal.

It should be understood that the execution sequence of step S202 and step S204 is not sequential, while step S203 is executed after step S202 and step S205 is executed after step S204.

It should be noted that, the first test flag signal is an internal flag signal introduced for the data mask pin DM to indicate whether the data mask pin DM is a test object in the pod mode; the second test flag signal is an internal flag signal introduced for the data pin DQ to indicate whether the data pin DQ is a test object in the pod mode. The first test flag signal and the second test flag signal are decoded according to MR61 OP [4:0], and the specific reference is given in the table 1.

In some embodiments, for the data mask pin DM, the method further comprises:

determining a first non-test state control signal and a second impedance control signal;

determining a first impedance control signal based on one of a first operation code and a second operation code according to a first test flag signal when the semiconductor memory is in a preset test mode; or determining a first impedance control signal based on the first non-test state control signal when the semiconductor memory is not in the preset test mode;

one of the first impedance control signal and the second impedance control signal is selected to control the impedance of the data mask pin according to an operating state of the semiconductor memory.

It should be noted that, although the functions of the data mask pin DM and the data pin DQ are different, for the convenience of industrial manufacturing, the data mask pin DM and the data pin DQ each employ similar signal control principles and circuit structures. Specifically, each pin may be considered to have a Read-related attribute and a Write-related attribute, and the final impedance of each pin is controlled by valid signals in both the signal corresponding to the Read-related attribute and the signal corresponding to the Write-related attribute, such that each pin supports a Read function (Read function) and a Write function (Write function) respectively under different operating scenarios (although the Read function of the DM is not enabled).

In one case, the first non-test state control signal is used to indicate the impedance of the data mask pin except for a preset test state, and the second impedance control signal is used to indicate the impedance of the data pin in an output driving state. Here, the impedance of the data mask pin except for the preset test state may include the impedance at the time of normal writing and the impedance at the time of non-reading and non-writing, which both belong to the write-related attribute.

At this time, the first non-test state control signal may be understood as a signal corresponding to the write correlation property, and the second impedance control signal may be understood as a signal corresponding to the read correlation property. Thus, in the PODTM mode, determining a first impedance control signal corresponding to the PODTM mode according to one of the first operation code or the second operation code; or in the non-PODTM mode, determining a first impedance control signal corresponding to the write-related attribute according to the first non-test state control signal; then, according to the working state of the semiconductor memory, the impedance of the data mask pin is controlled by using a first impedance control signal corresponding to the PODTM mode or the write related attribute or a second impedance control signal corresponding to the read related attribute. Specifically, the operation states of the semiconductor memory may include a write state, a read state, a non-read non-write state, and a preset test mode (pod mode). When the semiconductor memory is in a writing state, a non-reading non-writing state or a preset test mode, controlling the impedance of the data mask pin by using a first impedance control signal; (2) The impedance of the data mask pin is controlled using the second impedance control signal when the semiconductor memory is in a read state.

Thus, by incorporating the signal control strategy of the data mask pin DM in the pod mode into the signal control strategy of the write-related attribute, impedance control of the pod mode is realized.

In another case, the first non-test state control signal is used to indicate the impedance of the data pin in the output driving state, and the second impedance control signal is used to indicate the impedance of the data mask pin in other than the preset test state.

At this time, the first non-test state control signal may be understood as a signal corresponding to the read-related property, and the second impedance control signal may be understood as a signal corresponding to the write-related property. Thus, in the PODTM mode, determining a first impedance control signal corresponding to the PODTM mode according to one of the first operation code or the second operation code; or in the non-PODTM mode, determining a first impedance control signal corresponding to the read-related attribute according to the first non-test state control signal; then, according to the working state of the semiconductor memory, the impedance of the data mask pin is controlled by using a first impedance control signal corresponding to the PODTM mode or the read related attribute or a second impedance control signal corresponding to the write related attribute. Specifically, the operation states of the semiconductor memory may include a write state, a read state, a non-read non-write state, and a preset test mode (pod mode). Wherein, (1) when the semiconductor memory is in a write state or a non-read non-write state, controlling the impedance of the data mask pin with a second impedance control signal; (2) When the semiconductor memory is in a read state or a preset test mode, the impedance of the data mask pin is controlled by using the first impedance control signal.

Thus, by incorporating the signal control strategy of the data mask pin DM in the pod mode into the signal control strategy related to the read attribute, the impedance control of the pod mode is realized.

Similarly, the following exemplary specific signal control schemes for the data pins DQ are provided.

In some embodiments, for the data pins DQ, the method further comprises:

determining a third non-test state control signal, a fourth impedance control signal and a fifth impedance control signal;

determining a third impedance control signal based on one of the first operation code and the second operation code according to the second test flag signal when the semiconductor memory is in the preset test mode; or determining a third impedance control signal based on the third non-test state control signal when the semiconductor memory is not in the preset test mode;

according to the working state of the semiconductor memory, the third impedance control signal and the fifth impedance control signal are selected to control the impedance of the data pin, or the fourth impedance control signal and the fifth impedance control signal are selected to control the impedance of the data pin.

Thus, in one case, the third non-test state control signal is used to indicate the impedance of the corresponding data pin in the termination state, and the fourth impedance control signal and the fifth impedance control signal are used together to indicate the impedance of the corresponding data pin in the output driving state. Specifically, the operation states of the semiconductor memory may include a write state, a read state, a non-read non-write state, and a preset test mode (pod mode). When the semiconductor memory is in a writing state, a non-reading non-writing state or a preset test mode, controlling the impedance of the data pin by using a third impedance control signal and a fifth impedance signal; (2) The impedance of the data pin is controlled by the fourth impedance control signal and the fifth impedance control signal when the semiconductor memory is in a read state.

In this way, by incorporating the signal control strategy of the data pin in the pod mode into the signal control strategy of the write-related attribute, impedance control of the pod mode is achieved.

In another case, the third non-test state control signal and the fifth impedance control signal are used together to indicate the impedance of the corresponding data pin in the output driving state, and the fourth impedance control signal is used to indicate the impedance of the corresponding data pin in the termination state. Specifically, the operation states of the semiconductor memory may include a write state, a read state, a non-read non-write state, and a preset test mode (pod mode). When the semiconductor memory is in a writing state or a non-reading and non-writing state, controlling the impedance of the data pin by using a fourth impedance control signal and a fifth impedance signal; (2) When the semiconductor memory is in a read state or a preset test mode, the impedance of the data pin is controlled by the third impedance control signal and the fifth impedance control signal.

Thus, by incorporating the signal control strategy of the data pin in the PODTM mode into the signal control strategy related to the read attribute, impedance control of the PODTM mode is achieved.

It should be appreciated that the Write function involves controlling only the pull-up impedance (as the termination impedance), and the Read function involves controlling both the pull-up impedance and the pull-down impedance. Since the data mask pin DM enables only the Write function and not the Read function, the data mask pin DM only involves a control signal of the pull-up impedance, which is set to a fixed level signal to turn off the function of the pull-down impedance. In addition, since the data pin DQ supports both the Write function and the Read function, the data pin DQ may relate to a control signal of a pull-up impedance and a control signal of a pull-down impedance.

Therefore, for the data mask pin DM, its read-related properties relate to only one signal (either the first non-test state control signal or the second impedance control signal) for achieving control of the pull-up impedance; for the data pin DQ, the read-related property relates to two signals (third non-test state control signal+fifth impedance control signal, or fourth impedance control signal+fifth impedance control signal), which respectively implement control of the pull-up impedance and the pull-down impedance.

The embodiment of the disclosure provides a control method, which allows a first mode register and a second mode register related to a data mask pin DM to directly define the impedance of the data mask pin DM when a semiconductor memory is in a preset test mode, and does not need to increase the definition of an output driving state and a related control circuit aiming at the preset test mode for the data mask pin DM, so that the adaptation of the preset test mode and the data mask pin DM is ensured, the impedance of the data mask pin can be tested in the preset test mode, and circuit processing errors are avoided.

In one embodiment of the present disclosure, referring to fig. 3, a schematic structural diagram of a semiconductor memory 30 provided by an embodiment of the present disclosure is shown. As shown in fig. 3, the semiconductor memory 30 includes a first mode register 301, a second mode register 302, a data mask pin 310, and a first driving circuit 311, and the first driving circuit 311 is connected to the first mode register 301, the second mode register 302, and the data mask pin 310, respectively; wherein, the liquid crystal display device comprises a liquid crystal display device,

A data mask pin 310 configured to receive an input mask signal for writing data;

the first driving circuit 311 is configured to control the impedance of the data mask pin 310 to be a first impedance parameter according to the first mode register 301 if the data mask pin 310 is selected as a test object when the semiconductor memory 30 is in a preset test mode; alternatively, if the data mask pin 310 is not the test object, the impedance of the data mask pin 310 is controlled to be the second impedance parameter according to the second mode register 302.

Here, the semiconductor memory 30 further includes at least one data pin for receiving or outputting data, the first mode register 301 for indicating an impedance of the at least one data pin in an output driving state as a first impedance parameter, and the second mode register 302 for indicating an impedance of the at least one data pin in a terminating state as a second impedance parameter.

In this way, when the semiconductor memory 30 is in the preset test mode, the first mode register 301 and the second mode register 302 are allowed to directly define the impedance of the data mask pin 310, and the definition of the output driving state and the related control circuit are not required to be increased for the preset test mode for the data mask pin 310, so that the adaptation of the preset test mode to the data mask pin 310 is ensured, the impedance of the data mask pin can be tested in the preset test mode, and the circuit processing error is avoided.

In some embodiments, as shown in fig. 4A, the semiconductor memory 30 further includes at least one second driving circuit 321, and each second driving circuit 321 is connected to the first mode register 301, the second mode register 302, and one data pin 320; wherein, the liquid crystal display device comprises a liquid crystal display device,

the second driving circuit 321 is configured to control the impedance of the corresponding data pin 320 to be a first impedance parameter through the first mode register 301 if the corresponding data pin 320 is selected as a test object when the semiconductor memory 30 is in the preset test mode; alternatively, if the corresponding data pin 320 is not the test object, the impedance of the corresponding data pin 320 is controlled to be the second impedance parameter by the second mode register 302.

It should be understood that only one data pin 320 is shown schematically in fig. 4A, and that there are actually more data pins in the semiconductor memory 30. The disclosed embodiments are not limited in the number of data mask pins 310 and data pins 320.

It should be noted that the preset test mode may be a pod mode, which allows the host to test the pull-up impedance of the data mask pin or the data pin.

In some embodiments, as shown in fig. 4B, the semiconductor memory 30 further includes a third mode register 303 and a first decoding module 304; wherein, the liquid crystal display device comprises a liquid crystal display device,

A first mode register 301 configured to store and output a first operation code;

a second mode register 302 configured to store and output a second operation code;

a third mode register 303 configured to store and output a third operation code; wherein the third operation code is used for indicating whether the semiconductor memory 30 enters a preset test mode;

the first decoding module 304 is configured to receive the third operation code, decode the third operation code, and output a first test flag signal; wherein, the first test flag signal is used to indicate whether the data mask pin 310 is a test object;

the first driving circuit 311 is further configured to receive the first test flag signal, the first operation code, and the second operation code; and selects one of the first operation code and the second operation code to control the impedance of the data mask pin 310 according to the first test flag signal in case that the semiconductor memory 30 enters the preset test mode.

In some embodiments, as shown in fig. 4B, the first decoding module 304 is further configured to perform decoding processing on the third operation code, and output at least one second test flag signal; the second test mark signal is used for indicating whether one data pin is a test object or not;

The second driving circuit 321 is further configured to receive the corresponding second test flag signal, the first operation code, and the second operation code; and in case that the semiconductor memory 30 enters a preset test mode, one of the first operation code and the second operation code is selected to control the impedance of the data pin 320 according to the second test flag signal.

It should be noted that, the first test flag signal is an internal flag signal introduced to the data mask pin 310 to indicate whether the data mask pin 310 is a test object in the pod mode; the second test flag signal is an internal flag signal introduced for the data pin 320 to indicate whether the data pin 320 is a test object in the pod mode. The first test flag signal and the second test flag signal are obtained by decoding according to the third operation code.

Thus, in the presently disclosed embodiment, by the third operation code in the third mode register, determining whether the semiconductor memory 30 enters the pod mode, and selecting a test object from the data mask pin and the at least one data pin if the pod mode is entered; then, the impedance of the selected test object is controlled to be a first impedance parameter (essentially, pull-up output driving impedance) through a first operation code in the first mode register, and the impedance of the unselected test object is controlled to be a second impedance parameter (essentially, termination impedance) through a second operation code in the second mode register, so that an impedance test result of the test object is obtained. The definition of the output driving state and a related control circuit are not required to be added for the preset test mode for the data mask pins, so that the adaptation of the preset test mode and the data mask pins is ensured, the impedance of the data mask pins can be tested in the preset test mode, and circuit processing errors are avoided.

It should be noted that, the standard number of the first mode register is 5, and the first operation code refers to the 2 nd to 1 st operation codes stored in the first mode register, and is denoted as MR5 OP [2:1]; the standard number of the second mode register is 34, and the second operation code refers to the 2 nd bit to 0 th bit operation codes stored in the second mode register and is expressed as MR34 OP [2:0]; the standard number of the third mode register is 61, and the third operation code refers to the 4 th bit to 0 th bit operation codes stored in the third mode register, and is denoted by MR61 OP [4:0].

As shown in fig. 5, taking an 8-bit (X8) semiconductor memory 30 as an example, the first decoding module 304 is configured to receive the third operation code MR61 OP [4:0], and decode to obtain a first test flag signal pod_dm_en and second test flag signals pod_dq0_en to pod_dq7_en. Here, the second test flag signals pod_dq0_en to pod_dq7_en are used to indicate whether the data pins DQL0 to DQL7 are test objects in pod, respectively. It should be appreciated that the logic circuits in the first decoding block 304 are designed according to the foregoing table 1.

The following exemplary description of the specific structure of the first driving circuit 311 is provided.

In the disclosed embodiment, the semiconductor memory 30 is further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal zq1_code [ N-1:0].

As shown in fig. 6, the first driving circuit 311 may include:

a first signal processing module 41 configured to receive a first test flag signal PODTM_DM_EN, a first operation code MR5 OP [2:1], a second operation code MR34 OP [2:0], and a first non-test state control signal; when the semiconductor memory 30 is in the preset test mode, a first impedance control signal is output based on one of the first operation code MR5 OP [2:1] and the second operation code MR34 OP [2:0] according to the first test flag signal PODTM_DM_EN; alternatively, when the semiconductor memory 30 is not in the preset test mode, the first impedance control signal is output based on the first non-test state control signal.

A first logic module 42 configured to receive the first impedance control signal, the second impedance control signal, and the first calibration signal zq1_code [ N-1:0]; selecting and logically combining the first impedance control signal, the second impedance control signal and the first calibration signal ZQ1_CODE [ N-1:0] to output a first target signal PU1_MAIN_CODE;

the first driving module 43 includes a plurality of first impedance units configured to receive the first target signal PU1_main_code, and controls the plurality of first impedance units using the first target signal PU1_main_code to control the impedance of the data mask pin 310.

It should be understood that the data mask pin 310 only supports the Write function, does not need to output data to the outside, and in the end state, only involves the level up function and not the level down function, so that only the first impedance control signal and the second impedance control signal controlling the level up function exist in the first driving circuit 311 and do not involve the relevant signals controlling the level down function. In addition, the pull-up resistance of each first impedance unit should be a standard resistance. However, as environmental parameters such as temperature and voltage in the actual working environment change, the resistance value of the first impedance unit also changes correspondingly. Thus, the first calibration signal ZQ1_CODE [ N-1:0] is used to calibrate the resistance of each first impedance unit to a standard resistance. Here, all the first impedance units share the first calibration signal zq1_code [ N-1:0].

It should be noted that the first impedance control signal and the second impedance control signal correspond to two attributes, namely, a write-related attribute and a read-related attribute, respectively. It should be appreciated that in the non-pod mode, depending on the actual operating conditions, one of the first and second impedance control signals is active, which is combined with the first calibration signal zq1_code [ N-1:0] to obtain the first target signal PU1_main_code; in addition, in the PODTM mode, the second impedance control signal is inactive, and the first target signal PU1_MAIN_CODE is obtained by combining the first impedance control signal and the first calibration signal ZQ1_CODE [ N-1:0]. Here, the active signals in the first impedance control signal and the second impedance control signal are used for turning on or off the level pull-up function of the first impedance unit, and the first calibration signal zq1_code [ N-1:0] is used for calibrating the resistance value of the first impedance unit to the standard resistance value when the level pull-up function of the first impedance unit is turned on.

In some embodiments, as shown in fig. 6, the first signal processing module 41 includes:

the second decoding module 411 is configured to receive the first operation CODE MR5 OP [2:1], decode the first operation CODE MR5 OP [2:1], and output a first decoding signal ronpu_code [ M ]: 0];

a third decoding module 412 configured to receive the second operation CODE MR34 OP [2:0], decode the second operation CODE MR34 OP [2:0], and output a second decode signal RTT_CODE [ M:0];

the first selection module 413 is configured to receive the first test flag signal pod_dm_en, the first decoding signal ronpu_code [ M:0] and a second decode signal rtt_code [ M:0]; and selects the first decoding signal ronpu_code [ M ] according to the first test flag signal pod_dm_en: outputting a first test state control signal by one of 0 and a second decoding signal RTT_CODE [ M:0];

a second selection module 414 configured to receive the test enable signal pod_en, the first test state control signal, and the first non-test state control signal; and selecting one of the first test state control signal and the first non-test state control signal to output a first impedance control signal according to the test enable signal PODTM_EN.

It should be understood that the logic circuits in the second decoding module 411 are designed according to the foregoing table 2, i.e. the first decoding signal is used to characterize the resistance value of the driving impedance Ron (the first impedance parameter), and the logic circuits in the third decoding module 412 are designed according to the foregoing table 3, i.e. the second decoding signal is used to characterize the resistance value of the terminating impedance RTT (the second impedance parameter). In addition, M is a positive integer, and the specific value of M needs to be determined according to the actual working scene.

It should be noted that, the test enable signal pod_en is used to indicate whether the semiconductor memory is in the preset test mode pod, and is also decoded according to the third control code MR61 OP [4:0], as in the foregoing table 1, when the value of MR61 OP [4:0] is other combinations than 00000B in the table 1, it is indicated that the semiconductor memory is in the preset test mode pod, and the test enable signal pod_en is in the first level state (for example, logic "1"); when MR61 OP [4:0] =00000b, it is explained that the semiconductor memory is not in the preset test mode PODTM, the test enable signal podtm_en is in the second level state (e.g. logic "0"). Alternatively, it may be understood that if one of the first test flag signal or the second test flag signal is in the first level state, the test enable signal pod_en is in the first level state, and if both the first test flag signal and the second test flag signal are in the second level state, the test enable signal pod_en is in the second level state.

For the first driving circuit 311 shown in fig. 6, there may be two specific embodiments according to the definition of the first non-test state control signal and the second impedance control signal.

In one embodiment, the first non-test state control signal is used to indicate the impedance of the data mask pin except for a preset test state, and the second impedance control signal is used to indicate the impedance of the data pin in an output driving state. That is, the impedance control of the pod mode is achieved by incorporating the signal control strategy of the data mask pin in the pod mode into the signal control strategy of the write-related attribute.

Accordingly, as shown in FIG. 7, the first impedance control signal is represented by ODT_MUX [ M:0], and the second impedance control signal is represented by IMPpu_CODE [ M ]: 0] represents. In particular, compared to fig. 6, the first driving circuit 311 in fig. 7 further includes a first preprocessing module 44 and a second preprocessing module 45, where the first preprocessing module 44 is configured to decode the first operation CODE MR5 OP [2:1] to obtain a second impedance control signal imppu_code [ M ]: 0], the second preprocessing module 45 is configured to determine the first non-test state control signal according to MR34[5:3] related to rtt_wr, MR35[2:0] related to rtt_nom_wr, MR35[5:3] related to rtt_nom_rd, MR34[2:0] related to rtt_park, MR33[5:3] related to dqs_rtt_park, and the specific meaning of the above signals is please refer to the specification of DDR5 SPEC, and this part of signals does not affect implementation of the non-disclosed embodiments, and is not repeated. In addition, in the following description, if the semiconductor memory 30 is in the pod mode, the test enable signal pod_en is logic "1", and if the semiconductor memory 30 is not in the pod mode, the test enable signal pod_en is logic "0"; if the data mask pin 310 is a test object in the pod mode, the first test flag signal pod_dm_en is logic "1", and if the data mask pin 310 is not a test object in the pod mode, the first test flag signal pod_dm_en is logic "0".

The working principle of fig. 7 is described below in three working scenarios.

Working scene one: the semiconductor memory 30 enters the pod mode and the data mask pin 310 is the test object. At this time, since the first test flag signal pod_dm_en is logic "1", the first selection module 413 outputs the first decoding signal ronpu_code [ M:0] outputting to obtain a first test state control signal; since the test enable signal podtm_en is logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal odt_mux [ M:0]. As described above, the second impedance control signal imppu_code [ M:0] in the pod mode is inactive, so the first logic module 42 actually logically combines the first impedance control signal odt_mux [ M:0] with the first calibration signal zq1_code [ N-1:0] to obtain the first target signal PU1_main_code, thereby controlling the impedance of the data mask pin 310. Here, the invalidation of the second impedance control signal imppu_code [ M:0] can be achieved in at least two ways: corresponding signal blocking logic is added to the first preprocessing module 44 or to the first logic module 42.

As can be seen from the above, for scenario one, the impedance of the data mask pin 310 is actually controlled by the first opcode MR5 OP [2:1 ].

And a second working scene: the semiconductor memory 30 enters the pod mode and the data mask pin 310 is not the test object. At this time, since the first test flag signal pod_dm_en is logic "0", the first selection module 413 decodes the second decoding signal rtt_code [ M:0] outputting to obtain a first test state control signal; since the test enable signal podtm_en is logic "1", the second selection module 414 outputs the first test state control signal determined by the first selection module 413 to obtain the first impedance control signal odt_mux [ M:0]. As described above, the second impedance control signal imppu_code [ M:0] in the pod mode is inactive, so the first logic module 42 actually logically combines the first impedance control signal odt_mux [ M:0] with the first calibration signal zq1_code [ N-1:0] to obtain the first target signal PU1 main_code, thereby controlling the impedance of the data mask pin 310.

As can be seen from the above, for scenario two, the impedance of the data mask pin 310 is actually controlled by the second opcode MR34 OP [2:0 ].

And a working scene III: the semiconductor memory 30 does not enter the pod mode. At this time, since the test enable signal pod_en is logic "0", the second selecting module 414 outputs the first non-test state control signal determined by the second preprocessing module 45 to obtain the first impedance control signal odt_mux [ M:0]; while the first preprocessing module 44 outputs the second impedance control signal imppu_code [ M:0]. Since the data mask pin 310 only supports the Write function, the second impedance control signal imppu_code [ M:0] is inactive and the first impedance control signal odt_mux [ M:0] is active in the non-pod mode, the first logic module 42 combines the first impedance control signal odt_mux [ M:0] with the first calibration signal zq1_code [ N-1:0] to obtain the first target signal PU1_main_code, thereby controlling the impedance of the data mask pin 310.

As can be seen from the above, for the third operating scenario, the impedance of the data mask pin 310 is controlled by the second preprocessing module 45, depending on the actual operating state.

In another embodiment, the first non-test state control signal is used to indicate the impedance of the data pin in the output driving state, and the second impedance control signal is used to indicate the impedance of the data mask pin in other than the preset test state. That is, impedance control of the pod mode is achieved by incorporating a signal control strategy of the data mask pin in the pod mode into a signal control strategy of the read-related attribute.

Accordingly, as shown in fig. 8, the first impedance control signal is represented by imppu_code [ M:0] and the second impedance control signal is represented by odt_ctrl [ M:0]. In particular, in contrast to fig. 6, the semiconductor memory 30 in fig. 8 also comprises a first preprocessing module 44 and a second preprocessing module 45, wherein the first preprocessing module 44 is configured to decode the first operation code MR5 OP [2:1] to obtain a first non-test state control signal, and the second preprocessing module 45 is configured to determine the second impedance control signal according to the MR34[5:3] related to rtt_wr, the MR35[2:0] related to rtt_nom_wr, the MR35[5:3] related to rtt_nom_rd, the MR34[2:0] related to rtt_park, and the MR33[5:3] related to dqs_rtt_park.

Similarly, the working principle of fig. 8 is explained below in three working scenarios.

Working scene one: the semiconductor memory 30 enters the pod mode and the data mask pin 310 is the test object. At this time, since the first test flag signal pod_dm_en is logic "1", the first selection module 413 outputs the first decoding signal ronpu_code [ M:0] outputting to obtain a first test state control signal; since the test enable signal pod_en is logic "1", the second selecting module 414 outputs the first test state control signal determined by the first selecting module 413, to obtain a first impedance control signal imppu_code [ M:0]. As described above, the second impedance control signal ODT_CTRL [ M:0] in PODTM mode is inactive, so the first logic module 42 effectively logically combines the first impedance control signal IMPpu_CODE [ M:0] with the first calibration signal ZQ1_CODE [ N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask pin 310.

Thus, for scenario one, the impedance of the data mask pin 310 is still controlled by the first opcode MR5OP [2:1 ].

And a second working scene: the semiconductor memory 30 enters the pod mode and the data mask pin 310 is not the test object. At this time, since the first test flag signal pod_dm_en is logic "0", the first selection module 413 decodes the second decoding signal rtt_code [ M:0] outputting to obtain a first test state control signal; since the test enable signal pod_en is logic "1", the second selecting module 414 outputs the first test state control signal determined by the first selecting module 413, to obtain a first impedance control signal imppu_code [ M:0]. As described above, the second impedance control signal odt_ctrl in the pod mode is inactive, so the first logic module 42 will actually output the first impedance control signal imppu_code [ M:0] and the first calibration signal zq1_code [ N-1:0] to obtain a first target signal PU1_main_code, thereby controlling the impedance of the data mask pin 310.

Thus, for scenario two, the impedance of the data mask pin 310 is still controlled by the second opcode MR34 OP [2:0 ].

And a working scene III: the semiconductor memory 30 does not enter the pod mode. At this time, since the test enable signal pod_en is logic "0", the second selecting module 414 outputs the first non-test state control signal determined by the first preprocessing module 44, to obtain a first impedance control signal imppu_code [ M:0]. While the second preprocessing module 45 outputs the second impedance control signal odt_ctrl M: 0. As described above, since the data mask pin DM only supports the Write function, the first impedance control signal imppu_code [ M:0] is inactive and the second impedance control signal odt_ctrl [ M:0] is active in the non-pod mode, the first logic module 42 combines the second impedance control signal odt_ctrl [ M:0] with the first calibration signal zq1_code [ N-1:0] to obtain the first target signal PU1_main_code, thereby controlling the impedance of the data mask pin 310.

Thus, for scenario three, the impedance of the data mask pin 310 is also controlled by the second preprocessing module 45, depending on the actual operating state.

In fig. 7 and 8, the "/" symbol is marked on the signal path to indicate that a plurality of signal paths actually exist therein, and only one signal path is drawn for illustration. In other words, MR34 OP [2:0], MR5 OP [2:1], RONpu_CODE [ M:0], rtt_code [ M:0], imppu_code [ M:0], ZQ1_CODE [ N-1:0], ODT_CTRL [ M:0], odt_mux [ M: each of 0, PU1 MAIN CODE contains a plurality of sub-signals, each having a respective signal path.

The signal processing procedure in the first driving circuit 311 is described below with reference to fig. 7 or 8.

In some embodiments, as shown in fig. 7 or 8, the first decoding signal ronpu_code [ M:0], the second decode signal rtt_code [ M:0], the first test state control signal, the first non-test state control signal, and the first impedance control signal each include an (m+1) bit sub-signal, denoted as [ M:0], the first selection module 413 includes (m+1) first data selectors, and the second selection module 414 includes (m+1) second data selectors; wherein, the input end of a first data selector receives a first decoding signal ROnpu_CODE [ M: a one-bit sub-signal of 0] and a one-bit sub-signal of a second decoding signal RTT_CODE [ M:0], wherein the output end of a first data selector is used for outputting the one-bit sub-signal of a first test state control signal, and the control ends of all the first data selectors receive a first test flag signal PODTM_DM_EN; an input end of a second data selector receives the one-bit sub-signal of the first test state control signal and the one-bit sub-signal of the first non-test state control signal, an output end of the second data selector is used for outputting the one-bit sub-signal of the first impedance control signal, and control ends of all the second data selectors receive the test enable signal PODTM_EN; wherein M is a positive integer.

It should be noted that the first test state control signal is denoted as a first test state control signal [ M:0], the first non-test state control signal is denoted as a first non-test state control signal [ M:0], and the first impedance control signal is denoted as a first impedance control signal [ M:0]. Thus, the 1 st first data selector receives the RONpu_CODE [0], the RTT_CODE [0] and the PODTM_DM_EN, respectively, and selects one of the RONpu_CODE [0] and the RTT_CODE [0] to output a first test state control signal [0] according to the PODTM_DM_EN, the 1 st second data selector receives the first test state control signal [0], the first non-test state control signal [0] and the PODTM_EN, respectively, and selects one of the first test state control signal [0] and the first non-test state control signal [0] to output a first impedance control signal [0] according to the PODTM_EN, and the other can be understood by reference.

In some embodiments, the second impedance control signal comprises an (M+1) bit sub-signal and the first calibration signal ZQ1_CODE [ N-1:0] comprises an N bit sub-signal. The first target signals include a set A of sub-signals, and each set of sub-signals includes N bits of sub-signals, the 1 st set of signals in the first target signals is denoted as PU1_MAIN_CODE_1[N-1:0, the 2 nd set of signals in the first target signals is denoted as PU1_MAIN_CODE_2[ N-1:0] … … the A st set of signals in the first target signals is denoted as PU1_MAIN_CODE_A [ N-1:0].

The first driving module 43 includes a first impedance units, and each first impedance unit is configured to receive a group of sub-signals in the first target signal PU1 MAIN CODE; wherein, as shown in fig. 7 or fig. 8, the first logic module 42 is specifically configured to determine whether the level pull-up function of at least one first impedance unit is enabled according to the first impedance control signal and the second impedance control signal; and determining the level state of the a-th group of sub-signals in the first target signal PU1_MAIN_CODE according to the first calibration signal under the condition that the level pull-up function of the a-th first impedance unit is started so as to control the resistance value of the a-th first impedance unit to be a standard resistance value; or under the condition that the level pull-up function of the a-th first impedance unit is not started, determining that the a-th group of sub-signals in the first target signal PU1_MAIN_CODE are all in a first level state; wherein a, N and A are integers, a is less than or equal to A, and (M+1) is less than or equal to A.

It should be understood that the plurality of first impedance units are in a parallel state, and each first impedance unit may provide a standard resistance value RZQ. Thus, if the pull-up impedance of the data mask pin 310 needs to be adjusted to RZQ/2, the level pull-up function of the 2 first impedance units is turned on, and the level pull-up functions of the remaining first impedance units are turned off; if the pull-up impedance of the data mask pin 310 needs to be adjusted to RZQ/3, the level pull-up function of the 3 first impedance units is enabled, and the level pull-up function of the remaining first impedance units is turned off, as will be understood in other cases.

It should be appreciated that for the first logic module 42, only one valid signal exists among both the first impedance control signal and the second impedance control signal. In the case of M+1.ltoreq.A, a one-bit sub-signal in the active signal controls whether the level pull-up function of one or more first impedance units is enabled.

Illustratively, in the case where m+1=a=7, assuming that an effective signal among both the first impedance control signal and the second impedance control signal is imppu_code [6:0], imppu_code [0] controls the 1 st first impedance unit, imppu_code [1] controls the 2 nd first impedance unit … … imppu_code [6] controls the 7 th first impedance unit. Specifically, assuming imppu_code [6:0] =1111111, the level value of each group of sub-signals (7 groups in total) in the first target signal is correspondingly the same as the level value of the first calibration signal, so that the pull-up resistance of the 7 first impedance units is RZQ, and thus the pull-up resistance of the data mask pin 310 is RZQ/7; assuming imppu_code [6:0] =1111000, the level values of the 1 st group of sub-signals to the 3 rd group of sub-signals in the first target signal are all in a first level state, and the level value of each group of sub-signals in the 4 th group of sub-signals to the 7 th group of sub-signals is the same as the level value of the first calibration signal, so that the 1 st to 3 rd first impedance units are in an off state, and the pull-up resistances of the 4 th to 7 th first impedance units are all RZQ, so that the pull-up resistance of the data mask pin 310 is RZQ/4. Other situations can be understood with reference.

Illustratively, in the case where m+1=4, a=7, it is assumed that the effective signal among both the first impedance control signal and the second impedance control signal is imppu_code [3:0], imppu_code [0] controls the 1 st first impedance unit, imppu_code [1] controls the 2 nd first impedance unit and the 3 rd first impedance unit, imppu_code [2] controls the 4 th first impedance unit and the 5 th impedance unit, and imppu_code [3] controls the 6 th first impedance unit and the 7 th first impedance unit. Specifically, assuming imppu_code [3:0] =1111, the level value of each group of sub-signals in the first target signal is the same as the level value of the first calibration signal, so that the pull-up resistance of the 7 first impedance units is RZQ, and thus the pull-up resistance of the data mask pin 310 is RZQ/7; assuming imppu_code [3:0] =1100, the level values of the 1 st group of sub-signals to the 3 rd group of sub-signals in the first target signal are all in a first level state, and the level value of each group of sub-signals in the 4 th group of sub-signals to the 7 th group of sub-signals is the same as the level value of the first calibration signal correspondingly, so that the 1 st to 3 rd first impedance units are in an off state, and the pull-up resistances of the 4 th to 7 th first impedance units are all RZQ, so that the pull-up resistance of the data mask pin 310 is RZQ/4. Other situations can be understood with reference.

On the basis, if the level pull-up function of a certain first impedance unit is started, the pull-up resistance value of the first impedance unit is calibrated to a standard resistance value by using a first calibration signal; conversely, if the level pull-up function of the first impedance unit is not enabled, the relevant circuit of the first impedance unit is disconnected by using the fixed signal in the first level state.

In some embodiments, as shown in fig. 7 or fig. 8, each first impedance unit includes N first switching tubes (e.g., the first switching tube 431 in fig. 7 or fig. 8), N second switching tubes (e.g., the second switching tube 432 in fig. 7 or fig. 8), and 2N first resistors (e.g., the first resistor 433 in fig. 7 or fig. 8), the control end of the nth first switching tube in the a first impedance unit is connected to the nth sub-signal in the a group sub-signal in the first target signal, the first end of one first switching tube is connected to the first end of one first resistor, and the second end of one first switching tube is connected to one power supply signal; the control end of a second switching tube is connected with a ground signal VSS, the first end of the second switching tube is connected with the ground signal VSS, the second end of the second switching tube is connected with the first end of a first resistor, and the second ends of 2N first resistors are connected with the data mask pins. N is less than or equal to N. Particularly, the signal connected to the control end of the second switching tube needs to be determined according to specific circuit logic, and is mainly used for controlling the second switching tube to be in a non-conductive state.

It should be noted that, in fig. 7 or fig. 8, taking the 1 st first impedance unit as an example, the 1 st first impedance unit is configured to receive the first group of sub-signals PU1_main_code_1[N-1:0 in the first target signal, and PU1_main_code_1[N-1:0 includes N sub-signals PU1_main_code_1[0, PU1_main_code_1[1] … … PU1_main_code_1[N-1], where each sub-signal is configured to correspondingly control an operating state of one of the first switching tubes, so as to control the first impedance unit to perform the level pull-up function or not perform the level pull-up function with a standard resistance value.

In addition, in fig. 7 or 8, the 1 st first impedance unit shows 3 first switching tubes (only one first switching tube 431 is labeled), 3 second switching tubes (only one second switching tube 432 is labeled), and 6 first resistors (only one first resistor 433 is labeled), but in a practical scenario, the number of first switching tubes/second switching tubes/first resistors may be more or less.

It should be appreciated that the data mask pin 310 only supports the data write function, providing termination impedance, so the level pull down function need not be performed. Therefore, the first ends of all the second switching tubes are grounded to the signal VSS, which is equivalent to that all the second switching tubes are not turned on.

The following exemplary description of the specific structure of the second driving circuit 321 is provided. It should be understood that some signals in the second driving circuit 321 and some signals in the first driving circuit 311 have substantially the same source and waveform, although the names are different, and thus the same english name is adopted.

In the disclosed embodiment, the semiconductor memory 30 is further configured to determine a third non-test state control signal, a fourth impedance control signal, a fifth impedance control signal, a second calibration signal zq2_code [ N-1:0], and a third calibration signal zq3_code [ N-1:0].

As shown in fig. 9, the second driving circuit 312 may include:

a second signal processing module 51 configured to receive a second test flag signal PODTM_DQ_EN (e.g., PODTM_DQ0_EN, or PODTM_DQ1_EN … …, or PODTM_DQ7_EN as described above), a first operation code MR5 OP [2:1], a second operation code MR34 OP [2:0], and a third non-test state control signal; and outputting a third impedance control signal based on one of the first operation code MR5 OP [2:1] and the second operation code MR34 OP [2:0] according to the second test flag signal PODTM_DQ_EN when the semiconductor memory 30 is in the preset test mode; alternatively, when the semiconductor memory 30 is not in the preset test mode, outputting a third impedance control signal based on the third non-test state control signal;

A second logic module 521 configured to receive the third impedance control signal, the fourth impedance control signal, and the second calibration signal zq2_code [ N-1:0]; selecting and logically combining the third impedance control signal, the fourth impedance control signal and the second calibration signal ZQ2_CODE [ N-1:0] to output a second target signal PU2_MAIN_CODE;

a third logic block 522 configured to receive the fifth impedance control signal and a third calibration signal zq3_code [ N-1:0]; and the fifth impedance control signal and the third calibration signal ZQ3_CODE [ N-1:0] are subjected to logic combination processing, and a third target signal PD_MAIN_CODE is output;

a second driving module 53 including a plurality of second impedance units configured to receive the second target signal PU2_main_code and the third target signal pd_main_code; and controls the plurality of second impedance units using the second target signal PU2_ MAIN _ CODE and the third target signal PD _ MAIN _ CODE to control the impedance of the corresponding data pin 320.

It should be noted that, each data pin 320 corresponds to a respective second driving circuit 321, and only one second driving circuit 321 is taken as an example for explanation in the embodiment of the disclosure.

It should be appreciated that the data pin 320 supports both the Write function and the Read function, and involves both the level pull-up function and the level pull-down function, so that not only the third and fourth impedance control signals controlling the level pull-up function, but also the fifth impedance control signal controlling the level pull-down function are present in the second drive circuit 321.

It should be noted that the second calibration signal zq2_code [ N-1:0] is used for calibrating the pull-up resistance value, that is, the second calibration signal zq2_code [ N-1:0] is used for calibrating the pull-up resistance value of each second impedance unit to the standard resistance value. The third calibration signal ZQ3_CODE [ N-1:0] is used for calibrating the pull-down resistance, i.e. the third calibration signal ZQ3_CODE [ N-1:0] is used for calibrating the pull-down resistance of each second impedance unit to the standard resistance.

In addition, since the first calibration signal zq1_code [ N-1:0] and the second calibration signal zq2_code [ N-1:0] are both used to calibrate the pull-up resistance value, in some embodiments, the deviations of the first impedance unit and the second impedance unit may be considered to be within the error allowable range, and thus the first calibration signal zq1_code [ N-1:0] and the second calibration signal zq2_code [ N-1:0] may be the same signal.

It should be noted that, for the second driving circuit 321, the second logic module 521 combines the effective signal of the third impedance control signal and the fourth impedance control signal with the second calibration signal zq2_code [ N-1:0] to form the second target signal PU2_main_code for controlling the level pull-up function of the second impedance unit 53. The circuit structure and the signal processing process of the partial circuit can be correspondingly understood by referring to the first driving circuit 311, and are not described herein.

In addition, the second driving circuit 321 combines the fifth impedance control signal with the third calibration signal zq3_code [ N-1:0] through the third logic module 522 to form a third target signal pd_main_code for controlling the level pull-down function of the second impedance unit 53.

In some embodiments, as shown in fig. 9, the second signal processing module 51 may include:

the fourth decoding module 511 is configured to receive the first operation CODE MR5 OP [2:1], decode the first operation CODE MR5 OP [2:1], and output a third decoding signal ronpu_code [ M ]: 0];

a fifth decoding module 512 configured to receive the second operation CODE MR34 OP [2:0], decode the second operation CODE MR34 OP [2:0], and output a fourth decoding signal RTT_CODE [ M:0];

the third selection module 513 is configured to receive the second test flag signal pod_dq_en, the third decoding signal ronpu_code [ M:0] and a fourth decode signal rtt_code [ M:0]; and selects the third decoding signal ronpu_code [ M ] according to the second test flag signal: outputting a third test state control signal by one of 0 and a fourth decoding signal RTT_CODE [ M:0];

a fourth selection module 514 configured to receive the test enable signal pod_en, the third test state control signal, and the third non-test state control signal; selecting one of the third test state control signal and the third non-test state control signal to output a third impedance control signal according to the test enable signal PODTM_EN; the test enable signal pod_en is used to indicate whether the semiconductor memory 30 is in a predetermined test mode.

For the second driving circuit 321 shown in fig. 9, there may be two specific embodiments according to the definition of the third non-test state control signal and the fourth impedance control signal.

In one embodiment, the third non-test state control signal is used to indicate the impedance of the corresponding data pin in the termination state, and the fourth impedance control signal and the fifth impedance control signal are used together to indicate the impedance of the corresponding data pin in the output driving state. That is, the impedance control of the pod mode is achieved by incorporating the signal control strategy of the data pin in the pod mode into the signal control strategy of the write-related attribute.

Accordingly, as shown in FIG. 10, the third impedance control signal is represented by ODT_MUX [ M:0], and the fourth impedance control signal is represented by IMPpu_CODE [ M ]: 0] and the fifth impedance control signal is represented by imppd_code [ M:0] represents. In particular, compared to fig. 9, the second driving circuit 321 in fig. 10 further includes a third preprocessing module 54 and a fourth preprocessing module 55, where the third preprocessing module 44 is configured to decode the first operation CODE MR5 OP [2:1] to obtain a fourth impedance control signal imppu_code [ M ]: 0], the fourth preprocessing module 55 is configured to determine the third non-test state control signal according to MR34[5:3] related to rtt_wr, MR35[2:0] related to rtt_nom_wr, MR35[5:3] related to rtt_nom_rd, MR34[2:0] related to rtt_park, MR33[5:3] related to dqs_rtt_park. In addition, in the following description, if the semiconductor memory 30 is in the pod mode, the test enable signal pod_en is logic "1", and if the semiconductor memory 30 is not in the pod mode, the test enable signal pod_en is logic "0"; if the corresponding data pin 320 is a test object in the pod mode, the corresponding first test flag signal pod_dq_en is logic "1", and if the corresponding data pin 320 is not a test object in the pod mode, the corresponding first test flag signal pod_dq_en is logic "0".

The second driving circuit 321 in fig. 10 is substantially the same as the first driving circuit 311 in fig. 7, and the description of fig. 7 can be correspondingly understood with reference to the foregoing description, which is not repeated in the embodiments of the disclosure. In addition, the second driving circuit 321 in fig. 10 further includes a control portion for the level pull-down impedance, that is, a third logic module 522, and the signal processing principle thereof is described later. It should be appreciated that since the data pin 320 supports the Write function and the Read function, in the non-pod mode, it is necessary to determine whether the third impedance control signal is valid or the fourth impedance control signal is valid according to the actual working requirement, and then logically combine the valid signal with the second calibration signal zq2_code [ M:0] to obtain the second target signal PU2_main_code.

In another embodiment, the third non-test state control signal and the fifth impedance control signal are used together to indicate the impedance of the corresponding data pin in the output driving state, and the fourth impedance control signal is used to indicate the impedance of the corresponding data pin in the termination state. That is, impedance control of the pod mode is achieved by incorporating a signal control strategy of the data pin in the pod mode into a signal control strategy of the read-related attribute.

Accordingly, as shown in fig. 11, the third impedance control signal is represented by imppu_code [ M:0] and the fourth impedance control signal is represented by odt_ctrl [ M:0], and the fifth impedance control signal is represented by imppd_code [ M ]: 0] represents. In particular, compared to fig. 9, the semiconductor memory 30 in fig. 11 also includes a third preprocessing module 54 and a fourth preprocessing module 55, where the third preprocessing module 54 is configured to decode the first operation code MR5 OP [2:1] to obtain a third non-test state control signal, and the fourth preprocessing module 55 is configured to determine the fourth impedance control signal according to MR34[5:3] related to rtt_wr, MR35[2:0] related to rtt_nom_wr, MR35[5:3] related to rtt_nom_rd, MR34[2:0] related to rtt_park, and MR33[5:3] related to dqs_rtt_park.

The second driving circuit 321 in fig. 11 is substantially the same as the first driving circuit 311 in fig. 8, and the description of fig. 8 is correspondingly understood with reference to the foregoing description, which is not repeated in the embodiments of the disclosure. In addition, the second driving circuit 321 in fig. 11 further includes a control portion for the level pull-down impedance, that is, a third logic module 522, and the signal processing principle thereof is described later.

The signal processing procedure in the second drive circuit 321 is explained below with reference to fig. 10 or 11.

In some embodiments, the third decode signal RONpu_CODE [ M:0], a fourth decode signal rtt_code [ M:0], a third test state control signal, a third non-test state control signal, and a third impedance control signal each include an (m+1) bit sub-signal, the third select module 513 includes (m+1) third data selectors, and the fourth select module 514 includes (m+1) fourth data selectors; wherein an input terminal of a third data selector receives a third decoding signal ronpu_code [ M: a one-bit sub-signal of 0] and a one-bit sub-signal of a fourth decoding signal RTT_CODE [ M:0], the output end of a third data selector is used for outputting the one-bit sub-signal of a third test state control signal, and the control ends of all the third data selectors receive a second test flag signal PODTM_DQ_EN; an input terminal of a fourth data selector receives the one-bit sub-signal of the third test state control signal and the one-bit sub-signal of the third non-test state control signal, an output terminal of the fourth data selector outputs the one-bit sub-signal of the third impedance control signal, and control terminals of all the fourth data selectors receive the test enable signal pod_en.

It should be noted that the third test state control signal is denoted as a third test state control signal [ M:0], the third non-test state control signal is denoted as a third non-test state control signal [ M:0], and the third impedance control signal is denoted as a third impedance control signal [ M:0]. Thus, the 1 st third data selector receives the RONpu_CODE [0], the RTT_CODE [0] and the PODTM_DQ_EN, respectively, and selects one of the RONpu_CODE [0] and the RTT_CODE [0] to output a third test state control signal [0] according to the PODTM_DQ_EN, the 1 st fourth data selector receives the third test state control signal [0], the third non-test state control signal [0] and the PODTM_EN, respectively, and selects one of the third test state control signal [0] and the third non-test state control signal [0] to output a third impedance control signal [0] according to the PODTM_EN, and the other can be referred to understand the analogy.

In some embodiments, the fourth impedance control signal includes (M+1) bit sub-signals, the second calibration signal ZQ2_CODE [ N-1:0] and the third calibration signal ZQ3_CODE [ N-1:0] each include N bit sub-signals, the second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE each include A sets of sub-signals, and each set of sub-signals includes N bits of sub-signals. The second driving module 53 includes a number a of second impedance units, and each of the second impedance units is configured to receive a set of sub-signals in the second target signal PU2_main_code and a set of sub-signals in the third target signal pd_main_code; wherein the second logic module 521 is specifically configured to determine whether the level pull-up function of at least one second impedance unit is enabled according to the third impedance control signal and the fourth impedance control signal; and under the condition that the level pull-up function of the a second impedance unit is started, determining the level state of the a group of sub-signals in the second target signal PU2_MAIN_CODE according to the second calibration signal ZQ2_CODE [ N-1:0] so as to control the resistance value of the a second impedance unit to be a standard resistance value; or, in the case that the level pull-up function of the a-th second impedance unit is not enabled, determining that the a-th group of sub-signals in the second target signal PU2 MAIN CODE are all in the first level state; a third logic module 522, specifically configured to determine whether the level pull-down function of the at least one second impedance unit is enabled according to the fifth impedance control signal; and determining the level state of the a-th group of sub-signals in the third target signal PD_MAIN_CODE according to the third calibration signal ZQ3_CODE [ N-1:0] under the condition that the level pull-down function of the a-th second impedance unit is started so as to control the resistance value of the a-th second impedance unit to be a standard resistance value; alternatively, it is determined that the a-th group of sub-signals in the third target signal pd_main_code are all in the second level state without enabling the level pull-down function of the a-th second impedance unit.

It should be noted that, the second logic module 521 combines the effective signal of the third impedance control signal and the fourth impedance control signal with the second calibration signal zq2_code [ N-1:0] to obtain the second target signal PU2_main_code, so as to control the level pull-up function of the second impedance unit. The second logic module 521 has substantially the same structure and function as the first logic module 42, and the working principle thereof can be seen from the foregoing description of the first logic module 42, which is not repeated herein.

The third logic module 533 is configured to combine the fifth impedance control signal imppd_code [ M:0] with the third calibration signal zq3_code [ N-1:0] to obtain a third target signal pd_main_code, thereby controlling the level pull-down function of the second impedance unit. Similarly, a one-bit sub-signal of the fifth impedance control signal imppd_code [ M:0] controls whether the level pull-down function of one or more second impedance units is enabled. On the basis, if the level pull-down function of a certain second impedance unit function is started, the pull-down resistance value of the second impedance unit is calibrated to a standard resistance value by utilizing a third calibration signal ZQ3_CODE [ N-1:0], so that the level pull-down function is executed; conversely, if the level pull-down function of the second impedance unit is not enabled, the relevant circuit of the second impedance unit is disconnected by using the fixed signal in the second level state.

In some embodiments, each of the second impedance units includes N third switching tubes (e.g., third switching tube 531 in fig. 10 or 11), N fourth switching tubes (e.g., fourth switching tube 532 in fig. 10 or 11), and 2N second resistors (e.g., second resistor 533 in fig. 10 or 11), the control terminal of the nth third switching tube in the a-th second impedance unit is connected to the nth sub-signal in the a-th group of sub-signals in the second target signal, the first terminal of one third switching tube is connected to the first terminal of one second resistor, and the second terminal of one third switching tube is connected to the power supply signal; the control end of an nth fourth switching tube in the nth second impedance unit is connected with an nth sub-signal in an nth group of sub-signals in the third target signal, the first end of the fourth switching tube is connected with a ground signal, the second end of the fourth switching tube is connected with the first end of a second resistor, and the second ends of 2N second resistors are connected with corresponding data pins.

In fig. 10 or 11, taking the 1 st second impedance unit as an example, the 1 st second impedance unit is configured to receive the first group of sub-signals PU2_main_code_1[N-1:0 in the second target signal and the first group of sub-signals pd_main_code_1[N-1:0 in the third target signal. Wherein, the PU2_MAIN_CODE_1[N-1:0 comprises the sub-signals of PU2_MAIN_CODE_1[0 and PU2_MAIN_CODE_1[1] … … PU2_MAIN_CODE_1[N-1, each sub-signal is used for correspondingly controlling the working state of a third switch tube so as to control the second impedance unit to execute the level pull-up function or not to execute the level pull-up function with the standard resistance value; the PD_MAIN_CODE_1[N-1:0 comprises the sub-signals PD_MAIN_CODE_1[0 and PD_MAIN_CODE_1[1] … … PD_MAIN_CODE_1[N-1, and each sub-signal is used for correspondingly controlling the working state of a fourth switching tube so as to control the second impedance unit to execute the level pull-down function or not to execute the level pull-down function at a standard resistance value.

In addition, in fig. 10 or 11, the 1 st second impedance unit shows 3 third switching tubes (only one third switching tube 531 is labeled), 3 fourth switching tubes (only one fourth switching tube 532 is labeled), and 6 second resistors (only one second resistor 533 is labeled), but in a practical scenario, the number of third switching tubes/fourth switching tubes/second resistors may be more or less.

In the foregoing, the first level state is a high level state, and the second level state is a low level state. The high-level state refers to a level value that turns on the N-channel field effect transistor or turns off the P-channel field effect transistor, and the low-level state refers to a level value that turns off the N-channel field effect transistor or turns on the P-channel field effect transistor.

The first switching tube and the third switching tube are P-type channel field effect tubes, and the second switching tube and the fourth switching tube are N-type channel field effect tubes; the control end of the P-type channel field effect transistor is a grid electrode, the second end of the P-type channel field effect transistor is a source electrode, the first end of the P-type channel field effect transistor is a drain electrode, the control end of the N-type channel field effect transistor is a grid electrode, the second end of the N-type channel field effect transistor is a drain electrode, and the first end of the N-type channel field effect transistor is a source electrode; the standard resistance values were 240 ohms.

The embodiment of the disclosure provides a semiconductor memory, which allows a first mode register and a second mode register related to a data pin to directly define the impedance of the data mask pin when the semiconductor memory is in a preset test mode, the data mask pin does not need to increase the definition of an output driving state and a related control circuit aiming at the preset test mode, the adaptation of the preset test mode and the data mask pin is ensured, the impedance of the data mask pin can be tested in the preset test mode, and circuit processing errors are avoided.

In yet another embodiment of the present disclosure, reference is made to fig. 12, which shows a schematic diagram of the composition and structure of an electronic device 60 provided by an embodiment of the present disclosure. As shown in fig. 12, an electronic device 60 may include a semiconductor memory 30 as described in any of the previous embodiments.

In the disclosed embodiment, the semiconductor memory 30 may be a DRAM chip.

Further, in some embodiments, the DRAM chip conforms to DDR5 memory specifications.

Embodiments of the present disclosure generally relate to a method and related control circuit for controlling a data mask pin and a data pin of a semiconductor memory. When the semiconductor memory is in a preset test mode, the first mode register and the second mode register related to the data pins are allowed to directly define the impedance of the data mask pins, the data mask pins do not need to increase definition of output driving states and related control circuits aiming at the preset test mode, the adaptation of the preset test mode and the data mask pins is ensured, the impedance of the data mask pins can be tested in the preset test mode, and circuit processing errors are avoided.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A control method, characterized by being applied to a semiconductor memory, the semiconductor memory including a data mask pin, and the data mask pin being for receiving an input mask signal of write data; the method comprises the following steps:

when the semiconductor memory is in a preset test mode, if the data mask pin is selected as a test object, controlling the impedance of the data mask pin to be a first impedance parameter through a first mode register; or alternatively, the process may be performed,

if the data mask pin is not the test object, controlling the impedance of the data mask pin to be a second impedance parameter through a second mode register;

The semiconductor memory further comprises at least one data pin, the data pin is used for receiving or outputting data, the first mode register is used for indicating that the impedance of at least one data pin in an output driving state is a first impedance parameter, and the second mode register is used for indicating that the impedance of at least one data pin in a termination state is a second impedance parameter.

2. The control method according to claim 1, wherein when the semiconductor memory is in a preset test mode, the method further comprises:

if the data pin is selected as a test object, controlling the impedance of the data pin to be a first impedance parameter through the first mode register; or alternatively, the process may be performed,

and if the data pin is not the test object, controlling the impedance of the data pin to be a second impedance parameter through the second mode register.

3. The control method according to claim 1, characterized in that the method further comprises:

determining that the semiconductor memory enters a preset test mode and selecting a test object through a third mode register; or alternatively, the process may be performed,

and determining that the semiconductor memory does not enter a preset test mode through the third mode register.

4. A control method according to claim 3, wherein in the case where it is determined that the semiconductor memory enters a preset test mode, the method further comprises:

acquiring a first operation code in the first mode register, a second operation code in the second mode register and a third operation code in the third mode register;

decoding the third operation code to obtain a first test mark signal; wherein the first test flag signal indicates whether the data mask pin is a test object;

and selecting one of the first operation code and the second operation code to control the impedance of the data mask pin according to the first test mark signal.

5. The control method according to claim 4, characterized in that the method further comprises:

determining a first impedance control signal based on one of the first operation code and the second operation code according to the first test flag signal when the semiconductor memory is in a preset test mode; or determining a first impedance control signal based on the first non-test state control signal when the semiconductor memory is not in a preset test mode;

Selecting one of the first impedance control signal and the second impedance control signal to control the impedance of the data mask pin according to the working state of the semiconductor memory;

the first non-test state control signal is used for indicating the impedance of the data mask pin in a state other than a preset test state, and the second impedance control signal is used for indicating the impedance of the data pin in an output driving state; or, the first non-test state control signal is used for indicating the impedance of the data pin in an output driving state, and the second impedance control signal is used for indicating the impedance of the data mask pin in a state other than a preset test state.

6. The control method according to claim 4, wherein in the case where it is determined that the semiconductor memory enters a preset test mode, the method further comprises:

decoding the third operation code to obtain at least one second test mark signal; wherein one of the second test flag signals indicates whether one of the data pins is a test object;

and selecting one of the first operation code and the second operation code to control the impedance of the corresponding data pin according to the second test mark signal.

7. The control method according to claim 6, characterized in that the method further comprises:

determining a third impedance control signal based on one of the first operation code and the second operation code according to the second test flag signal when the semiconductor memory is in a preset test mode; or determining a third impedance control signal based on the third non-test state control signal when the semiconductor memory is not in a preset test mode;

according to the working state of the semiconductor memory, selecting the third impedance control signal and the fifth impedance control signal to control the impedance of the data pin, or selecting the fourth impedance control signal and the fifth impedance control signal to control the impedance of the data pin;

the third non-test state control signal is used for indicating the impedance of the corresponding data pin in a termination state, and the fourth impedance control signal and the fifth impedance control signal are used for indicating the impedance of the corresponding data pin in an output driving state; or the third non-test state control signal and the fifth impedance control signal are used for indicating the impedance of the corresponding data pin in the output driving state together, and the fourth impedance control signal is used for indicating the impedance of the corresponding data pin in the termination state.

8. The control method according to claim 4, wherein the preset test mode is a pod mode for testing an impedance of the data mask pin or at least one of the data pins after packaging;

the standard number of the first mode register is 5, and the first operation code refers to the 2 nd bit to 1 st bit operation codes stored in the first mode register; the standard number of the second mode register is 34, and the second operation code refers to the 2 nd bit to 0 th bit operation code stored in the second mode register; the standard number of the third mode register is 61, and the third operation code refers to the 4 th bit to 0 th bit operation code stored in the third mode register.

9. A semiconductor memory, characterized in that the semiconductor memory comprises a first mode register, a second mode register, a data mask pin and a first driving circuit, and the first driving circuit is respectively connected with the first mode register, the second mode register and the data mask pin; wherein, the liquid crystal display device comprises a liquid crystal display device,

the data mask pin is configured to receive an input mask signal of write data;

10. The semiconductor memory according to claim 9, further comprising at least one second driving circuit, and each of the second driving circuits is connected to the first mode register, the second mode register, and one of the data pins; wherein, the liquid crystal display device comprises a liquid crystal display device,

the second driving circuit is configured to control the impedance of the data pin to be a first impedance parameter through the first mode register if the corresponding data pin is selected as a test object when the semiconductor memory is in a preset test mode; or if the corresponding data pin is not the test object, controlling the impedance of the data pin to be a second impedance parameter through the second mode register.

11. The semiconductor memory of claim 10, further comprising a third mode register and a first decode module; wherein, the liquid crystal display device comprises a liquid crystal display device,

the first mode register is configured to store and output a first operation code;

the second mode register is configured to store and output a second operation code;

the third mode register is configured to store and output a third operation code; the third operation code is used for indicating whether the semiconductor memory enters a preset test mode or not;

the first decoding module is configured to receive a third operation code, decode the third operation code and output a first test mark signal; the first test flag signal is used for indicating whether the data mask pin is a test object or not;

the first driving circuit is further configured to receive the first test flag signal, the first operation code and the second operation code; and under the condition that the semiconductor memory enters a preset test mode, selecting one of the first operation code and the second operation code to control the impedance of the data mask pin according to the first test mark signal.

12. The semiconductor memory of claim 11, further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal; the first calibration signal is used for calibrating a pull-up resistance value;

the first driving circuit includes:

a first signal processing module configured to receive the first test flag signal, the first operation code, the second operation code, and the first non-test state control signal; outputting a first impedance control signal based on one of the first operation code and the second operation code according to the first test flag signal when the semiconductor memory is in a preset test mode; or outputting a first impedance control signal based on the first non-test state control signal when the semiconductor memory is not in a preset test mode;

a first logic module configured to receive the first impedance control signal, the second impedance control signal, and the first calibration signal; selecting and logically combining the first impedance control signal, the second impedance control signal and the first calibration signal to output a first target signal;

The first driving module comprises a plurality of first impedance units and is configured to receive the first target signals, and the first impedance units are controlled by the first target signals so as to control the impedance of the data mask pins;

13. The semiconductor memory of claim 12, wherein the first signal processing module comprises:

the second decoding module is configured to receive the first operation code, decode the first operation code and output a first decoding signal;

the third decoding module is configured to receive the second operation code, decode the second operation code and output a second decoding signal;

a first selection module configured to receive the first test flag signal, the first decode signal, and the second decode signal; selecting one of the first decoding signal and the second decoding signal to output a first test state control signal according to the first test flag signal;

A second selection module configured to receive a test enable signal, the first test state control signal, and the first non-test state control signal; selecting one of the first test state control signal and the first non-test state control signal to output the first impedance control signal according to the test enabling signal; the test enabling signal is used for indicating whether the semiconductor memory is in a preset test mode or not.

14. The semiconductor memory of claim 13, wherein the first decode signal, the second decode signal, the first test state control signal, the first non-test state control signal, and the first impedance control signal each comprise (m+1) bit sub-signals, the first select module comprises (m+1) first data selectors, and the second select module comprises (m+1) second data selectors; wherein, the liquid crystal display device comprises a liquid crystal display device,

the input end of the first data selector is used for respectively receiving a one-bit sub-signal of the first decoding signal and a one-bit sub-signal of the second decoding signal, the output end of the first data selector is used for outputting the one-bit sub-signal of the first test state control signal, and the control ends of all the first data selectors are used for receiving the first test mark signal;

An input end of the second data selector receives the one-bit sub-signal of the first test state control signal and the one-bit sub-signal of the first non-test state control signal, an output end of the second data selector is used for outputting the one-bit sub-signal of the first impedance control signal, and control ends of all the second data selectors receive the test enabling signal;

wherein M is a positive integer.

15. The semiconductor memory of claim 14, wherein the second impedance control signal comprises an (m+1) -bit sub-signal, the first calibration signal comprises an N-bit sub-signal, the first target signal comprises a group a sub-signals, and each group of sub-signals comprises an N-bit sub-signal;

the first driving module comprises A first impedance units, and each first impedance unit is used for receiving a group of sub-signals in the first target signal; wherein, the liquid crystal display device comprises a liquid crystal display device,

the first logic module is specifically configured to determine whether a level pull-up function of at least one first impedance unit is enabled according to the first impedance control signal and the second impedance control signal; under the condition that the level pull-up function of the a-th first impedance unit is started, determining the level state of the a-th group of sub-signals in the first target signal according to the first calibration signal so as to control the resistance value of the a-th first impedance unit to be a standard resistance value; or under the condition that the level pull-up function of the a-th first impedance unit is not started, determining that the a-th group of sub-signals in the first target signal are all in a first level state;

Each first impedance unit comprises N first switching tubes, N second switching tubes and 2N first resistors, the control end of the nth first switching tube in the a first impedance unit is connected with the nth sub-signal in the a group of sub-signals in the first target signal, the first end of one first switching tube is connected with the first end of one first resistor, and the second end of one first switching tube is connected with one power supply signal; the control end of the second switching tube is in signal connection with the ground, the first end of the second switching tube is in signal connection with the ground, the second end of the second switching tube is connected with the first end of the first resistor, and the second ends of the 2N first resistors are connected with the data mask pins;

wherein N, a, N, A is an integer, N is less than or equal to N, a is less than or equal to A, and (M+1) is less than or equal to A.

16. The semiconductor memory according to claim 11, wherein,

the first decoding module is further configured to decode the third operation code and output at least one second test flag signal; wherein, one of the second test flag signals is used for indicating whether one of the data pins is a test object;

The second driving circuit is further configured to receive the corresponding second test flag signal, the first operation code and the second operation code; and under the condition that the semiconductor memory enters a preset test mode, selecting one of the first operation code and the second operation code to control the impedance of the data pin according to the second test mark signal.

17. The semiconductor memory of claim 16, further configured to determine a third non-test state control signal, a fourth impedance control signal, a fifth impedance control signal, a second calibration signal, and a third calibration signal; the second calibration signal is used for calibrating the pull-up resistance value, and the third calibration signal is used for calibrating the pull-down resistance value;

the second driving circuit includes:

a second signal processing module configured to receive the second test flag signal, the first operation code, the second operation code, and the third non-test state control signal; outputting a third impedance control signal based on one of the first operation code and the second operation code according to the second test flag signal when the semiconductor memory is in a preset test mode; or outputting a third impedance control signal based on the third non-test state control signal when the semiconductor memory is not in the preset test mode;

A second logic module configured to receive the third impedance control signal, the fourth impedance control signal, and the second calibration signal; selecting and logically combining the third impedance control signal, the fourth impedance control signal and the second calibration signal to output a second target signal;

a third logic module configured to receive the fifth impedance control signal and the third calibration signal; performing logic combination processing on the fifth impedance control signal and the third calibration signal, and outputting a third target signal;

a second driving module including a plurality of second impedance units configured to receive the second target signal and the third target signal; and controlling a plurality of second impedance units by using the second target signal and the third target signal so as to control the impedance of the corresponding data pins;

18. The semiconductor memory according to claim 17, wherein the second signal processing module comprises:

the fourth decoding module is configured to receive the first operation code, decode the first operation code and output a third decoding signal;

a fifth decoding module configured to receive the second operation code, decode the second operation code, and output a fourth decoded signal;

a third selection module configured to receive the second test flag signal, the third decode signal, and the fourth decode signal; selecting one of the third decoding signal and the fourth decoding signal to output a third test state control signal according to the second test flag signal;

a fourth selection module configured to receive a test enable signal, the third test state control signal, and the third non-test state control signal; selecting one of the third test state control signal and the third non-test state control signal to output the third impedance control signal according to the test enabling signal; the test enabling signal is used for indicating whether the semiconductor memory is in a preset test mode or not.

19. The semiconductor memory of claim 18, wherein the third decode signal, the fourth decode signal, the third test state control signal, the third non-test state control signal, and the third impedance control signal each comprise (m+1) bit sub-signals, the third select module comprises (m+1) third data selectors, and the fourth select module comprises (m+1) fourth data selectors; wherein, the liquid crystal display device comprises a liquid crystal display device,

the input end of the third data selector receives the one-bit sub-signal of the third decoding signal and the one-bit sub-signal of the fourth decoding signal, the output end of the third data selector is used for outputting the one-bit sub-signal of the third test state control signal, and the control ends of all the third data selectors receive the second test flag signal;

the input end of the fourth data selector receives the one-bit sub-signal of the third test state control signal and the one-bit sub-signal of the third non-test state control signal, the output end of the fourth data selector is used for outputting the one-bit sub-signal of the third impedance control signal, and the control ends of all the fourth data selectors receive the test enabling signal.

20. The semiconductor memory of claim 19, wherein the fourth impedance control signal comprises an (m+1) -bit sub-signal, the second and third calibration signals each comprise an N-bit sub-signal, the second and third target signals each comprise a group a sub-signals, and each group of sub-signals comprises an N-bit sub-signal;

the second driving module comprises A second impedance units, and each second impedance unit is used for receiving a group of sub-signals in the second target signal and a group of sub-signals in the third target signal; wherein, the liquid crystal display device comprises a liquid crystal display device,

the second logic module is specifically configured to determine whether a level pull-up function of at least one second impedance unit is enabled according to the third impedance control signal and the fourth impedance control signal; under the condition that the level pull-up function of the a-th second impedance unit is started, determining the level state of the a-th group of sub-signals in the second target signal according to the second calibration signal so as to control the resistance value of the a-th second impedance unit to be a standard resistance value; or, under the condition that the level pull-up function of the a-th second impedance unit is not started, determining that the a-th group of sub-signals in the second target signal are all in a first level state;

The third logic module is specifically configured to determine whether a level pull-down function of at least one second impedance unit is enabled according to the fifth impedance control signal; and under the condition that the level pull-down function of the a-th second impedance unit is started, determining the level state of the a-th group of sub-signals in the third target signal according to the third calibration signal so as to control the resistance value of the a-th second impedance unit to be a standard resistance value; or, determining that the a-th group of sub-signals in the third target signal are all in the second level state under the condition that the level pull-down function of the a-th second impedance unit is not started;

each second impedance unit comprises N third switching tubes, N fourth switching tubes and 2N second resistors, the control end of the nth third switching tube in the a second impedance unit is connected with the nth sub-signal in the a group of sub-signals in the second target signal, the first end of one third switching tube is connected with the first end of one second resistor, and the second end of one third switching tube is connected with a power supply signal; the control end of an nth fourth switching tube in the a second impedance unit is connected with an nth sub-signal in an a group of sub-signals in the third target signal, the first end of the fourth switching tube is connected with a ground signal, the second end of the fourth switching tube is connected with the first end of a second resistor, and the second ends of 2N second resistors are connected with corresponding data pins.

21. The semiconductor memory according to any one of claims 15 to 20, wherein,

the first level state is a high level state, and the second level state is a low level state;

the first switching tube and the third switching tube are P-type channel field effect tubes, and the second switching tube and the fourth switching tube are N-type channel field effect tubes;

the control end of the P-type channel field effect transistor is a grid electrode, the second end of the P-type channel field effect transistor is a source electrode, the first end of the P-type channel field effect transistor is a drain electrode, the control end of the N-type channel field effect transistor is a grid electrode, the second end of the N-type channel field effect transistor is a drain electrode, and the first end of the N-type channel field effect transistor is a source electrode;

the standard resistance values were 240 ohms.

22. An electronic device comprising the semiconductor memory according to any one of claims 9-21.